JP2003108086A - Active matrix type display device - Google Patents

Active matrix type display device

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Publication number
JP2003108086A
JP2003108086A JP2001301919A JP2001301919A JP2003108086A JP 2003108086 A JP2003108086 A JP 2003108086A JP 2001301919 A JP2001301919 A JP 2001301919A JP 2001301919 A JP2001301919 A JP 2001301919A JP 2003108086 A JP2003108086 A JP 2003108086A
Authority
JP
Japan
Prior art keywords
signal
gate
power supply
level shift
line driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001301919A
Other languages
Japanese (ja)
Inventor
Koji Hirozawa
Yusuke Tsutsui
孝司 廣澤
雄介 筒井
Original Assignee
Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
三洋電機株式会社
鳥取三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, 三洋電機株式会社, 鳥取三洋電機株式会社 filed Critical Sanyo Electric Co Ltd
Priority to JP2001301919A priority Critical patent/JP2003108086A/en
Publication of JP2003108086A publication Critical patent/JP2003108086A/en
Application status is Pending legal-status Critical

Links

Abstract

(57) [Problem] To provide an active matrix display device with low power consumption. In an active matrix display device having a plurality of level shift circuits, a power supply voltage and a predetermined signal are input, and only during a predetermined period of the signal,
A power supply control circuit for supplying a pulse voltage to a certain level shift circuit, and the level shift circuit boosts another signal only during a period in which the pulse voltage is input, so that the level shift circuit consumes static electricity. Power can be reduced. As a result, power consumption of the active matrix display device can be reduced.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch for each pixel.
Active matrix display device with a switching element
In particular, the present invention relates to a booster circuit arranged around a display area. 2. Description of the Related Art Currently used display devices are broadly classified.
To passive matrix type and active matrix type
Can be classified. Of these, active matrix display devices
The position of each pixel depends on the image data of that pixel.
Touch to display by applying voltage (or passing current)
It is a display device of Ip. [0003] Liquid crystal display (Liquid Crystal Display:
LCD) encloses liquid crystal between opposing substrates, and
A voltage is applied to the formed pixel electrode to reduce the transmittance of the liquid crystal.
This is a display device that displays by changing it.
Active matrix display devices are especially used for monitors.
It has become mainstream. In addition, electroluminescence (Electr
o Luminescence (EL) display device is formed for each pixel.
The current is passed from the pixel electrode to the EL element.
Active matrix EL
Display devices have been actively studied for practical use. In particular, a thin film transformer used for a switching element
Semiconductor (Thin Film Transistor: TFT) layer
A so-called low-temperature policy manufactured without using a high-temperature process
In the case of recon (poly Silicon: p-Si) TFT,
Various peripheral circuits can be integrated on a substrate
And the number of driving ICs connected to the surroundings can be reduced.
Therefore, manufacturing costs can be reduced. Low temperature p-
SiTFT is not limited to LCD and EL display devices,
Zuma display, field effect display (FED), etc.
Can be used in various active matrix display devices
it can. FIG. 5 shows a conventional active matrix type table.
It is a key map showing an indicator. Various circuits on glass substrate
An external control circuit 200 is provided on the display panel 100 disposed therein.
It is connected. The external control circuit 200 includes a display panel 100
Control signals, video signals, and power supply voltage for operating the
VDD and the like are supplied to the display panel 100. External control circuit
Reference numeral 200 denotes a normal CMOS circuit, for example, a 3V
It operates at a low voltage, and the output control signal also has an amplitude of 3V.
You. The display panel 100 has a display area 10 and each
A seed peripheral circuit is arranged. The display area 10 includes a matrix
A plurality of pixel electrodes 11 arranged in a matrix,
Drain lines 12 and a plurality of gate lines extending in the row direction
13 are arranged, that of the drain line 12 and the gate line 13
The TFTs 14 are arranged corresponding to the respective intersections. T
The drain of the FT 14 is connected to the drain line 12 and the gate is
And the source is connected to the pixel electrode 11 respectively.
ing. Although not shown, each pixel electrode 11 has
Color filters of any of RGB primary colors are arranged correspondingly
And perform color display. On the side of the display area 10, a drain line driver is provided.
The gate 21 and the precharge circuit 22
Bars 23 are arranged respectively. Drain wire driver
21, precharge circuit 22, gate line driver 23
And an external control circuit 200, respectively.
Various control signals and video signals output from the circuit 200 are
Level shift circuits 30a to 30f for boosting are connected.
ing. Next, an active matrix type display device will be described.
The operation will be described. The gate line driver 23
The gate lines CKV are sequentially selected and the gate signal CKV is applied.
At the same time, the gate line driver 23
The switches in the gate line driver 23 connected respectively (FIG.
(Not shown) is applied.
You. Write permission to the switch in the gate line driver 23
Only while the signal ENB is applied at a high level,
The selected gate line 13 is a high-level gate signal.
The signal CKV is output. The gate signal CKV is high level.
When it reaches the level, the TFT 1 connected to the gate line 13
Turn on 4. Then, the gate line driver 23 operates in the vertical scan mode.
Select first gate line 13 by start signal STV
Then, the next gate line 13 according to the vertical clock signal CKV
And switch to select. The drain line driver 21 includes a plurality of drains.
A predetermined drain line 12 is sequentially selected from the drain line 12 and the drain line 12 is selected.
RGB to pixel electrode 11 through in-line 12 and TFT 14
Video signal. Drain line driver 21 is horizontal
The first drain line 12 is projected by the start signal STH.
An image signal is supplied, and the next signal is supplied according to the horizontal clock signal CKH.
The video signal is supplied by sequentially switching to the drain line 12. The precharge circuit 22 is connected to the drain line 12
Precharge data PCD before the video signal is input to
For the portion connected to the selected gate line 13
Eliminates the effects of the voltage held by the liquid crystal and
Of the portion connected to the gate line 13
Eliminates the effects of voltage and changes in voltage due to video signals
Enhances the response of the liquid crystal to In addition, this active mat
The liquid crystal display device is more suitable than the gate line 13 is selected.
Before (Hereinafter, a representative “horizontal retrace period” is exemplified.)
And the precharge data for all drain lines 12
The batch precharge method in which the PCD is applied simultaneously
Used. In the display panel 100, each dry
Circuit and each transistor are formed on a glass substrate.
Made of a polycrystalline silicon film
Many pixel electrodes 1 are connected to the drain line 12 and the gate line 13
1 is connected, the operating power of the external control circuit 200 is
Operation at a low voltage of about 3 V
No. Therefore, the control signal supplied from the external control circuit 200 is
Signal to a higher voltage, for example, 15V.
The operation speed of the display device is realized by TFT.
You. Each of the level shift circuits 30a to 30f controls each control signal.
Are respectively boosted and arranged for each control signal.
ing. For example, the horizontal clock signal CKH is
3V amplitude low voltage clock output from the external control circuit 200
CKH1 and CKH2 to the level shift circuit 30a.
Therefore, they are combined and generated by boosting to 15V.
It is. FIG. 6 is a circuit diagram showing the drain line driver 21.
FIG. The drain line driver 21 is connected to the scanner 24
It has a plurality of RGB selection circuits 25. Scanner 24
The number of shift registers 26
The control signal supplied from the external control circuit 200 is
Signals CKH1 and CKH2 by the level shift circuit 30.
The horizontal clock signal CKH that has been synthesized and boosted
It is. The RGB selection circuit 25 outputs the output of the shift register 26.
Three drain line selection TFT2 whose power is connected to the gate
7 and the drain of each drain line selection TFT 27
Is connected to one of the data lines 31RGB.
The source of each drain line selection TFT 27 is the drain line 12
It is connected to the. The first stage shift register 26a has a horizontal switch.
Start signal STH is input. Horizontal start signal ST
H is about 1.5 μsec during one horizontal scan period of about 64 μsec.
This signal is a High level signal only during the period. Shift cash register
The star 26a receives water when the horizontal start signal STH is input.
The output of the output terminal Q is H during one cycle of the flat clock signal CKH.
It goes to the high level. By the output of the shift register 26a
Thus, of the drain line selection TFT 27, 27Ra, 2Ra
7Ga and 27Ba are turned on, and the data line 31 is turned on.
The video signals of R, G, and B are respectively applied to the drain lines 12Ra,
It is supplied to 12Ga and 12Ba. Shift register 26
The next shift register 26c is turned on by the output of b.
You. Hereinafter, similarly, the shift register 26 is sequentially turned on.
To select the drain line 12 in sequence and supply video signals to all pixels.
Pay. All drain lines 12 for one row are selected.
After that, the vertical clock signal CKV has the next cycle. Game
The line driver 23 is connected to the switch connected to the gate line 13.
Input a low-level write enable signal ENB to the
When the switch is turned off, the gate signal of the gate line 13 is
Signal CKV to a low level, and the next gate line 13
Signal CKV is set to High level and selected. Selection
After that, the switch connected to the gate line 13 is written.
Signal ENB is applied at a low level and the gate
The signal CKV becomes Low level and the drain line driver
Operation of 21 and writing of video signal to drain line 12
Is limited. When the write enable signal ENB is High level
The gate signal STH of the gate line 13
Input, and the output of the shift register 26a is High level.
Become The gate line driver 23 is also composed of a scanner.
Have been. FIG. 7 is a timing chart showing the relationship between various control signals.
FIG. For example, the horizontal clock signal CKH and the horizontal
Relationship between start signal STH and write enable signal ENB
Is as follows. 5 cycles of horizontal clock signal CKH
During this period, the write enable signal ENB is at the low level.
Write enabled during one cycle of the next horizontal clock signal
The signal ENB changes from a low level to a high level,
Further, from the next horizontal clock, the horizontal start signal S
TH is High for two periods of the horizontal clock signal CKH.
Become a level. After that, during the horizontal scanning period, writing is allowed.
The enable signal ENB and the horizontal start signal STH are low level.
It becomes. When the horizontal scanning period ends, the horizontal
The write enable signal ENB is set to H in accordance with the clock signal.
It goes to the high level, and the same operation is repeated. Generally, an external control circuit is required.
1 for each wiring that transmits each control signal to the display panel
Two level shift circuits are provided and the clock signal
Each level shift circuit controls each control only for a certain period according to
Boost the control signal. Generally, a level shift circuit raises a signal.
Even when the voltage is not supplied
Power continues to be consumed. This is called static power consumption.
Conversely, while the control signal is being boosted, the level shift circuit
Consumes more power, so-called dynamic power consumption. Sa
Furthermore, the higher the frequency of the control signal, the higher the level shift circuit
, The dynamic power consumption increases. In particular, mobile phones and personal digital assistants are also active.
A live matrix type display device is used,
There is an increasing demand for lower power consumption of this type of display device.
I have. The present invention provides an active mat with lower power consumption.
An object of the present invention is to provide a liquid crystal display device. [0023] The present invention achieves the above object.
It is made in order to
A plurality of gate lines are arranged, and a plurality of
A drain line and a predetermined drain of the plurality of drain lines;
Drain line to sequentially select IN lines and supply video signals
A driver and a predetermined gate line among the plurality of gate lines.
Gate line driver that sequentially selects and supplies gate signals
And the drain line driver and the gate line driver
Are arranged in a matrix corresponding to the intersection of
A plurality of switches for supplying the video signals to the pixel electrodes in response to the
Matrix display device having a switching element
The gate line driver and the drain line driver
Boost multiple control signals supplied to driver
A level shift circuit having a plurality of level shift circuits;
At least one of the levels is boosted by the level shift circuit.
Sequential operation that operates only during a predetermined period according to the control signal
Active matrix type display device which is a level shift circuit
Place. Further, the sequential level shift circuit is provided
Only when the pulse voltage is supplied, the pulse voltage
And the pulse voltage is applied to another of the level shift circuits.
The drain line driver or
// Active matrices supplied to gate line driver
It is a box type display device. Further, the active matrix type display
The apparatus comprises: a video signal for the plurality of drain lines;
Precharge that supplies a precharge signal before supplying
The pulse voltage is applied to the gate line drive.
To control the gate signal supply to the gate line
The sequential operation level is controlled by a write enable signal.
Shift circuit before the video signal is supplied to the drain line.
Precharge the precharge signal.
Active matrix type display device. Alternatively, the power supply voltage and the level shift circuit
At least one of the control signals boosted by the
One is supplied and the pulse voltage is changed to the sequential operation level.
Actuator having power supply control circuit for outputting to shift circuit
This is a live matrix display device. Further, the power supply control circuit includes a power supply
Voltage and supplied to the gate line driver to the gate line
And a write enable signal that controls the gate signal supply
The power supply control circuit is configured to control the write control signal
Prohibits gate signal supply to the gate line,
Active matrix display for outputting the pulse voltage
Device. Alternatively, the power supply control circuit includes a power supply
A voltage and a plurality of the control signals are supplied;
The control circuit determines a predetermined timing from the plurality of control signals.
Generates a power supply permission signal that changes in
Active matrix that outputs pulse voltage according to signal
This is a display device having a rectangular shape. Furthermore, the power supply control circuit includes a power supply
Voltage and a gate line supplied to the gate line driver.
A write enable signal for controlling the supply of a gate signal;
Switching of drain line to be supplied to rain driver and selected
The horizontal clock signal that controls the timing
Generating the power supply permission signal, and
A pulse voltage output circuit, the sequential operation level shift circuit;
Is a horizontal start to start the gate driver
An active matrix display device that boosts signals
You. Alternatively, a plurality of gates extending in the row direction are arranged.
Gate line and a plurality of drain lines extending in the column direction.
And a predetermined drain line among the plurality of drain lines in order.
A drain line driver for selecting and supplying a video signal;
Sequentially selecting a predetermined gate line from the plurality of gate lines;
A gate line driver for supplying a gate signal to the
Corresponds to the intersection between the in-line driver and the gate line driver
Are arranged in a matrix, and the video signals are arranged in accordance with the gate signal.
Multiple switching elements that supply image signals to pixel electrodes
And supplying the video signal to the plurality of drain lines.
Precharge circuit that supplies a precharge signal before
And the drain line driver includes the video signal.
Signal, horizontal clock signal, horizontal start signal,
In the gate line driver, the gate signal, write
Enable signal, vertical clock signal, vertical start signal input
Input to the drain line driver and gate line driver
Boosted various signals and the precharge signal
And includes at least first and second level shift circuits.
Active matrix display with level shift circuit
A power supply voltage, said first level shift circuit;
The first signal boosted by the path is input, and the first signal
Power supply that maintains a specified voltage for a specified period of time.
Power supply control circuit that outputs pulse voltage
The pulse voltage is supplied to the second level shift circuit.
And the second level shift circuit receives the pulse
Only during the period in which the voltage is supplied, the second signal is boosted.
It is a active matrix type display device. Further, the first signal is the write enable signal.
The second signal is a precharge signal.
Is an active matrix type display device. Alternatively, a plurality of gates extending in the row direction are arranged.
Gate line and a plurality of drain lines extending in the column direction.
And a predetermined drain line among the plurality of drain lines in order.
A drain line driver for selecting and supplying a video signal;
Sequentially selecting a predetermined gate line from the plurality of gate lines;
A gate line driver for supplying a gate signal to the
Corresponds to the intersection between the in-line driver and the gate line driver
Are arranged in a matrix, and the video signals are arranged in accordance with the gate signal.
A plurality of switching elements for supplying image signals to pixel electrodes;
Having the video signal,
A horizontal clock signal and a horizontal start signal are input,
The gate line driver has the gate signal, write enable
Signal, vertical clock signal, vertical start signal
Input to the drain line driver and gate line driver.
Boosted various signals, and at least the third to fifth levels
That have a plurality of level shift circuits including
In the active matrix type display device, the third laser
A third signal boosted by a bell shift circuit;
Fourth signal boosted by a fourth level shift circuit
Is input, and from the third signal and the fourth signal,
A power supply permission signal that maintains a specified voltage for a specified period
Supply permission signal generation circuit that outputs a signal, power supply voltage,
The power supply permission signal is input, and the power supply permission signal
Is a power supply voltage that maintains a predetermined voltage for a predetermined period of time.
A power supply control circuit that outputs a pulse voltage,
The pulse voltage is input to the fifth level shift circuit.
And the fifth level shift circuit outputs the pulse voltage
Active to boost the fifth signal only during the supplied period
It is a matrix type display device. Further, the third signal is the write enable signal.
The fourth signal is the horizontal clock signal.
And the third signal is the horizontal start signal.
An active matrix display device. First, a first embodiment of the present invention will be described.
explain about. FIG. 1 shows a first embodiment of the present invention.
1 shows an active matrix type display device. Subordinate
As before, a liquid crystal display device is exemplified, and the configuration is the same as the conventional one.
The same numbers are given to the same, and the description is omitted. Display in which various circuits are arranged on a glass substrate
The external control circuit 200 is connected to the panel 100.
You. The external control circuit 200 is connected to the display panel 100
Control signals, video signals, and power supply voltage for operating the
VDD and the like are supplied to the display panel 100. External control circuit
Reference numeral 300 denotes a normal CMOS circuit having a low voltage of 3V.
And the output control signal also has an amplitude of 3V. The display panel 100 has a display area 10 and each
A seed peripheral circuit is arranged. The display area 10 includes a matrix
A plurality of pixel electrodes 11 arranged on the upper side,
Drain lines 12 and a plurality of gate lines extending in the row direction
13 are arranged, that of the drain line 12 and the gate line 13
The TFTs 14 are arranged corresponding to the respective intersections. T
The drain of the FT 14 is connected to the drain line 12 and the gate is
And the source is connected to the pixel electrode 11 respectively.
ing. Although not shown, each pixel electrode 11 has
Color filters of any of RGB primary colors are arranged correspondingly
And perform color display. On the side of the display area 10, a drain line driver is provided.
The gate 21 and the precharge circuit 22
Bars 23 are arranged respectively. Drain wire driver
21, precharge circuit 22, gate line driver 23
And an external control circuit 200, respectively.
Various control signals and video signals output from the circuit 200 are
Level shift circuits 30a to 30f for boosting are connected.
ing. Next, the active matrix type display device
The operation will be described. The gate line driver 23
The gate lines CKV are sequentially selected and the gate signal CKV is applied.
At the same time, the gate line driver 23
The switches in the gate line driver 23 connected respectively (FIG.
(Not shown) is applied.
You. Write permission to the switch in the gate line driver 23
Only while the signal ENB is applied at a high level,
The selected gate line 13 is a high-level gate signal.
The signal CKV is output. The gate signal CKV is high level.
When it reaches the level, the TFT 1 connected to the gate line 13
Turn on 4. Then, the gate line driver 23 operates in the vertical scan mode.
Cut to the next gate line 13 sequentially according to the start signal STV
Change and select. The drain line driver 21 includes a plurality of drains.
A predetermined drain line 12 is sequentially selected from the drain line 12 and the drain line 12 is selected.
RGB to pixel electrode 11 through in-line 12 and TFT 14
Video signal. Once the drain line driver 21
, One or more drain lines 12 are selected. Do
The rain line driver 21 responds to the horizontal start signal STH.
Video signal to the first drain line 12
To the next drain line 12 according to the clock signal CKH.
Instead, a video signal is supplied. The precharge circuit 22 is connected to the drain line 12
Precharge data PCD before the video signal is input to
For the portion connected to the selected gate line 13
Eliminates the effects of the voltage held by the liquid crystal,
Enhances the response of the liquid crystal to voltage changes due to In addition,
This active matrix type display device has a horizontal retrace period.
And the precharge data for all drain lines 12
The batch precharge method in which the PCD is applied simultaneously
Used. The present embodiment differs from the prior art in that the power supply voltage
VDD and the precharge signal PCG
The shift circuit 30f is a power supply control circuit (“CN” in the drawing).
T ") 32. This power supply system
The control circuit 32 receives the write enable signal ENB and the power supply voltage V
DD and the write enable signal ENB is Lo.
The power supply voltage VDD is output only during the period of the w level. output
The supplied power supply voltage VDD is supplied to the level shift circuit 30f.
Used to boost the precharge signal PCG
You. Therefore, in the display device according to the present embodiment,
During the period when the write enable signal ENB is at the low level.
Only, the level shift circuit 30f of the precharge signal PCG
At the same time when the pulse voltage PVD is supplied.
The charge signal PCG is boosted. Conversely, the precharge signal
The pulse voltage PVD is supplied except during the period in which the signal PCG is boosted.
Is not supplied, the level shift of the precharge signal PCG is performed.
The static power consumption of the gate circuit 30f can be reduced. So
As a result, this embodiment reduces the power consumption of the display device.
can do. Next, referring to FIG. 2A, each level shift will be described.
The operation of the gate circuit 30 will be described in more detail. This implementation
Form of a level shift circuit
The output varies according to the balance of conduction in the balun.
Level shift circuit ". Input signal CLK1
And CLK2 are pulse signals having opposite polarities and the same timing.
No. The input power supply voltages VDD1 to VDD3 are 12
A voltage of V is applied. CLK1 is transmitted through the wiring 300a.
Therefore, an N-channel (hereinafter, referred to as “N-type”)
It is connected to the resistor 301n. CLK2 is the wiring 3
00b, a P-channel type (hereinafter referred to as “P-type”)
You. ) Transistor 301p and P-type transistor 30
Connected to 2p gate. Hereinafter, 3V is applied to CLK1 and 0V is applied to CLK2.
Consider a case where a signal is input. CLK1 is connected to the wiring 30
0a, the N-type transistor 301n and the N-type transistor
A voltage of 3 V is applied to the source of the transistor 302n. C
LK2 is connected to the P-type transistor 3 via the wiring 300b.
A voltage of 0 V is applied to the gate of 01p. Then, P type
The transistor 301p has a voltage of 12V from VDD1.
Conduction occurs because the voltage is applied. P-type transistor 301
The gate of the N-type transistor 301n connected to p
Also, the shadow caused by the resistance of the P-type transistor 301p and the wiring
A voltage higher than 3V is printed while being suppressed by sound
Be added. Already, the source of the N-type transistor 301n
Since a voltage of about 3 V is applied to the
The transistor 301n also conducts. And each transistor
Due to the influence of the resistance of the wiring 301 and the wiring, the node 3
03a is stable at about 8V, and the N-type
The source of the register 304n is set to 300 by CLK2.
A voltage of 0 V is applied via b. for that reason,
The gate voltage is 8V, the source voltage is 0V, and the difference is
Since the voltage is 8 V, the N-type transistor 301n conducts well.
I do. On the other hand, the P-type transistor 302p has its source
Since a voltage of 12 V is applied from VDD2,
It is always conductive. Therefore, always use N-type transistor
The gate of 302n has a P-type transistor 302p and a
While being suppressed by the resistance of the wire,
Pressure is applied. In this example, wiring is performed from CLK1.
Through the source of the N-type transistor 302n
However, since a voltage of 3 V is applied, the N-type
The transistor 302n also conducts. And each transistor 3
02 and the resistance of the wiring, etc.
The voltage passing through 3b is stable at about 8V, and the P-type
A voltage of about 8 V is applied to the gate of the star 304p. P
The source of the type transistor 304p always has VDD3
As a result, a voltage of 12 V is applied. Therefore,
The source voltage is 8V, the source voltage is 12V, and the difference is
4V, the P-type transistor 301p is
Conduction is weaker than that of the transistor 301n. node
From 305, the one with strong conduction, that is, the gate and SO
Voltage of the transistor 304 having a larger potential difference from the source
And outputs the voltage. for that reason,
In this example, the potential difference between the gate and the source is 8V.
A signal of voltage 0V for conducting the type transistor 304n is output.
Is forced. The output signal is output to the inverter 30
6 and the inverter 307 stabilize the voltage.
Then, it is output to each peripheral circuit. Such a "balance level shift circuit"
Then, in principle, static power consumption cannot be eliminated. Subordinate
Therefore, from outside the level shift circuit,
Power supply to the power supply
The present invention, in which the supply of voltage is stopped,
Lance level shift circuit "
It works. Next, the power supply control circuit will be described with reference to FIG.
The road 32 will be described. The power supply circuit 32 has a power supply voltage V
DD is supplied and the write enable signal ENB is set to Hi.
Only when the pulse voltage PVD is input at the gh level,
Output at High level, write permission
Using the signal ENB as a gate and the power supply voltage VDD as a source
And a P-type transistor having a pulse voltage PVD as a drain.
Data 308. The level shift shown in each circuit diagram of FIG.
The configuration of the power circuit and the power supply control circuit is one example each
However, the invention of the present application is of course not limited to this. FIG. 3 is a timing chart showing the relationship between various control signals.
FIG. Horizontal clock signal CKH and write
Between write enable signal ENB and precharge signal PCG
Will be described. The precharge signal PCG is about 64
The potential is set to Hig for about 3 μsec during one horizontal scanning period of μsec.
This is a signal that goes to the h level. Precharge signal PCG
In the period during which the level becomes High, the display device
Charge data PCD is written to the drain line. On the other hand, the write enable signal ENB is
After the end of the scanning period, the horizontal
It is at a low level for five periods of the clock signal CKH. Writing
Signal ENB falls to a low level
The horizontal clock signal is delayed by one cycle from the horizontal clock signal.
The precharge signal PCG rises during three periods of CKH.
To a High level. And the precharge signal
One cycle delay from horizontal clock signal when PCG falls
As a result, the write enable signal ENB rises,
Be a bell. Then, during the horizontal scanning period, write permission
The signal ENB rises to a high level, and
The charge signal PCG falls to a low level.
You. When the horizontal scanning period ends, the write permission
The enable signal ENB falls and goes to a low level.
Is repeated. This write enable signal ENB is Lo
The precharge signal PCG is boosted only during the period of the w level.
Operates the level shift circuit 30f, and
During most periods, do not operate the level shift circuit 30f.
No. As described above, in this embodiment, the level switch
For controlling supply of pulse voltage to the shift circuit 30
The enable signal ENB is the rising edge of the precharge signal PCG.
The timing of rising and falling is not aligned,
Write during Low level period of precharge signal PCG
Be within the Low level period of the enable signal ENB
There is a difference. This is, as shown in FIG.
Each circuit uses many transistors and inverters.
Make sure that no voltage is applied to the transistors and inverters.
It takes a little time to drive, and each node
It takes some time for the voltage to stabilize
Signal delay, but this signal delay
Plays the role of absorbing differences. The feature of this embodiment is that the timing shown in FIG.
Write enable signal ENB and
Signal (hereinafter referred to as “first
Signal ". ) Within a period of maintaining a constant voltage
The polarity is inverted twice, that is, the pulse rises and rises
Another signal that falls (hereinafter, referred to as a “second signal”)
Exists, and the second signal is raised by the level shift circuit.
The first signal and the power supply voltage
While the first signal maintains a constant voltage.
Power supply to the level shift circuit that boosts the second signal only
By providing a power supply control circuit that supplies voltage,
In this level shift circuit, the first signal is a constant voltage.
To reduce static power consumption during periods other than maintaining pressure
It is possible. Period in which the first signal maintains a constant voltage
Between the rise of the second signal and the fall
The closer the period is, the greater the effect of reducing static power consumption
No. Next, a second embodiment of the present invention will be described.
I will tell. FIG. 4 is an illustration of an accelerator according to a second embodiment of the present invention.
1 shows a active matrix display device. Same as before
The same reference numerals are given to the portions described above, and description thereof is omitted. This embodiment is different from the prior art and the first embodiment.
The first point is that the supply permission signal generation circuit (“G
EN ") 32 receives the input horizontal clock signal CKH and
And the power supply permission signal VE from the write permission signal ENB.
NB and generates a power supply control circuit together with the power supply voltage VDD.
Input to the path 32, and then the power supply control circuit 32
Power supply permission signal VENB is input at High level
Only during the period when the pulse voltage PVD is
b, and the level shift circuit 30b outputs the pulse voltage P
When the horizontal start signal STH is boosted using VD
That is the point. The supply permission signal generation circuit 33 is provided with a horizontal clock.
Input signal CKH and write enable signal ENB
And a new power supply permission signal VENB is generated to supply power.
This is a circuit for supplying to the supply control circuit 32. Power supply voltage VDD
Power supply system that receives power supply permission signal VENB
The control circuit 32 outputs the power supply permission signal VENB to a high level.
The level of the horizontal start signal STH only during the period when
The pulse voltage PVD is supplied to the shift circuit. Output
The pulse voltage PVD is supplied to the level shift circuit 30b.
And is used to boost the horizontal start signal STH. In addition to FIG. 4, the timing chart of FIG.
Referring to the generation of the power supply permission signal VENB,
Will be explained. The rise of a horizontal clock pulse
At the same time, the pulse of the write enable signal ENB rises.
You. Then, after a delay of eight horizontal clock cycles,
Input signal CKH and write enable signal ENB
The supply permission signal generation circuit 33 outputs the power supply permission signal.
No. VENB rises. And 6 rounds of horizontal clock
During the period, the power supply permission signal VENB is set at the high level.
And keep falling. This is repeated to supply power
A permission signal VENB is generated. And power supply permission
The signal VENB and the power supply voltage VDD are supplied to the power supply control circuit 3
2 and the power supply control circuit 32 permits the power supply
Only during the period when the signal VENB is at the High level,
The level shift circuit that boosts the start signal STH
Supply voltage PVD. In this embodiment, the horizontal start signal
Although the level shift circuit that boosts STH has been illustrated,
The level shift is not limited to this, but boosts other signals.
It can also be applied to circuits. Also power supply
In order to generate the permission signal VENB, in the present embodiment, the water
Using flat clock signal CKH and write enable signal ENB
However, the present invention is of course not limited to this.
It is possible to use the clock signal and the precharge signal PSG.
I don't know. The feature of this embodiment is that the first embodiment
The period during which a signal maintains a constant voltage
If there is no signal with rising and falling pulses
In both cases, the horizontal clock in the timing chart of FIG.
Signal with a short cycle, such as the
Signal ". ) And a constant voltage for a predetermined period
Another signal to be maintained (hereinafter, referred to as “fourth signal”)
Generates a new power supply permission signal based on the
Providing a supply permission signal generation circuit to supply to the control circuit
Thereby, the role of the first signal in the first embodiment is
That is, a power supply control signal to be fulfilled is generated. The power supply control circuit is provided in the first embodiment.
The power supply permission signal and the power supply voltage are
While the power supply enable signal maintains a certain voltage.
Only another signal (hereinafter, referred to as a “fifth signal”)
The power supply voltage is supplied to the level shift circuit for boosting. this
Enables power supply in this level shift circuit.
Static power consumption during periods other than when the signal maintains a constant voltage
Reduce. Further, in the present embodiment, the period of the third signal
The power supply permission signal can be freely generated within the range of
When the power supply permission signal maintains a constant voltage,
The period between the rise of the fifth signal and the fall
Since the length can be made closer, compared to the first embodiment
This can also increase the effect of reducing static power consumption. In each embodiment, the level shift
A display panel with a built-in circuit has been exemplified,
The position of the level shift circuit of the present invention is limited to the display panel.
For example, the level shift circuit is placed in the external control circuit.
It does not matter. According to the present invention, an antenna having a level shift circuit is provided.
In the active matrix display device, the power supply voltage and
A first level shift which is one of the level shift circuits
The first signal boosted by the circuit is input and the first signal
A power supply voltage that maintains a predetermined voltage for a predetermined period of a signal
A power supply control circuit that outputs a pulse voltage that is
The pulse voltage is applied to a level shifter other than the first level shift circuit.
Input to the second level shift circuit which is one of the shift circuits.
Pulse voltage is supplied to the second level shift circuit.
Only during the period when the second signal is boosted
Thus, the second level shift circuit includes almost the second level shift circuit.
The power supply voltage is supplied only during the signal boosting period
become. Therefore, the static power consumption of the second level shift circuit is reduced.
Power can be reduced. For example, the first signal is a write enable signal
Yes, if the second signal is a precharge signal,
Only the enable signal has relatively low pulse rise frequency
Therefore, the voltage that was always supplied in the past is considered as static power consumption.
Is consumed without being used in the level shift circuit.
I was The present invention is applied to a level shift circuit for boosting this signal.
Can significantly reduce static power consumption.
You. Further, a predetermined period of the first signal and a second signal
The shorter the boosting period, the lower the effect of static power consumption
Is big. The present invention has a level shift circuit.
Active matrix display devices
A third level shift circuit which is one of the shift circuits.
And a third level shift circuit
The fourth level which is one of the level shift circuits other than
The fourth signal boosted by the shift circuit is input,
From the third signal and the fourth signal, the power supply permission signal
A power supply voltage that maintains a specified voltage for a specified period
It has a power supply control circuit that outputs
The voltage is supplied to a third level shift circuit and a fourth level shift circuit.
The fifth level which is one of the level shift circuits other than the circuit
The pulse voltage is supplied to a bell shift circuit,
The fifth signal is boosted only during the
As a result, the third signal and the fifth level shift circuit are supplied to the fifth level shift circuit.
From the fourth signal and the fourth signal by the power supply control circuit.
A power supply that maintains a constant voltage only during the signal boost period
Only during the period of generating the permission signal and boosting the fifth signal,
Since the power supply voltage can be supplied, the fifth level switch
Static power consumption of the switching circuit can be reduced. For example, the third signal is a write enable signal
Where the fourth signal is a horizontal clock signal and the fifth signal is a horizontal clock signal.
If the signal is a flat start signal, the supply permission signal permission circuit
The frequency of the rise is relatively low, and the cycle is horizontal.
One cycle based on the write enable signal longer than the
Delay using a horizontal clock signal with a short period
Depending on the method, the period is almost close to the horizontal start signal
A power supply permission signal can be generated and output. Soshi
The power supply control circuit receives the power supply permission signal and the power
A source voltage is input, a pulse voltage is generated and output. Pa
The horizontal voltage is almost equal to the horizontal start signal.
Input to the level shift circuit that boosts the start signal
The flat start signal is boosted. The horizontal start signal is also
In the past, because the frequency of startups was relatively low,
Most of the supplied voltage is consumed as static power consumption.
I was Therefore, a level shift circuit that boosts this signal
If the present invention is applied to static electricity consumption,
Can be. In this case, power is supplied within the period of the third signal.
The power supply permission signal can be freely generated and the power supply
A period in which the permission signal maintains a constant voltage, and a period in which the fifth signal
Shorten the length of time between rising and falling
To reduce static power consumption further.
Can be As described above, the present invention provides a level shift circuit.
By reducing static power consumption on roads,
Realizing low power consumption of active matrix display devices
Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conceptual diagram of an active matrix display device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a level shift circuit and a circuit diagram of a power supply control circuit. FIG. 3 is a timing chart of each control signal of the display device of the present invention. FIG. 4 is a conceptual diagram of an active matrix display device according to a second embodiment of the present invention. FIG. 5 is a conceptual diagram of a conventional active matrix type display device. FIG. 6 is a circuit diagram of a drain line driver. FIG. 7 is a timing chart of each control signal of a conventional display device. [Description of Signs] 10: Display area 11: Pixel electrode 12: Drain line 13: Gate line 14: TFT 21: Drain line driver 22: Precharge circuit 23: Gate line driver 24: Scanner 25: RGB selection circuit 26: Shift Register 27: drain line selection TFT 30a-30f: level shift circuit 31: data line 32: power supply control circuit (CNT) 33: supply permission new combined correct solution (GEN) 100: display panel 200: external control circuit 300a, 300b : Wirings 301n, 302n, 304n: N-channel transistors 301p, 302p, 304p: P-channel transistors 303a, 303b, 305: Nodes 306, 307: Inverter

Continued on the front page (51) Int.Cl. 7 Identification FI FI Theme Court II (Reference) G09G 3/20 G09G 3/20 612G 621 621L (72) Inventor Yusuke Tsutsui 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka No. Sanyo Electric Co., Ltd. F term (reference) 2H092 GA59 JA24 NA26 PA06 2H093 NA16 NC01 NC16 NC22 NC26 NC27 NC34 ND39 5C006 BB16 BC03 BC11 BC20 BF03 BF46 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ03 JJ04 KK07 KK47

Claims (1)

  1. Claims: 1. A plurality of gate lines extending in a row direction and a plurality of drain lines, a plurality of drain lines extending in a column direction and a predetermined drain line among the plurality of drain lines. , A drain line driver for sequentially selecting and supplying a video signal, a gate line driver for sequentially selecting a predetermined gate line from the plurality of gate lines and supplying a gate signal, the drain line driver and the gate line driver A plurality of switching elements arranged in a matrix corresponding to the intersection with the pixel signal and supplying the video signal to a pixel electrode in accordance with the gate signal, wherein the gate line driver and the drain A plurality of level shift circuits for respectively boosting a plurality of control signals supplied to the line driver, wherein at least one of the level shift circuits , Active matrix display device, wherein the level shift circuit is only a predetermined period of time corresponding to the control signal for boosting a sequential operation level shift circuit operates. 2. The sequential level shift circuit is supplied with the pulse voltage only during a period in which the pulse voltage is supplied, and the pulse voltage is boosted by another level shift circuit, and the pulse voltage is boosted by another level shift circuit. 2. The active matrix display device according to claim 1, wherein the active matrix display device is supplied to a gate line driver. 3. The active matrix type display device has a precharge circuit for supplying a precharge signal to the plurality of drain lines before supplying the video signal, and the pulse voltage is controlled by the gate voltage. The sequential operation level shift circuit is supplied to a line driver and controlled by a write enable signal for controlling supply of a gate signal to a gate line, and the sequential operation level shift circuit boosts a precharge signal for precharging the drain line prior to supply of a video signal. The active matrix display device according to claim 2, wherein: 4. A power supply control circuit which is supplied with at least one of a power supply voltage and the control signal boosted by the level shift circuit and outputs the pulse voltage to the sequential operation level shift circuit. The active matrix display device according to claim 1, wherein: 5. The power supply control circuit is supplied with a power supply voltage and a write enable signal that is supplied to the gate line driver and controls supply of a gate signal to a gate line. 5. The active matrix display device according to claim 4, wherein the pulse voltage is output only while the write control signal inhibits supply of a gate signal to a gate line. 6. The power supply control circuit is supplied with a power supply voltage and a plurality of control signals, and the power supply control circuit outputs a power supply permission signal that changes at a predetermined timing from the plurality of control signals. The active matrix display device according to claim 4, wherein the active matrix display device generates and outputs a pulse voltage according to the power supply permission signal. 7. The power supply control circuit includes a power supply voltage, a write enable signal supplied to the gate line driver to control supply of a gate signal to a gate line, and a write enable signal supplied to the drain driver to be selected. A horizontal clock signal for controlling switching timing is supplied, the power supply permission signal is generated, the pulse voltage is output in response to the signal, and the sequential operation level shift circuit is a horizontal start signal for starting the gate driver. 7. The active matrix display device according to claim 6, wherein the voltage is increased. 8. An image by sequentially selecting a plurality of gate lines extending in a row direction, a plurality of drain lines extending in a column direction, and a predetermined drain line among the plurality of drain lines. A drain line driver for supplying a signal, a gate line driver for sequentially selecting a predetermined gate line from among the plurality of gate lines and supplying a gate signal, and an intersection between the drain line driver and the gate line driver. A plurality of switching elements arranged in a matrix to supply the video signal to a pixel electrode according to the gate signal, and a precharge signal to the plurality of drain lines before supplying the video signal to the plurality of drain lines And a precharge circuit,
    The drain line driver receives the video signal, the horizontal clock signal, and the horizontal start signal. The gate line driver receives the gate signal, the write enable signal, the vertical clock signal, and the vertical start signal. In an active matrix display device which boosts various signals input to a driver and a gate line driver and the precharge signal and has a level shift circuit including at least first and second level shift circuits,
    A power supply that receives a power supply voltage and a first signal boosted by the first level shift circuit and outputs a pulse voltage that is a power supply voltage that maintains a predetermined voltage for a predetermined period of the first signal. A supply control circuit, wherein the pulse voltage is input to the second level shift circuit, and the second level shift circuit boosts a second signal only during a period in which the pulse voltage is supplied. An active matrix type display device characterized by the above-mentioned. 9. The active matrix display device according to claim 8, wherein said first signal is said write enable signal, and said second signal is said precharge signal. 10. An image by sequentially selecting a plurality of gate lines extending in a row direction, a plurality of drain lines extending in a column direction, and a predetermined drain line among the plurality of drain lines. A drain line driver for supplying a signal, a gate line driver for sequentially selecting a predetermined gate line from among the plurality of gate lines and supplying a gate signal, and an intersection between the drain line driver and the gate line driver. A plurality of switching elements for supplying the video signal to the pixel electrode in accordance with the gate signal, wherein the drain line driver receives the video signal, a horizontal clock signal, and a horizontal start signal. The gate line driver receives the gate signal, the write enable signal, the vertical clock signal, and the vertical start signal.
    In the active matrix display device which boosts various signals input to the drain line driver and the gate line driver and has at least a plurality of level shift circuits including third to fifth level shift circuits, the third level shift circuit The third signal boosted by
    The fourth signal boosted by the level shift circuit is input, and a supply permission signal for outputting a power supply permission signal for maintaining a predetermined voltage for a predetermined period from the third signal and the fourth signal for a predetermined period A power supply control circuit that receives a power supply voltage and the power supply permission signal, and outputs a pulse voltage that is a power supply voltage that maintains a predetermined voltage for a predetermined period of the power supply permission signal. Wherein the pulse voltage is input to the fifth level shift circuit, and the fifth level shift circuit boosts a fifth signal only during a period in which the pulse voltage is supplied. Type display device. 11. The active matrix according to claim 10, wherein the third signal is the write enable signal, the fourth signal is the horizontal clock signal, and the third signal is the horizontal start signal. Type display device.
JP2001301919A 2001-09-28 2001-09-28 Active matrix type display device Pending JP2003108086A (en)

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Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007322649A (en) * 2006-05-31 2007-12-13 Hitachi Displays Ltd Image display device
US7864141B2 (en) * 2004-06-22 2011-01-04 Samsung Electronics Co., Ltd. Display device and a driving method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7864141B2 (en) * 2004-06-22 2011-01-04 Samsung Electronics Co., Ltd. Display device and a driving method thereof
JP2007322649A (en) * 2006-05-31 2007-12-13 Hitachi Displays Ltd Image display device

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