JP2007286266A - Display drive device, flat display device and display driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably turn output signals of shift registers in all stages into an active state upon turning off a power supply by a simple configuration without adding a new transistor to an electrode substrate having a driving circuit. <P>SOLUTION: A display drive device 20A includes: shift registers 12, 13 in a plurality of stages each having an input terminal where an input signal enters, a first voltage electrode where a first power supply voltage is applied, a first clock terminal where a first clock signal enters, and an output terminal where an output signal exits; and a supply circuit 20 to supply a voltage to turn an output signal into an active state to the input terminal of the shift register in the first stage and to the first voltage electrodes and the first clock terminals of shift registers in all stages upon turning off the power supply. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display driving device, a flat display device including the display driving device, and a display driving method.

  A flat display device typified by a liquid crystal display device is thin, lightweight, and has low power consumption, and is therefore used as a display device for various devices. Among them, an active matrix liquid crystal display device in which a transistor is arranged for each pixel is widely used as a display device for a notebook personal computer or a portable information terminal. In addition, a technology for forming a thin film transistor made of polysilicon having a high electron mobility by a relatively low temperature process as compared with a transistor made of amorphous silicon used in a conventional liquid crystal display device has been established. The transistor used for the semiconductor device can be downsized. As a result, the pixel portion in which the pixel transistors are arranged at the intersections of the plurality of scanning lines and the plurality of signal lines and the driving circuit for driving the pixel transistors via the scanning lines and the signal lines are manufactured by the same manufacturing process. It can be integrally formed on the electrode substrate. A supply circuit for supplying various signals to these drive circuits is provided outside the electrode substrate provided with the scanning line drive circuit and the signal line drive circuit, and functions as an external circuit.

  Examples of the driving circuit of the flat display device include a scanning line driving circuit that outputs pulses to a plurality of scanning lines and a signal line driving circuit that outputs pulses to a plurality of signal lines. Each drive circuit includes a plurality of shift registers electrically connected in a column. Each shift register has an input circuit, an output circuit, and a reset circuit, shifts the phase of a pulse input to the input circuit, and outputs the pulse from the output circuit (for example, Patent Document 1 or Patent Document 2). reference). In addition, the shift register is often configured using only one of a pMOS transistor and an nMOS transistor in order to shorten the manufacturing process and realize cost reduction.

  For example, as shown in FIG. 12, the shift register SR101 (n) constituting the scanning line driving circuit includes an output circuit 101, an input circuit 102, a reset circuit 103, and a GON circuit 104 that forcibly turns on all scanning lines. It is configured. The shift register SR101 (n) includes clock terminals 111 and 112 that receive clock signals CK1, CK2, and CK3, an input terminal 113 that receives an input signal IN, and an output terminal 114 that outputs an output signal OUT. Yes.

  The output circuit 101 includes a transistor T101 and a transistor T102. The source of the transistor T101 is electrically connected to the first voltage electrode 115, and the drain thereof is electrically connected to the output terminal 114. The source of the transistor T102 is electrically connected to the output terminal 114, and the drain thereof is electrically connected to the clock terminal 111. The first voltage electrode 115 is supplied with a high level power supply voltage VDD.

  The input circuit 102 includes a transistor T103 and a transistor T104. The source of the transistor T103 is electrically connected to the control electrode (gate) of the transistor T102, and the drain and control electrode (gate) thereof are electrically connected to the input terminal 113. The source of the transistor T104 is electrically connected to the first voltage electrode 115, the drain is electrically connected to the control electrode (gate) of the transistor T101, and the control electrode (gate) is The input terminal 113 is electrically connected. Here, a conduction path (conduction path) to the control electrode of the transistor T101 is represented as a node n1, and a conduction path to the control electrode of the transistor T102 is represented as a node n2.

  The reset circuit 103 includes a transistor T105 and a transistor T106. The source of the transistor T105 is electrically connected to the control electrode of the transistor T101, and the drain and control electrode (gate) thereof are electrically connected to the clock terminal 112. The source of the transistor T106 is electrically connected to the first voltage electrode 115, the drain thereof is electrically connected to the control electrode of the transistor T102, and the control electrode (gate) thereof is connected to the transistor T101. Are electrically connected to the control electrode.

  The GON circuit 104 includes a transistor T107 and a transistor T108. The source of the transistor T107 is electrically connected to the first voltage electrode 115, the drain thereof is electrically connected to the control electrode of the transistor T101, and the control electrode (gate) is forcibly turned on as a control signal. It is electrically connected to the control signal line 116 to which the signal GON is input. The source of the transistor T108 is electrically connected to the control electrode of the transistor T102, the drain thereof is electrically connected to the second voltage electrode 117, and the control electrode (gate) is connected to the control signal line. 116 is electrically connected.

  Here, in a scanning line driving circuit having a configuration that does not include the GON circuit 104, when the power supply of the flat display device is turned off, its output becomes high impedance. All the scanning lines hold the VDD potential (VDD level) except for the selected stage when the power is turned off. However, since the held voltage VDD is gradually discharged due to the leakage current of the scanning line driving circuit and the supply circuit, Therefore, it becomes the GND potential. However, since it takes a considerable time (several seconds) until the output of the scanning line driving circuit becomes substantially the same potential as the GND potential, the pixel transistor keeps the OFF state, and each pixel maintains the previous potential. Will remain. Thereafter, the pixel potential is gradually discharged by the leak current of the pixel transistor, the signal line driver circuit, and the supply circuit, and finally becomes the GND potential.

  Similarly, the counter electrode Vcom is also gradually discharged by the leakage current of the supply circuit and finally becomes the GND potential. However, it takes a considerable time (several seconds or so) until the pixel potential becomes substantially the same potential as the counter electrode Vcom. ), The behavior is that the previous display screen gradually disappears. Since this time is relatively long for human eyes, in other words, it is a sufficiently visible time, so when the power is turned off, the previous display screen is held and appears to disappear gradually. There is.

  In order to quickly erase the afterimage of the display screen generated when the power is turned off as described above, as shown in FIG. 13, all the output signals OUT of the scanning line driving circuit are set to the low level almost simultaneously with the power off. At the same time as turning on all the pixel transistors, each output signal OUT of the signal line driver circuit, that is, the analog switch control signal (ASW control signal) is also all set to the low level, and the Vcom signal is input from the signal line driver circuit to the signal line. . If such measures are taken, the same potential as the Vcom potential (white potential in the case of normally white) is written to each pixel at the same time as the power is turned off, so that no afterimage is generated. In order to realize this, a GON circuit 104 is provided. The GON circuit 104 is a circuit that sets all the output signals OUT of the shift register SR101 (n) to a low level when the power is turned off.

  Here, the operation of the scanning line driving circuit for setting all the output signals OUT of the scanning line driving circuit to the low level will be described. The signal line driver circuit basically performs the same operation.

  As shown in FIG. 14, normally, when the power source (power switch) of the liquid crystal display device is ON (when the power source is ON), the power source voltage VDD of the scanning line driving circuit is high level and the power source voltage VSS is low level. The clock signals CK1 to CK3 and the start signal STP repeat high level and low level, and the forced on signal GON is high level. These signals are input from the supply circuit to the scanning line driving circuit.

  When the power supply of the liquid crystal display device is turned off at time t1 (when the power supply is turned off), the forced on signal GON becomes low level, and the clock signals CK1 to CK3 and the start signal STP become high level. When the forced on signal GON becomes low level, the transistors T107 and T108 are turned on (see FIG. 12) in all the stages (stages) of the shift registers SR101 (n), the node n1 becomes high level, and the node n2 Becomes low level, and high level clock signals CK1 to CK3 (clock signal CK1 in FIG. 12) are supplied to the output terminal 114 from the clock terminal 111, so that the output signal OUT becomes high level. As a result, all the scanning lines become high level.

  At time t2, after the node n2 becomes sufficiently low, the clock signals CK1 to CK3 become low. When the clock signals CK1 to CK3 become low level, the bootstrap is activated in all the shift registers SR101 (n), the node n2 becomes LL level (voltage level lower than the low level), and the output signal OUT becomes low level ( Active state). As a result, all the scanning lines become low level.

In this way, all the output signals OUT of the scanning line driving circuit become low level, and all the pixel transistors are turned on. Similarly, each output signal OUT of the signal line driving circuit, that is, each analog switch control signal is all set to low level, each analog switch connected to each signal line is turned ON, and each analog switch is connected to each analog switch. By supplying a Vcom signal to a video signal line (DATA line), the pixel potential becomes the same as the Vcom potential, and a white potential (in the case of normally white) is written to each pixel, so that no afterimage is generated. .
JP 2003-346492 A JP 2002-313093 A

  However, the above-described operation requires a two-stage operation in which the forced on signal GON is set to the low level at time t1, and then the clock signals CK1 to CK3 and the start signal STP are set to the low level at time t2. This is because if the time for writing the low level to the node n2 is not sufficient, the bootstrap does not function and the output signal OUT does not become a sufficiently low level. Furthermore, it is necessary to keep the clock signals CK1 to CK3 at the high level between the times t1 and t2. Since these operations must be performed after the power is turned off, the configuration of the supply circuit becomes complicated. In addition, since the GON circuit 104, that is, the transistors T107 and T108 must be provided on the electrode substrate (inside the panel), the configuration of the drive circuit on the electrode substrate becomes complicated, leading to a decrease in yield and an increase in power consumption. I will.

  The present invention has been made in view of the above, and an object of the present invention is to provide an output signal of a shift register in all stages at the time of power-off with a simple configuration without adding a new transistor on an electrode substrate having a drive circuit. It is to provide a display drive device, a flat display device, and a display drive method that can surely bring the display device into an active state.

  A first feature according to the embodiment of the present invention is that, in the display driving device, provided in a conductive path that electrically connects an output terminal that outputs an output signal and a first voltage electrode that receives a first voltage. Provided in a conductive path that electrically connects the first transistor having the control electrode, the output terminal, and the first clock terminal to which the first clock signal is input, to the input terminal to which the input signal is input. A second transistor having a control electrode electrically connected to a conduction path or a conduction path to a second voltage electrode to which a second voltage is input, and conduction between the control electrode of the second transistor and the input terminal A third transistor having a control electrode provided in a path or a conduction path between the control electrode of the second transistor and the second voltage electrode and electrically connected to the conduction path to the input terminal; Transistor A plurality of shift registers each having a fourth transistor having a control electrode provided in a conduction path electrically connecting the control electrode and the first voltage electrode and electrically connected to the conduction path to the input terminal And supplying a voltage for activating the output signal to the input terminal of the first stage shift register, the first voltage electrode and the first clock terminal of the shift register of all stages in response to power off. A circuit.

  In the first feature according to the embodiment of the present invention, in the shift registers of all stages, the first transistor and the second transistor are stably turned on when the power is turned off. Ensure that the signal is active.

  A second feature according to the embodiment of the present invention is that the flat display device includes the display driving device according to the first feature described above and a display unit driven by the display driving device.

  The second feature according to the embodiment of the present invention exhibits the same operation as the first feature described above.

  A third feature of the embodiment of the present invention is that, in the display driving method, the conductive path is provided to electrically connect the output terminal from which the output signal is output and the first voltage electrode to which the first voltage is input. A first transistor having a control electrode electrically connected to the conductive path connected to the first electrode, and a conductive path electrically connecting the output terminal and the first clock terminal to which the first clock signal is input. A second transistor having a control electrode electrically connected to a conduction path to an input terminal to which an input signal is input or a conduction path to a second voltage electrode to which a second voltage is input; Provided in a conduction path between the control electrode of the second transistor and the input terminal or a conduction path between the control electrode of the second transistor and the second voltage electrode, and is electrically connected to the conduction path to the input terminal. With a control electrode And a fourth transistor having a control electrode that is provided in a conduction path that electrically connects the control electrode of the first transistor and the first voltage electrode, and that is electrically connected to the conduction path to the input terminal The transistors are turned on in response to power-off with respect to the input terminal of the first-stage shift register, the first voltage electrode, and the first clock terminal of all-stage shift registers. Is to supply a voltage.

  The third feature according to the embodiment of the present invention provides the same operation as the first feature described above.

  According to the present invention, the output signals of the shift registers in all stages can be surely made active when the power is turned off with a simple configuration without adding a new transistor to the internal circuit on the electrode substrate.

  The best mode for carrying out the present invention will be described with reference to FIGS. The flat display device according to the embodiment of the present invention is, for example, an active matrix liquid crystal display device.

  As shown in FIG. 1, the flat display device 1 according to the embodiment of the present invention includes a first electrode substrate 4 provided with a display unit 3 having a plurality of pixel electrodes 2, a pixel electrode 2 facing the display unit 3. A second electrode substrate 6 provided with a counter electrode 5 electrically opposed to the first electrode substrate 4, a display layer 8 provided by a sealing material 7 between the first electrode substrate 4 and the second electrode substrate 6, and the like. ing. Here, since the flat display device 1 is a liquid crystal display device, the display layer 8 is a liquid crystal layer made of a liquid crystal material.

  As shown in FIG. 2, the display unit 3 includes a plurality of scanning lines G1, G2 to Gn (collectively referred to as Gn) and a plurality of signal lines S1, S2 to Sm (collectively referred to as Sm). Are provided so as to cross each other. A pixel transistor 9 and a pixel electrode 2 are disposed at each intersection of each scanning line Gn and each signal line Sm. Here, as the pixel transistor 9, for example, a polysilicon thin film transistor is used. The pixel transistor 9 has a gate connected to the scanning line Gn, a source connected to the signal line Sm, and a drain connected to the pixel electrode 2 and an auxiliary capacitor (not shown).

  On the first electrode substrate 4, a scanning line driving circuit 10 and a signal line driving circuit 11 are provided as driving circuits for driving the display unit 3. The display unit 3, the scanning line driving circuit 10, and the signal line driving circuit 11 are integrally formed on the first electrode substrate 4 by the same manufacturing process.

  The scanning line driving circuit 10 includes a vertical shift register 12. The vertical shift register 12 shifts the phase of the vertical start signal STV synchronized with the vertical clock signal CKV by one stage with respect to the scanning line Gn, and outputs the shifted signal as a vertical scanning pulse. The output of the vertical scanning pulse is supplied to the corresponding scanning line Gn.

  The signal line drive circuit 11 includes a horizontal shift register 13, a video signal line 14 to which the video signal DATA is input, and a plurality of analog switches 15 connected to each signal line Sm. The horizontal shift register 13 shifts the phase of the horizontal start signal STH synchronized with the horizontal clock signal CKH by one stage with respect to the signal line Sm, and each shifted analog signal as a horizontal scanning pulse, that is, an analog switch control signal. 15 is output. Each analog switch 15 samples the video signal DATA supplied to the video signal line 14 according to the horizontal scanning pulse and outputs it to the signal line Sm.

  The scanning line driving circuit 10 and the signal line driving circuit 11 are connected to a supply circuit 20 that supplies various signals to them. The supply circuit 20 is provided not on the first electrode substrate 4 or the second electrode substrate 6 but on a printed circuit board (PCB substrate) which is an external substrate thereof. The supply circuit 20 functions as an external circuit, and constitutes the display driving device 20A together with the scanning line driving circuit 10 and the signal line driving circuit 11.

  As shown in FIG. 3, the supply circuit 20 includes a DC / DC converter circuit 21, a power supply switching circuit 22, a timing controller 23, a level shifter 24, and the like.

  The DC / DC converter circuit 21 includes a VDD generation circuit 21a that generates a power supply voltage VDD (first voltage) as a drive power supply and a VSS generation circuit 21b that generates a power supply voltage VSS (second voltage) as a drive power supply. I have. For example, the DC / DC converter circuit 21 generates a power supply voltage VDD of 11.5V from a 3V input voltage by a VDD generation circuit 21a, and further generates a power supply voltage VSS of −5.5V by a VSS generation circuit 21b. The power supply voltage VDD and the power supply voltage VSS are supplied to the vertical shift register 12 and the horizontal shift register 13.

  The power supply switching circuit 22 includes an input voltage monitoring circuit 22a that monitors the input voltage, and two switches SW1 and SW2 that are configured by transistors and the like. The power supply switching circuit 22 is a circuit that monitors the input voltage by the input voltage monitoring circuit 22a and controls on / off of the two switches SW1 and SW2 according to the input voltage. For example, the power supply switching circuit 22 supplies the power supply voltage VDD as it is to the vertical shift register 12 and the horizontal shift register 13 when the input voltage is input (when the power supply is ON), and when the input voltage is cut off (power supply) In the case of OFF), the power supply voltage VSS is supplied to the vertical shift register 12 and the horizontal shift register 13 instead of the power supply voltage VDD.

  The timing controller 23 is a circuit that generates clock signals CK1, CK2, and CK3 (corresponding to CKV or CKH in FIG. 2) and a start signal STP (corresponding to STV or STH in FIG. 2). The timing controller 23 includes an input voltage monitoring circuit 23a that monitors the input voltage. The input voltage monitoring circuit 23a monitors the input voltage and supplies the clock signals CK1 to CK3 and the start signal STP according to the input voltage. It is a circuit to control. For example, the timing controller 23 supplies the clock signals CK1 to CK3 and the start signal STP to the level shifter 24 when the input voltage is input (when the power is ON), and when the input voltage is interrupted (when the power is OFF). ), And a ground signal (GND signal) is supplied to the level shifter 24.

  The level shifter 24 is a circuit that shifts the levels of the clock signals CK1 to CK3 and the start signal STP supplied from the timing controller 23. For example, the level shifter 24 boosts the clock signals CK <b> 1 to CK <b> 3 and the start signal STP from 3 V to 11.5 V when the input voltage is input (when the power is turned on), and outputs the voltage to the vertical shift register 12 and the horizontal shift register 13. Supply. In addition, when the input voltage is cut off (when the power is off), the level shifter 24 applies the voltage of −5.5 V from the VSS generation circuit 21b according to the ground signal from the timing controller 23 and the clock signals CK1 to CK3 and The start signal STP is supplied to the vertical shift register 12 and the horizontal shift register 13.

  Next, the configuration of the vertical shift register 12 and the horizontal shift register 13 will be described. As the vertical shift register 12 and the horizontal shift register 13, for example, a three-phase shift register is used.

  As shown in FIG. 4, the vertical shift register 12 and the horizontal shift register 13 are respectively configured by a plurality of stages of shift registers SR1, SR2-SRn (collectively referred to as SRn) electrically connected in a column. . Here, each of the shift registers SR1, SR2 to SRn corresponds to a first stage (first stage) and a second stage (second stage) to an nth stage (nth stage), respectively.

  The shift register SRn outputs an input line 25 to which the start signal STP or the output signal OUT from the previous shift register SRn is input as an input signal IN, a clock line 26 to which clock signals CK1 to CK3 are input, and an output signal OUT. The output line 27 to be connected is connected. The clock signals CK1 to CK3 are the vertical clock signal CKV in the vertical shift register 12 and the horizontal clock signal CKH in the horizontal shift register 13.

  As shown in FIG. 5, the shift register SRn includes an output circuit 31, an input circuit 32, and a reset circuit 33. The shift register SRn includes a first clock terminal 41 and a second clock terminal 42 to which the clock signals CK1 to CK3 are input, an input terminal 43 to which the input signal IN is input, and an output terminal 44 to which the output signal OUT is output. ing.

  Here, the first clock terminal 41 and the second clock terminal 42 are electrically connected to the clock line 26, the input terminal 43 is also electrically connected to the input line 25, and the output terminal 44 is also an output line. 27 (see FIG. 4). The output circuit 31, the input circuit 32, and the reset circuit 33 are electrically connected to the first voltage electrode 51 to which the power supply voltage VDD (first voltage) is input.

  The output circuit 31, the input circuit 32, and the reset circuit 33 are configured by transistors T1 to T6, respectively. Here, as a transistor, a pMOS transistor is used as an example. The configuration of each shift register SRn is the same. Here, the transistors T1 to T6 are provided in a conductive path (conductive path) that electrically connects two elements such as a terminal and an electrode, and the conductive path is energized based on the potential of the control electrode (gate). It is a switch element to cut off.

  The output circuit 31 includes a first transistor T1 provided in a conductive path between the output terminal 44 and the first voltage electrode 51 and having a control electrode (gate), and between the output terminal 44 and the first clock terminal 41. The second transistor T2 is provided in the conductive path and has a control electrode (gate).

  The source of the transistor T1 is electrically connected to the first voltage electrode 51, and the drain thereof is electrically connected to the output terminal 44. The source of the transistor T2 is electrically connected to the output terminal 44, and the drain thereof is electrically connected to the first clock terminal 41. Here, for example, a clock signal CK1 is input to the n-th first clock terminal 41 as a first clock signal, and a high-level power supply voltage VDD is supplied to the first voltage electrode 51.

  Such an output circuit 31 outputs an output signal OUT through the output terminal 44. When the transistor T1 is on and the transistor T2 is off, the power supply voltage VDD is output from the output terminal 44 as the output signal OUT, and when the transistor T1 is off and the transistor T2 is on, One clock signal (for example, clock signal CK1) is output from the output terminal 44 as the output signal OUT.

  The input circuit 32 includes a third transistor T3 having a control electrode (gate) provided in a conduction path between the control electrode of the transistor T2 and the input terminal 43, and a control electrode of the transistor T1 and the first voltage electrode 51. And a fourth transistor T4 having a control electrode (gate) provided in a conduction path therebetween.

  The source of the transistor T3 is electrically connected to the control electrode of the transistor T2, and the drain and control electrode thereof are electrically connected to the input terminal 43. The source of the transistor T4 is electrically connected to the first voltage electrode 51, the drain thereof is electrically connected to the control electrode of the transistor T1, and the control electrode is electrically connected to the input terminal 43. Has been.

  Such an input circuit 32 receives the input signal IN through the input terminal 43. When the input signal IN is at a high level, the transistors T3 and T4 are off. When the input signal IN is at a low level, the transistors T3 and T4 are on, and the power supply voltage VDD is the first voltage. An input from the electrode 51 is input to the node n1, and an input signal IN is input from the input terminal 43 to the node n2. Note that the conductive path to the control electrode of the transistor T1 is represented as a node n1, and the conductive path to the control electrode of the transistor T2 is represented as a node n2.

  The reset circuit 33 includes a fifth transistor T5 having a control electrode (gate) provided in a conductive path between the control electrode of the transistor T1 and the second clock terminal 42, and the control electrode and the first voltage electrode 51 of the transistor T2. And a sixth transistor T6 having a control electrode (gate) provided in a conductive path between the first and second electrodes.

  The source of the transistor T5 is electrically connected to the control electrode of the transistor T1, and the drain and control electrode thereof are electrically connected to the second clock terminal. The source of the transistor T6 is electrically connected to the first voltage electrode 51, the drain thereof is electrically connected to the control electrode of the transistor T2, and the control electrode is electrically connected to the control electrode of the transistor T1. It is connected to the. Here, for example, the clock signal CK2 is input to the n-th second clock terminal 42 as the second clock signal.

  Such a reset circuit 33 turns on one of the transistor T1 and the transistor T2 and turns off the other in response to a second clock signal (for example, the clock signal CK2). When the second clock signal is at a high level, the transistor T5 is turned off. When the second clock signal is at a low level, the transistor T5 is turned on, and the second clock signal is transferred from the clock terminal 42 to the node n1. The transistor T6 is also turned on, and the power supply voltage VDD is input from the first voltage electrode 51 to the node n2.

  Each shift register SRn shifts the phase of the input signal IN input in synchronization with two clock signals (first clock signal CK1 and second clock signal CK2), and sequentially outputs the shifted output signal OUT. . The vertical shift register 12 outputs the output signal OUT from each shift register SRn to each scanning line Gn as a vertical scanning pulse. On the other hand, the horizontal shift register 13 outputs the output signal OUT from each shift register SRn to each analog switch 15 as a horizontal scanning pulse, that is, an analog switch control signal.

  Here, a start signal STP (corresponding to STV or STH in FIG. 1) is input to the first-stage shift register SR1 as an input signal IN, and the second- to n-th shift registers SR2 to SRn are input. The output signal OUT from the preceding shift register SR is input as the input signal IN.

  Specifically, the start signal STP is input as the input signal IN to the first-stage shift register SR1. In the first-stage shift register SR1, the clock signal CK1 is input to the first clock terminal 41 as the first clock signal, and the clock signal CK2 is input to the second clock terminal 42 as the second clock signal.

  The output signal OUT of the shift register SR1 is input as the input signal IN to the second stage shift register SR2. In the second-stage shift register SR2, the clock signal CK2 is input to the first clock terminal 41 as the first clock signal, and the clock signal CK3 is input to the second clock terminal 42 as the second clock signal.

  The output signal OUT of the shift register SR2 is input as the input signal IN to the third stage shift register SR3. In the third-stage shift register SR3, the clock signal CK3 is input to the first clock terminal 41 as the first clock signal, and the clock signal CK1 is input to the second clock terminal 42 as the second clock signal.

  The clock signals CK1 to CK3 are repeatedly input to the first clock terminal 41 and the second clock terminal 42 of the fourth and subsequent stage shift registers SR in the same manner as the first to third stage shift registers SR.

  Next, the operation of the shift register SRn (operation in the power-on state and operation in the power-off state) will be described. First, the operation of the shift register SRn in the power-on state will be described.

  As shown in FIG. 6, in the power-on state of the flat display device 1 (the power state of the flat display device 1 is ON), the power supply voltage VDD is high level, the power supply voltage VSS is low level, and the clock signals CK1 to CK1. CK3 and the start signal STP repeat high level and low level, and each shift register SRn performs a propagation operation.

  When a low-level input signal IN is input to the input terminal 43 at time T1, the transistor T3 and the transistor T4 are turned on. Since the second clock signal CK2 is at a high level, the transistor T5 is in an off state. The node n1 is supplied with the power supply voltage VDD from the transistor T4 and becomes high level, and the transistor T1 and the transistor T6 are turned off. The low level input signal IN supplied from the transistor T3 causes the node n2 to be in a floating state and to be at a low level. As a result, the transistor T2 is turned on, and the high-level first clock signal CK1 is supplied to the output terminal 44 through the transistor T2, so that the output signal OUT maintains the high level.

  When the potential of the input signal IN is changed from a low level to a high level at time T2, the transistors T3 and T4 are turned off. When the transistor T4 is turned off, the node n1 enters a floating state, but since the transistor T5 is turned off, the high-level potential of the node n1 is held by the parasitic capacitance of the transistor T2. By maintaining the potential of the node n1 at a high level, the transistor T1 and the transistor T6 remain off.

  Further, at time T2, the potential of the input signal IN changes from the low level to the high level, and at the same time, the potential of the first clock signal CK1 is inverted from the high level to the low level. Since the transistor T3 and the transistor T6 are off and in the floating state, the node n2 has a potential (LL level) lower than the low level. This is because there is a parasitic capacitance between the gate and the source of the transistor T2 or between the gate and the drain. Therefore, when the gate, that is, the node n2, is in a floating state, the potential of the node n2 is accompanied by the potential fluctuation between the drain and source of the transistor T2. This is because of fluctuations.

  In this manner, a phenomenon in which the potential of a node in a floating state varies under the influence of potential variation in a connection destination transistor is referred to as a bootstrap, and the node at this time is referred to as a bootstrap node. As a result, the low-level first clock signal CK1 is supplied from the transistor T2 to the output terminal 44, so that the output signal OUT becomes low level. When the node n2 is set to the LL level by the bootstrap, a complete low level voltage is supplied to the output terminal 44. In order to make the bootstrap function reliably, the channel width W of the transistor T2 is preferably set sufficiently larger than the channel widths of the transistors T3 and T6.

  At time T3, when the first clock signal CK1 becomes high level and the potential of the second clock signal CK2 becomes low level, the transistor T5 is turned on. At this time, since the transistor T4 is in an off state, the node n1 is at a low level. As a result, the transistors T1 and T6 are turned on, the node n2 is at a high level, and the transistor T2 is turned off. As a result, the power supply voltage VDD is supplied to the output terminal 44 through the transistor T1, so that the potential of the output signal OUT becomes high level (inactive state).

  After time T3, the input signal IN is fixed at a high level, so that the node n1 is at a low level, the node n2 is at a high level, and the output signal OUT is at a high level regardless of the potential of the first clock signal CK1. Fixed. Thus, the output signal OUT is obtained by shifting the phase of the input signal IN. Here, by setting the channel width W of the transistor T1 sufficiently larger than the channel width of the transistor T5, the influence of the coupling between the gate and the drain of the transistor T5 is reduced, and the node n1 is held at a low level. Can do.

  Next, the operation when the power of the shift register SRn is turned off will be described.

  As shown in FIG. 7, in the power-on state (when the power is on) of the flat display device 1, as described above, the power supply voltage VDD is high level, the power supply voltage VSS is low level, and the clock signals CK <b> 1 to CK <b> 3 and the start are started. The signal STP repeats a high level and a low level, and each shift register SRn performs a propagation operation.

  As shown in FIGS. 7 and 8, when the power switch of the liquid crystal display device is turned off at the time t1 (when the power is off), the clock signals CK1 to CK3, the start signal STP, and the power supply voltage VDD are simultaneously set to the low level voltage (power supply voltage). VSS).

  At this time, in the non-selection stage (non-scanning stage, for example, m stage) immediately before the power is turned off, the power supply voltage VDD and the second clock signal CK2 are at low level, so that the transistor T4 and the transistor T5 are turned off. Due to the bootstrap effect of the transistor T1, the node n1 becomes the LL level. Since the node n1 becomes the LL level, the transistor T1 is turned on, and the output signal OUT becomes a complete low level. Further, since the transistor T6 is turned on, the node n2 is at a low level, and the transistor T2 is turned off because the source, drain, and gate thereof are all at a low level.

  At this time, in the selection stage (scanning stage, for example, n stage) immediately before the power is turned off, the transistor T4 and the transistor T5 are turned on, so that the node n1 is at a low level. Since the transistors T3 and T6 are off, the node n2 maintains the LL level immediately before the power is turned off, and the potential of the output signal OUT maintains the low level (active state).

  Further, at this time, in the stage immediately after the selected stage immediately before the power is turned off (one stage after the scan stage, for example, n + 1 stage), the transistor T4 and the transistor T5 are turned on, so that the node n1 is at the low level. . Since the transistors T3 and T6 are off, as the clock signal CK3 changes from the high level to the low level, the node n2 becomes the LL level due to the bootstrap effect of the transistor T2. As a result, the transistor T2 is turned on, and the low-level first clock signal CK1 is supplied to the output terminal 44 through the transistor T2, so that the potential of the output signal OUT becomes low level (active state).

  In this manner, since the output signal OUT is at the low level in all the stages of the shift registers SRn, all the scanning lines Gn are at the low level. Thereby, all the pixel transistors 9 are turned on. Similarly, each output signal OUT of the signal line driver circuit, that is, the analog switch control signal is all set to the low level, and the Vcom signal is supplied to the video signal line 14 so that the white potential is written to each pixel. Will no longer occur.

  As described above, according to the embodiment of the present invention, the input terminal 43 of the first-stage shift register SR1, the first voltage electrode 51 of the all-stage shift register SRn, and the first clock according to the power-off. By supplying a voltage for activating the output signal OUT to the terminal 41, the node n2 and the node n1 are stably at the LL level when the power is turned off in the shift registers SRn in all stages. T1 and the transistor T2 are stably turned on, and the output signal OUT of the shift registers SRn in all stages is surely set to the low level (active state). Accordingly, the output signals of the shift registers SRn in all stages can be reliably obtained when the power is turned off with a simple configuration without adding a new transistor on the first electrode substrate 4 having the scanning line driving circuit 10 and the signal line driving circuit 11. Can be low level. As a result, the afterimage on the display screen when the power is turned off can be quickly erased.

  Furthermore, since only one step of setting the power supply voltage VDD, the clock signals CK1 to CK3, and the start signal STP to the low level at the same time is required, the configuration of the supply circuit 20 can be simplified. In addition, since it is not necessary to add a GON circuit to the scanning line driving circuit 10 and the signal line driving circuit 11, the configuration of the scanning line driving circuit 10 and the signal line driving circuit 11 is not complicated, and the yield at the time of manufacture is deteriorated. And an increase in power consumption can be prevented.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the transistor T3 is provided in the conduction path between the control electrode of the transistor T2 and the input terminal 43. However, the present invention is not limited to this. For example, as shown in FIG. You may make it provide in the conduction | electrical_connection path between the control electrode of the transistor T2, and the 2nd voltage electrode 52. FIG. In this case, the source of the transistor T3 is electrically connected to the control electrode of the transistor T2, the drain thereof is electrically connected to the second voltage electrode 52, and the control electrode is electrically connected to the input terminal 43. Connected.

  Further, as shown in FIG. 10, the transistor T5 may be provided in a conductive path between the control electrode of the transistor T1 and the second voltage electrode 52. In this case, the source of the transistor T5 is electrically connected to the control electrode of the transistor T1, the drain thereof is electrically connected to the second voltage electrode 52, and the control electrode is connected to the second clock terminal 42. Is electrically connected.

  In addition, in the above-described embodiment, the shift register SRn is configured to use the three-phase clock signals CK1 to CK3 and the six transistors T1 to T6, but is not limited thereto.

  In the shift register SRn as shown in FIG. 11, the reset circuit 33 is provided in a conductive path between the transistor T6 and the control electrode of the transistor T2 and the first voltage electrode 51, and is connected to the second clock terminal 42. A ninth transistor T9 having a control electrode electrically connected thereto.

  This shift register SRn is provided with an inverter circuit 34 for supplying an inverted potential of the node n2 to the node n1. The inverter circuit 34 is provided in a conduction path between the control electrode of the transistor T1 and the first voltage electrode 51, and is a seventh transistor T7 having a control electrode electrically connected to the conduction path to the control electrode of the transistor T2. And an eighth transistor T8 having a control electrode provided in a conductive path between the control electrode of the transistor T1 and the second voltage electrode 52 and electrically connected to a conduction path to the second voltage electrode 52. Has been.

  Such a shift register SRn is characterized in that a low level voltage is always supplied from the inverter circuit 34 to the node n1 when not selected, and there is no period during which the node n1 is floating when not selected. The operation of SRn can be further stabilized. Also in the shift register SRn as shown in FIG. 11, immediately after the power supply is turned off, the power supply voltage VDD, the clock signals CK1 to CK3 and the start signal STP are simultaneously set to the low level, so that the output signal OUT is stably set to the low level. It is possible to obtain the same effect as that of the above-described embodiment.

  Further, in the above-described embodiment, a plurality of shift registers SRn are mounted on both the vertical shift register 12 of the scanning line driving circuit 10 and the horizontal shift register 13 of the signal line driving circuit 11, but the present invention is not limited thereto. For example, it may be configured to be mounted on at least one of the vertical shift register 12 of the scanning line driving circuit 10 and the horizontal shift register 13 of the signal line driving circuit 11.

  In the above-described embodiment, the shift register SRn is configured using only the pMOS transistor. However, the present invention is not limited to this. For example, the shift register SRn is configured using only the nMOS transistor instead of the pMOS transistor. May be. In this case, it is necessary to invert the potential of each signal when a pMOS transistor is used.

  In the above-described embodiment, as an application example of the shift register SRn to the flat display device 1, a liquid crystal layer corresponding to the display layer 8 between the first electrode substrate 4 and the second electrode substrate 6 disposed to face each other. In the flat display device 1 having a structure in which the drive circuit 10 is held, the drive circuits 10 and 11 each having a plurality of shift registers SRn connected in series are arranged on the first electrode substrate 4, but the present invention is not limited to this. Absent. For example, in the flat display device 1 having a structure in which the organic EL corresponding to the display layer 8 is held between the first electrode substrate 4 and the second electrode substrate 6 that are disposed to face each other, the driving circuits 10 and 11 are similarly implemented. A shift register SRn of the form can be used.

It is sectional drawing which shows schematic structure of the flat display apparatus which concerns on one Embodiment of this invention. It is a top view which shows schematic structure of the flat display apparatus shown in FIG. It is a block diagram which shows schematic structure of the supply circuit with which the flat display apparatus shown in FIG.1 and FIG.2 is provided. FIG. 3 is a block diagram illustrating a schematic configuration of a drive circuit included in the flat display device illustrated in FIGS. 1 and 2. FIG. 5 is a circuit diagram illustrating a schematic configuration of a shift register included in the drive circuit illustrated in FIG. 4. 5 is a timing chart of the shift register shown in FIG. 4 in a power-on state. 5 is a timing chart when the power of the shift register shown in FIG. 4 is turned off. FIG. 5 is a schematic diagram showing each voltage when the power of the shift register shown in FIG. 4 is turned off. FIG. 5 is a circuit diagram showing a first modification of the shift register shown in FIG. 4. FIG. 6 is a circuit diagram showing a second modification of the shift register shown in FIG. 4. FIG. 6 is a circuit diagram showing a third modification of the shift register shown in FIG. 4. It is a circuit diagram which shows schematic structure of the conventional shift register. It is a schematic diagram which shows each voltage at the time of the power supply OFF of the shift register shown in FIG. 13 is a timing chart when the power of the shift register shown in FIG. 12 is turned off.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flat display device 3 Display part 10, 11 Drive circuit (scanning line drive circuit, signal line drive circuit)
DESCRIPTION OF SYMBOLS 20 Supply circuit 20A Display drive device 41, 42 Clock terminal 43 Input terminal 44 Output terminal 51 1st voltage electrode 52 2nd voltage electrode CK1-CK3 Clock signal IN Input signal OUT Output signal SRn Shift register T1 1st transistor T2 2nd Transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor VDD first voltage (power supply voltage)
VSS Second voltage (power supply voltage)

Claims (5)

A first transistor having a control electrode provided in a conductive path that electrically connects an output terminal to which an output signal is output and a first voltage electrode to which a first voltage is input, and the output terminal and the first clock Provided in a conductive path that electrically connects a first clock terminal to which a signal is input, and a conductive path to an input terminal to which an input signal is input or a conductive path to a second voltage electrode to which a second voltage is input A second transistor having a control electrode electrically connected to the second transistor, a conduction path between the control electrode of the second transistor and the input terminal, or the control electrode of the second transistor and the second transistor. A third transistor having a control electrode provided in a conduction path between the voltage electrode and electrically connected to the conduction path to the input terminal; the control electrode of the first transistor; and the first power supply. It provided an electrode in a conductive path for electrically connecting a shift register of a plurality of stages and a fourth transistor having electrically control electrode connected to the conduction path to the input terminals, respectively,
A voltage for activating the output signal to the input terminal of the shift register at the first stage, the first voltage electrode and the first clock terminal of the shift register at all stages in response to power off. A supply circuit for supplying,
A display driving device comprising: The plurality of shift registers are:
A conductive path that electrically connects the control electrode of the first transistor and a second clock terminal to which a second clock signal is input, or between the control electrode and the second voltage electrode of the first transistor. A fifth transistor having a control electrode that is provided in the conduction path and electrically connected to the conduction path to the second clock terminal;
A control electrode provided in a conduction path for electrically connecting the control electrode of the second transistor and the first voltage electrode, and electrically connected to a conduction path to the control electrode of the first transistor A sixth transistor having:
Each with
The display driving apparatus according to claim 1, wherein the supply circuit supplies a voltage for making the output signal active to the second clock terminal in response to power-off. The plurality of shift registers are:
A control electrode provided in a conduction path for electrically connecting the control electrode of the second transistor and the first voltage electrode, and electrically connected to a conduction path to the control electrode of the first transistor A sixth transistor having:
A control electrode provided in a conduction path for electrically connecting the control electrode of the first transistor and the first voltage electrode, and electrically connected to a conduction path to the control electrode of the second transistor A seventh transistor having:
An eighth electrode having a control electrode provided in a conductive path electrically connecting the control electrode of the first transistor and the second voltage electrode and electrically connected to a conduction path to the second voltage electrode; Transistors
Each with
The display driving apparatus according to claim 1, wherein the supply circuit supplies a voltage for making the output signal active to the second clock terminal in response to power-off. A display driving device according to any one of claims 1 to 3,
A display unit driven by the display driving device;
A flat display device comprising: A control electrode provided in a conductive path that electrically connects an output terminal from which an output signal is output and a first voltage electrode to which a first voltage is input, and is electrically connected to the conductive path to the first electrode A conductive path electrically connecting the output terminal and the first clock terminal to which the first clock signal is input, and a conduction path to the input terminal to which the input signal is input or A second transistor having a control electrode electrically connected to a conduction path to a second voltage electrode to which a second voltage is input, and conduction between the control electrode and the input terminal of the second transistor; A third transistor having a control electrode provided in a path or a conduction path between the control electrode of the second transistor and the second voltage electrode and electrically connected to the conduction path to the input terminal; The above A fourth transistor having a control electrode provided in a conduction path electrically connecting the control electrode of the first transistor and the first voltage electrode and electrically connected to the conduction path to the input terminal; The transistors are connected to the input terminals of the first-stage shift registers of the plurality of stages of shift registers, the first voltage electrodes and the first clock terminals of the shift registers of all stages according to power off. A display driving method, characterized by supplying a voltage for turning on.

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