KR102135432B1 - Display device - Google Patents

Abstract

The display device includes a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of gate lines, a data driver driving the plurality of data lines, and a gate in response to a mode signal and a gate pulse signal. A clock driver generating a clock signal, a gate driver driving the plurality of gate lines in response to the gate clock signal, and controlling the data driver and the gate driver in response to an image signal and a control signal input from the outside, , A timing controller generating the gate pulse signal and the mode signal, and setting a frequency of the gate pulse signal and a level of the mode signal according to the type of the image signal. The clock generator sets the voltage level of the gate clock signal in response to the mode signal.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a low power consumption display device.

2. Description of the Related Art In general, a display device includes a display panel for displaying an image and a data driver and gate driver for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel includes a switching transistor, a liquid crystal capacitor, and a storage capacitor. The data driver outputs a data driving signal to the data lines, and the gate driver outputs a gate driving signal for driving the gate lines.

The display device may display an image by applying a gate-on voltage to a gate electrode of a switching transistor connected to a gate line to be displayed, and then applying a data voltage corresponding to the display image to a source electrode.

Recently, as the spread of portable electronic devices has been expanded, various methods for reducing power consumption have been sought. In particular, since most of the power consumed in portable electronic devices such as tablet PCs and notebooks are occupied by the display device, efforts to reduce the power of the display device are required.

Accordingly, an object of the present invention is to provide a display device with reduced power consumption.

Another object of the present invention is to provide a display device with reduced power consumption and improved reliability.

According to an aspect of the present invention for achieving the above object, the display device includes: a display panel including a plurality of pixels connected to a plurality of data lines and a plurality of gate lines, and driving the plurality of data lines A data driver, a clock generator generating a gate clock signal in response to a mode signal and a gate pulse signal, a gate driver driving the plurality of gate lines in response to the gate clock signal, and an image signal input from the outside, and Controlling the data driver and the gate driver in response to a control signal, generating the gate pulse signal and the mode signal, and setting the frequency of the gate pulse signal and the level of the mode signal according to the type of the image signal Includes timing controller. The clock generator sets the voltage level of the gate clock signal in response to the mode signal.

In this embodiment, the clock generator generates the gate clock signal swinging between the gate-on voltage and the second ground voltage in response to the gate pulse signal while the mode signal indicates the first mode, and the While the mode signal indicates the second mode, the gate clock signal is generated to swing between the gate-on voltage and the first ground voltage of a voltage level different from the second ground voltage in response to the gate pulse signal.

In this embodiment, the timing controller sets the mode signal to a first signal level corresponding to the first mode when the video signal is a video, and sets the mode signal when the video signal is a still image. Set to a second signal level corresponding to the second mode.

In this embodiment, the timing controller generates the gate pulse signal of a first frequency when the video signal is the video, and a second frequency slower than the first frequency when the video signal is the still image. The gate pulse signal is generated.

In this embodiment, the voltage generator generates the gate-on voltage, the first ground voltage, and the second ground voltage and provides the clock generator.

In this embodiment, the gate driver may include a first gate driver driving first gate lines among the plurality of gate lines, and a second gate driver driving second gate lines among the plurality of gate lines. Includes.

In this embodiment, the timing controller further generates a start pulse signal, and the first gate driver corresponds to the first gate lines, respectively, each of which is the gate clock signal, the previous stage carry signal, and the next stage. A plurality of stages receiving the carry signal, the first ground voltage and the second ground voltage, and providing a gate signal to the carry signal and the corresponding first gate line, and the gate clock signal, the previous stage carry signal, and the And a dummy stage receiving the start pulse signal, the first ground voltage and the second ground voltage, and outputting a dummy carry signal and a dummy gate signal. The first stage of the plurality of stages receives the start pulse signal as the previous stage carry signal. The carry signal from the previous stage is a carry signal output from the previous stage among the plurality of stages, and the carry signal from the next stage is a carry signal output from the next stage among the plurality of stages.

In this embodiment, the clock generator sets the second ground voltage provided to the first gate driver to the first ground voltage level while the mode signal indicates the second mode.

In this embodiment, the clock generator further generates a reset signal. The reset signal is set to a first level while the mode signal indicates the second mode. Each of the plurality of stages in the first gate driver includes a first reset transistor connected between a first output terminal outputting the carry signal and the first ground voltage, and including a gate terminal connected to the reset signal, And a second reset transistor connected between a second output terminal outputting the gate signal and the first ground voltage and including a gate terminal connected to the reset signal.

In this embodiment, the clock generator further generates an inverted gate clock signal complementary to the gate clock signal, the timing controller further generates a start pulse signal, and the second gate driver generates the second gate line. Each corresponding to, and each receives the gate clock signal, the previous stage carry signal, the next stage carry signal, the first ground voltage and the second ground voltage, and the gate signal to the carry signal and the corresponding second gate line A dummy stage receiving a plurality of stages and the gate clock signal, a previous stage carry signal, the start pulse signal, the first ground voltage and the second ground voltage, and outputting a dummy carry signal and a dummy gate signal It includes. The first stage of the plurality of stages receives the start pulse signal as the previous stage carry signal, wherein the previous stage carry signal is a carry signal output from the previous stage among the plurality of stages, and the next stage carry The signal is a carry signal output from the next stage among the plurality of stages.

In this embodiment, the clock generator sets the second ground voltage provided to the second gate driver to the first ground voltage level while the mode signal indicates the second mode.

In this embodiment, the clock generator further generates a reset signal. The reset signal is set to a first level while the mode signal indicates the second mode. Each of the plurality of stages in the first gate driver includes a first reset transistor connected between a first output terminal outputting the carry signal and the first ground voltage, and including a gate terminal connected to the reset signal, And a second reset transistor connected between a second output terminal outputting the gate signal and the first ground voltage and including a gate terminal connected to the reset signal.

In this embodiment, the first gate driver is arranged adjacent to the first short side of the display panel, and the second gate driver is arranged adjacent to the second short side of the display panel.

In this embodiment, the first gate lines and the second gate lines are alternately arranged one by one.

In this embodiment, a plurality of termination resets corresponding to each of the plurality of gate lines, each having a gate terminal connected between an end of the corresponding gate line and the first ground voltage, and connected to an adjacent next gate line Transistors.

In this embodiment, the first ground voltage is -5V, and the second ground voltage is -10V.

According to the present invention, when the still image is displayed, the frequency of the gate clock signal can be lowered to reduce power consumed by the display device. In particular, reliability of the display device may be improved by controlling the gate driver to operate stably even when the frequency of the gate clock signal is lowered.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a view showing the configuration of the first gate driver shown in FIG. 1.
FIG. 3 is a view showing the configuration of the second gate driver shown in FIG. 1.
4 is a diagram illustrating an example of a configuration of a stage in the first gate driver illustrated in FIG. 2.
5 is a view for explaining the operation of some transistors in the stage shown in FIG. 4.
6 is a diagram illustrating input and output signals of the stages illustrated in FIGS. 4 and 5 as an example.
7 is a view for explaining the operation of some of the transistors in the stage shown in FIG. 4.
8 is a diagram illustrating input and output signals of the stages illustrated in FIGS. 4 and 7 as an example.
9 is a view for explaining the operation of some of the transistors in the stage shown in FIG. 4.
10 is a diagram showing input and output signals of the stages illustrated in FIGS. 4 and 9 as an example.
11 is a block diagram showing the configuration of a display device according to another embodiment of the present invention.
12 is a diagram illustrating an example of a configuration of a stage in the first gate driver illustrated in FIG. 11.
13 is a timing diagram exemplarily showing input signals and output signals of a stage in the first gate driver illustrated in FIG. 12.
14 is a diagram illustrating a configuration according to another embodiment of the first gate driver and the second gate driver illustrated in FIG. 1.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device 100 includes a display panel 110, a timing controller 120, a clock generator 130, a voltage generator 140, a data driver 150, a first gate driver 160, and And a second gate driver 170.

The display device 100 includes a liquid crystal display (LCD) device, a plasma panel display (PDP) device, an organic light emitting diode (OLED) display device, and an electric field effect display (Field Emission) Display, FED) device.

The display panel 110 includes a plurality of data lines DL1-DLm and a plurality of gate lines GL1-GLn arranged to cross the data lines DL1-DLm, and a plurality of pixels connected to them ( PX). The plurality of data lines DL1-DLm and the plurality of gate lines GL1-GLn are isolated from each other. Each pixel PX includes a switching transistor connected to corresponding data lines and gate lines, a liquid crystal capacitor and a storage capacitor connected thereto.

The timing controller 120 receives a video signal RGB and control signals CTRL for controlling its display, for example, a vertical sync signal, a horizontal sync signal, a main clock signal, and a data enable signal. . The timing controller 120 processes the data signal DATA and the data driving control signal CONT that process the image signal RGB according to the operating conditions of the display panel 110 based on the control signals CTRL. 150), and the start pulse signal STV is provided to the first gate driver 160 and the second gate driver 170. The data driving control signal CONT may include a horizontal synchronization start signal, a clock signal, and a line latch signal.

The timing controller 120 provides a mode signal (MODE) and a gate pulse signal (CPV) to the clock generator 130. The timing controller 120 stores the image signal RGB in an internal memory (not shown). The timing controller 120 compares the previous image signal PRGB and the image signal RGB stored in the internal memory, and if the previous image signal PRGB and the image signal RGB are different for a predetermined time, the image signal RGB It is determined that it is a video. If the previous image signal PRGB and the image signal RGB match, it is determined that the image signal RGB is a still image. The timing controller 120 operates in the first mode when it is determined that the video signal RGB is a video, and sets the mode signal MODE to a first signal level (for example, a high level). The timing controller 120 operates in the second mode when it is determined that the image signal RGB is a still image, and sets the mode signal MODE to a second signal level (for example, a low level).

The timing controller 120 generates a gate pulse signal CPV having a first frequency (eg, 60 Hz) during the first mode in which the image signal RGB is determined to be a moving image. The timing controller 120 generates a gate pulse signal CPV at a second frequency (eg, 1 Hz) lower than the first frequency during the second mode in which the image signal RGB is determined to be a still image. The timing controller 120 may also change the frequency of the data driving control signal CONT provided to the data driver 150 according to the frequency of the gate pulse signal CPV.

The power consumed by the display device 100 is reduced by lowering the frequency of the gate pulse signal CPV during the second mode in which the image signal RGB is determined to be a still image.

The clock generator 130 generates the gate clock signal CKV and the inverted gate clock signal CKVB in response to the mode signal MODE and the gate pulse signal CPV from the timing controller 120. If the mode signal MODE is a first signal level corresponding to the first mode, the clock generator 130 may switch between the gate-on voltage VON and the second ground voltage VSS2 in response to the gate pulse signal CPV. A swinging gate clock signal CKV and an inverted gate clock signal CKVB are generated. If the mode signal (MODE) is a second signal level corresponding to the second mode, the clock generator 130 responds to the gate pulse signal CPV between the gate-on voltage VON and the first ground voltage VSS1. A swinging gate clock signal CKV and an inverted gate clock signal CKVB are generated.

The voltage generator 140 generates the gate-on voltage VON, the first ground voltage VSS1 and the second ground voltage VSS2 required for the operation of the clock generator 130. For example, the gate-on voltage VON is +15V, the first ground voltage VSS1 is -5V, and the second ground voltage VSS2 is -10V.

The clock generator 130 responds to the mode signal MODE from the timing controller 120 and sets the first ground voltage VSS1 and the second ground voltage VSS2 to the first gate driver 160 and the second gate driver ( 170). If the mode signal MODE is a first signal level corresponding to the first mode, the clock generator 130 removes the first ground voltage VSS1 and the second ground voltage VSS2 from the voltage generator 140 as it is. It is provided as a first gate driver 160 and a second gate driver 170. If the mode signal MODE is a second signal level corresponding to the second mode, the clock generator 130 changes the second ground voltage VSS2 to the same voltage level as the first ground voltage VSS1 and outputs the same. For example, when the mode signal MODE is the second signal level, the clock generator 130 holds both the first ground voltage VSS1 and the second ground voltage VSS2 at -5V.

The data driver 150 outputs gradation voltages for driving the data lines DL1-DLm according to the data signal DATA and the data driving control signal CONT from the timing controller 120.

Each of the first gate driver 160 and the second gate driver 170 is an amorphous silicon gate (ASG) using an amorphous silicon thin film transistor a-Si TFT, an oxide semiconductor, a crystalline semiconductor, and a polycrystalline semiconductor It may be implemented as a circuit using the like and formed on the same substrate as the display panel 110. The first gate driver 160 is arranged adjacent to the first short side of the display panel 110, and the second gate driver 170 is arranged adjacent to the second short side of the display panel 110.

The first gate driver 160 responds to a start pulse signal (STV) from the timing controller 120 and a gate clock signal (CKV) from the clock generator 130 to control the number of gate lines GL1-GLn. 1 Drive the gate lines GL1, GL3, ..., GLn-1. The first gate lines GL1, GL3, ..., GLn-1 are odd-numbered gate lines among the plurality of gate lines GL1-GLn.

The second gate driver 170 is one of the plurality of gate lines GL1-GLn in response to the start pulse signal STV from the timing controller 120 and the inverted gate clock signal CKVB from the clock generator 130. The second gate lines GL2, GL4, ..., GLn are driven. The second gate lines GL2, GL2, ..., GLn are even gate lines of the plurality of gate lines GL1-GLn.

FIG. 2 is a view showing the configuration of the first gate driver shown in FIG. 1.

Referring to FIG. 2, the first gate driver 160 includes a plurality of stages ST1 to STn-1 and a dummy stage STn+1. The plurality of stages ST1 to STn-1 respectively correspond to the first gate lines GL1 to GLn-1, which are odd-numbered gate lines. The first stage ST1 among the plurality of stages ST1 to STn-1 includes a start pulse signal STV, a gate clock signal CKV, a first ground voltage VSS1, a second ground voltage VSS2, and the following. However, the carry signal CR3 is received, and the carry signal CR1 and the gate signal G1 are output.

Each of the remaining stages STi (where i=3, 5, ..., n-1) other than the first stage ST1 among the plurality of stages ST1 to STn-1 is a previous carry signal ( CRi-2), gate clock signal CKV, first ground voltage VSS1, second ground voltage VSS2, and next carry signal CRi+2, and carry signal CRi and gate signal ( Gi).

The dummy stage STn+1 receives the previous stage carry signal CRn-2, the gate clock signal CKV, the first ground voltage VSS1, the second ground voltage VSS2, and the start pulse signal STV. , Carry signal CRn+1 and gate signal GDn+1 are output.

FIG. 3 is a view showing the configuration of the second gate driver shown in FIG. 1.

Referring to FIG. 3, the second gate driver 170 includes a plurality of stages ST2 to STn and a dummy stage STn+2. The plurality of stages ST2 to STn respectively correspond to the second gate lines GL2 to GLn, which are even-numbered gate lines. The first stage ST2 among the plurality of stages ST2 to STn includes a start pulse signal STV, an inverted gate clock signal CKVB, a first ground voltage VSS1, a second ground voltage VSS2, and a next stage The carry signal CR4 is received, and the carry signal CR2 and the gate signal G2 are output.

Among the plurality of stages ST2 to STn, except for the first stage ST2, each of the stages STi (where i=4, 6, ..., n) is a previous carry signal CRi-2 , Receives the inverted gate clock signal CKVB, the first ground voltage VSS1, the second ground voltage VSS2 and the next carry signal CRi+2, and receives the carry signal CRi and the gate signal Gi. Output.

The dummy stage STn+2 receives the previous stage carry signal CRn-2, the inverted gate clock signal CKVB, the first ground voltage VSS1, the second ground voltage VSS2, and the start pulse signal STV. Then, carry signal CRn+2 is output.

4 is a diagram illustrating an example of a configuration of a stage in the first gate driver illustrated in FIG. 2. Although only the stages in the first gate driver are illustrated and described, the stages in the second gate driver also have the same configuration as the stages in the first gate driver shown in FIG. 4. However, each of the stages in the first gate driver receives a gate clock signal, and each of the stages in the second gate driver receives an inverted gate clock signal.

Referring to FIG. 4, the i-th stage STi includes transistors T1 to T15 and a capacitor C1. The i-th stage STi includes the previous stage carry signal CRi-2, the gate clock signal CKV, the first ground voltage VSS1, the second ground voltage VSS2, and the next stage carry signal CRi+2. It receives and outputs a carry signal CRi and a gate signal Gi.

When the previous stage carry signal CRi-2 transitions to the high level, the transistor T4 is turned on, and the voltage level of the node Q rises. At this time, when the gate clock signal CKV transitions to a high level, the transistor T1 is turned on and the gate clock signal CKV is output as the gate signal Gi. In addition, the voltage level of the node Q is boosted to a higher level by the capacitor C1, so that the first transistor T1 remains turned on.

As the voltage level of the node Q rises, and the gate clock signal CKV transitions to a high level, the transistor T15 is turned on, and the carry signal CRi is output at a high level.

When the next carry signal CRi+2 output from the next stage STi+2 is activated at a high level in response to the carry signal CRi, the transistors T9, T9-1, T2, and T17 are turned on. When the transistors T9 and T9-1 are turned on, the node Q is discharged to the second ground voltage VSS2. When the transistor T2 is turned on, the output terminal from which the gate signal Gi is output is discharged to the first ground voltage VSS1. When the transistor T17 is turned on, the output terminal to which the carry signal CRi is output is discharged to the second ground voltage VSS2.

5 is a view for explaining the operation of some transistors in the stage shown in FIG. 4. 6 is a diagram illustrating input and output signals of the stages illustrated in FIGS. 4 and 5 as an example.

4, 5 and 6, the gate clock signal CKV swings between the gate-on voltage VON and the second ground voltage VSS2, and the first ground voltage VSS1 is -5V, It is assumed that the second ground voltage VSS2 is -10V.

As described above, the timing controller 120 (shown in FIG. 1) outputs a mode signal MODE at a second signal level when the image signal RGB is a still image, and a gate pulse signal compared to when the image signal RGB is a first mode. Lower the frequency of (CPV). When the frequency of the gate pulse signal CPV is lowered in the second mode, the frequency of the gate clock signal CKV generated by the clock generator 130 (shown in FIG. 1) is also lowered. During the second mode, the gate clock signal CKV has a longer time to be maintained at the second ground voltage VSS2 than the first mode. The gate clock signal CKV, the Q node signal QN, and the next carry signal CRi+2 provided to the drain terminal of the transistor T1 are the second ground voltage VSS2, and the gate line GLi is While not being driven, the gate signal Gi is at the first ground voltage VSS1 level. The transistors T1 and T2 remain turned off while the gate line GLi is not driven, but the voltage (-10V) applied to the gate terminal of each of the transistors T1 and T2 is applied to the source terminal. Due to the difference between the voltages (-5V), the transistors T1 and T2 are biased. When the second mode is maintained for a long time and repeatedly, a change in threshold voltage of the transistors T1 and T2 may occur or damage may occur. This is a factor that deteriorates the reliability of the display device 100.

7 is a view for explaining the operation of some of the transistors in the stage shown in FIG. 4. 8 is a diagram illustrating input and output signals of the stages illustrated in FIGS. 4 and 7 as an example.

4, 7 and 8, the timing controller 120 (shown in FIG. 1) outputs a mode signal MODE of the second signal level when the image signal RGB is a still image, and the first Lower the frequency of the gate pulse signal (CPV) compared to the mode.

The clock generator 130 (shown in FIG. 1) swings between the gate-on voltage VON and the first ground voltage VSS1 in response to the second signal level mode signal MODE and the gate pulse signal CPV. The gate clock signal CKV is generated. Also, the clock generator 130 outputs the second ground voltage VSS2 at the same voltage (-5V) as the first ground voltage VSS1. Therefore, the gate clock signal CKV provided to the drain terminal of the transistor T1, the signal QN of the Q node, and the next carry signal CRi+2, the carry signal CRi, and the gate signal Gi are all It is the first ground voltage VSS1 level.

The transistors T1 and T2 remain turned off while the gate line GLi is not driven. When the transistors T1-T15 in the stage STi are formed of an amorphous silicon gate (ASG) or an oxide semiconductor, leakage current Ids flows when Vgs=0V. When a little leakage current Ids flows through the transistor T2, the gate signal Gi is held by the first ground voltage VSS1, thereby minimizing the influence of the gate signal Gi due to noise. .

9 is a view for explaining the operation of some of the transistors in the stage shown in FIG. 4. 10 is a diagram showing input and output signals of the stages illustrated in FIGS. 4 and 9 as an example.

4, 9 and 10, the timing controller 120 (shown in FIG. 1) outputs a mode signal MODE at a second signal level when the image signal RGB is a still image, and the first Lower the frequency of the gate pulse signal (CPV) compared to the mode.

The clock generator 130 (shown in FIG. 1) swings between the gate-on voltage VON and the second ground voltage VSS2 in response to the mode signal MODE and the gate pulse signal CPV of the second signal level. The gate clock signal CKV is generated. Also, the clock generator 130 outputs the first ground voltage VSS1 at the same voltage (-10V) as the second ground voltage VSS2. Therefore, the gate clock signal CKV provided to the drain terminal of the transistor T1, the signal QN of the Q node, and the next carry signal CRi+2, the carry signal CRi, and the gate signal Gi are all It is the second ground voltage VSS2 level.

The transistors T1 and T2 remain turned off while the gate line GLi is not driven. When the transistors T1-T15 in the stage STi are formed of an amorphous silicon gate (ASG) or an oxide semiconductor, leakage current Ids flows when Vgs=0V. When a little leakage current Ids flows through the transistor T2, the gate signal Gi is held by the first ground voltage VSS1, thereby minimizing the influence of the gate signal Gi due to noise. .

7 to 10, the gate clock signal CKV, the signal QN of the Q node, and the next-stage carry signal CRi+2, the carry signal CRi, and the gate signal Gi are all removed. It is possible to prevent damage to the transistors T1 to T15 in the stage STi (shown in FIG. 4) by making the same as one of the first ground voltage VSS1 and the second ground voltage VSS2, and the gate signal due to noise ( Gi) can be minimized.

11 is a block diagram showing the configuration of a display device according to another embodiment of the present invention.

The display device 200 illustrated in FIG. 11 has a configuration similar to that of the display device illustrated in FIG. 1, but the clock generator 230 further generates a reset signal RST. The clock generator 230 generates a reset signal RST, which is a pulse signal that is periodically activated while the mode signal MODE from the timing controller 220 is the second signal level. The reset signal RST is provided to the first gate driver 260 and the second gate driver 270. Instead of the clock generator 230 generating a reset signal RST, in another embodiment, the timing controller 220 may generate a reset signal RST.

12 is a diagram illustrating an example of a configuration of a stage in the first gate driver illustrated in FIG. 11. 13 is a timing diagram exemplarily showing an input signal and an output signal of a stage in the first gate driver illustrated in FIG. 12.

The stage SSTi shown in FIG. 12 has the same configuration as the stage STi shown in FIG. 4, but further includes reset transistors RT1, RT2, and RT3. Among the components in the stage SSTi illustrated in FIG. 12, a duplicate description of the same components as the stage STi illustrated in FIG. 4 will be omitted.

12 and 13, the reset transistor RT1 includes a gate terminal connected between the gate terminal of the transistor T15 and the first ground voltage VSS1 and controlled by the reset signal RST. The reset transistor RT2 is connected between the output terminal of the carry signal CRi and the first ground voltage VSS1, and includes a gate terminal controlled by the reset signal RST. The reset transistor RT3 is connected between the output terminal of the gate signal Gi and the first ground voltage VSS1, and includes a gate terminal controlled by the reset signal RST.

The reset signal RST is periodically activated during the second mode in which the mode signal MODE is the second signal level. When the reset signal RST is activated to a high level (eg, a gate-on voltage VON level), all of the reset transistors RT1, RT2, and RT3 are turned on. Therefore, the gate terminal of the transistor T15, the output terminal of the carry signal CRi, and the output terminal of the gate signal Gi are set to the first ground voltage VSS1. As the time for which the carry signal CRi and the gate signal Gi are maintained at the first ground voltage VSS1 during the second mode increases, the carry signal CRi and the gate signal Gi may be changed due to noise. . As the reset transistors RT1, RT2, and RT3 are periodically turned on, a malfunction of the display device 100 may be prevented by holding the carry signal CRi and the gate signal Gi with the first ground voltage VSS1. have. Therefore, the reliability of the display device 100 is improved.

14 is a diagram illustrating a configuration according to another embodiment of the first gate driver and the second gate driver illustrated in FIG. 1.

Referring to FIG. 14, the first gate driver 160 includes a plurality of stages ST1 to STn-1, a dummy stage STn+1, and termination reset transistors NT2 to NTn. The second gate driver 170 includes a plurality of stages ST2 to STn, a dummy stage STn+2, and termination reset transistors NT1 to NTn-1.

Since the connection relationship of the plurality of stages ST1 to STn-1 and the dummy stage STn+1 in the first gate driver 160 is the same as illustrated in FIG. 2, a duplicate description is omitted. In addition, since the connection relationship between the plurality of stages ST2 to STn and the dummy stage STn+2 in the second gate driver 170 is the same as that shown in FIG. 3, a redundant description is omitted.

The termination reset transistors NT2 to NTn in the first gate driver 160 respectively correspond to the second gate lines GL2 to GLn, and the termination reset transistors NT1 to NTn- in the second gate driver 170, respectively. 1) respectively correspond to the first gate lines GL1 to GLn-1. The termination reset transistors NT1 to NTn discharge the corresponding gate line to the first ground voltage VSS1.

For example, the termination reset transistor NT1 includes a gate terminal connected between the corresponding first gate line GL1 and the first ground voltage VSS1 and connected to the next adjacent second gate line GL2. The termination reset transistor NT2 includes a gate terminal connected between the corresponding second gate line GL2 and the first ground voltage VSS1 and connected to the next adjacent first gate line GL3.

The termination reset transistors NT1 to NTn discharge the corresponding gate line as the first ground voltage VSS1 when the next gate line is driven with the gate-on voltage. The termination reset transistors NT1 to NTn may improve the discharge rate when the gate signals G1 to Gn are discharged from the gate-on voltage VON to the first ground voltage VSS1.

Although described with reference to the above embodiments, those skilled in the art understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Will be able to. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical spirit within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention. .

100: display device 110: display panel
120 timing controller 130: clock generator
140: voltage generator 150: data driver
160: first gate driver 170: second gate driver
ST1~STn: Stage STn+1, STn+2: Dummy stage

Claims (16)

A display panel including a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, respectively;
A data driver driving the plurality of data lines;
A clock generator which generates a gate clock signal in response to the mode signal and the gate pulse signal;
A gate driver driving the plurality of gate lines in response to the gate clock signal; And
The data driver and the gate driver are controlled in response to an image signal and a control signal input from the outside, and the gate pulse signal and the mode signal are generated. Includes a timing controller to set the level of the mode signal,
The clock generator,
While the mode signal indicates the first mode, generate the gate clock signal swinging between the gate-on voltage and the second ground voltage in response to the gate pulse signal,
A display device for generating the gate clock signal swinging between the gate-on voltage and the first ground voltage of a voltage level different from the second ground voltage in response to the gate pulse signal while the mode signal indicates the second mode. . delete According to claim 1,
The timing controller,
When the video signal is a video, the mode signal is set to a first signal level corresponding to the first mode, and when the video signal is a still image, the mode signal is set to a second signal level corresponding to the second mode. Display device characterized in that it is set. The method of claim 3,
The timing controller,
Generating the gate pulse signal at a first frequency when the image signal is the video, and generating the gate pulse signal at a second frequency slower than the first frequency when the image signal is the still image. Display device. According to claim 1,
And a voltage generator generating the gate-on voltage, the first ground voltage, and the second ground voltage and providing them to the clock generator. The method of claim 5,
The gate driver,
A first gate driver driving first gate lines among the plurality of gate lines; And
And a second gate driver driving second gate lines among the plurality of gate lines. The method of claim 6,
The timing controller further generates a start pulse signal,
The first gate driver,
Each corresponding to the first gate lines, each receiving the gate clock signal, the previous stage carry signal, the next stage carry signal, the first ground voltage and the second ground voltage, and the carry signal and the corresponding first A plurality of stages providing a gate signal to the gate line; And
And a dummy stage receiving the gate clock signal, the previous stage carry signal, the start pulse signal, the first ground voltage and the second ground voltage, and outputting a dummy carry signal and a dummy gate signal.
The first of the plurality of stages receives the start pulse signal as the previous carry signal,
The previous carry signal is a carry signal output from a previous stage of the plurality of stages, and the next carry signal is a carry signal output from a next stage of the plurality of stages. The method of claim 7,
The clock generator,
And setting the second ground voltage provided to the first gate driver to the first ground voltage level while the mode signal indicates the second mode. The method of claim 7,
The clock generator further generates a reset signal,
Set the reset signal to a first level while the mode signal indicates the second mode,
Each of the plurality of stages in the first gate driver,
A first reset transistor connected between a first output terminal outputting the carry signal and the first ground voltage and including a gate terminal connected to the reset signal; And
And a second reset transistor connected between a second output terminal outputting the gate signal and the first ground voltage and including a gate terminal connected to the reset signal. The method of claim 6,
The clock generator further generates an inverted gate clock signal complementary to the gate clock signal,
The timing controller further generates a start pulse signal,
The second gate driver,
Each corresponding to the second gate lines, each receiving the gate clock signal, the previous carry signal, the next carry signal, the first ground voltage and the second ground voltage, and the carry signal and the corresponding second A plurality of stages providing a gate signal to the gate line; And
And a dummy stage receiving the gate clock signal, the previous stage carry signal, the start pulse signal, the first ground voltage and the second ground voltage, and outputting a dummy carry signal and a dummy gate signal.
The first of the plurality of stages receives the start pulse signal as the previous carry signal,
The previous carry signal is a carry signal output from a previous stage of the plurality of stages, and the next carry signal is a carry signal output from a next stage of the plurality of stages. The method of claim 10,
The clock generator,
And setting the second ground voltage provided to the second gate driver to the first ground voltage level while the mode signal indicates the second mode. The method of claim 10,
The clock generator further generates a reset signal,
Set the reset signal to a first level while the mode signal indicates the second mode,
Each of the plurality of stages in the first gate driver,
A first reset transistor connected between a first output terminal outputting the carry signal and the first ground voltage and including a gate terminal connected to the reset signal; And
And a second reset transistor connected between a second output terminal outputting the gate signal and the first ground voltage and including a gate terminal connected to the reset signal. The method of claim 6,
The first gate driver is arranged adjacent to the first short side of the display panel, and the second gate driver is arranged adjacent to the second short side of the display panel. The method of claim 6,
The display device of claim 1, wherein the first gate lines and the second gate lines are alternately arranged one by one. According to claim 1,
And further comprising a plurality of termination reset transistors corresponding to each of the plurality of gate lines, each connected between the termination of the corresponding gate line and the first ground voltage, and having a gate terminal connected to an adjacent next gate line. Display device characterized by. According to claim 1,
The first ground voltage is -5V, and the second ground voltage is -10V.

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