KR20120063677A

KR20120063677A - Electrophoretic display device and method for operating the same

Info

Publication number: KR20120063677A
Application number: KR1020100124751A
Authority: KR
Inventors: 오충완; 정대성
Original assignee: 엘지디스플레이 주식회사
Priority date: 2010-12-08
Filing date: 2010-12-08
Publication date: 2012-06-18

Abstract

PURPOSE: An electrophoretic image display device and a driving method thereof are provided to prevent degradation of a gate driving unit by maintaining potential of a Qb node at a low level. CONSTITUTION: An electrophoretic display panel comprises pixel cells. A data driving unit provides a data signal to a data line. A gate driving unit is comprised of a plurality of stages. The plurality of stages supplies a gate output signal of a high level to a gate line. A timing controller provides a clock signal to the gate driving unit. The timing controller maintains the clock signal and driving voltage at a low level. A pull-up transistor driving unit(510) controls potential of a Q node. A pull-down transistor driving unit(520) controls potential of a Qb node. A gate signal output unit(530) comprises a seventh transistor(T7) and an eighth transistor(T8).

Description

Electrophoretic Display Device and Method for Operating The Same}

The present invention relates to a flat panel display, and more particularly to an electrophoretic display.

The electrophoretic display device refers to a device for displaying an image by using electrophoretic phenomenon in which colored charged particles move by an electric field applied from the outside. The electrophoretic display is particularly suitable for the field of e-book which does not require the rapid replacement of the screen because it can maintain a constant screen for a long time even without applying a constant voltage.

In addition, unlike the liquid crystal display device, the electrophoretic display device does not have a dependency on a viewing angle and has an advantage of providing an image that is comfortable to the eye to the extent that it is similar to paper.

The electrophoretic display includes a display panel in which pixels are arranged in a matrix, a gate driver and a data driver for driving the display panel. In the lower array of the display panel, gate lines and data lines are arranged to cross each other, and thin film transistors (TFTs) and pixel cells are formed in each of the crossing regions.

In addition, a common electrode is formed on the upper array of the display panel, and a plurality of microcapsules are sandwiched between the upper array and the lower array of the display panel.

The above-mentioned electrophoretic display maintains the state of the charged particles divided by the previous last supplied data unless new data is input, and as a result, the still image is naturally realized, so that once the desired image is After this implementation, it is no longer necessary to drive the drives normally in maintaining this state. That is, the electrophoretic display drives the driving units idle in the still image state.

The deterioration problem of the gate driver is serious in the electrophoretic display device in which the drivers are idle-driven in the still image state. Hereinafter, the deterioration problem of the gate driver will be described in detail.

First, the gate driver includes a shift register composed of a plurality of stages for sequentially generating gate output signals to be supplied to respective gate lines. At this time, the stages are dependently connected to each other and sequentially generate an output signal Vout by shifting the gate start signal Vst in response to control signals such as a clock signal applied from the outside in a normal driving state.

In a typical electrophoretic display, the potential of the Q node, which is a node connected to the gate terminal of a pull-up transistor located at the output terminal of each stage and activating the output of the stage, has a high voltage in two stages near the point of occurrence of the output signal Vout. After rising to the high level, the voltage is maintained at the low level in synchronization with the end of generation of the output signal Vout.

The potential of the Qb node, which is a node that is connected to the gate terminal of the pull-down transistor located at the output terminal of each stage and deactivates the output of the stage, drops to a low level when the Q node rises to the high level in one stage, and then the output signal In synchronism with the end of generation of Vout, the signal is held at a high level. By the way, the potential of the Qb node is changed to a low level once in one frame when the gate driver is normally driven, but is kept only at a high level when the gate driver is idle.

That is, the potential of the Qb node is maintained at a high level throughout the period in which the still picture is maintained. However, since the still picture state may last for several minutes to several hours, if the potential of the Qb node is maintained at a high level for a long time, gate bias stress is accumulated at the gate terminals of the transistors connected to the Qb node.

Accumulated gate bias stress increases the threshold voltages of the transistors and decreases the mobility, thereby degrading the operation characteristics of the gate driver. When the gate driver degrades, it is impossible to realize good image quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide an electrophoretic display device and a driving method thereof capable of preventing deterioration of a gate driver.

In addition to the aspects of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

In addition, other features and advantages of the present invention may be newly understood through practice of the present invention.

According to an aspect of the present invention, there is provided an electrophoretic display device including: an electrophoretic display panel in which pixel cells are arranged for each pixel region defined by an intersection of a plurality of gate lines and a plurality of data lines; A data driver supplying a data signal to the data line; At least one high potential DC voltage having a high level and a plurality of stages sequentially supplying a gate output signal of a high level to the gate line sequentially shifted according to a clock signal in which the high level and the low level are periodically inverted. A gate driver configured; And generating the clock signal and supplying the clock signal to the gate driver, and maintaining the clock signal and the driving voltage at a low level for a predetermined time when the gate output signal of the high level is supplied to the last gate line of the plurality of gate lines. It characterized in that it comprises a timing control unit.

According to another aspect of the present invention, there is provided a method of driving an electrophoretic display, including: a gate start signal, at least one clock signal at which a high level and a low level are periodically inverted, and at least one having a high level Generating a high potential DC voltage; Generating a high level gate output signal sequentially shifted according to the gate start signal, the at least one clock signal, and the at least one high potential DC voltage, and supplying the gate output signal to a plurality of gate lines; And when the gate output signal having the high level is supplied to the last gate line of the plurality of gate lines, maintaining the clock signal and the high potential DC voltage at a low level for a predetermined time.

According to the present invention, when the gate output signal is input to the last gate line, all control signals input to the gate driver are kept at a low level so that the potential of the Qb node is kept at a low level when the gate driver is idle. There is an effect that can prevent deterioration.

In addition, the present invention has the effect of improving the image quality of the electrophoretic display by preventing the deterioration of the gate driver.

1 is a view showing the configuration of an electrophoretic display device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a gate driver illustrated in FIG. 1.
FIG. 3 is a timing diagram for describing an operation of the gate driver illustrated in FIG. 2.
4 is a diagram showing the circuit configuration of the stage shown in FIG.
FIG. 5 is a timing diagram for explaining the operation of the stage shown in FIG. 4; FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In describing embodiments of the present invention, when a structure is described as being formed "on" or "below" another structure, this description is intended to provide a third term between these structures as well as when the structures are in contact with each other. It is to be interpreted as including even if the structure is interposed. However, where the term "immediately above" or "immediately below" is used, it is to be construed that these structures are limited to being in contact with each other.

1 is a view showing the configuration of an electrophoretic display device according to an embodiment of the present invention. As shown in FIG. 1, an electrophoretic display device according to an exemplary embodiment of the present invention includes an electrophoretic display panel 200, a data driver 210, a gate driver 220, a common voltage supply unit 230, and a power supply unit. 240, and a timing controller 250.

First, m_n (m, n is a positive integer) pixel cells 202 are arranged in the electrophoretic display panel 200. The pixel cells 202 are defined by m data lines D1 through Dm and n gate lines G1 through Gn arranged to cross each other on a lower substrate of the electrophoretic display panel 200. .

Thin film transistors (TFTs) are connected to intersections of the data lines D1 to Dm and the gate lines G1 to Gn. The gate electrodes of the TFTs are connected to the gate lines G1 to Gn, the source electrodes are connected to the data lines D1 to Dm, and the drain electrodes are connected to the pixel electrodes 203 of the pixel cells 202. The TFTs turn on in response to the gate output signals supplied through the gate lines G1 to Gn to select pixel cells 202 of one horizontal line to be displayed.

Meanwhile, a common electrode 204 for supplying a common voltage Vcom to all the pixel cells 202 is formed on the upper substrate of the electrophoretic display panel 200, and a plurality of microcapsules are disposed between the upper substrate and the lower substrate. Are interposed. Each of the microcapsules includes negatively charged (+) white particles and positively (+) negative black particles.

Next, the data driver 210 supplies a data signal to the data lines D1 to Dm of the electrophoretic display panel 200, and the gate driver 220 is a gate line of the electrophoretic display panel 200. Gate output signals to the gates G1 to Gn, and the common voltage supply unit 230 supplies a common voltage Vcom to the common electrode 204 of the electrophoretic display panel 200.

Specifically, the data driver 210 includes a plurality of integrated circuits each including a shift register, a latch, a decoder, a level shifter, and the like. The data driver 210 latches the digital data Data under the control of the timing controller 250 and converts the digital data Data into a data signal having an appropriate size through a decoder and a level shifter, thereby converting the data lines D1 through D1 through the data driver 210. To Dn).

The gate driver 220 sequentially generates gate output signals synchronized with data signals supplied to the data lines D1 to Dm and supplies the gate lines G1 to Gn under the control of the timing controller 250. The gate driver 220 includes a shift register having n stages ST1 to STn connected to each other, and the gate output signals are sequentially generated with delayed phases through the shift register.

In an embodiment, the shift register may be formed on the non-display area of the electrophoretic display panel 200 through the same process as the TFTs in the pixel cells 202 in a gate in panel (GIP) manner.

Hereinafter, the configuration of the gate driver 220 will be briefly described with reference to FIG. 2.

FIG. 2 is a diagram illustrating a configuration of a gate driver illustrated in FIG. 1. As shown in FIG. 2, the gate start signal Vst is input as a start signal to the first stage ST1 constituting the shifter register, and the previous stage is used as the start signal to the second to nth stages ST2 to STn. Output signals Vout are respectively input.

Each of the stages ST1 to STn operates in response to the clock signal CLK or CLKB, so that the gate output signals VOUT1 to VOUTn have a width corresponding to the duty of the clock signal and are shifted in phase by one horizontal period 1H. Generates.

In one embodiment, the clock signal CLK may be input to an odd stage and the clock signal CLKB may be input to an even stage.

Meanwhile, as illustrated in FIG. 3, the gate driver 220 according to an embodiment of the present invention supplies a high level gate output signal Voutn to the last gate line Gn for a predetermined time Δt. In response to the low level clock signals CLK and CLKB input under the control of the timing controller 250 and the first and second high potential DC voltages V _DD and V _DD1 of the low level, the disc may be dis- played in the still picture state. By discharging the enable node, deterioration of the switches connected to the disable node is prevented.

According to an embodiment, the predetermined time Δt may be a period from when the high level gate output signal is applied from the gate driver 220 to the last gate line Gn until a time when a new data signal is input. .

Next, the power supply 240 controls the gate driver 220 under the control of the timing controller 250, and the first and second high potential DC voltages V _DD having a low potential voltage V _SS and a high or low level. , V _DD1 ).

In detail, the power supply unit 240 supplies the first and second high potential DC voltages V _DD and V _DD1 having high levels to the gate driver 220, and then the first control signal is input from the timing controller 250. 3, the potentials of the first and second high potential DC voltages V _DD and V _DD1 are lowered to a low level for a predetermined time Δt and supplied to the gate driver 220.

Subsequently, after a predetermined time Δt elapses, the power supply unit 240 supplies the potentials of the first and second high potential DC voltages V _DD and V _DD1 when a second control signal is input from the timing controller 250. The voltage is raised to a high level and supplied to the gate driver 220.

As such, in the case of the present invention, the reason why the power supply 240 supplies the first and second high potential DC voltages V _DD and V _DD1 of the low level to the gate driver 220 for a predetermined time Δt is as follows. This is to prevent deterioration of the gate driver 220.

Next, the timing controller 250 is used to control the data driver 210, the gate driver 220, and the power supply 240, and the vertical / horizontal synchronization signals V and H from a system (not shown). And a data control signal DDC for controlling the operation timing of the data driver 210 by receiving the clock signal CLK, a gate control signal GDC for controlling the operation timing of the gate driver 220, and a power supply. First and second control signals are generated to change the level of the output voltage of the supply unit 240.

The gate control signal GDC includes a gate start signal Vst, gate shift clock signals CLK and CLKB, and a gate output enable signal. The data control signal DDC includes a source start signal and a source shift clock signal. Source output enable signal and the like.

In an exemplary embodiment, the timing controller 250 may generate a clock signal CLK input to an odd stage and a clock signal CLKB input to an even stage. The clock signals CLKB have opposite phases.

In particular, the timing controller 250 according to the present invention, as described above, to prevent deterioration of the gate driver 220, as shown in FIG. 3, from the gate driver 220 to the last gate line Gn. After the high level gate output signal Voutn is applied, the clock signals CLK and CLKB, which are maintained at the low level for a predetermined time Δt, are generated and supplied to the gate driver 220, and during the predetermined time Δt. First and second control signals for generating the first and second high potential DC voltages V _DD and V _DD1 to be maintained at a low level are generated and supplied to the power supply 250.

Hereinafter, the configuration and operation of the stage illustrated in FIG. 2 will be described in detail with reference to FIGS. 4 and 5.

4 is a circuit diagram illustrating a circuit configuration of a first stage among the plurality of stages illustrated in FIG. 2, and FIG. 5 is a timing diagram illustrating timings of control signals and driving voltages applied to the first stage.

4 and 5, the first stage ST1 includes a pull-up transistor driver 510, a pull-down transistor driver 520, and a gate signal output unit 530. In the following description, a Q node means a control node for generating a high level gate output signal, and a Qb node means a control node for generating a low level gate output signal.

First, the pull-up transistor driver 510 controls the potential VQ of the Q node according to the gate start signal Vst, the gate output signal Vout2 of the next stage ST2, and the potential VQb of the Qb node. .

In detail, the pull-up transistor driver 510 includes a first transistor T1, a second transistor T2, and a third transistor T3 to control the potential VQ of the Q node. The gate terminal of the first transistor T1 is connected to the input terminal of the gate start signal Vst, the drain terminal is connected to the output terminal of the first high potential DC voltage V _DD , and the source terminal is connected to the Q node. The gate terminal of the second transistor T2 is connected to the output terminal of the next stage ST2, the drain terminal is connected to the Q node, and the source terminal is connected to the output terminal of the low potential voltage V _SS . The gate terminal of the third transistor T3 is connected to the Qb node, the drain terminal is connected to the Q node, and the source terminal is connected to the output terminal of the low potential voltage V _SS .

The pull-up transistor driver 510 controls the potential VQ of the Q node to the first high level H1 in the period t1, and the potential VQ of the Q node higher than the first high level H1 in the period t2. The control is performed at the second high level H2, and the potential VQ of the Q node is controlled at the low level L in the period t3.

Next, the pull-down transistor driver 520 controls the potential VQb of the Qb node according to the gate start signal Vst, the potential VQ of the Q node, and the second high potential DC voltage V _DD1 .

In detail, the pull-down transistor driver 520 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6 to control the potential VQb of the Qb node. The gate terminal and the drain terminal of the fourth transistor T4 are commonly connected to the output terminal of the second high potential DC voltage V _DD1 , and the source terminal is connected to the Qb node.

The gate terminal of the fifth transistor T5 is connected to the Q node, the drain terminal is connected to the Qb node, and the source terminal is connected to the output terminal of the low potential voltage V _SS .

The gate terminal of the sixth transistor T6 is connected to the input terminal of the gate start signal Vst, the drain terminal is connected to the Qb node, and the source terminal is connected to the output terminal of the low potential voltage V _SS .

The pull-down transistor driver 520 controls the potential VQb of the Qb node to the low level L in the t1 and t2 sections, and the potential VQb of the Qb node to the high level H in the t3 section.

The pull-down transistor driver 520 according to an exemplary embodiment of the present invention performs the timing controller 250 for a predetermined time Δt after the gate output signal is applied to the last gate line Gn among the sections after the t3 section. The potential VQb of the Qb node is maintained at the low level H through the low level clock signal CLK and the low level first and second high potential DC voltages V _DD and V _DD1 . This causes the Qb node to discharge.

Next, the output unit 114 selects one of the clock signal CLK and the low potential voltage V _SS according to the potential VQ of the Q node and the potential VQb of the Qb node, and outputs the gate output signal Vout1. Will output

In detail, the gate signal output unit 530 includes a seventh transistor T7 that is a pull-up transistor and an eighth transistor T8 that is a pull-down transistor. The gate terminal of the seventh transistor T7 is connected to the Q node, the drain terminal is connected to the output terminal of the clock signal CLK, and the source terminal is connected to the output node NO. The gate terminal of the eighth transistor T8 is connected to the Qb node, the drain terminal is connected to the output node NO, and the source terminal is connected to the output terminal of the low potential voltage V _SS .

The gate signal output unit 530 outputs the high level clock signal CLK through the seventh transistor T7 during the t2 period in which the potential VQ of the Q node is controlled to the second high level H2, and Qb. The low potential voltage V _SS is output through the eighth transistor T8 during the period t3 in which the potential VQb of the node is controlled to the high level H.

Hereinafter, the circuit operation of the stage shown in FIG. 4 will be described with reference to FIGS. 4 and 5.

First, the first and sixth transistors T1 and T6 are turned on in response to the high level gate start signal Vst during the t1 period. Accordingly, the potential VQ of the Q node is maintained at the first high level H1 by the high potential DC voltage V _DD applied through the first transistor T1, and the potential VQb of the Qb node is maintained. Is maintained at the low level L by the low potential voltage V _SS applied through the sixth transistor T6. During this t1 period, the fifth transistor T5 is turned on as the potential VQ of the Q node rises.

Next, during the period t2, the first transistor T1 is turned off in response to the low level gate start signal Vst to float the Q node. At this time, when the clock signal CLK is applied to the seventh transistor T7 which is a pull-up transistor, the Q node potential VQ is at the second high level under the influence of the gate-drain capacitance Cqout of the seventh transistor T7. Bootstsapping with (H2). As a result, the seventh transistor T7 is turned on to output the clock signal CLK as the high level gate output signal Vout1. On the other hand, even during the t2 period, even if the sixth transistor T6 is turned off in response to the low level gate start signal Vst, the fifth transistor T5 remains turned on, and thus the potential VQb of the Qb node. Keeps the low level.

Next, during the period t3, the second transistor T2 is turned on in response to the gate output signal Vout2 of the next stage ST2 having a high level to electrically connect the output terminal of the low potential voltage V _SS and the Q node. Is connected to lower the potential VQ of the Q node to a low level. As the potential VQ of the Q node falls to the low level, the fifth transistor T5 is turned off to float the Qb node. At this time, when the fourth transistor T4 is turned on by the second high potential DC voltage V _DD1 , the potential VQb of the Qb node is applied to the second high potential DC voltage applied through the fourth transistor T4. V _DD1 ) to rise to a high level. As a result, the eighth transistor T8, which is a pull-down transistor, is turned on to output the low potential voltage V _SS as the gate output signal Vout2.

In addition, the third transistor T3 is turned on to electrically connect the output terminal of the low potential voltage V _SS to the Q node, and then the second transistor T3 is applied by the gate output signal Vout2 of the next stage ST2 at a low level. Even when the transistor T2 is turned off, the potential VQ of the Q node is continuously maintained at the low level for the period t3, thereby continuously turning on the third transistor T3 and the eighth transistor T8.

On the other hand, in the case of an electrophoretic display, the time for which the potential VQb of the Qb node is kept at a high level in the still picture state is much longer than that of other flat panel displays. In other flat panel display devices, the potential VQb of the Qb node is changed to a low level every t1 and t2 intervals when a still image is implemented, so that the time that the potential VQb of the Qb node remains high is one frame period. Shorter, the gate bias stress accumulated at the gate terminals of the third transistor T3 and the eighth transistor T8 can be easily solved in one frame period.

On the other hand, the electrophoretic display temporarily stops the gate driver 220 when new data is not input after the image is displayed. Therefore, since the potential VQb of the Qb node remains at a high level, gate bias stress is accumulated at the gate terminals of the third and eighth transistors T3 and T8.

Therefore, when the high level gate output signal Voutn is applied to the last gate line Gn of the gate lines, the electrophoretic display device according to the present invention may be configured to include the clock signals CLK and CLKB for a predetermined time Δt. Both the high potential DC voltage V _DD and the second high potential DC voltage V _DD1 are kept at a low level to discharge the Qb node to the gate terminals of the third and eighth transistors T3 and T8. Eliminates accumulated gate bias stress.

Those skilled in the art to which the present invention pertains will understand that the above-described present invention can be implemented in other specific forms without changing the technical spirit or essential features.

Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

200: display panel 210: data driver
220: gate driver 230: common voltage supply
240: power supply unit 250: timing control unit
510: pull-up transistor driver 520: pull-down transistor driver
530: gate output signal output unit

Claims

An electrophoretic display panel in which pixel cells are arranged in pixel regions defined by intersections of a plurality of gate lines and a plurality of data lines;
A data driver supplying a data signal to the data line;
At least one high potential DC voltage having a high level and a plurality of stages sequentially supplying a gate output signal of a high level to the gate line sequentially shifted according to a clock signal in which the high level and the low level are periodically inverted. A gate driver configured; And
The clock signal is generated and supplied to the gate driver, and the clock signal and the driving voltage are maintained at a low level for a predetermined time when the gate output signal of the high level is supplied to the last gate line of the plurality of gate lines. Electrophoretic display device comprising a timing controller.

The method of claim 1,
And a power supply unit configured to supply one of a high level high potential DC voltage or a low level high potential DC voltage to the gate driver under the control of the timing controller.

The method of claim 2,
The timing controller transmits a first control signal to the power supply unit when the gate output signal of the high level is supplied to the last gate line, and transmits a second control signal to the power supply unit when the predetermined time elapses.
The power supply unit lowers the high potential DC voltage to a low level when the first control signal is received from the timing controller, and sets the high potential DC voltage to a high level when the second control signal is received from the timing controller. Electrophoretic display device characterized in that the rising.

The method of claim 1, wherein the high potential DC voltage,
A first high potential direct current voltage for charging a first control node for maintaining a gate output signal of the current stage at a high level; And
A second high potential DC voltage for charging a second control node for maintaining the gate output signal of the current stage at a low level,
And the first and second high potential DC voltages are maintained at a low level for the predetermined time.

The method of claim 4, wherein each stage,
A pull-up transistor driver for controlling a potential of the first control node according to a gate start signal or a gate output signal of a previous stage, a gate output signal of a next stage, and a potential of the second control node;
A pull-down transistor driver configured to control a potential of the second control node according to a gate start signal or a gate output signal of a previous stage, a potential of the first control node, and the second high potential DC voltage; And
A gate output signal output unit configured to output a gate output signal of the current stage according to driving of the pull-up transistor driver and the pull-down transistor driver;
And the pull-down transistor driver is configured to discharge the potential of the second control node during the predetermined time by using a low level clock signal and a low level first and second high potential DC voltages.

The method of claim 5,
The pull-up transistor driver includes a first transistor configured to charge the first node to the first high potential DC voltage, and second and third transistors configured to discharge a potential charged in the first node,
The pull-down transistor driver includes a fourth transistor configured to charge the second node to the second high potential DC voltage, and fifth and sixth transistors configured to discharge a potential charged in the second node.
The gate output signal output unit may include a pull-up transistor configured to output the clock signal to the gate line according to the potential of the first node, and a pull-down transistor to discharge the gate output signal according to the potential of the second node. Electrophoretic display.

The method of claim 1, wherein the clock signal,
A first clock signal supplied to the odd stage and a second clock signal supplied to the even stage,
And the first clock signal and the second clock signal are kept at a low level for the predetermined time and have opposite phases for the time except for the predetermined time.

The method of claim 1,
And the predetermined time is a time interval after a high level gate output signal is supplied to the last gate line and before a new data signal is applied to the data line.

As a driving method of an electrophoretic display device,
Generating a gate start signal, at least one clock signal whose high level and low level are periodically inverted, and at least one high potential DC voltage having a high level;
Generating a high level gate output signal sequentially shifted according to the gate start signal, the at least one clock signal, and the at least one high potential DC voltage, and supplying the gate output signal to a plurality of gate lines; And
And when the gate output signal of the high level is supplied to the last gate line of the plurality of gate lines, maintaining the clock signal and the high potential DC voltage at a low level for a predetermined time. How to drive the display device.

10. The method of claim 9,
The clock signal and the high potential DC voltage are maintained at a low level for a time interval after the high gate output signal is supplied to the last gate line and before a new data signal is applied to the data line. Method of driving an electrophoretic display device.