KR20140096613A

KR20140096613A - Shift register and method for driving the same

Info

Publication number: KR20140096613A
Application number: KR1020130009396A
Authority: KR
Inventors: 김태상
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-28
Filing date: 2013-01-28
Publication date: 2014-08-06
Also published as: KR102023641B1

Abstract

A shift register of the present invention consists of a plurality of stages, each of which comprises: a first switching thin film transistor (TFT) turned on by a start signal applied to a gate electrode, and supplying a pulse signal of a high potential driving voltage to a first node; a pull-up TFT turned on by the pulse signal of the high potential driving voltage formed on the first node and outputting an output signal to an output terminal while a click signal is applied; a second switching TFT turned on by the output signal boosted by the click signal, and supplying the high potential driving voltage to the first node; a third switching TFT turned on by a reset signal supplied to the gate electrode, and supplying a low potential driving voltage to the first node; and a pull-down TFT turned on by the reset signal supplied to the gate electrode, and supplying the low potential driving voltage to the output terminal to drop the output signal.

Description

[0001] SHIFT REGISTER AND METHOD FOR DRIVING THE SAME [0002]

The present invention relates to a shift register having improved driving reliability and a driving method thereof.

As mobile electronic devices such as mobile communication terminals and notebook computers are developed, there is an increasing demand for flat panel display devices applicable thereto. In response, a liquid crystal display device (LCD), a plasma display device (PDP), an organic light emitting display device (OLED), and the like have been commercialized.

The gate driving circuit of the display devices includes a shift register for sequentially supplying gate pulses to a plurality of gate lines. The shift register sequentially outputs gate pulses through a plurality of stages including a plurality of transistors and capacitors.

Recently, a TFT (thin film transistor) of the shift register is embedded in a substrate of a display panel by using a GIP (gate in panel) method.

The TFTs constituting the GIP type shift register serve to supply gate pulses to the TFTs of the respective pixels formed on the display panel. Therefore, not only the characteristics of the basic TFT such as the mobility and the leakage current but also the durability and the electrical reliability that can maintain the long-term lifetime are very important. The semiconductor layer of the TFT is formed of amorphous silicon or polycrystalline silicon. The amorphous silicon is advantageous in that the film forming process is simple and the production cost is low, but the electrical reliability is not ensured.

In order to solve such a problem, researches using an oxide semiconductor as a semiconductor layer of a TFT are progressing. Oxide semiconductors are evaluated as amorphous and stable materials. If an oxide semiconductor is used as a semiconductor layer of a TFT, a TFT can be manufactured at a low temperature by using existing process equipment without purchasing an additional process equipment. There are several advantages such as omission of process.

FIG. 1 is a circuit diagram of a conventional shift register including an oxide TFT, and FIG. 2 is a diagram showing a drive waveform of the shift register shown in FIG. 1 shows a circuit of one stage among a plurality of stages constituting a shift register.

Referring to FIGS. 1 and 2, a shift register according to the related art includes a start signal VST, a reset signal RST, a plurality of clock signals CLK and CLKB, an initialization signal Vinid, , VSS) to generate a scan signal having a high potential driving voltage (VDD) or a low potential driving voltage (VSS) level, and sequentially supplies the scan signals generated in the plurality of stages to the gate line of the display panel. To this end, each stage of the shift register includes the first TFT (T1) to the eighth TFT (T8) and the capacitor (C).

The first to sixth TFTs T6 to T6 are turned on by the start signal VST, the reset signal RST, the boosting clock signal CLKB or the initialization signal Vinitial as a switching TFT, And supplies driving voltages VDD and VSS to the node.

The seventh TFT T7 is a full-up TFT for outputting a high voltage VDD, which is turned on by a signal input to the Q node and outputs a scan signal of a high potential voltage at an output terminal OUT.

The eighth TFT T8 is a full down TFT for outputting a low potential voltage VSS and is turned on by a signal input to the QB node to output a scan signal of a low potential voltage to the output terminal. That is, the scan signal of the high potential voltage is lowered to the low potential voltage level.

Here, the QB node which is the gate node of the fourth TFT (T4) and the eighth TFT (T8) maintains the high voltage for most of the time (90% or more time) in one frame period.

FIG. 3 is a graph showing a positive bias temperature stress (PBTS) characteristic of an oxide TFT that constitutes a GIP type shift register according to the prior art.

Referring to FIG. 3, the fourth TFT (T4) and the eighth TFT (T8, pull-down TFT) connected to the QB node are shifted in the positive direction by the positive bias deterioration (PBTS). The shift of the fourth TFT (T4) and the eighth TFT (T8, pull-down TFT) affects the falling time operation.

Since the shift register according to the related art generates the output signals VGH and VGL using the boosting of the clock signal CLK, the output signal is affected by the width of the clock signal CLK. In order to increase the output time of the signal, the width of the clock signal CLK should be increased. However, when the width of the clock signal is increased, the high output signal VGH and the low output signal VGL overlap each other and the shift register operates normally There is a problem that can not be done.

When the fourth TFT (T4) and the eighth TFT (T8, pull-down TFT) are deteriorated, the noise of the signal applied to the Q node increases, so that a multi output is generated. The output characteristic of the sixth TFT T6 which is lowered to the low potential driving voltage VSS is reduced to lower the driving reliability of the GIP shift register.

The Bias Temperature Stress (BTS) characteristic of the oxide TFT is affected by the voltage level of the gate bias, the time and the temperature, and the positive bias deterioration (PBTS) as compared to the negative bias deterioration (NBTS) Vth) shift phenomenon occurs conspicuously.

Therefore, when the GIP type shift register including the oxide TFT is applied, the driving reliability of the shift register is deteriorated due to deterioration of the TFT according to the driving time, and distortion occurs in the output signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is a technical object to improve deterioration of a TFT constituting a GIP (gate in panel) shift register.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is a technical object to enhance driving reliability of a shift register of the GIP scheme and to prevent occurrence of distortion of an output signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is a technical object of the present invention to simplify the logic of a shift register to form a narrow bezel liquid crystal panel.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

A shift register of the present invention includes: a first switching TFT (thin film transistor) which is turned on by a start signal applied to a gate electrode and supplies a pulse signal of a high potential driving voltage to a first node; A pull-up TFT which is turned on by a pulse signal of a high potential driving voltage formed at the first node and outputs an output signal to an output terminal while a clock signal is applied; A second switching TFT which is turned on by an output signal boosted by the clock signal to supply the high potential driving voltage to the first node; A third switching TFT which is turned on by a reset signal supplied to the gate electrode to supply a low potential driving voltage to the first node; And a pull-down TFT which is turned on by the reset signal supplied to the gate electrode and supplies the low-potential driving voltage to the output terminal to lower the output signal.

The present invention can improve deterioration of TFTs constituting a shift register of a GIP (gate in panel) scheme.

The present invention can improve the driving reliability of the shift register of the GIP scheme and prevent the output signal from being distorted.

The present invention simplifies the logic of the shift register of the GIP type and can form a narrow bezel liquid crystal panel.

In addition, other features and advantages of the present invention may be newly understood through embodiments of the present invention.

1 is a circuit diagram of a conventional shifter resistor including an oxide TFT.
2 is a view showing a driving waveform of the shift register shown in FIG.
FIG. 3 is a graph showing the positive bias temperature stress characteristic of an oxide TFT constituting a GIP shift register according to the prior art.
4 is a view schematically showing a display device to which a shift register according to an embodiment of the present invention is applied.
5 is a circuit diagram of a shift register according to an embodiment of the present invention.
6 is a diagram illustrating a driving waveform of a shift register according to an embodiment of the present invention.
7 is a diagram illustrating a driving method of a stage according to a driving waveform of a shift register according to an embodiment of the present invention.
8 is a diagram showing output signals of a multi-stage shift register using four clock signals (CLK).
FIG. 9 is a diagram illustrating a reduced effect of the TFT and the signal line of the shift register according to the embodiment of the present invention.

It should be noted that, in the specification of the present invention, the same reference numerals as in the drawings denote the same elements, but they are numbered as much as possible even if they are shown in different drawings.

Hereinafter, a shift register and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a view schematically showing a display device to which a shift register according to an embodiment of the present invention is applied.

4, a liquid crystal display device to which a shift register 110 according to an embodiment of the present invention is applied includes a liquid crystal panel 100 in which pixels are arranged in a matrix form and displays an image according to supplied image data (data voltage) ; A backlight unit (not shown) for supplying light to the liquid crystal panel 100; And a driving circuit for driving the light sources of the liquid crystal panel 100 and the backlight unit (not shown).

The liquid crystal panel 100 includes a lower substrate (TFT array substrate) and an upper substrate (color filter array substrate) which are adhered to each other and a liquid crystal layer formed between the lower substrate and the upper substrate. A lower polarizing film is disposed on the back surface of the lower substrate, and an upper polarizing film is disposed on the upper surface of the upper substrate.

The upper substrate of the liquid crystal panel 100 includes a color filter for converting light incident through the pixels of the lower substrate into color light to display a color image.

The lower substrate of the liquid crystal panel 100 includes M gate lines G1 through Gn and N data lines D1 through Dn. In addition, a shift register 110 is formed in a non-display area of the lower substrate by the GIP method.

Pixels are defined by intersection of gate lines and data lines formed on a lower substrate, and each pixel includes a thin film transistor (TFT) and a storage capacitor (Cst). In addition, the liquid crystal panel 100 includes a pixel electrode for applying a data voltage to a pixel and a common electrode for applying a common voltage Vcom.

The TFT of each pixel is switched by the scan signal supplied through the gate line, and when the TFT is turned on, the data voltage supplied through the data line is supplied to the pixel.

The arrangement state of the liquid crystal is changed in each pixel by the electric field difference between the data voltage and the common voltage, and the image is displayed by adjusting the arrangement of the liquid crystals and adjusting the transmittance of the light incident from the backlight unit.

The driving circuit unit includes a main controller 200, a shift register 110 (gate driver), a backlight driving unit (not shown), and a power supply unit (not shown).

The main controller 200 includes a timing controller T-con and a data driver as a single chip. The main controller 200 includes a plurality of May be connected to the pad 300.

The main controller 200 converts the digital image data (R, G, B) into analog image data (data voltage). Then, an analog data voltage is supplied to each pixel through the data lines of the liquid crystal panel 100.

The main controller 200 generates digital image data (R, G, B) by arranging the video signals from the outside on a frame-by-frame basis, and supplies the generated digital image data to the data driver.

The main controller 200 generates a gate control signal GCS for controlling the shift register 110 and a data control signal DCS for controlling the data driver using the input timing signal TS.

Here, the timing signal TS includes a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a clock signal CLK.

The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE).

The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE), a polarity control signal (POL) . &Lt; / RTI >

The main controller 200 includes a start signal VST, a reset signal RST and a clock signal CLK initialization signal Vinitial for driving the GIP shift register 110 using the timing signal TS, And supplies it to the shift register 110. In addition, the driving power supplies VDD and VSS are supplied to the shift register 110. [

The shift register 110 generates a scan signal and supplies the scan signal to each of the plurality of gate lines. The shift register 110 includes a plurality of stages corresponding to a plurality of gate lines formed in the liquid crystal panel 100.

The shift register 110 generates a scan signal using the input start signal VST, the reset signal RST and the clock signal CLK initialization signal Vinitial and outputs the scan signal as an output signal to the liquid crystal panel 100 To the gate lines of the second transistor Q1. The shift register 110 may be formed on the left and right sides of the non-display area (pad area) of the lower substrate as the liquid crystal panel 100 is enlarged.

FIG. 5 is a circuit diagram of a shift register according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating driving waveforms of a shift register according to an embodiment of the present invention.

5 and 6, each of a plurality of stages constituting a shift register 110 according to an embodiment of the present invention includes a switching block A and a buffer block B. Referring to FIG. The start signal VST, the reset signal RST, the clock signal CLK initialization signal Vin and the driving power sources VDD and VSS are supplied to the shift register 110 to generate a scan signal.

Here, the start signal VST is a pulse signal for starting the rising of the output signal, and the reset signal RST is a pulse signal for starting falling of the output signal. That is, the output signal is maintained by the start signal VST until the reset signal RST is input.

The start signal VST and the reset signal RST are pulse signals which are turned off after the gate-on voltage level is maintained in two horizontal (2H) periods. Output of the output signal is started by the start signal VST, The output of the output signal is terminated by the reset signal RST. Since the start signal VST and the reset signal RST are signals for controlling the start and end of the output signal, they do not overlap with each other.

The clock signal CLK maintains a gate-on voltage level in two horizontal (2H) periods, then has a clock form in which the induced voltage repeats over a certain period of time, and is synchronized with the start signal VST, Can have an overlapping phase. In FIG. 6, an example in which the clock signal CLK and the start signal VST overlap each other for one horizontal period (1H) is shown. However, the present invention is not limited to this, and a clock signal whose phase is sequentially delayed by 1/2 clock or 2 clocks may be input to the stage ST.

The switching block A includes first to third switching TFTs 111, 112 and 113, a first capacitor Ca and a second capacitor Cb. The buffer block B includes a pull-up TFT 114 and a pull-down TFT 115.

The pull-up TFT 114 and the pull-down TFT 115 formed in the plurality of switching TFTs 111, 112, and 113 and the buffer block B configured in the switching block A are formed of an N type semiconductor Layer or a P-type semiconductor layer.

The switching block A uses the input start signal VST, the reset signal RST and the initialization signal Vinitial to rise the output signal and shift the signal of the Q node (first node). So that the output signal is falling, that is, the output signal is a low potential voltage.

The buffer block B shifts the clock signal CLK of the high potential drive voltage VDD level according to the signal shifted by the start signal VST and outputs the shifted clock signal CLK as an output signal, ) To the low potential driving voltage (VSS) level according to the reset signal RST.

Here, the high potential driving voltage VDD can be supplied from + 20V to + 30V, and the low potential driving voltage VSS can be supplied from -10V to -20V.

7 is a diagram illustrating a driving method of a stage according to a driving waveform of a shift register according to an embodiment of the present invention.

Referring to Fig. 7 together with Figs. 5 and 6, the first switching TFT 111 is turned on by the start signal VST supplied to the gate electrode. The source electrode of the first switching TFT 111 is connected to the first power supply line L1 to be supplied with the high potential driving voltage VDD and the drain electrode thereof is connected to the Q node VDD) to the Q node (first node).

7A, the first switching TFT 111 is turned on only when the start signal VST of the gate-on voltage level is supplied to turn on the high-potential driving voltage VDD to the Q-node ).

The first switching TFT 111 is turned on by an initialization signal (Vinitial) supplied to the gate electrode and supplies a high potential driving voltage VDD to the Q node (first node) Initialize. The first switching TFT 111 is formed in a double gate structure in order to improve a driving defect caused by a negative shift of an initial threshold voltage Vth.

The gate electrode of the second switching TFT 112 is connected to the second node n2 connected to the output terminal OUT. The source electrode of the second switching TFT 112 is connected to the first power supply line L1 to be supplied with the high potential driving voltage VDD and the drain electrode thereof is connected to the Q node VDD) to the Q node (the first node).

Here, after the clock signal CLK ends, the second switching TFT 112 outputs the clock signal CLK when the voltage of the Q node (first node) falls below the high potential driving voltage VDD from the 2VDD level, And the Q node (first node) is kept constantly at the high potential driving voltage VDD. The second switching TFT 112 is turned on to charge the first capacitor Ca formed between the Q node (first node) and the second node n2 to the high potential driving voltage VDD.

The third switching TFT 113 is turned on by the reset signal RST supplied to the gate electrode. The source electrode of the third switching TFT 113 is connected to the second power supply line L2 to supply the low potential driving voltage VSS and the drain electrode is connected to the Q node (first node) VSS) to the Q node (first node).

7 (B), the third switching TFT 113 is turned on only when the reset signal RST of the gate-on voltage level is supplied to turn on the low potential driving voltage VSS to the Q node ).

The first terminal of the first capacitor Ca is connected to the Q node (first node), and the second terminal is connected to the second node n2 connected to the output terminal OUT. The first first capacitor Ca maintains the Q node (first node) constantly at the high potential driving voltage VDD to output the noise of the output signal OUT to the output OUT which is boosted by the clock signal CLK. ).

The first terminal of the second capacitor Cb is connected to the Q node (first node), and the second terminal is connected to the third node n3 to which the reset signal RST is supplied. The second capacitor Cb maintains the Q node (the first node) and the third node n3 at a constant voltage to remove the noise of the reset signal RST.

The gate electrode of the pull-up TFT 114 is connected to the Q node (first node) and turned on by a pulse signal of a high potential driving voltage (VDD) level applied to the Q node (first node). The source electrode of the pull-up TFT 114 is supplied with the clock signal CLK of the high potential driving voltage (VDD) level. The drain electrode of the pull-up TFT 114 is connected to the output terminal OUT to output the output signal of the high potential driving voltage VDD to the output terminal OUT.

As shown in Fig. 7A, the pull-up TFT 114 is turned on by the clock signal of the high potential driving voltage VDD applied to the Q node (first node) by the start signal VST. The pull-up TFT 114 outputs an output signal to the output terminal OUT while the clock signal CLK is applied, and is turned off in synchronization with the reset signal RST. That is, the pull-up TFT 114 uses the clock signal CLK of the high potential driving voltage (VDD) level to rise the output signal and output it to the output terminal OUT.

Here, the pull-up TFT 114 is turned on by setting the Q node (first node) to the high potential driving voltage VDD by the start signal VST, and the output terminal is driven to the 2VDD level by the clock signal CLK. (Bootstrap).

6 and 7B, when the clock signal CLK ends, the pull-up TFT 114 is turned off and the voltage of the output terminal falls from the 2VDD level to the VDD level. Thereafter, the reset signal is maintained at the VDD level for a predetermined time (for example, 2.0us to 2.5us) until the reset signal is applied to the third switching TFT 113 and the pull-down TFT 115 at (RST).

The gate electrode of the pull-down TFT 115 is connected to the third node n3. The source electrode of the pull-down TFT 115 is connected to the second power supply line L2 and a low potential driving voltage VSS is supplied. The drain electrode of the pull-down TFT 115 is connected to the output terminal OUT.

7 (B), the pull-down TFT 115 is turned on by the reset signal RST of the high-potential driving voltage VDD applied to the third node n3 to turn the output signal of the output terminal to the low potential And falls to the driving voltage VSS.

In the shift register according to the embodiment of the present invention, when the first switching TFT 111 is turned on, the high-potential driving voltage VDD is supplied to the Q node (first node), and the third switching TFT 113 is turned on A low potential driving voltage VSS is supplied to the Q node (first node). This makes it possible to prevent the pull-up TFT 114 connected to the Q node (first node) from deteriorating positively or negatively.

8 is a diagram showing output signals of a multi-stage shift register using four clock signals (CLK).

As shown in FIG. 8, an output signal of the multi-stage shift register can be generated by using four clock signals CLK overlapping one horizontal (1H) period in two horizontal (2H) periods. That is, the four clock signals CLK are sequentially applied to m stages, and output signals are sequentially generated at m stages. In FIG. 7, timing of the output signals for the (N-1) th stage, the (N) th stage, the (N + 1) th stage, and the (N + 2)

Output lines of each of the m stages ST1 to STm constituting the shift register are connected to m gate lines GL1 to GLm formed in the liquid crystal panel, respectively.

Each of the m stages ST1 to STm starts driving by the start pulse signal SVST and generates a gate-on voltage level < RTI ID = 0.0 >Quot; out " Accordingly, a scan pulse of a gate-on voltage level (VDD) is supplied to each of the plurality of gate lines GL1 to GLm for a predetermined horizontal period, and a low-potential driving voltage VSS of a gate- .

The shift register according to the embodiment of the present invention removes the QB node which is essential in the shift register of the related art to improve the positive bias deterioration (PBTS) phenomenon of the QB node and increase the driving reliability of the GIP type shift register have.

FIG. 9 is a diagram illustrating a reduced effect of the TFT and the signal line of the shift register according to the embodiment of the present invention.

Referring to FIG. 9, in comparison between the shift register according to the embodiment of the present invention and the logic of the shift register according to the related art, it is possible to reduce the number of the switching TFTs for rising and falling of the output signal by three for each stage have.

In the shift register according to the related art, seven input signal lines are formed. In the present invention, a signal line for supplying a clock signal (CLKB) to the QB node formed in the prior art Thereby forming six input signal lines.

This can reduce the number of TFTs and signal lines, reduce the logic area of the GIP to form a shift register compared to conventional devices, and improve the product's competitiveness by enabling narrow bezel design .

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal panel 110: shift register
111: first switching TFT 112: second switching TFT
113: third switching TFT 114: pull-up TFT
115: pull-down TFT Ca: first capacitor
Cb: second capacitor ST: stage
200: main controller 300: pad

Claims

A first switching TFT (thin film transistor) which is turned on by a start signal applied to the gate electrode and supplies a pulse signal of a high potential driving voltage to the first node;
A pull-up TFT which is turned on by a pulse signal of a high potential driving voltage formed at the first node and outputs an output signal to an output terminal while a clock signal is applied;
A second switching TFT which is turned on by an output signal boosted by the clock signal to supply the high potential driving voltage to the first node;
A third switching TFT which is turned on by a reset signal supplied to the gate electrode to supply a low potential driving voltage to the first node; And
And a pull-down TFT which is turned on by the reset signal supplied to the gate electrode and supplies the low-potential driving voltage to the output terminal to lower the output signal.

The method according to claim 1,
The first terminal is connected to the first node and the second terminal is connected to the second node connected to the output terminal, and the first node is maintained at a constant voltage to eliminate noise of the output signal And a shift register.

The method according to claim 1,
A second capacitor connected to a third node to which a first terminal is connected to the first node and a second terminal to which the reset signal is supplied and which maintains the third node at a constant voltage to remove noise of the reset signal; Wherein the shift register further comprises a shift register.

The method according to claim 1,
Wherein the pull-up TFT uses the clock signal of the high potential driving voltage level to raise the output signal to output to the output terminal.

The method according to claim 1,
And the second switching TFT is turned on when the voltage of the first node falls below the high potential driving voltage after the clock signal is terminated to maintain the first node at the high potential driving voltage. register.

The method according to claim 1,
The start signal is supplied to the gate electrode of the first switching TFT, the source electrode is connected to the first power supply line to which the high potential driving voltage is supplied, the drain electrode is connected to the first node,
A gate electrode of the second switching TFT is connected to the output terminal, a source electrode is connected to the first power supply line, a drain electrode is connected to the first node,
The reset signal is supplied to a gate electrode of the third switching TFT, the source electrode is connected to a second power supply line to which the low potential driving voltage is supplied, the drain electrode is connected to the first node,
A gate electrode of the pull-up TFT is connected to the first node, a source electrode is connected to a signal line to which the clock signal is applied, a drain electrode is connected to the output terminal,
A gate electrode of the pull-down TFT is connected to a third node to which the reset signal is applied, a source electrode is connected to a second power supply line to which the low potential driving voltage is supplied, and a drain electrode is connected to the output terminal Shift register.

The method according to claim 1,
Wherein the first switching TFT is formed in a double gate structure and is turned on by an initialization signal supplied to the gate electrode to supply the high potential driving voltage to the first node.

The method according to claim 1,
A high-potential driving voltage is formed at the first node by the start signal (VST) to turn on the pull-up TFT, and the pull-up TFT is turned on to bootstrap the output terminal through a clock signal. register.

The driving method of a shift register according to any one of claims 1 to 8,
The pull-up TFT is turned on by the clock signal to form a double high-potential driving voltage at the output terminal,
When the clock signal is terminated, the pull-up TFT is turned off, so that the voltage of the output terminal is lowered to the high potential driving voltage at twice the high potential driving voltage,
The voltage of the output terminal is maintained at the high potential driving voltage for a predetermined time before the reset signal is applied to the pull-down TFT,
And the voltage of the output terminal is lowered to the low potential voltage by the reset signal.

10. The method of claim 9,
Wherein four clock signals overlapping one horizontal period in two horizontal periods are sequentially applied to the plurality of stages to output an output signal sequentially shifted by one horizontal period.