KR20080033630A - Shift register and organic light emitting display device using the same - Google Patents

Abstract

A shift register and an organic light emitting display device using the same are provided to decrease a dead space in the shift register by forming the shift register with a small number of elements and clock signals. A shift register includes plural cascaded stages. Each of the stages includes first to third voltage level controllers(410,420,430) and first and second transistors(M1,M2). The first voltage level controller controls a voltage level at a first node, an output terminal thereof, corresponding to a first output signal of a former stage or a start pulse and first and second clock signals. The second voltage level controller controls a voltage level of a second node, an output terminal thereof, corresponding to the voltage level of the first node and the first clock signal. The third voltage level controller controls the voltage level of a third node, an output terminal thereof, corresponding to voltage levels of the first and second nodes. A gate electrode of the first transistor is connected to the third node. The first transistor is connected between a first voltage source and a fourth node. A gate electrode of the second transistor is connected to the second node. The second transistor is connected between a second voltage source and the fourth node.

Description

Shift register and organic light emitting display device using the same

1 is a block diagram showing the configuration of a general shift register.

2 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an example of a shift register included in the scan driver of FIG. 2.

FIG. 4 is a detailed circuit diagram illustrating an example of any stage shown in FIG. 3.

FIG. 5 is a waveform diagram of input / output signals of the shift register shown in FIGS. 3 and 4.

  <Explanation of symbols for the main parts of the drawings>

110: scan driver 120: data driver

130: image display unit 140: pixels

150: timing controller 410: first voltage level controller

420: second voltage level controller 430: third voltage level controller

ST: Stage of Shift Register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register and an organic light emitting display device using the same, and more particularly, to a shift register provided in a driving circuit for driving a pixel column of an organic light emitting display device and an organic light emitting display device using the same.

In general, a flat panel display such as an organic light emitting display includes an array of pixels arranged in a matrix at intersections of data lines, scan lines, and / or emission control lines.

Here, the scan lines and the emission control lines are horizontal lines of the matrix pixel array and are selected by the shift register to receive the scan signal and the emission control signal, respectively.

1 is a block diagram showing the configuration of a general shift register.

Referring to FIG. 1, the shift register includes a plurality of stages ST1 to STn connected dependently to an input line of the start pulse SP.

Each of the stages ST1 to STn sequentially generates a start pulse SP or an output signal of a previous stage in response to clock signals supplied from input lines of a clock signal (not shown).

The stages ST1 to STn are used to drive scan lines connected to scan lines connected to a driving circuit for driving pixel columns of the organic light emitting display device or to drive light emission control lines connected to light emission control lines. Can be. That is, the output signal output from the stages ST1 to STn is supplied to the pixel array through the scan lines and / or the emission control lines to be used as the scan signals SS1 to SSn and / or the emission control signals EMI1 to EMIn. Can be.

Such a shift register is included in a scan driver for driving scan lines and / or emission control lines. The scan driver may be mounted in the form of a chip after the pixel array is formed. It is also common to form with an array.

Accordingly, there is a need to seek a method of improving the efficiency of the manufacturing process by simplifying the process of forming the pixel array and the scan driver.

In addition, by configuring the shift register using a relatively small number of devices and clock signals, it is necessary to make the design of the shift register easier and to reduce dead space.

Accordingly, an object of the present invention is to configure a shift register using a relatively small number of devices and clock signals, thereby making it easier to design the shift register, reducing dead space, and improving the efficiency of the manufacturing process. One shift register and an organic light emitting display device using the same are provided.

In order to achieve the above object, a first aspect of the present invention provides a shift register having a plurality of stages connected dependently to an input line of a start pulse, wherein each stage is a first stage of the start pulse or a previous stage. A first voltage level controller for controlling the voltage level of the first node N1 as its output terminal in response to the output signal and the first and second clock signals CLK1 and CLK2; A second voltage level controller for controlling the voltage level of the second node N2 which is its output terminal in response to the first clock signal, and its output terminal corresponding to the voltage levels of the first and second nodes; A third voltage level controller controlling a voltage level of a third node (the first output node of the stage N3), a gate electrode connected to the third node, a first power source VDD and a fourth node (the Second output node of the stage And a first transistor connected between N4) and a gate electrode connected to the second node, and a second transistor connected between the fourth node and a second power supply VSS.

Preferably, the first voltage level controller includes: a third transistor connected between the first power supply and the first node, a gate electrode connected to an input line of the first clock signal, the first node, and the And a fourth transistor connected between the input lines of the second clock signal and a gate electrode connected to the input line of the first output signal of the start pulse or the previous stage. The third and fourth transistors may be P-type transistors. And a first capacitor connected between the input line of the first output signal of the start pulse or the previous stage and the first node. The second voltage level controller is connected between the first power supply and the second node, a fifth transistor having a gate electrode connected to the first node, and connected between the second node and the second power supply. And a sixth transistor having a gate electrode connected to the input line of the first clock signal. The fifth and sixth transistors may be P-type transistors. The third voltage level controller is connected between the first power supply and the third node, a seventh transistor having a gate electrode connected to the second node, and is connected between the third node and the second power supply. And an eighth transistor, the gate electrode of which is connected to the first node. The seventh and eighth transistors are P-type transistors. The first and second transistors may be P-type transistors. And a second capacitor connected between the second node and the fourth node. The voltage of the second power supply is set to a value lower than the voltage of the first power supply. The first clock signal and the second clock signal have opposite waveforms.

According to a second aspect of the present invention, there is provided an image display unit including a plurality of pixels electrically connected to scan lines, emission control lines, and data lines, and at least one of applying scan signals and emission control signals to the scan lines and emission control lines, respectively. And a data driver for applying a data signal to the data lines, wherein the shift register has a plurality of stages that are dependently connected to an input line of a start pulse. The stage controls a voltage level of the first node N1, which is its output terminal, corresponding to the first output signal and the first and second clock signals CLK1 and CLK2 of the start pulse or the previous stage. The voltage level controller and the voltage level of the second node N2 which is its output terminal in response to the voltage level of the first node and the first clock signal. A second voltage level control unit controlling a voltage level and a third level controlling a voltage level of a third node (a first output node of the stage, N3), which is an output terminal thereof, in response to the voltage levels of the first and second nodes. A first transistor connected to a voltage level controller, a gate electrode connected to the third node, and connected between a first power supply VDD and a fourth node (the second output node N4 of the stage), and the second node. An organic light emitting display device including a second transistor connected to a gate electrode thereof and connected between the fourth node and a second power supply VSS is provided.

Preferably, the first voltage level controller includes a P-type third transistor connected between the first power supply and the first node, and a gate electrode connected to an input line of the first clock signal; A fourth type transistor is connected between a node and an input line of the second clock signal, and a gate electrode is connected to an input line of the first output signal of the start pulse or the previous stage. The second voltage level controller is connected between the first power supply and the second node, and has a P-type fifth transistor having a gate electrode connected to the first node, and between the second node and the second power supply. And a sixth transistor of P type connected to an input line of the first clock signal. The third voltage level controller is connected between the first power supply and the third node, and has a P type seventh transistor connected to the second node, and between the third node and the second power supply. And a P-type eighth transistor connected to the gate electrode and connected to the first node. The first and second transistors are P type transistors. The first clock signal and the second clock signal have opposite waveforms.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 5 attached to the preferred embodiments in which those skilled in the art can easily carry out the present invention.

2 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an organic light emitting display device according to an exemplary embodiment of the present invention is formed in an area partitioned by scan lines S1 to Sn, emission control lines E1 to En, and data lines D1 to Dm. The image display unit 130 including the pixels 140, the scan driver 110 for driving the scan lines S1 to Sn, and the emission control lines E1 to En, and the data lines D1 to Dm. And a timing controller 150 for controlling the data driver 120 and the scan driver 110 and the data driver 120.

The scan driver 110 receives the scan driving control signal SCS including the start pulse SP, the clock signal CLK, and the like from the timing controller 150 to generate a scan signal, and generates the scan signal from the scan lines. It is supplied in (S1 to Sn). In addition, the scan driver 110 generates an emission control signal in response to the scan driving control signal SCS, and supplies the generated emission control signal to the emission control lines E1 to En.

To this end, the scan driver 110 sequentially generates a scan signal and / or a light emission control signal in response to the start pulse SP and the clock signals CLK, and scan lines S1 to Sn and light emission control lines, respectively. And at least one shift register to apply to (E1 to En).

Here, although the case where both the scan signal and the light emission control signal are generated by the scan driver 110 has been described, the present invention is not limited thereto. For example, the scan driver for generating the scan signal and the emission control driver for generating the emission control signal may be provided separately. In this case, the scan driver and the emission control driver may each include at least one shift register.

The data driver 120 receives a data driving control signal DCS and data from the timing controller 150 to generate a data signal. The data signal generated by the data driver 120 is supplied to the data lines D1 to Dm in synchronization with the scan signal.

The timing controller 150 generates the scan driving control signal SCS and the data driving control signal DCS in response to the synchronization signals supplied from the outside. The scan driving control signal SCS generated by the timing controller 150 is supplied to the scan driver 110, and the data driving control signal DCS is supplied to the data driver 120. In addition, the timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The image display unit 130 includes a plurality of pixels 140 electrically connected to the scan lines S1 to Sn, the emission control lines E1 to En, and the data lines D1 to Dm. Each pixel 140 receives a first pixel power source ELVDD and a second pixel power source ELVSS from the outside, and scan signals, emission control signals, and data signals from the scan driver 110 and the data driver 120, respectively. Get supplied. Each pixel 140 supplied with the first and second pixel power sources ELVDD and ELVSS and the scan signal, the emission control signal, and the data signal is selected by the scan signal to correspond to the data signal for a period corresponding to the emission control signal. To generate light. To this end, each of the pixels 140 includes at least an organic light emitting diode, and when formed in an active type, the pixels 140 may further include an active element such as a P-type transistor.

3 is a block diagram illustrating an example of a shift register included in the scan driver of FIG. 2. For convenience, FIG. 3 illustrates a shift register for sequentially generating emission control signals EMI1 to EMIn. However, the present invention is not limited thereto, and the shift register according to the present invention may be used for various phase delays of the input signal. It can be used as.

Referring to FIG. 3, the shift register is connected to an input line of the start pulse SP and is connected to a supply line of two clock signals CLK among supply lines of four clock signals CLK1 to CLK4, respectively. A plurality of stages ST11 to ST1n are provided. Here, the first and second clock signals CLK1 and CLK2 have opposite waveforms. That is, the second clock signal CLK2 is a clock signal CLK1B having a waveform opposite to that of the first clock signal CLK1. In addition, the third and fourth clock signals CLK3 and CLK4 also have opposite waveforms, that is, the fourth clock signal CLK4 is a clock signal CLK3B having a waveform opposite to the third clock signal CLK3. The periods of the first clock signal CLK1 and the third clock signal CLK3 are the same, and these clock signals CLK have a phase difference by a predetermined period. For example, the first clock signal CLK1 and the third clock signal CLK3 may have a phase difference corresponding to a quarter period (or 3/4 period).

The stages ST11 to ST1n are connected to input lines of two clock signals CLK having opposite waveforms among the input lines of the four clock signals CLK1 to CLK4, and thus clock signals CLK having opposite waveforms. Driven by). That is, each of the stages ST11 to ST1n receives the first and second clock signals CLK1 and CLK2, or receives the third and fourth clock signals CLK3 and CLK4.

In addition, each of the stages ST11 to ST1n has two output terminals. In this case, the first output terminal connected to the input terminal of the next stage STi + 1 has the same waveform as the start pulse SP or the first output signal Vni-1 of the previous stage, but has a predetermined phase. The first output signal Vni of the delayed form is output. The second output terminal connected to the emission control line E has a waveform opposite to the start pulse SP or the first output signal Vni-1 of the previous stage, and has a phase delayed by a predetermined period. The control signal EMIi is output.

The first stage ST11 outputs the output signals Vn1 and EMI1 by phase-delaying the start pulse SP supplied to the first and second clock signals CLK1 and CLK2 for a predetermined period. .

The second stage ST12 phase-delays the first output signal Vn1 of the first stage ST11 supplied to itself in response to the third and fourth clock signals CLK3 and CLK4 by a predetermined period. Output (Vn2, EMI2).

The third stage ST13 phase-delays the first output signal Vn2 of the second stage ST12 supplied to itself in response to the first and second clock signals CLK1 and CLK2 by a predetermined period, and outputs the output signal. Output (Vn3, EMI3). At this time, the input terminals of the first and second clock signals CLK1 and CLK2 of the third stage ST13 are opposite to the input terminals of the first and second clock signals CLK1 and CLK2 of the first stage ST11. Is set.

The fourth stage ST14 phase-delays the first output signal Vn3 of the third stage ST13 supplied to the third and fourth clock signals CLK3 and CLK4 by a predetermined period to output the output signal. Output (Vn4, EMI4). At this time, the input terminals of the third and fourth clock signals CLK3 and CLK4 of the fourth stage ST14 are opposite to the input terminals of the third and fourth clock signals CLK3 and CLK4 of the second stage ST12. Is set.

The fifth to nth stages ST15 to ST1n are driven by the driving as described above, and are the first stages of the previous stage STi-1 supplied to the first to fourth clock signals CLK1 to CLK4. The output signals Vni and EMIi are output by phase-delaying the output signal Vni-1 by a predetermined period.

The emission control signals EMI1 to EMIn generated in each of the stages ST11 to ST1n are sequentially supplied to the emission control lines E1 to En.

FIG. 4 is a detailed circuit diagram illustrating an example of any stage shown in FIG. 3. For convenience, FIG. 4 shows an arbitrary stage supplied with the first and second clock signals.

Referring to FIG. 4, an arbitrary stage STi corresponds to the first output signal Vni-1 and the first and second clock signals CLK1 and CLK2 of the start pulse SP or the previous stage. The first voltage level controller 410 for controlling the voltage level of the first node N1, which is an output terminal, and its own output terminal corresponding to the voltage level of the first node N1 and the first clock signal CLK1. The second voltage level controller 420 for controlling the voltage level of the second node N2 and the third node N3 which is its output terminal corresponding to the voltage levels of the first and second nodes N1 and N2. A third voltage level controller 430 for controlling the voltage level of the first node, a first transistor M1 for controlling the voltage level of the fourth node N4 corresponding to the voltage level of the third node N3, and a second The second transistor M2 controls the voltage level of the fourth node N4 corresponding to the voltage level of the node N2.

Here, the third node N3 and the fourth node N4 are output nodes of the stage STi. More specifically, the third node N3 is the first output node of the stage STi and is connected to the input line of the next stage STi + 1 to the next stage STi + 1 to the first output signal Vni). The fourth node N4 is a second output node of the stage STi and is connected to any one of the emission control lines E. The emission control signal Ei is connected to the emission control line Ei. EMIi) is supplied.

The first voltage level controller 410 includes third to fourth transistors M3 and M4 connected in series between the third power source VDD and the input line of the second clock signal CLK2.

The third transistor M3 is connected between the third power supply VDD and the first node N1, and the gate electrode of the third transistor M3 is connected to the input line of the first clock signal CLK1. The third transistor M3 is a P-type transistor, and is turned on when the first clock signal CLK1 having a low level voltage value is supplied to connect the first power source VDD and the first node N1. Connect electrically.

The fourth transistor M4 is connected between the first node N1 and the input line of the second clock signal CLK2, and the gate electrode of the fourth transistor M4 is formed of the start pulse SP or the previous stage. 1 is connected to the input line of the output signal Vni-1. The fourth transistor M4 is a P-type transistor, and is turned on when the first output signal Vni-1 of the previous stage or the start pulse SP having a low voltage value is supplied. The first node N1 is charged to a voltage value corresponding to the voltage level of the clock signal CLK2.

The second voltage level controller 420 includes fifth to sixth transistors M5 and M6 connected in series between the first power source VDD and the second power source VSS. Here, the voltage of the second power source VSS is set to a value lower than the voltage of the first power source VDD.

The fifth transistor M5 is connected between the first power supply VDD and the second node N2, and the gate electrode of the fifth transistor M5 is connected to the first node N1. The fifth transistor M5 is a P-type transistor and is turned on when the voltage level of the first node N1 is low to electrically connect the first power supply VDD and the second node N2. .

The sixth transistor M6 is connected between the second node N2 and the second power supply VSS, and the gate electrode of the sixth transistor M6 is connected to the input line of the first clock signal CLK1. The sixth transistor M6 is a P-type transistor, and is turned on when the first clock signal CLK1 having a low level voltage value is supplied to supply the second node N2 and the second power supply VSS. Connect electrically.

The third voltage level controller 430 includes seventh to eighth transistors M7 and M8 connected in series between the first power source VDD and the second power source VSS.

The seventh transistor M7 is connected between the first power supply VDD and the third node N3, and the gate electrode of the seventh transistor M7 is connected to the second node N2. The seventh transistor M7 is a P-type transistor and is turned on when the voltage level of the second node N2 is low to electrically connect the first power source VDD and the third node N3. .

That is, when the seventh transistor M7 is turned on, since the third node N3 has a high level voltage value, the third node N3 is connected to the third node N3 which is the first output node of the stage STi. The first output signal Vni of the high level is supplied to the input line of the stage STi + 1.

The eighth transistor M8 is connected between the third node N3 and the second power supply VSS, and the gate electrode of the eighth transistor M8 is connected to the first node N1. The eighth transistor M8 is a P-type transistor and is turned on when the voltage level of the first node N1 is low to electrically connect the third node N3 and the second power supply VSS. .

That is, when the eighth transistor M8 is turned on, the third node N3 has a low level voltage value. Therefore, the first output signal Vni of the low level is input to the input line of the next stage STi + 1. ) Is supplied.

The first transistor M1 is connected between the first power supply VDD and the fourth node N4, and the gate electrode of the first transistor M1 is connected to the third node N3. The first transistor M1 is a P-type transistor and is turned on when the voltage level of the third node N3 is low to electrically connect the first power source VDD and the fourth node N4. . That is, when the first transistor M1 is turned on, the fourth node N4 is charged to a high level voltage value corresponding to the first power source VDD. Therefore, when the first transistor M1 is turned on, the fourth node N4, which is the second output node of the stage STi, is charged to a high value and the light emission control line Ei connected to the fourth node N4. ) Is supplied with a high level light emission control signal EMIi.

The second transistor M2 is connected between the fourth node N4 and the second power supply VSS, and the gate electrode of the second transistor M2 is connected to the second node N2. The second transistor M2 is a P-type transistor and is turned on when the voltage level of the second node N2 is low to electrically connect the fourth node N4 and the second power supply VSS. . That is, when the second transistor M2 is turned on, the fourth node N4 is charged to a low level voltage value corresponding to the second power source VSS. Therefore, when the second transistor M2 is turned on, the fourth node N4 is charged to a low value and the low level emission control signal EMIi is applied to the emission control line Ei connected to the fourth node N4. ) Is supplied.

In addition, the stage STi may include a first capacitor C1 connected between the input line of the first output signal Vni-1 of the start pulse SP or the previous stage and the first node N1; The semiconductor device further includes a second capacitor C2 connected between the second node N2 and the fourth node N4.

The first capacitor C1 stabilizes the voltage between the gate electrode and the source electrode of the fourth transistor M4 connected to both terminals thereof, thereby enabling the fourth transistor M4 to operate stably. . In addition, the second capacitor C2 stabilizes the voltage between the gate electrode and the source electrode of the second transistor M2 connected to both terminals thereof, thereby enabling the second transistor M2 to operate stably. That is, in the present invention, the first and second capacitors C1 and C2 are formed for more stable operation. However, the present invention is not limited thereto, and for example, the first and / or second capacitors C1 and C2 may be removed.

As described above, when the circuit of the stages STi is designed, a shift register is formed using a relatively small number of devices, that is, a relatively small number of transistors M and capacitors C and clock signals CLK. By constructing, the shift register can be more easily designed and dead space can be reduced.

In addition, the manufacturing process is simplified by designing all the transistors M1 to M8 included in an arbitrary stage STi of the same type.

In particular, in a flat panel display such as an active organic light emitting display device, a P-type transistor is included in a pixel array, and stages included in a shift register of a scan driver are composed of transistors of the same type as the transistors included in the pixel array. In this case, the shift register may be simultaneously formed while performing the process of forming the pixel array on the substrate. Thus, by simultaneously forming the pixel array and the scan driver without further increasing the process steps, the manufacturing process of the display device is simplified and facilitated, and the efficiency thereof is improved.

However, the present invention is not limited to the case where the shift register is formed together with the pixel array on the substrate, and may be applied to the case where the shift register is embedded in a chip or the like and mounted on the substrate on which the pixel array is formed.

Hereinafter, the operation of the shift register illustrated in FIGS. 3 and 4 will be described in detail with reference to the waveform of the input / output signal illustrated in FIG. 5. For convenience, factors such as the threshold voltage of the transistor will not be considered.

Referring to FIG. 5, first, a low level start pulse SP, a low level first clock signal CLK1, and a high level second clock signal CLK2 are supplied to a first stage ST11 during a t1 period. do. Here, it is assumed that the circuit configuration of the first stage ST11 is the same as that shown in FIG. 4.

Then, the third and sixth transistors M3 and M6 are turned on in response to the low level first clock signal CLK1, and the fourth transistor M4 is turned on in response to the low level start pulse SP. Is turned on.

When the third and fourth transistors M3 and M4 are turned on, the first node N1 is electrically connected to an input line of the first power source VDD and the second clock signal CLK2. At this time, since the voltage levels of the first power supply VDD and the second clock signal CLK2 are both high level, the first node N1 is charged to a high level voltage. When the sixth transistor M6 is turned on, the second node N2 is electrically connected to the second power source VSS. That is, the second node N2 is charged at a low level voltage.

As the first node N1 is charged to the high level voltage, the fifth and eighth transistors M5 and M8 are turned off. As the second node N2 is charged to the low level voltage, the seventh transistor M7 and the ninth transistor M9 are turned on.

When the seventh transistor M7 is turned on, the first power supply VDD and the third node N3 are electrically connected, and the third node N3 is charged to a high level voltage. Accordingly, while the first transistor M1 is turned off, the first output of the high level from the third node N3, which is the first output node, to the input line of the next stage (ie, the second stage, ST12). The signal Vn1 is supplied.

In addition, when the ninth transistor M9 is turned on, the fourth node N4, which is the second output node, and the second power source VSS are electrically connected to each other, and thus the first emission control line may be formed from the fourth node N4. The low level light emission control signal EMI1 is supplied to E1).

Thereafter, the low level start pulse SP, the high level first clock signal CLK1 and the low level second clock signal CLK2 are supplied to the first stage ST11 during the period t2_1.

Then, the third and sixth transistors M3 and M6 are turned off in response to the high level first clock signal CLK1.

The fourth transistor M4 is turned on in response to the low level start pulse SP, and the low level voltage of the second clock signal CLK2 is transmitted to the first node N1. As a result, the first node N1 is charged to a low level voltage.

When the first node N1 is charged to the low level voltage, the fifth and eighth transistors M5 and M8 are turned on. Accordingly, the second node N2 is charged to the high level voltage of the third power source VDD, and the third node N3 is charged to the low level voltage of the fourth power source VSS.

As the second node N2 is charged to the high level voltage, the seventh and second transistors M7 and M2 are turned off.

Meanwhile, as the third node N3 is charged to the low level voltage, the first transistor M1 is turned on so that the fourth node N4 is charged to the high level voltage of the first power source VDD. Accordingly, the high level emission control signal EMI1 is supplied to the first emission control line E1 connected to the fourth node N4. In addition, the low level first output signal Vn1 is supplied to the input line of the next stage (ie, the second stage ST12) connected to the third node N3.

Thereafter, the high level start pulse SP, the high level first clock signal CLK1 and the low level second clock signal CLK2 are supplied to the first stage ST11 during the t2_2 period.

Then, the third, fourth, and sixth transistors M3, M4, and M6 are turned off in response to the high level start pulse SP and the first clock signal CLK1 to turn off the previous state, that is, the state of the period t2_1. Keep it. Accordingly, during the period t2_1, similarly to the period t2_1, the high level first emission control signal EMI1 and the low level first output signal Vn1 respectively correspond to the first emission control line E1 and the next stage (that is, the first stage). 2 stages are output to the input line of ST12).

Thereafter, the high level start pulse SP, the low level first clock signal CLK1, and the high level second clock signal CLK2 are supplied to the first stage ST11 during the period t3.

Then, the fourth transistor M4 is turned off in response to the high level start pulse SP, and the third and sixth transistors M3 and M6 are corresponding to the low level first clock signal CLK1. Is turned on.

When the third transistor M3 is turned on, the first node N1 is charged to the high level voltage of the first power supply VDD, thereby turning off the fifth and eighth transistors M5 and M8. . When the sixth transistor M6 is turned on, the second node N2 is charged to the low level voltage of the second power supply VSS.

As the second node N2 is charged to the low level voltage, the seventh and second transistors M7 and M2 are turned on.

When the seventh transistor M7 is turned on, the third node N3 is charged to the high level voltage of the first power supply VDD, and accordingly the first transistor M1 is turned off, while the next stage (I.e., the first output signal Vn1 of high level is output to the input line of the second stage ST12.

In addition, when the second transistor M2 is turned on, the fourth node N4 is charged to the low level voltage of the second power supply VSS, and accordingly, the emission control line connected to the fourth node N4 is applied. The low level first emission control signal EMI1 is output to E1).

Thereafter, the high level start pulse SP, the high level first clock signal CLK1, and the low level second clock signal CLK2 are supplied to the first stage ST11 during the period t4.

Then, the third, fourth, and sixth transistors M3, M4, and M6 are turned off in response to the high level start pulse SP and the first clock signal CLK1 to turn off the previous state, that is, the state of the period t3. Keep it. Accordingly, during the period t4, similarly to the period t3, the low level first emission control signal EMI1 and the high level first output signal Vn1 are respectively applied to the first emission control line E1 and the next stage (that is, the first stage). 2 stages are output to the input line of ST12).

Thereafter, as the same signals as those in the t3 and t4 sections are repeatedly supplied to the first stage ST11, the voltage level of the first emission control signal EMI1 is maintained at the low level for the remaining sections, and the first output is performed. The voltage level of the signal Vn1 is maintained at a high level.

Meanwhile, the second stage ST12 is supplied to itself using the first output signal Vn1 from the first stage ST11 and the third and fourth clock signals CLK3 and CLK4 instead of the start pulse SP. The first output signal Vn1 from the first stage ST11 is delayed by half a clock, i.e., a quarter cycle of the clock signal, and output.

More specifically, during the period t2_1, the second stage ST12 includes the first output signal Vn1 of the low stage first stage ST11, the low level third clock signal CLK3, and the high level fourth clock signal. Corresponding to CLK4, the low level second emission control signal EMI2 and the high level second stage ST2 output the first output signal Vn2. Here, since the operation of the second stage ST12 during the t2_1 period is the same as the operation of the first stage ST11 during the t1 period, a detailed description thereof will be omitted.

Thereafter, during the period t2_2, the second stage ST12 receives the first output signal Vn1 of the low stage first stage ST11, the third clock signal CLK3 of high level, and the fourth clock signal CLK4 of low level. In response to the output of the high level second emission control signal EMI2 and the low level second stage ST12, the first output signal Vn2 is output. Here, since the operation of the second stage ST12 during the t2_2 section is the same as the operation of the first stage ST11 during the t2_1 section, a detailed description thereof will be omitted.

Thereafter, during the period t3_1, the second stage ST12 receives the first output signal Vn1 of the first stage ST11 of the high level, the third clock signal CLK3 of the high level, and the fourth clock signal of the low level. The high level second emission control signal EMI2 and the first level output signal Vn2 of the low level second stage ST12 are output in response to the CLK4. Here, since the operation of the second stage ST12 during the t3_1 section is the same as the operation of the first stage ST11 during the t2_2 section, a detailed description thereof will be omitted.

Thereafter, the second stage ST12 operates in the same manner as the operation of ST11 of the first stage in the t3 and t4 sections. That is, the voltage level of the second emission control signal EMI2 output from the second stage ST12 is maintained at the low level for the remaining period, and the voltage level of the first output signal Vn2 of the second stage ST12 is Maintain high level.

By the driving as described above, the stages ST of the shift register according to the present invention first and second the first output signal Vn (or the start pulse SP) of the previous stage inputted thereto. In response to the clock signals CLK1 and CLK2 or the third and fourth clock signals CLK3 and CLK4, the phase is delayed by half a clock cycle, i.e., 1/4 cycle of the clock signal, and output to the output line.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various modifications are possible within the scope of the technical idea of the present invention.

As described above, according to the shift register according to the present invention, by designing the shift register using a relatively small number of elements and clock signals, the design of the shift register can be made easier and the dead space can be reduced.

In addition, the transistors included in each stage may be designed in the same type to simplify the manufacturing process. In particular, by employing a scan driver including a shift register composed of P-type transistors in an organic light emitting display device including a pixel array composed of P-type transistors, the pixel array and the scan driver may be increased without further processing steps. It can be formed at the same time. As a result, the manufacturing process of the display device is simplified and facilitated, and the efficiency of the manufacturing process is improved.

Claims (18)

A shift register having a plurality of stages connected dependently to an input line of a start pulse, the shift register comprising: Each stage, A first voltage level control unit controlling a voltage level of the first node N1 as its output terminal in response to the first output signal and the first and second clock signals CLK1 and CLK2 of the start pulse or the previous stage; Wow, A second voltage level controller for controlling the voltage level of the second node N2 which is its output terminal in response to the voltage level of the first node and the first clock signal; A third voltage level controller for controlling a voltage level of a third node (the first output node N3 of the stage), which is an output terminal thereof, corresponding to the voltage levels of the first and second nodes; A first transistor connected to the third node and connected between a first power supply VDD and a fourth node (the second output node N4 of the stage); And a second transistor connected to the second node and connected between the fourth node and a second power supply (VSS). According to claim 1, The first voltage level control unit, A third transistor connected between the first power supply and the first node and having a gate electrode connected to an input line of the first clock signal; And a fourth transistor connected between the first node and an input line of the second clock signal and having a gate electrode connected to an input line of the first output signal of the start pulse or the previous stage. The method of claim 2, And the third and fourth transistors are P-type transistors. The method of claim 2, And a first capacitor connected between the input line of the first output signal of the start pulse or the previous stage and the first node. According to claim 1, The second voltage level control unit, A fifth transistor connected between the first power supply and the second node and having a gate electrode connected to the first node; And a sixth transistor connected between the second node and the second power supply and having a gate electrode connected to an input line of the first clock signal. The method of claim 5, And the fifth and sixth transistors are P-type transistors. According to claim 1, The third voltage level control unit, A seventh transistor connected between the first power supply and the third node, and a gate electrode connected to the second node; And an eighth transistor connected between the third node and the second power supply, and a gate electrode connected to the first node. The method of claim 7, wherein And the seventh and eighth transistors are P-type transistors. According to claim 1, And the first and second transistors are P-type transistors. According to claim 1, And a second capacitor connected between the second node and the fourth node. According to claim 1, And the voltage of the second power supply is set to a value lower than the voltage of the first power supply. According to claim 1, And the first clock signal and the second clock signal have opposite waveforms. An image display unit including a plurality of pixels electrically connected to scan lines, emission control lines, and data lines; A scan driver including at least one shift register for applying a scan signal and a light emission control signal to the scan lines and the light emission control lines, respectively; And a data driver for applying a data signal to the data lines. The shift register has a plurality of stages connected dependently to the input line of the start pulse, Each stage, A first voltage level control unit controlling a voltage level of the first node N1 as its output terminal in response to the first output signal and the first and second clock signals CLK1 and CLK2 of the start pulse or the previous stage; Wow, A second voltage level controller for controlling the voltage level of the second node N2 which is its output terminal in response to the voltage level of the first node and the first clock signal; A third voltage level controller for controlling a voltage level of a third node (the first output node N3 of the stage), which is an output terminal thereof, corresponding to the voltage levels of the first and second nodes; A first transistor connected to the third node and connected between a first power supply VDD and a fourth node (the second output node N4 of the stage); And a second transistor connected to the second node and connected between the fourth node and a second power supply (VSS). The method of claim 13, The first voltage level control unit, A third type P transistor connected between the first power supply and the first node and having a gate electrode connected to an input line of the first clock signal; An organic field comprising a P-type fourth transistor connected between the first node and an input line of the second clock signal and having a gate electrode connected to an input line of the first output signal of the start pulse or the previous stage; Light emitting display. The method of claim 13, The second voltage level control unit, A fifth P-type transistor connected between the first power supply and the second node and having a gate electrode connected to the first node; And a P-type sixth transistor connected between the second node and the second power supply and having a gate electrode connected to an input line of the first clock signal. The method of claim 13, The third voltage level control unit, A P-type seventh transistor connected between the first power supply and the third node, and a gate electrode connected to the second node; And a P-type eighth transistor connected between the third node and the second power supply and having a gate electrode connected to the first node. The method of claim 13, And the first and second transistors are P type transistors. The method of claim 13, And the first clock signal and the second clock signal have opposite waveforms.

Images