KR100940401B1 - Shift Register and Scan Driver of usign the same - Google Patents

Abstract

Disclosed are a shift register and a scanning driver using the same in each stage. The shift register uses at least four transistors and two capacitors. Each shift register uses one clock signal to form a scan signal. In addition, in the case of configuring a scan driver using a shift register, a clock signal and an inverted clock signal are alternately inputted for each adjacent shift register. In addition, the carry signal and the reset signal generated in the adjacent shift registers are used to control the operation of the transistors constituting each shift register.

Scan driver, shift register, scan signal

Description

Shift Register and Scan Driver of usign the same

The present invention relates to an organic light emitting display device, and more particularly, to a scan driving device for driving an organic light emitting display device and a shift register included therein.

The organic light emitting device performs a light emitting operation with a predetermined brightness according to the driving current supplied as the self-luminous element. The organic light emitting device is classified into an active type and a passive type according to a driving method. In particular, the active type includes an active element in each pixel, and has an operating mechanism capable of storing a data signal for determining a luminance for a predetermined period of time. In this active type, a scan signal is supplied to each of a plurality of pixels arranged in a matrix form, and generates a driving current according to the data signal applied thereto.

The display panel including each pixel is provided with a scan driver for supplying a scan signal and a data driver for supplying a data signal. In addition, the scan driving device or the data driving device may be manufactured integrally with the panel according to a system on panel (SOP) technology manufactured in the same process as the pixels of the panel.

FIG. 1 is a block diagram showing a conventional scan driver, and FIG. 2 is a timing diagram for explaining the operation of the scan driver of FIG.

1 and 2, the scan driving device is composed of a plurality of stages. The stage is a shift register. The stage receives a plurality of clock signals and performs a logical operation on the received clock signal to form an activated scan signal at a specific timing.

The manner in which the stage receives the clock signals to form the scan signal may be variously changed according to the type of the scan driver. However, a technique of receiving a plurality of clock signals and forming a scan signal through processing of the received clock signals is dominant.

In order to operate the scan driver, the plurality of clock signals must be supplied from the outside. Therefore, there is a burden that a separate circuit for generating a plurality of clock signals externally is provided. In addition, the circuit configuration of stages provided to perform logic operations or processing processes for a plurality of clock signals has a complicated aspect.

This means that the area occupied by each stage must be increased in order to implement a shift register having a complicated circuit configuration. If the area occupied by the scan driver is relatively increased in the process of forming the scan driver together with the pixels on the same panel, a problem occurs that the area of the light emitting panel defined by the pixels is decreased.

A first object of the present invention for solving the above problems is to provide a shift register that can minimize the number of clock signals supplied to form a scan signal and can form the scan signal through a simple circuit.

Further, a second object of the present invention is to provide a scan driving apparatus using, in each stage, a shift register provided by the achievement of the first object.

The present invention for achieving the first object, the first transistor is connected to the first node, for receiving a negative power supply voltage, and performing the on / off operation according to the previous carry signal; A second transistor configured to receive a clock signal or an inverted clock signal and perform an on / off operation according to the voltage of the first node to form a scan signal; A third transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a carry signal or a reset signal; A fourth transistor connected to the first node for receiving a positive power supply voltage and subsequently performing an on / off operation according to a reset signal; A first capacitor coupled between the positive power supply voltage and the first node; And a second capacitor connected between the first node and the second transistor and configured to regulate a voltage of the first node through coupling.

In addition, the present invention for achieving the second object, in the scan driving apparatus having a plurality of stages arranged sequentially, forming a plurality of scan signals delayed by one half clock, receiving a clock signal, the start applied A first stage for generating a first scan signal and a first carry signal in response to an on / off operation according to a pulse and then a reset signal; And receiving an inverted clock signal, the first carry signal, and a third carry signal generated at a later stage, thereby receiving the second scan signal, the second carry signal, and the second reset signal, which are delayed by the first scan signal. A first stage or a second stage, the first stage or the second stage connected to a first node, for receiving a negative power supply voltage and performing an on / off operation according to a previous carry signal; transistor; A second transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a scan signal; A third transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a carry signal or a reset signal; A fourth transistor connected to the first node for receiving a positive power supply voltage and subsequently performing an on / off operation according to a reset signal; A first capacitor coupled between the positive power supply voltage and the first node; And a second capacitor connected between the first node and the second transistor and configured to adjust a voltage of the first node through a coupling.

According to the present invention described above, a scan signal can be formed using one clock signal and a clock signal inverted to the supplied clock signal. In addition, a signal necessary for the operation of the scan signal and the surrounding shift registers can be formed using the clock signal and the signals supplied from the shift registers arranged around the surroundings. Therefore, it is possible to form scan signals that are sequentially generated through a simple circuit configuration.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

3 is a circuit diagram showing a shift register constituting a scan driver according to a preferred embodiment of the present invention.

Referring to FIG. 3, the shift register according to the present embodiment is composed of four transistors and two capacitors. In addition, the four transistors are preferably composed of PMOS transistors.

The first transistor M1 receives the negative power supply voltage VSS and performs an on / off operation according to the previous carry signal CR [k-1]. In addition, the first transistor M1 is connected to a first node N1. The previous carry signal CR [k-1] is a carry signal outputted from the previous shift register when a plurality of shift registers are arranged to form a scan driver.

The second transistor M2 receives the clock signal CLK or the inverted clock signal / CLK and performs an on / off operation according to the control of the voltage of the first node N1. In particular, the second transistor induces a bootstrap operation of the second capacitor C2 to regulate the voltage of the first node N1. The second transistor forms the scan signal SCAN [k] under the control of the voltage of the first node N1.

The third transistor M3 receives the clock signal CLK or the inverted clock signal / CLK, performs an on / off operation according to the control of the voltage of the first node N1, and carries a signal CR [k] and a reset signal RS [k]. To form.

The fourth transistor M4 receives the positive power supply voltage VDD and then performs an on / off operation under the control of the reset signal RS [k + 1]. The subsequent reset signal RS [k + 1] is a reset signal output from a subsequent shift register when a plurality of shift registers are arranged to form a scan driver. The positive power supply voltage VDD passing through the fourth transistor M4 is transferred to the first node N1.

In addition, a first capacitor C1 and a second capacitor C2 are connected to the first node N1. The first capacitor C1 is connected between the positive power supply voltage VDD and the first node N1, and the second capacitor C2 is connected between the first node N1 and the second transistor M2.

4 is a timing diagram illustrating the operation of the shift register of FIG. 3 according to a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram for describing an operation of the shift register in the section T1 of FIG. 4.

In FIG. 5, the portion treated with a dotted line represents an off state path, and the portion treated with a solid line represents an on state path.

In addition, although only the clock signal CLK is illustrated in FIG. 4, the same applies when the inverted clock signal / CLK is applied. That is, the operation at the high level and the low level of the inverted clock signal / CLK works in the same way as the application of the clock signal CLK.

4 and 5, the carry signal CR [k−1] is changed to the low level in the period T1 when the clock signal CLK is at the high level. The first transistor M1 is turned on and the fourth transistor M4 is turned off by the low level carry signal CR [k-1]. In addition, the voltage of the first node N1 is set to the high level before the low level carry signal CR [k-1] is applied. The low level signal is input to the first node N1 by the turned-on first transistor M1.

The second transistor M2 and the third transistor M3 are turned on by the voltage of the first node N1 at the low level. The high level clock signal CLK is output as the scan signal SCAN [k] by the turned-on second transistor M2. In addition, the high level clock signal CLK is output as a carry signal CR [k] and a reset signal RS [k] through the turned-on third transistor M3. Therefore, the scan signal SCAN [k], the carry signal CR [k] and the reset signal RS [k] have the same output waveform.

The capacitor C2 stores the voltage difference of the VDD magnitude by the scan signal SCAN [k] having a high level.

FIG. 6 is a circuit diagram for describing an operation of a shift register in a period T2 of FIG. 4.

In FIG. 6, the portion treated with a dotted line represents an off state path, and the portion treated with a solid line represents an on state path.

4 and 6, the clock signal CLK changes to a low level in the period T2. Further, the carry signal CR [k-1] is changed to high level. In addition, the reset signal RS [k + 1] maintains a high level.

First, the fourth transistor M4 is kept off by the high level reset signal RS [k + 1], and the first transistor M1 is turned off by the high level carry signal CR [k-1]. Therefore, the supply of the signal of the positive power supply voltage VDD and the negative power supply voltage VSS toward the first node N1 is cut off.

In addition, the second transistor M2 and the third transistor M3 are turned on by the voltage of the first node N1 of the low level set in the period T1. The low level clock signal CLK is transferred to the second capacitor C2 through the turned-on second transistor M2. In addition, a voltage difference of about VDD is already stored in the second capacitor C2 in the period T1. Therefore, when the low level clock signal CLK is applied to one end of the second capacitor C2, the voltage of the first node N1 is further lowered by the charge coupling. This may be referred to as a bootstrap operation using a capacitor. That is, when the low level clock signal CLK is applied, the second capacitor C2 lowers the voltage of the first node N1 to maintain the voltage difference as much as VDD.

The second transistor M2 and the third transistor M3 are turned on by the dropped voltage of the first node N1. The clock signal CLK at the low level is formed as the scan signal SCAN [k] through the turned-on second transistor M2. In addition, a low level carry signal CR [k] and a reset signal RS [k] are output through the turned-on third transistor M3.

FIG. 7 is a circuit diagram for describing an operation of a shift register in a period T3 of FIG. 4.

In FIG. 7, the portion treated with a dotted line represents an off state path, and the portion treated with a solid line represents an on state path.

4 and 7, in the period T3, the clock signal CLK is changed to the high level, and the carry signal CR [k-1] is set to the high level. In addition, the reset signal RS [k + 1] is changed to the low level.

The fourth transistor M4 is turned on by the reset signal RS [k + 1] changed to the low level. In addition, the voltage of the first node N1, which is lowered to the voltage of about 2VDD level in the previous section T2, rises to the VDD level. During the rise, the second transistor M2 and the third transistor M3 remain turned on, and the scan signals SCAN [k] and the carry signal CR [k] output high clock signals. Therefore, in the section T3, the two outputs SCAN [k] and CR [k] output high levels.

Thereafter, when the period T3 ends and the reset signal RS [k + 1] rises to the high level, the fourth transistor M4 is turned off. In addition, the voltage of the first node N1 is sufficiently raised to the VDD level. Therefore, the second transistor M2 and the third transistor M3 are turned off, and the change of the clock signal CLK is not reflected as the scan signal SCAN [k], the carry signal CR [k] and the reset signal RS [k]. That is, the scan signal SCAN [k], the carry signal CR [k], and the reset signal RS [k] maintain the high level after that.

This is due to the phenomenon that the change of the clock signal CLK is not reflected in the output terminal as the transistors M2 and M3 are kept off. Finally, the scan signal SCAN [k] and the carry signal CR [k] in the high level state are continuously maintained by the capacitance in the wiring line or the like.

Fig. 8 is a circuit diagram showing another shift register constituting the scan drive device according to the preferred embodiment of the present invention.

Referring to FIG. 8, the shift register according to the present embodiment is composed of five transistors and two capacitors. The shift resist disclosed in FIG. 8 is the same as the shift register of FIG. 3 except that the fifth transistor M5 is interposed in the path to which the clock signal CLK is applied. In addition, the on / off operation of the fifth transistor M5 is the same as the on / off operation of the second and third transistors M2 and M3 of FIG. 8. Therefore, the operation of the shift register shown in FIG. 8 is the same as that described in FIGS.

FIG. 9 is a block diagram illustrating a scan driving apparatus using the shift register shown in FIGS. 3 and 8 according to a preferred embodiment of the present invention.

Referring to FIG. 9, the scan driving apparatus according to the present invention includes a plurality of stages 100, 110, 120, 130, and 140. Each stage is the shift register of FIG. 3 or FIG. 8.

In addition, for convenience of description, the positive power supply voltage VDD and the negative power supply voltage VSS are omitted in the drawing. Accordingly, it is to be understood that the positive power supply voltage VDD and the negative power supply voltage VSS are supplied to each stage of the block book shown in FIG. 9.

First, the start pulse SP, the reset signal RS [2], and the clock signal CLK are applied to the first stage 100. The start pulse SP corresponds to a carry signal for controlling the on / off operation of the first transistor M1 of FIG. 3 or 8. By the above-described operations, the first stage outputs the scan signal SCAN [1] and the carry signal CR [1].

The carry signal CR [1], the inverted clock signal / CLK and the reset signal RS [3] generated in the first stage 100 are input to the second stage 110. According to the operation already described, the second stage 110 outputs the scan signal SCAN [2] and the carry signal CR [2]. The reset signal RS [2] is also output. The reset signal RS [2] is generated at the same output terminal as the carry signal CR [2]. That is, the carry signal CR [2] and the reset signal RS [2] are substantially the same. The generated carry signal CR [2] is input to the third stage and the reset signal RS [2] is input to the first stage 100.

The above operation is also performed in time series in subsequent stages 110, 120, 130, and 140.

In addition, in the nth stage 140 which is the last stage, the carry signal CR [n-1] is received from the n-1th stage, and the clock signal CLK or the inverted clock signal / CLK is received. The reception of the clock signal CLK or the inverted clock signal / CLK is determined by whether the n-th stage 140 is odd or even. That is, the odd-numbered clock signal CLK is inputted, and the odd-numbered clock signal CLK / CLK is inputted. In addition, the reset signal ERS is applied to the n-th stage 140.

If the reset signal ERS is not used for the n-th stage 140, the last stage is used as a dummy stage. That is, it may be configured to operate only with a function of forming a reset signal and not use the generated scan signal.

FIG. 10 is a timing diagram illustrating an operation of the scan driving device of FIG. 9 in accordance with a preferred embodiment of the present invention.

By the arrangement of the stages described above, the scan signals SCAN [1, 2, ..., n] are sequentially output from the stages.

Therefore, the scan supply apparatus according to the present invention forms a scan signal using one clock signal and a clock signal inverted from the clock signal. In addition, each stage constituting the scanning supply apparatus uses the shift register of Figs. Therefore, there is an advantage that scan signals can be formed even through a simple circuit configuration.

1 is a block diagram showing a conventional scanning drive device.

FIG. 2 is a timing diagram for describing an operation of the scan driving device of FIG. 1.

3 is a circuit diagram showing a shift register constituting a scan driver according to a preferred embodiment of the present invention.

4 is a timing diagram illustrating the operation of the shift register of FIG. 3 according to a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram for describing an operation of the shift register in the section T1 of FIG. 4.

FIG. 6 is a circuit diagram for describing an operation of a shift register in a period T2 of FIG. 4.

FIG. 7 is a circuit diagram for describing an operation of a shift register in a period T3 of FIG. 4.

Fig. 8 is a circuit diagram showing another shift register constituting the scan drive device according to the preferred embodiment of the present invention.

FIG. 9 is a block diagram illustrating a scan driving apparatus using the shift register shown in FIGS. 3 and 8 according to a preferred embodiment of the present invention.

FIG. 10 is a timing diagram illustrating an operation of the scan driving device of FIG. 9 in accordance with a preferred embodiment of the present invention.

Claims (7)

A first transistor connected to the first node for receiving a negative power supply voltage and performing an on / off operation according to a previous carry signal; A second transistor configured to receive a clock signal or an inverted clock signal and perform an on / off operation according to the voltage of the first node to form a scan signal; A third transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a carry signal or a reset signal; A fourth transistor connected to the first node for receiving a positive power supply voltage and subsequently performing an on / off operation according to a reset signal; A first capacitor coupled between the positive power supply voltage and the first node; And And a second capacitor coupled between the first node and the second transistor and configured to regulate a voltage of the first node through coupling. The shift register of claim 1, wherein the first to fourth transistors are PMOS transistors. The fifth driving circuit of claim 1, wherein the shift register is configured to perform an on / off operation according to a voltage of the first node, and to transfer the clock signal or the inverted clock signal to the second transistor and the third transistor. The shift register further comprises a transistor. delete In the scanning driving apparatus having a plurality of stages arranged in sequence, and forming a plurality of scanning signals delayed by one half clock, A first stage for receiving a clock signal and generating a first scan signal and a first carry signal according to an on / off operation according to an applied start pulse and a reset signal; And Receives the inverted clock signal, the first carry signal, and a third carry signal generated at a later stage to generate a second scan signal, a second carry signal, and the second reset signal, which are delayed by a half clock with the first scan signal. Including a second stage for The first stage or the second stage, A first transistor connected to the first node for receiving a negative power supply voltage and performing an on / off operation according to a previous carry signal; A second transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a scan signal; A third transistor configured to receive the clock signal or the inverted clock signal and perform an on / off operation according to the voltage of the first node to form a carry signal or a reset signal; A fourth transistor connected to the first node for receiving a positive power supply voltage and subsequently performing an on / off operation according to a reset signal; A first capacitor coupled between the positive power supply voltage and the first node; And And a second capacitor connected between the first node and the second transistor and configured to regulate a voltage of the first node through coupling. The method of claim 5, wherein the scan driver is configured to perform an on / off operation according to the voltage of the first node and to transfer the clock signal or the inverted clock signal to the second transistor and the third transistor. The scanning drive device further comprises a transistor. delete

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