KR100931472B1 - Scan driver and organic light emitting display using the same - Google Patents

Abstract

PURPOSE: A scan driving part and an organic electroluminescent display device using the same are provided to reduce a dimension of a driving circuit by mounting a scan driving circuit which generates a scan signal and a light emitting control driving circuit which generates a light emitting control signal inside one scan driving part. CONSTITUTION: A plurality of stages supplies a light emitting control signal and a scan signal to light emitting control lines and scan lines corresponding to light emitting clock signals and scan clock signals supplied from outside. Each stage includes a first sub stage(SST1) and a second sub stage(SST2). The first sub stage outputs a first output signal and a second output signal corresponding to at least two light emitting clock signals having an opposite wavelength among the light emitting clock signals. The second sub stage outputs a scan signal corresponding to at least one among the scan clock signals and the second output signal from the first sub stage.

Description

Scan driver and organic light emitting display using the same {Scan Driver and Organic Light Emitting Display Using the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan driver and an organic light emitting display device using the same, and more particularly, to a scan driver and an organic light emitting display device using the same to reduce the area of a driving circuit and to improve driving force.

Recently, development of an organic light emitting display (OLED) that is light in weight and capable of driving at low response speed and with low power consumption has been actively developed. An organic light emitting display is a type of flat panel display that displays an image using an organic light emitting diode that generates light by recombination of electrons and holes.

Such an organic light emitting display device generates light by supplying a current corresponding to a data signal to an organic light emitting diode using a transistor formed for each pixel to display an image.

To this end, the organic light emitting display device includes a pixel unit including a plurality of pixels, a data driver supplying a data signal to the pixels, and a scan driver supplying a scan signal to the pixels. The pixels included in the pixel portion are selected when the scan signal is supplied to the scan line to receive the data signal from the data line. The pixels supplied with the data signal display an image while generating light of luminance corresponding to the data signal.

On the other hand, the organic light emitting display device may further include a light emission control driver for supplying a light emission control signal to the pixels. The emission control signal is supplied to set the pixels to a non-emission state while the initialization signal and the data signal are supplied to the pixels, and to control the emission time. To this end, the emission control signal is supplied overlapping with the previous scan signal and the current scan signal to prevent light emission of the pixels, and when the supply of the data signal is completed, the light emission control signal transitions to the opposite polarity to emit light.

In general, such a light emission control signal is generated in a circuit separate from the circuit in which the scan signal is generated and supplied to the pixels. That is, conventionally, a scan driver for generating a scan signal and a light emission control driver for generating a light emission control signal are respectively formed and operated individually. As a result, a problem arises in that the area occupied by the driving circuit increases.

In particular, in the case of a large panel, in order to prevent a driving failure due to a signal delay caused by an increase in the load of the scan line and the light emission control line, both the scan driver and the light emission control driver are disposed on both sides of the panel to improve driving force. However, according to this, the area occupied by the driving circuit increases, which causes a problem in that many restrictions occur in the design.

Accordingly, an object of the present invention is to provide a scan driver and an organic light emitting display device using the same, which can improve driving force while reducing the area of a driving circuit.

In order to achieve the above object, the first aspect of the present invention is dependently connected to an input terminal of a start pulse and emits light control signals and light emission control signals in response to light emission clock signals and scan clock signals supplied from the outside. And a plurality of stages for supplying a scan signal, each stage comprising: at least two light emitting clock signals having waveforms opposite to each other among the output signal from the start pulse or the previous stage and the light emitting clock signals; A first sub-stage corresponding to the emission control signal (first output signal) and a second output signal having a waveform opposite to the emission control signal, the second output signal and the scan from the first sub-stage; A second sub-stage outputting the scan signal in response to at least one of clock signals; Provides a scan driver.

Here, the second sub-stage is set to the voltage level of the scan clock signal supplied to the second sub-stage corresponding to the second output signal set to a low level while the high-level emission control signal is output from the first sub-stage. The scanning line can be charged.

In addition, a second aspect of the present invention provides a pixel portion including a plurality of pixels positioned at intersections of scan lines, light emission control lines, and data lines, and a scan signal and light emission control signal using the scan lines and light emission control lines, respectively. And a scan driver to supply a data signal to the data lines, the scan driver being connected to an input terminal of a start pulse and corresponding to light emitting clock signals and scan clock signals supplied from the outside. And a plurality of stages for supplying a light emission control signal and a scan signal to the light emission control lines and the scan lines, respectively, wherein each of the stages is an output signal from the start pulse or the previous stage and one of the light emission clock signals. The emission control signal (first output signal) corresponding to at least two emission clock signals having opposite waveforms; And a first sub-stage for outputting a second output signal having a waveform opposite to the light emission control signal, and the scan corresponding to at least one of the second output signal and the scan clock signals from the first sub-stage. An organic light emitting display device including a second sub-stage for outputting a signal is provided.

According to the present invention, the output signal of the emission control driver circuit for generating the emission control signal can be used as an input signal of the scan driver circuit, and the stage circuits of the two driver circuits can be combined into one stage circuit. .

Accordingly, the driving force can be improved while reducing the area of the driving circuit by incorporating the scan driving circuit for generating the scan signal and the light emission control driving circuit for generating the light emission control signal in one scan driver.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a block diagram illustrating a schematic configuration of an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1, an organic light emitting display device according to an exemplary embodiment of the present invention includes a scan driver 10, a data driver 20, a pixel unit 30, and a timing controller 50.

The scan driver 10 sequentially controls the scan signal and the emission control signal to the scan lines S1 to Sn and the emission control lines E1 to En while being controlled by the timing controller 50. Then, the pixels 40 are selected by the scan signal and are sequentially set to the non-emission state by the emission control signal while being sequentially supplied with the data signal. On the other hand, the pixels 40 emit light at luminance corresponding to the data signal by the emission control signal transitioned to the opposite polarity after the supply of the data signal is completed.

However, in this embodiment, the scan driver 10 is disposed on both sides of the pixel unit 30 to supply the scan signal and the emission control signal to the pixel unit 30 in both directions. That is, in this embodiment, the two scan drivers 10 are simultaneously driven to supply the scan signal and the emission control signal to the respective scan lines S1 to Sn and the emission control lines E1 to En in both directions. In this way, if the scan driver 10 is designed on both sides of the pixel unit 30, a driving error can be prevented even in a large panel having a large load. However, the present invention is not limited thereto. For example, the scan driver 10 may be disposed only on one side of the pixel unit 30.

The data driver 20 supplies a data signal to the data lines D1 to Dm while being controlled by the timing controller 50. Here, the data driver 20 supplies a data signal to the data lines D1 to Dm whenever the scan signal is supplied. Then, the pixels 20 charge a voltage corresponding to the data signal.

The pixel unit 30 includes a plurality of pixels 40 positioned at intersections of the scan lines S1 to Sn, the emission control lines E1 to En, and the data lines D1 to Dm. The pixel unit 30 receives the first and second pixel power sources ELVDD and ELVSS from the outside, and the first and second pixel power sources ELVDD and ELVSS are transferred to the respective pixels 40. Then, the pixels 40 emit light with luminance corresponding to the data signal to display an image.

The timing controller 50 generates a scan drive control signal and a data drive control signal in response to a synchronization signal supplied from the outside. As a result, the timing controller 50 controls the scan driver 10 and the data driver 20. In addition, the timing controller 50 transfers data supplied from the outside to the data driver 20. Then, the data driver 20 generates a data signal corresponding to the data.

FIG. 2 is a block diagram showing a schematic configuration of the scan driver shown in FIG. 1. 3 is a waveform diagram illustrating a driving waveform supplied to the stages illustrated in FIG. 2.

First, referring to FIG. 2, the scan driver 10 is dependently connected to an input terminal of the start pulse ESP and supplies a scan signal and a light emission control signal to the scan lines S and the light emission control lines E, respectively. Stages ST are provided.

Each stage ST includes a first sub-stage SST1 for generating a light emission control signal, and second and third sub-stages SST2 and SST3 for generating a scan signal.

However, in the present exemplary embodiment, it is assumed that the same emission control signal is simultaneously output to two consecutive emission control lines E in the first sub-stage SST1. In this case, the pulse width of the emission control signal generated in the first sub-stage SST1 may be determined by the pixels of the pixels during the initialization and / or data writing periods of the continuous pixels connected to the emission control lines E from which the emission control signal is output. It is set to a width sufficient to prevent light emission.

In addition, the second and third sub-stages SST2 and SST3 sequentially generate the scan signals using the output signals output from the first sub-stage SST1 and output them as successive pixels.

For example, the first sub-stage SST1 of the first stage ST1 may simultaneously output the same emission control signal to the first and second emission control lines E1 and E2. The second and third sub-stages SST2 and SST3 driven by receiving the output signal from the first sub-stage SST are sequentially scanned through the zeroth and first scan lines S0 and S1, respectively. You can print

However, the present invention is not limited thereto. For example, each first sub-stage SST1 may output the emission control signal only through one emission control line E. FIG. In this case, each stage ST may be composed of only the first and second sub-stages SST1 and SST2 for outputting the emission control signal and the scan signal to one emission control line E and the scan line S. FIG. .

The operation of the scan driver 10 described above will be described in detail with reference to the driving waveform shown in FIG. 3. , SCLK2 and SCLK3 are supplied to the stages ST.

Here, the start pulse ESP is supplied to the first sub-stage SST1 of the first stage ST1. The first light emitting clock signal ECLK1 and the inverted first light emitting clock signal ECLK1B are supplied to the first sub-stage SST1 of the odd stages ST1, ST3,... The second emission clock signal ECLK2 is a clock signal in which the first emission clock signal ECLK1 is phase-delayed by a predetermined period, and the second emission clock signal ECLK2 and the inverted second emission clock signal ECLK2B are The first sub-stage SST1 of even-numbered stages ST2, ST4,... Is supplied. Also, the first to third scan clock signals SCLK1 to SCLK3 are clock signals that are sequentially shifted by one horizontal period 1H, and any one of them is a second or third sub-stage ( SST2 and SST3) are selectively supplied. However, since the second and third sub-stages SST2 and SST3 are for sequentially outputting scan signals to the scan lines S, they are the phase delayed scan clock signals in the order of the scan lines S connected thereto. SCLK1, SCLK2 or SCLK3).

When the start pulse ESP and the emission clock signals ECLK1 and ECLK1B are supplied to the first sub-stage SST1 of the first stage ST1, the first sub-stage SST1 corresponds to the first and second substages SST1. The emission control signal (first output signal) is output to the emission control lines E1 and E2. In addition, the first sub-stage SST1 is the second and third sub-stages SST1 and SST2 and the second stage ST2 included in the same stage ST1, and the second output signal having a waveform opposite to the emission control signal. Outputs

Then, the second and third sub-stages SST2 and SST3 use the second output signal from the first sub-stage SST1 and the scan clock signals SCLK3 and SCLK1 from the timing controller 50. Scan signals are sequentially output to the first scan lines S0 and S1.

In addition, the second stage ST2 uses the second output signal supplied from the first sub-stage SST1 of the first stage ST1 as a start pulse in the same manner as the first stage ST1 to perform the third and second operations. The emission control signal and the scan signal are output to the fourth emission control lines E3 and E4 and the second and third scan lines S2 and S3, respectively.

The remaining stages ST also operate in the above-described manner and sequentially output the emission control signal and the scan signal to the emission control lines E and the scan lines S. FIG.

FIG. 4 is a circuit diagram illustrating a first embodiment of a circuit included in the stage illustrated in FIG. 2. For convenience, FIG. 4 shows a first stage and will be described in detail.

Referring to FIG. 4, the first stage ST1 sequentially scans the scan signal to the first sub-stage SST1 that outputs the emission control signal to the emission control lines E1 and E2 and the scan lines S0 and S1. And second and third sub-stages SST2 and SST3 for output.

The first sub-stage SST1 includes an input unit 12 and an output unit 14.

The input unit 12 includes a first light emission clock signal ECLK1 supplied from a first input terminal, an inverted first light emission clock signal ECLK1B supplied from a second input terminal, and a start pulse supplied from a third input terminal. In response to the ESP, either one of the first signal (high level) and the second signal (low level) are supplied. To this end, the input unit 12 includes the first to third transistors M1 to M3 and the first capacitor C1.

The first transistor M1 is connected between the first power supply VDD and the first node N1, and the gate electrode of the first transistor M1 is connected to the first input terminal. Here, the first input terminal is a terminal receiving the first light emitting clock signal ECLK1. The first transistor M1 is turned on when the first light emitting clock signal ECLK1 (low level) is supplied to supply the voltage of the first power source VDD to the first node N1.

The second transistor M2 is connected between the first node N1 and the second input terminal, and the gate electrode of the second transistor M2 is the first electrode and the first capacitor C1 of the third transistor M3. Is connected to. Here, the second input terminal is a terminal receiving the inverted first light emitting clock signal ECLK1B. The second transistor M2 is turned on or turned off in response to the voltage charged in the first capacitor C1.

The third transistor M3 is connected between the gate electrode of the second transistor M2 and the common node of the first capacitor C1 and the third input terminal. Here, the third input terminal is a terminal receiving the start pulse ESP. The gate electrode of the third transistor M3 is connected to the first input terminal. The third transistor M3 is turned on when the first light emitting clock signal ECLK1 (low level) is supplied, so that the third transistor M3 is connected to the common node of the gate electrode of the second transistor M2 and the first capacitor C1. 3 Connect the input terminal electrically.

The first capacitor C1 is connected between the gate electrode of the second transistor M2 and the first electrode. The first capacitor C1 may be turned on when the third transistor M3 is turned on and the start pulse ESP (low level) is supplied to the third input terminal. Charge the voltage, otherwise do not charge the voltage.

The output unit 14 controls whether the emission control signal is generated (or the voltage level of the emission control signal) in response to the first signal (high level) and the second signal (low level) supplied from the input unit 12. More specifically, the output unit 14 outputs the light emission control signal (high level) when the second signal is supplied to the first node N1, and otherwise does not output the light emission control signal (that is, light emission). The voltage level of the control signal is set to low level.

To this end, the output unit 14 includes fourth, sixth and eighth transistors M4, M6, and M8 connected to the first power source VDD and fifth and seventh devices connected to the second power source VSS. And a second capacitor C2 connected between the ninth transistors M5, M7, and M9 and the gate electrode and the first electrode of the ninth transistor M9.

The fourth transistor M4 is connected between the first power supply VDD and the second node N2, and the gate electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 is turned on when a low level voltage is applied to the first node N1 to supply the voltage of the first power supply VDD to the second node N2, and in other cases. Is turned off.

The fifth transistor M5 is connected between the second node N2 and the second power supply VSS, and the gate electrode of the fifth transistor M5 is connected to the first input terminal. The fifth transistor M5 is turned on when the first light emission clock signal ECLK1 having a low level lower than the voltage level of the second node N2 is supplied to the first input terminal. The voltage of the second power source VSS is supplied, and is turned off in other cases.

The sixth transistor M6 is connected between the first power supply VDD and the third node N3, and the gate electrode of the sixth transistor M6 is connected to the second node N2. The sixth transistor M6 is turned on when a low level voltage is applied to the second node N2, and supplies the voltage of the first power source VDD to the third node N3. Is turned off.

The seventh transistor M7 is connected between the third node N3 and the second power supply VSS, and the gate electrode of the seventh transistor M7 is connected to the first node N1. The seventh transistor M7 is turned on when a low level voltage is applied to the first node N1, and supplies the voltage of the second power supply VSS to the third node N3. Is turned off.

The eighth transistor M8 is connected between the first power supply VDD and the fourth node N4, and the gate electrode of the eighth transistor M8 is connected to the third node N3. The eighth transistor M8 is turned on when a low level voltage is applied to the third node N3 to supply the voltage of the first power supply VDD to the fourth node N4, and in other cases. Is turned off. Here, since the fourth node N4 is connected to the emission control lines E1 and E2, when the eighth transistor M8 is turned on, a high level emission control signal is supplied to the emission control lines E1 and E2. .

The ninth transistor M9 is connected between the fourth node N4 and the second power supply VSS, and the gate electrode of the ninth transistor M9 is connected to the second node N2 and the second capacitor C2. do. The ninth transistor M9 is turned on or turned off in response to the voltage level of the second node N2. At this time, when the ninth transistor M9 is turned on, the voltage of the second power source VSS is supplied to the fourth node N4 to set the voltage level of the emission control signal to a low level.

The second capacitor C2 is connected between the gate electrode of the ninth transistor M9 and the first electrode. The ninth transistor M9 is turned on or turned off in response to the voltage charged in the second capacitor C2.

The second sub-stage SST2 scans the scan line S0 in response to one of the second output signal and the scan clock signals (eg, the third scan clock signal SCLK3) from the first sub-stage SST1. Output the signal. More specifically, the second sub-stage SST2 is formed by the third node N3 set to the low level while the high-level emission control signal is output from the first sub-stage SST1 to the fourth node N4. 2, the scan line SO is charged to the voltage level of the scan clock signal SCLK3 supplied to itself in response to the output signal.

To this end, the second sub-stage SST2 includes the tenth to twelfth transistors M10 to M12 and the third capacitor C3.

The tenth transistor M10 electrically connects the third node N3 and the second sub-stage SST2 of the first sub-stage SST1. For this purpose, the tenth transistor M10 is connected between the third node N3 of the first sub-stage SST1 and the fifth node N5 of the second sub-stage SST2. The gate electrode of the tenth transistor M10 is connected to the second power source VSS. The tenth transistor M10 is turned on in response to the voltage level of the second power supply VSS to supply the voltage of the third node N3 to the fifth node N5.

Here, in the tenth transistor M10, a parasitic capacitor (not shown) of the first sub-stage SST1 and a fourth capacitor C4 of the third sub-stage SST3 may be used to operate the second sub-stage SST2. It is adopted in order not to affect. As a result, the bootstrapping operation of the fifth node N5 is normally performed.

The eleventh transistor M11 is connected between the output terminal of the second sub-stage SST2 and the fourth input terminal, and the gate electrode of the eleventh transistor M11 is connected to the fifth node N5. The fourth input terminal is a terminal to which the third scan clock signal SCLK3 is input.

The eleventh transistor M11 is turned on when the low level voltage is supplied to the fifth node N5 to transfer the third scan clock signal SCLK3 to the scan line S0. That is, when the eleventh transistor M11 is turned on, the scan signal following the third scan clock signal SCLK3 is output to the scan line S0.

The third capacitor C3 is connected between the fifth node N5 and the scan line SO. The third capacitor C3 turns on the eleventh transistor M11 completely through a bootstrapping action when the third scan clock signal SCLK3 transitions to a low level.

The twelfth transistor M12 is connected between the output terminal of the second sub-stage SST2 and the first power supply VDD, and the gate electrode of the twelfth transistor M12 is the fourth node of the first sub-stage SST1. It is connected to (N4).

The twelfth transistor M12 is turned on when a low level voltage is supplied to the fourth node N4 (that is, when the voltage level of the light emission control signal is low level) to turn on the first power source VDD. The voltage is supplied to the scan line S0.

The third sub-stage SST3 includes thirteenth to fifteenth transistors M13 to M15 and a fourth capacitor C4.

However, the third sub-stage SST3 generates a scan signal in response to the first scan clock signal SCLK1 supplied from the fifth input terminal. Since it is the same as the second sub-stage SST2, a detailed description thereof will be omitted.

In this case, the scan clock signals SCLK3, SCLK1 or SCLK2 input to the second and third sub-stages SST2 and SST3 are supplied in a shifted form by one horizontal period in the order of the scan lines S. . For example, when the first to third scan clock signals SCLK1, SCLK2, and SCLK3 are supplied in a shifted form by one horizontal period and are clock signals having the same period, the third scan clock is transmitted to the second sub-stage SST2. The signal SCLK3 may be supplied, and the first scan clock signal SCLK1 shifted by one horizontal period compared to the third scan clock signal SCLK3 may be supplied to the third sub-stage SST3.

As a result, the second and third sub-stages SST2 and SST3 sequentially scan the scan lines S0 to S1 in response to the output signal from the first sub-stage SST1 and the scan clock signals SCLK3 and SCLK1. Generate a signal.

Meanwhile, in FIG. 4, the first sub-stage SST1 and the second and third sub-stages SST2 and SST3 have the same high level voltage source (first power supply VDD) and low level voltage source (second power source VSS). Although shown as being driven by), the present invention is not limited thereto.

For example, the high level voltage source and the low level voltage source of the first sub-stage SST1 are set to EVDD and EVSS, respectively, and the high level voltage source and the low level voltage source of the second and third sub-stages SST2 and SST3 are respectively. It may be set to SVDD and SVSS. A more detailed description thereof will be described later.

5A through 5E are circuit diagrams illustrating a driving process of the stage illustrated in FIG. 4.

Hereinafter, the driving process of the stage circuit according to the first embodiment will be described in detail with the waveform diagram shown in FIG. 3 and the stage circuit shown in FIGS. 4 to 5E.

First, during the first period T1 of FIG. 3, the start pulse ESP and the first emission clock signal ECLK1 are set to a low level voltage, and the inverted first emission clock signal ECLK1B is set to a high level voltage. do.

In this case, as illustrated in FIG. 5A, the first and third transistors M1 and M3 are turned on by the first light emission clock signal ECLK1.

When the first transistor M1 is turned on, the voltage of the first node N1 becomes the voltage of the first power supply VDD. That is, the voltage of the first signal (high level) is applied to the first node N1.

When the third transistor M3 is turned on, a low level voltage is applied to the gate electrode of the second transistor M2 by the start pulse ESP which is set to a low level voltage during the first period T1. The two transistors M2 are turned on.

In this case, the first capacitor C1 charges the voltage difference between the voltage of the first power supply VDD applied to the first node N1 and the low level applied to the gate electrode of the second transistor M2. Here, the low level voltage of the start pulse ESP may be set to the voltage of the second power supply VSS lower than the voltage of the first power supply VDD.

When the second transistor M2 is turned on, the high level voltage of the inverted first light emitting clock signal ECLK1B is supplied to the first node N1. Here, the high level voltage of the inverted first light emitting clock signal ECLK1B may be set equal to the voltage of the first power supply VDD. Then, even when the first and second transistors M1 and M2 are turned on at the same time, the voltage of the first node N1 can be stably maintained at a high level.

When the voltage of the first signal is applied to the first node N1, the fourth and seventh transistors M4 and M5 are turned off.

However, the fifth transistor M5 maintains the turn-off state by the voltage stored in the second capacitor C2 even when the first light emitting clock signal ECLK1 maintains the low level. The process of charging the voltage will be described later.) That is, the voltage of the first electrode of the fifth transistor M5 is set lower than the low level voltage of the first light emission clock signal ECLK1 by the second capacitor C2. As a result, the fifth transistor M5 is maintained in the turn-off state.

On the other hand, the sixth transistor M6 maintains the turn-on state by the voltage applied to the second node N2 (ie, the voltage charged in the second capacitor C2). As a result, the voltage of the first power VDD is applied to the third node N3.

When the voltage of the first signal is applied to the third node N3, the eighth transistor M8 is turned off while the voltages of the first signal are transferred to the fifth and sixth nodes N5 and N6. Accordingly, the eleventh and fourteenth transistors M11 and M14 maintain a turn-off state.

However, the ninth transistor M9 maintains the turn-on state by the voltage charged in the second capacitor C2. Accordingly, the voltage of the second power source VSS is applied to the fourth node N4 so that the emission control lines E1 and E2 maintain the output voltage of the second power source VSS. In this case, since the voltage enough to turn on the ninth transistor M9 is sufficiently stored in the second capacitor C2, the voltages of the light emission control lines E1 and E2 may be up to the voltage of the second power source VSS. Pulled down.

In addition, as the voltage of the second signal (low level) is applied to the fourth node N4, the twelfth and fifteenth transistors M12 and M15 are turned on. Accordingly, the scan lines S0 and S1 maintain the output voltage of the first power source VDD.

Thereafter, during the second period T2, the first light emitting clock signal ECLK1 and the inverted first light emitting clock signal ECLK1B transition to high and low level voltages, respectively, and the start pulse ESP applies a low level voltage. Keep it.

In this case, as illustrated in FIG. 5B, the first, third, and fifth transistors M1, M3, and M5 are turned off by the first light emission clock signal ECLK1. In this case, the second transistor M2 is turned on by the voltage charged in the first capacitor C1 in the previous period T1. Accordingly, the low level voltage of the inverted first light emission clock signal ECLK1B is applied to the first node N1.

When the voltage of the second signal (low level) is applied to the first node N1, the fourth and seventh transistors M4 and M7 are turned on.

When the fourth transistor M4 is turned on, the voltage of the second node N2 is increased to the voltage of the first power supply VDD. As a result, the sixth and ninth transistors M6 and M9 are turned off.

When the seventh transistor M7 is turned on, the voltage of the third node N3 is reduced to the voltage of the second power source VSS. Accordingly, the eighth transistor M8 is turned on while the voltages of the fifth and sixth nodes N5 and N6 are lowered to the low level voltage.

When the eighth transistor M8 is turned on, the voltage of the first power source VDD is applied to the fourth node N4. Accordingly, a high level emission control signal is supplied to the emission control lines E1 and E2.

On the other hand, when the eighth transistor M8 is turned on, the voltage of the first signal (high level) is applied to both electrodes of the second capacitor C2, so that the voltage is applied to the second capacitor C2 during the second period T2. It is not charged.

When the voltages of the second signal (low level) are applied to the fifth and sixth nodes N5 and N6, the eleventh and fourteenth transistors M11 and M14 are turned on. Accordingly, the high level voltages of the third scan clock signal SCLK3 and the first scan clock signal SCLK1 are supplied to the zeroth and first scan lines S0 and S1, respectively.

Here, the high level voltages of the third scan clock signal SCLK3 and the first scan clock signal SCLK1 may be set to the same value as the voltage of the first power source VDD. In this case, the scan lines S0 and S1 maintain the output voltage of the first power source VDD.

Thereafter, during the third to fifth periods T3 to T5, the first emission clock signal ECLK1 and the inverted first emission clock signal ECLK1B are maintained at high and low level voltages, respectively, and the start pulse ESP is performed. Transitions to a high level voltage.

During the third to fifth periods T3 to T5, the third transistor M3 is turned off by the first light emission clock signal ECLK1, and thus regardless of the voltage level of the start pulse ESP. The stage ST circuit maintains the previous state.

However, during the third period T3, the third scan clock signal SCLK3 transitions from the high level voltage to the low level voltage. In this case, the voltage of the fifth node N5 is increased by the bootstrapping effect of the parasitic capacitor (not shown) inside the third capacitor C3 and the eleventh transistor M11. The voltage drops below the voltage. Accordingly, as illustrated in FIG. 5C, the third scan clock signal SCLK3 is transmitted to the zeroth scan line S0 as it is through the eleventh transistor M11, and the voltage level of the zeroth scan line S0 reaches a low level. Full swing Therefore, a low level scan signal is output to the zeroth scan line S0 during the third period T3. At this time, since the first scan clock signal SCLK1 is maintained at the high level voltage, the first scan line S1 is maintained at the high level voltage state.

Thereafter, during the fourth period T4, the third scan clock signal SCLK3 transitions to the high level voltage and the first scan clock signal SCLK1 transitions to the low level voltage. When the third scan clock signal SCLK3 transitions to the high level voltage, the voltage of the fifth node N5 returns to the same voltage level as the second period T2, and as shown in FIG. 5D, the zeroth scan line S0. ) Is raised to a high level voltage. When the first scan clock signal SCLK1 transitions to the low level voltage, the sixth node may be caused by a bootstrapping effect by parasitic capacitors (not shown) inside the fourth capacitor C4 and the fourteenth transistor M14. The voltage of N6) is lowered to a voltage lower than the voltage of the second power supply VSS. Accordingly, as shown in FIG. 5D, the first scan clock signal SCLK1 is transmitted to the first scan line S1 as it is through the fourteenth transistor M14, and the voltage level of the first scan line S1 reaches a low level. Full swing Therefore, a low level scan signal is output to the first scan line S1 during the fourth period T4.

Thereafter, all of the third and first scan clock signals SCLK3 and SCLK1 are maintained at the high level voltage during the fifth period T5. Accordingly, during the fifth period T5, the high-level emission control signal is supplied to the emission control lines E1 and E2 in the same manner as the second period T2 as shown in FIG. 5B, and the scan lines S0 and S1 maintains the output voltage of the first power supply VDD.

Thereafter, during the sixth period T6, the first light emitting clock signal ECLK1 and the inverted first light emitting clock signal ECLK1B transition to low and high level voltages, respectively, and the start pulse ESP receives the high level voltage. Keep it.

In this case, as illustrated in FIG. 5E, the first, third, and fifth transistors M1, M3, and M5 are turned on by the first light emission clock signal ECLK1.

When the first transistor M1 is turned on, the voltage of the first node N1 is increased to the voltage of the first power source VDD. That is, the voltage of the first signal (high level) is applied to the first node N1. As a result, the fourth and seventh transistors M4 and M7 are turned off.

When the third transistor M3 is turned on, since the start pulse ESP set to the high level voltage is supplied to the gate electrode of the second transistor M2, the second transistor M2 is turned off.

At this time, since the voltage of both electrodes of the first capacitor C1 is set to the voltage of the first power source VDD, the voltage is not charged to the first capacitor C1. In fact, the first capacitor C1 charges a predetermined voltage only when the start pulse ESP is set to a low level voltage, and otherwise does not charge the voltage.

On the other hand, when the fifth transistor M5 is turned on, the voltage of the second node N2 is pulled down to the voltage of VSS + | Vth5│ (│Vth5│ is the threshold voltage of the fifth transistor M5). After the voltage of the second node N2 is down to the voltage of VSS + | Vth5 |, the fifth transistor M5 is turned off. At this time, VDD- (VSS + │Vth5│) is applied to the second capacitor C2 by the voltage of VSS + │Vth5│ applied to the second node N2 and the first power supply VDD applied to the fourth node N4. The above voltage is charged.

Thereafter, the ninth transistor M9 is turned on by the voltage stored in the second capacitor C2, and the voltage of the second power source VSS is applied to the fourth node N4. Accordingly, the voltages of the emission control lines E1 and E2 are pulled down to the low level voltage of the second power supply VSS. The twelfth and fifteenth transistors M12 and M15 are turned on so that the scan lines S0 and S1 are charged to a high level voltage.

Meanwhile, the sixth transistor M6 is turned on in response to the voltage of the second node N2, and the voltage of the first power source VDD is applied to the third node N3.

Accordingly, the eighth transistor M8 is turned off while the voltage of the first signal (high level) is applied to the fifth and sixth nodes N5 and N6. As a result, the eleventh and fourteenth transistors M11 and M14 maintain the turn-off state.

According to the present invention, the output signal of the light emission control driver circuit (i.e., the first sub-stage SST1) which generates the light emission control signal is converted into the scan driver circuits (i.e., the second to third sub-stages SST2 and SST3). In addition to using as an input signal, the stage circuits of the two driving circuits may be combined into one stage ST circuit. That is, the scan driving circuit for generating the scan signal and the light emission control driving circuit for generating the light emission control signal may be incorporated in one scan driver 10.

In addition, after the third scan clock signal SCLK3 transitions to the high level, the fifth and second horizontal periods 2H and the first scan clock signal SCLK1 become the high level, respectively, during the fifth horizontal clock period 1H. The voltage levels of the sixth nodes N5 and N6 are maintained at a low level. Therefore, since the transition of the scan clock signals SCLK3 and SCLK1 to the high level is sufficient to be transmitted to the scan lines S0 and S1 through the eleventh and fourteenth transistors M11 and M14, the twelfth and fifteenth transistors ( Even if M12 and M15 are not formed large, the voltage level of the scan signal is stably transitioned after the interval between the syringes of the respective scan lines S0 and S1 is completed. That is, according to the present invention, the size of the buffer transistors (that is, the twelfth and fifteenth transistors M12 and M15) can be reduced.

As described above, in the present invention, the scan driving circuit and the light emission control driving circuit may be incorporated in one scan driving unit 10, and the size of the buffer transistor may be reduced to reduce the area occupied by the driving circuit.

In addition, as the area of the driving circuit can be reduced, the space for forming the circuit can be easily secured, so that the scan driving units 10 are mounted on both sides of the panel, and the buffer transistors of the other driving circuits are largely formed in the secured area. It is also possible to improve the driving force such that the operating speed is improved.

Meanwhile, in the present embodiment, for convenience, the first to third sub-stages SST1 to SST3 are driven by the same reference power source, that is, the first power source VDD that is the same high level voltage source and the second power source VSS that is the low level voltage source. Although described as being driven, the present invention is not limited thereto.

For example, a high level voltage source and / or a low level having different potentials are provided in the first sub-stage SST1 for generating the emission control signal and the second to third sub-stages SST2, SST3 for generating the scan signal. The voltage source can be supplied. In this case, the high level and / or low level potentials of the light emission control signal and the scan signal may be different from each other by the reference power supply. In addition, the voltage range of the scan signal may also be adjusted by adjusting the voltage level of the scan clock signal SCLK. That is, in the foregoing description, the high level and low level voltages of the scan clock signal SCLK are assumed to be set equal to the voltage levels of the first power source VDD and the second power source VSS, respectively. As shown in the embodiment, the high level and low level voltages of the scan clock signal SCLK may be arbitrarily changed by the designer.

That is, even when the stage for generating the emission control signal and the stage for generating the scan signal are implemented in one stage circuit as in the present invention, it is possible to set the voltage ranges of the scan signal and the emission control signal differently.

Hereinafter, other embodiments of the stage circuit according to the present invention will be described with reference to FIGS. 6 to 8. However, when describing other embodiments of the present invention, the same reference numerals are given to the same parts as in the previous embodiment, and a detailed description thereof will be omitted.

FIG. 6 is a circuit diagram illustrating a second embodiment of a circuit included in the stage illustrated in FIG. 2.

Referring to FIG. 6, in the second embodiment of the present invention, the scan lines S0 and S1 are connected to the first power source VDD when the emission control signal is set to the low level in the above-described first embodiment. The twelfth and fifteenth transistors M12 and M15 are removed from the second and third substages SST2 and SST3.

As described above, even when the twelfth and fifteenth transistors M12 and M15 are removed from the second and third sub-stages SST2 and SST3, the scan signal is stable through the eleventh and fourteenth transistors M11 and M14 as described above. Transitions to a high level. Therefore, even if the stage circuit is constituted as in the second embodiment, there is no problem in substantial circuit driving, and the same effects as in the first embodiment can be obtained.

FIG. 7 is a circuit diagram illustrating a third embodiment of the circuit included in the stage illustrated in FIG. 2.

Referring to FIG. 7, in the third embodiment of the present invention, the tenth and thirteenth transistors M10 and M13 that are connected to the third node N3 in the above-described first embodiment are replaced by the third node M3. Instead, the stage ST circuit is implemented by connecting to the first node N1.

Here, since the voltage levels of the third node N3 and the first node N1 are set to be substantially the same when the stage ST circuit is driven, the stage ST circuit according to the third embodiment includes the first It is driven in the same manner as in the embodiment and has the same effect.

FIG. 8 is a circuit diagram illustrating a fourth embodiment of the circuit included in the stage illustrated in FIG. 2.

Referring to FIG. 8, in the fourth embodiment of the present invention, as in the second embodiment, the twelfth and fifteenth transistors M12 and M15 are removed from the second and third sub-stages SST2 and SST3. As in the third embodiment, the tenth and thirteenth transistors M10 and M13 are connected to the first node N1. Parts other than this are configured in the same manner as the first embodiment and driven in the same manner, and have the same effect. Therefore, detailed description thereof will be omitted.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various modifications are possible within the scope of the technical idea of the present invention.

1 is a block diagram showing a schematic configuration of an organic light emitting display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of the scan driver shown in FIG. 1; FIG.

FIG. 3 is a waveform diagram illustrating driving waveforms supplied to stages shown in FIG. 2. FIG.

4 is a circuit diagram showing a first embodiment of a circuit included in the stage shown in FIG.

5A through 5E are circuit diagrams illustrating a driving process of the stage illustrated in FIG. 4.

FIG. 6 is a circuit diagram showing a second embodiment of the circuit included in the stage shown in FIG.

FIG. 7 is a circuit diagram showing a third embodiment of the circuit included in the stage shown in FIG.

FIG. 8 is a circuit diagram showing a fourth embodiment of the circuit included in the stage shown in FIG.

<Explanation of symbols for the main parts of the drawings>

10: scan driver E: emission control line

S: scanning line ST: stage

SST: Substage

Claims (20)

It is connected to the input terminal of the start pulse dependently, and provided with a plurality of stages for supplying the emission control signal and the scanning signal to the emission control lines and the scanning lines, respectively, corresponding to the emission clock signals and the scan clock signals supplied from the outside, Each of the stages, The emission control signal (first output signal) and the emission control signal in response to an output signal from the start pulse or the previous stage and at least two emission clock signals having waveforms opposite to each other among the emission clock signals; A first sub-stage for outputting a second output signal having an opposite waveform, A second sub-stage outputting the scan signal corresponding to at least one of the second output signal from the first sub-stage and the scan clock signals, The first sub-stage, Among the first signal (high level) or the second signal (low level) to the first node in response to the output signal from the start pulse or the previous stage, the first light emitting clock signal, and the inverted first light emitting clock signal. Which one is supplied; A first transistor connected between a first power supply and the first node and having a gate electrode connected to an input terminal of the first light emitting clock signal; A second transistor connected between the first node and an input terminal of the inverted first light emitting clock signal; A first capacitor connected between the gate electrode of the second transistor and the first node; And a third transistor connected between an input terminal to which the output signal from the start pulse or the previous stage is input and a gate electrode of the second transistor, and a gate electrode connected to an input terminal of the first light emitting clock signal. Input unit, Outputs a high level light emission control signal to a light emission control line when the second signal is input to the first node, and a low level voltage to the light emission control line when the first signal is input to the first node; Outputs; A fourth transistor connected between the first power supply and the second node and having a gate electrode connected to the first node; A fifth transistor connected between the second node and a second power source and having a gate electrode connected to an input terminal of the first light emitting clock signal; A sixth transistor connected between the first power source and a third node and having a gate electrode connected to the second node; A seventh transistor connected between the third node and the second power supply and having a gate electrode connected to the first node; An eighth transistor connected between a fourth node to which the emission control signal is output and the first power source, and a gate electrode connected to the third node; A ninth transistor connected between the fourth node and the second power supply and having a gate electrode connected to the second node; And an output part including a second capacitor connected between the gate electrode and the first electrode of the ninth transistor. The second sub-stage, A tenth transistor connected between a node for outputting the second output signal of the first sub-stage and a fifth node, and a gate electrode connected to the second power source; An eleventh transistor connected between an input terminal of any one of the scan clock signals and a scan line, and a gate electrode connected to the fifth node; And a third capacitor connected between the gate electrode of the eleventh transistor and the scan line. The method of claim 1, The second sub-stage is configured to scan the scan line at a voltage level of a scan clock signal supplied to the second sub-stage corresponding to the second output signal set to a low level while the high-level emission control signal is output from the first sub-stage. Scan driving unit for charging the. delete delete The method of claim 1, And the first sub-stage outputs the same emission control signal to at least two consecutive emission control lines. The method of claim 5, Each of the stages, The second output signal from the first sub-stage and at least one scan clock signal supplied to the second sub-stage among the scan clock signals in a shifted form. And a third sub stage sequentially outputting the scan signal to the sub stage. The third sub stage, A thirteenth transistor connected between a node on which the second output signal of the first sub-stage is output and a sixth node and a gate electrode connected to the second power source; A scan electrode connected between an input terminal of another scan clock signal supplied to the second sub-stage in a shifted form and a scan line next to the scan line to which the second sub-stage is connected; A fourteenth transistor to be connected; And a fourth capacitor connected between the gate electrode of the fourteenth transistor and the next scan line. The method of claim 6, And the second and third sub-stages of the stages are supplied with any one of the first and third scan clock signals sequentially phase-delayed, in the order of the scan lines for outputting the scan signal. The method of claim 1, And the second output signal output from the first sub-stage is input as a start pulse of a first sub-stage provided in a next stage. delete delete delete delete The method of claim 1, And the tenth transistor is connected between the first node and the fifth node or between the third node and the fifth node. The method of claim 1, The second sub-stage, And a twelfth transistor connected to the fourth node and connected between the first power supply and the scan line. The method of claim 1, And a voltage level of the first power supplied to the first sub-stage is different from a voltage level of the high-level voltage source of the second sub-stage. The method of claim 1, And a voltage level of the second power supply supplied to the first sub-stage is different from a voltage level of the low-level voltage source of the second sub-stage. The method of claim 1, And a voltage level of the first power supply or the second power supply of the first sub-stage is different from that of the high level or low level voltage source of the scan clock signals, respectively. A pixel portion including a plurality of pixels positioned at intersections of scan lines, emission control lines, and data lines, a scan driver for supplying a scan signal and emission control signals to the scan lines and emission control lines, respectively; A data driver for supplying a data signal to the The scan driver may be connected to an input terminal of the start pulse and may be configured to supply a light emission control signal and a scan signal to the light emission control lines and the scan lines, respectively, in response to light emission clock signals and scan clock signals supplied from the outside. Including them, Each of the stages, The emission control signal (first output signal) and the emission control signal in response to an output signal from the start pulse or the previous stage and at least two emission clock signals having waveforms opposite to each other among the emission clock signals; A first sub-stage for outputting a second output signal having an opposite waveform, A second sub-stage outputting the scan signal corresponding to at least one of the second output signal from the first sub-stage and the scan clock signals, The first sub-stage, Among the first signal (high level) or the second signal (low level) to the first node in response to the output signal from the start pulse or the previous stage, the first light emitting clock signal, and the inverted first light emitting clock signal. Which one is supplied; A first transistor connected between a first power supply and the first node and having a gate electrode connected to an input terminal of the first light emitting clock signal; A second transistor connected between the first node and an input terminal of the inverted first light emitting clock signal; A first capacitor connected between the gate electrode of the second transistor and the first node; And a third transistor connected between an input terminal to which the output signal from the start pulse or the previous stage is input and a gate electrode of the second transistor, and a gate electrode connected to an input terminal of the first light emitting clock signal. Input unit, Outputs a high level light emission control signal to a light emission control line when the second signal is input to the first node, and a low level voltage to the light emission control line when the first signal is input to the first node; Outputs; A fourth transistor connected between the first power supply and the second node and having a gate electrode connected to the first node; A fifth transistor connected between the second node and a second power source and having a gate electrode connected to an input terminal of the first light emitting clock signal; A sixth transistor connected between the first power source and a third node and having a gate electrode connected to the second node; A seventh transistor connected between the third node and the second power supply and having a gate electrode connected to the first node; An eighth transistor connected between a fourth node to which the emission control signal is output and the first power source, and a gate electrode connected to the third node; A ninth transistor connected between the fourth node and the second power supply and having a gate electrode connected to the second node; And an output part including a second capacitor connected between the gate electrode and the first electrode of the ninth transistor. The second sub-stage, A tenth transistor connected between a node for outputting the second output signal of the first sub-stage and a fifth node, and a gate electrode connected to the second power source; An eleventh transistor connected between an input terminal of any one of the scan clock signals and a scan line, and a gate electrode connected to the fifth node; And a third capacitor connected between the gate electrode of the eleventh transistor and the scan line. The method of claim 18, The second sub-stage is configured to scan the scan line at a voltage level of a scan clock signal supplied to the second sub-stage corresponding to the second output signal set to a low level while the high-level emission control signal is output from the first sub-stage. An organic light emitting display that charges. The method of claim 18, And the scan driver is disposed on both sides of the pixel unit to supply the scan signal and the emission control signal to the pixel unit in both directions.

Images