CN112735315B

CN112735315B - Display panel and display device

Info

Publication number: CN112735315B
Application number: CN202011627772.XA
Authority: CN
Inventors: 陈惠莹; 邹宗骏; 孙莹; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2024-04-02
Anticipated expiration: 2040-12-31
Also published as: CN112735315A

Abstract

The application discloses a display panel and a display device, which relate to the technical field of display, and are provided with a display area and a non-display area, wherein the first scanning line and the second scanning line are positioned in the display area, the first scanning line comprises a first end and a second end, the second scanning line comprises a first end and a second end, and the second scanning line is electrically connected with the first scanning line; the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift registers, at least part of the shift registers comprise a first signal output end and a second signal output end, the first signal output end is electrically connected with the first scanning line, and the second signal output end is electrically connected with the second scanning line; the first signal output end and the second signal output end synchronously output a first effective pulse signal. The mode of adding the second scanning line is adopted, so that the driving capability of the display panel is enhanced, and the display effect of the display panel is improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display technology, a liquid crystal display panel (Liquid Crystal Display, LCD) and an organic light emitting display panel (Organic Light Emitting Diode, OLED) become two main display panels in the display field, and are widely used in applications such as computers, mobile phones, wearable devices, and vehicles.

Typically, both LCD and OLED based displays include a display area and a non-display area surrounding the display area, the display area including a plurality of rows and columns of sub-pixels and a plurality of scan lines, each scan line connecting a row of sub-pixels. The non-display area comprises a grid driving circuit which is used for generating a scanning signal and transmitting the scanning signal to the scanning line so as to control the sub-pixels in the display area to be lighted row by row. However, the scanning signal generated by the gate driving circuit has a fixed frequency, and the scanning time for each row of sub-pixels is fixed, so when the width and length of the display panel are relatively large, the position of the maximum load on the scanning line is unavoidable when the scanning line is long, and the display effect of the display position corresponding to the position is poor.

Disclosure of Invention

In view of this, the present application provides a display panel and a display device, which adopts a mode of adding a second scan line to enhance the driving capability of the display panel and improve the display effect of the display panel.

In order to solve the technical problems, the application has the following technical scheme:

in a first aspect, the present application provides a display panel provided with a display area and a non-display area at least partially surrounding the display area, the display panel comprising:

the first scanning line comprises a first end and a second end, the second scanning line comprises a first end and a second end, the first scanning line and the second scanning line extend along a first direction and are distributed along a second direction; the second scanning line is electrically connected with the first scanning line, and the first direction is intersected with the second direction;

the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift registers, at least part of the shift registers comprise a first signal output end and a second signal output end, the first signal output end is electrically connected with the first scanning line, and the second signal output end is electrically connected with the second scanning line; the first signal output end and the second signal output end synchronously output a first effective pulse signal.

In a second aspect, the present application further provides a display device, including a display panel, where the display panel is a display panel provided by the present application.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

according to the display panel and the display device, on the basis of being provided with the first scanning line, the second scanning line is further arranged, the second scanning line is electrically connected with the position with the largest load in the first scanning line, the first scanning line is electrically connected with the first signal output end of the shift register, the second scanning line is electrically connected with the second signal output end of the shift register, the first signal output end and the second signal output end synchronously output first effective pulse signals, the second scanning line compensates the position with the largest load in the first scanning line, the position with the larger load of the first scanning line still can be input with effective scanning signals, the charging time of the first scanning line is sufficient, the driving capability of the display panel is enhanced, and the display effect of the display panel is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating the connection of shift registers according to an embodiment of the present disclosure;

fig. 3 is a schematic partial structure of a display panel according to an embodiment of the disclosure;

fig. 4 is a schematic view of another partial structure of a display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic view of another partial structure of a display panel according to an embodiment of the present application;

fig. 6 is a schematic view of another partial structure of a display panel according to an embodiment of the disclosure;

fig. 7 is a schematic view of another partial structure of a display panel according to an embodiment of the disclosure;

FIG. 8 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same component by different names. The description and claims do not take the form of an element differentiated by name, but rather by functionality. As used throughout the specification and claims, the word "comprise" is an open-ended term, and thus should be interpreted to mean "include, but not limited to. By "substantially" is meant that within an acceptable error range, a person skilled in the art is able to solve the technical problem within a certain error range, substantially achieving the technical effect. Furthermore, the term "coupled" as used herein includes any direct or indirect electrical coupling. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical coupling to the second device, or through another device or coupling means coupled to ground. The description hereinafter sets forth the preferred embodiment for carrying out the present application, but is not intended to limit the scope of the present application in general, for the purpose of illustrating the general principles of the present application. The scope of the present application is defined by the appended claims. The same points between the embodiments are not described in detail.

The following detailed description refers to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic structural diagram of a display panel 100 according to an embodiment of the present application, fig. 2 is a schematic connecting diagram of a shift register 60 according to an embodiment of the present application, and referring to fig. 1 and 2, the present application provides a display panel 100, which is provided with a display area 10 and a non-display area 20 at least partially surrounding the display area 10, wherein the display panel 100 includes:

a first scan line 30 and a second scan line 40 located in the display area 10, the first scan line 30 including a first end 31 and a second end 32, the second scan line 40 including a first end 41 and a second end 42, the first scan line 30 and the second scan line 40 extending along a first direction D1 and being arranged along a second direction D2; the second scan line 40 is electrically connected to the first scan line 30, and the first direction D1 intersects the second direction D2;

the gate driving circuit 50 located in the non-display area 20, the gate driving circuit 50 includes a plurality of cascaded shift registers 60, at least part of the shift registers 60 includes a first signal output terminal Gout1 and a second signal output terminal Gout2, the first signal output terminal Gout1 is electrically connected with the first scan line 30, and the second signal output terminal Gout2 is electrically connected with the second scan line 40; wherein, the first signal output terminal Gout1 and the second signal output terminal Gout2 synchronously output the first effective pulse signal at the same time.

It should be noted that the embodiment shown in fig. 1 only schematically illustrates a part of the structures included in the display area 10 and the non-display area 20, and does not represent the specific dimensions thereof, wherein the number of shift registers 60 and scan lines does not represent the actual number, nor does the number of sub-pixels in the Pixel row represent the actual number; the embodiment shown in fig. 2 only schematically illustrates an implementation in which one shift register 60 is electrically connected to two scan lines, and of course, other structures are also included in the shift register 60, which is not limited in detail herein.

Specifically, as shown in fig. 1 and 2, the display panel 100 of the present application is provided with a display area 10 and a non-display area 20, the display area 10 is provided with a first scan line 30 and a second scan line 40, the first scan line 30 and the second scan line 40 extend along a first direction D1, are arranged along a second direction D2, the second scan line 40 is electrically connected to the first scan line 30, and optionally, there are multiple positions where the first scan line 30 is electrically connected to the second scan line 40. The application further includes a plurality of Data lines Data, wherein the Data lines Data and the scan lines define a plurality of sub-Pixel pixels, the plurality of sub-Pixel pixels are arranged along a first direction D1 to form a Pixel row, optionally, the sub-Pixel pixels in the same Pixel row are all connected with the same scan line, wherein a first scan line 30 in the application is electrically connected with the sub-Pixel pixels in the Pixel row, and a second scan line 40 is electrically connected with the first scan line 30.

Further, the non-display area 20 is provided with a gate driving circuit 50, the gate driving circuit 50 includes a plurality of cascaded shift registers 60, that is, in two adjacent shift registers 60, a signal output terminal in a previous shift register 60 is electrically connected to a signal input terminal in a next shift register 60, as shown in fig. 1, a shift signal terminal next is at least partially included in the shift registers 60, the first signal output terminal Gout1 is electrically connected to the first scan line 30, and the second signal output terminal Gout2 is electrically connected to the second scan line 40, and the first signal output terminal Gout1 and the second signal output terminal Gout2 synchronously output a first effective pulse signal at the same time, wherein the first signal output terminal Gout1, the second signal output terminal Gout2 and the shift signal terminal next can synchronously output the same signal at the same time, or can output different signals. In general, because the scanning time of each row of pixel lines is fixed, when the width-to-length ratio of the display panel is large, the length of the scanning line is long, in the same pixel line scanning time, for example, a position with a large load exists in the scanning line, for example, a position far away from the signal output end of the shift register along the extending direction of the scanning line, which results in insufficient charging time of the scanning line, so that the effective pulse signal of the signal output end is offset and climbs slowly, and the like, so that the display panel is abnormal.

It should be noted that, in the present application, the subpixel Pixel is electrically connected to the Pixel driving circuit, if the thin film transistor in the Pixel driving circuit is an N-type thin film transistor, the scan signals output by the first signal output terminal Gout1 and the second signal output terminal Gout2 jump from the low level state to the high level state, and then the data signals can be triggered to be transmitted to the subpixel Pixel for charging, that is, the type of the first effective pulse signal is a positive pulse; if the thin film transistor in the Pixel driving circuit is a P-type thin film transistor, the scan signals output by the first signal output end Gout1 and the second signal output end Gout2 jump from a high level state to a low level state and then trigger the data signals to be transmitted to the sub-Pixel for charging, i.e. the type of the first effective pulse signals is negative pulse.

Further, please continue to refer to fig. 2, the following describes that the first scan line 30 and the second scan line 40 synchronously output the effective pulse signals simultaneously, and the present application further includes a first clock signal line Ckv and a second clock signal line Ckv; the shift register 60 includes a latch 61, a first and logic operation circuit 62, and a first buffer 63; the clock signal input terminal of the latch 61 is electrically connected to the first clock signal line Ckv1, and the input terminal of the latch 61 is electrically connected to the output terminal of the latch 61 in the upper shift register 60; a first input terminal of the first and logic operation circuit 62 is electrically connected to an output terminal of the latch 61, and a second input terminal of the first and logic operation circuit 62 is electrically connected to the second clock signal line Ckv; the output end of the first AND logic operation circuit 62 is electrically connected with the input end of the first buffer 63, and the output end of the first buffer 63 is connected with the first end 31 of the first scanning line 30;

further, the shift register 60 further includes a second and logic circuit 64 and a second buffer 65, wherein a first input terminal of the second and logic circuit 64 is electrically connected to the output terminal of the latch 61, a second input terminal of the second and logic circuit 64 is electrically connected to the second clock signal line Ckv2, an output terminal of the second and logic circuit 64 is electrically connected to an input terminal of the second buffer 65, and an output terminal of the second buffer 65 is connected to the first terminal 41 of the second scan line 40. With the above configuration, the same shift register 60 is realized to include two output terminals, and simultaneously input effective pulse signals to the scanning lines in synchronization.

Alternatively, fig. 3 is a schematic diagram of a partial structure of a display panel according to an embodiment of the disclosure, and referring to fig. 3, the first scan line 30 and the second scan line 40 are located in different layers and are electrically connected through the via hole 70.

Specifically, as shown in fig. 3, in the present embodiment, the first scan line 30 and the second scan line 40 are located in different film layers and are electrically connected through the via hole 70, so as to realize the transmission of the scan signal from the second scan line 40 to the first scan line 30, and further, realize the transmission of the scan signal from the second scan line 40 to the position with the largest load in the first scan line 30, so as to realize the load compensation of the first scan line 30. In addition, the first scanning line 30 and the second scanning line 40 are arranged in different layers, which is favorable for reducing the space occupied by the second scanning line 40 in the display area after the second scanning line 40 is increased, and is favorable for improving the screen occupation ratio.

Optionally, as shown in fig. 3, the gate driving circuit 50 is driven by a single side;

the second end 32 of the first scan line 30 is electrically connected to the second end 42 of the second scan line 40.

Specifically, as shown in fig. 3, the gate driving circuit 50 is driven by a single side, wherein the second end 32 of the first scanning line 30 is electrically connected to the second end 42 of the second scanning line 40, when the gate driving circuit 50 is driven by a single side, one end of the first scanning line 30 far from the shift register 60 is the second end 32 of the first scanning line 30, and when the width of the display panel 100 is relatively large, the second end 32 of the first scanning line 30 is at the position with the largest load, and compensation needs to be performed on the second end 32 of the first scanning line 30, so that the scanning signal reaches the second end 32 of the first scanning line 30 more sufficiently, and the driving capability of the display panel 100 is enhanced.

Optionally, as shown in fig. 3, the second end 32 of the first scan line 30 is electrically connected to the second end 42 of the second scan line 40 through a plurality of vias 70;

the distance between two adjacent vias 70 increases gradually along the direction in which the second end 32 of the first scan line 30 points to the first end 31.

Specifically, as shown in fig. 3, the first scan line 30 and the second scan line 40 are electrically connected through the plurality of vias 70, the distance between two adjacent vias 70 is gradually increased along the direction that the second end 32 of the first scan line 30 points to the first end 31, such as L1 and L2 in fig. 3, the load of the L1 area is larger, the load of the L2 area is smaller, so that the signal compensation in the area with larger load is more fully performed, and therefore, the distance of L1 is smaller than the distance of L2, it is understood that the load of the second end 42 of the second scan line 40 is the largest, and in order to achieve a better compensation effect, the density of the vias 70 at the second end 42 of the second scan line 40 is set larger, and in the direction that the load is reduced, the density of the vias 70 is gradually reduced, so that the vias 70 are reasonably manufactured on the basis of achieving the better compensation load.

Alternatively, fig. 4 is a schematic diagram showing another partial structure of the display panel according to the embodiment of the present application, fig. 5 is a schematic diagram showing another partial structure of the display panel according to the embodiment of the present application, and referring to fig. 4 and 5, the gate driving circuit 50 is a dual-side driving circuit;

the non-display area 20 is further provided with a first frame area 21 and a second frame area 22, the plurality of cascaded shift registers 60 includes a plurality of cascaded first shift registers 61 located in the first frame area 21, and a plurality of cascaded second shift registers 62 located in the second frame area 22, at least part of the first shift registers 61 or the second shift registers 62 includes a first signal output terminal Gout1 and a second signal output terminal Gout2;

the first end 31 and the second end 32 of each first scanning line 30 are electrically connected to a first shift register 61 and a second shift register 62, respectively, and the first shift register 61 and the second shift register 62 electrically connected to one first scanning line 30 form a shift register group.

It should be noted that, the embodiments shown in fig. 4 and fig. 5 only schematically illustrate the electrical connection relation of the partial shift register 60, wherein the number of the sub-pixels electrically connected to the first scan line 30 does not represent the actual number.

Specifically, as shown in fig. 4 and 5, the gate driving circuit 50 is a dual-side driving circuit, the shift registers 60 are disposed on opposite sides of the non-display area 20, that is, the first frame area 21 is disposed with a plurality of cascaded first shift registers 61, the second frame area 22 is disposed with a plurality of cascaded second shift registers 62, at least part of the first shift registers 61 includes a first signal output terminal Gout1 and a second signal output terminal Gout2, or at least part of the second shift registers 62 includes a first signal output terminal Gout1 and a second signal output terminal Gout2, the first end 31 of each first scan line 30 is electrically connected with one first shift register 61, the second end 32 of each first scan line 30 is electrically connected with one second shift register 62, and the first shift registers 61 and the second shift registers 62 electrically connected with the same first scan line 30 form a shift register group, and one shift register group corresponds to one first scan line 30 and one second scan line 40. Thus, the gate driving circuit 50 with dual driving has stronger driving capability, and improves the display effect of the display panel 100.

Alternatively, as shown in fig. 4 and 5, the first end 41 of the second scan line 40 is electrically connected to the first shift register 61 or the second shift register 62, and the second end 42 of the second scan line 40 electrically connected to the same shift register group is electrically connected to the first position 33 of the first scan line 30, where the distance between the first position 33 of the first scan line 30 and the first end 31 of the first scan line 30 and the distance between the first position 33 of the first scan line 30 and the second end 32 of the first scan line 30 are equal within an error tolerance range.

It should be noted that in the embodiments shown in fig. 4 and 5, the second scan line may be electrically connected to the first shift register 61 or may be electrically connected to the second shift register 62, that is, the first shift register 61 may be used to provide the scan signal to the second scan line 40, and the second shift register 62 may be used to provide the scan signal to the second scan line 40.

Specifically, as shown in fig. 4 and 5, the first end 41 of the second scan line 40 is electrically connected to the first shift register 61 or the second shift register 62 in the present embodiment, it can be understood that each of the first scan lines 30 is correspondingly provided with a second scan line 40, when the gate driving circuit 50 is in bilateral driving, both ends of the first scan line 30 are electrically connected to the shift register 60, one end of the second scan line 40 is electrically connected to the shift register 60, alternatively, one end of the second scan line 40 may be electrically connected to the first shift register 61 located in the first frame area 21, or may be electrically connected to the second shift register 62 located in the second frame area 22, the other end of the second scan line 40 is electrically connected to the first scan line 30, and when the gate driving circuit 50 is in bilateral driving, the load of the middle position of the first scan line 30 is the largest, and thus the other end of the second scan line 40 is electrically connected to the middle position of the first scan line 30, i.e. the first position 33, and the first position 33 and the first scan line 30 are in the largest distance between the first position and the first scan line 30 and the first end 30 in the first frame area 22, and the first scan line 30 is in the largest distance, and the first position is equal to the first scan line 30, and the first scan line is in the first position and the largest distance is the distance between the first scan line and the first scan line 30 and the second scan line is in the first end and the second scan line 30.

Alternatively, fig. 6 is a schematic diagram of another partial structure of the display panel according to the embodiment of the present application, and referring to fig. 6, two adjacent second scan lines 40 are shown, wherein the first end 41 of one second scan line 40 is electrically connected to the first shift register 61, and the first end 41 of the other second scan line 40 is electrically connected to the second shift register 62.

It should be noted that, the embodiment shown in fig. 6 only schematically illustrates the electrical connection relationship of the partial shift register 60, where the number of the sub-pixels electrically connected to the first scan line 30 does not represent the actual number.

Specifically, as shown in fig. 6, based on the fact that the first end 41 of the second scan line 40 may be electrically connected to the first shift register 61 or the second shift register 62, in this embodiment, the first end 41 of one second scan line 40 is electrically connected to the first shift register 61, and the first end 41 of the other second scan line 40 is electrically connected to the second shift register 62, it can be understood that the second scan lines 40 are alternately arranged, so that the alternating driving of the second scan lines 40 is beneficial to reducing the burden of single-edge driving.

Alternatively, fig. 7 is a schematic diagram showing another partial structure of the display panel according to the embodiment of the present application, and referring to fig. 7, the first end 41 and the second end 42 of each second scan line 40 are electrically connected to the first shift register 61 and the second shift register 62 in the same shift register group respectively;

the first position 43 of the second scanning line 40 electrically connected to the same shift register group is electrically connected to the first position 33 of the first scanning line 30, wherein the distance between the first position 43 of the second scanning line 40 and the first end 41 of the second scanning line 40 and the distance between the first position 43 of the second scanning line 40 and the second end 42 of the second scanning line 40 are equal within an error allowance.

It should be noted that, the embodiment shown in fig. 7 only schematically illustrates the electrical connection relationship of the partial shift register 60, where the number of the sub-pixels electrically connected to the first scan line 30 does not represent the actual number.

Specifically, as shown in fig. 7, and in conjunction with fig. 1, the first end 41 and the second end 42 of each second scan line 40 are respectively electrically connected to the first shift register 61 and the second shift register 62 in the same shift register group, it is understood that when the gate driving circuit 50 is a dual-side driving, both ends of the second scan line 40 are electrically connected to the shift register 60, so that the burden of single-side driving can be reduced. Further, the first position 43 of the second scan line 40 electrically connected to the same shift register group is electrically connected to the first position 33 of the first scan line 30, and it is understood that the first position 43 of the second scan line 40 is an intermediate position of the second scan line 40, which is equal to the distance between the first end 41 of the second scan line 40 and the distance between the second end 42 of the second scan line 40, so that the load of driving on one side is reduced, and at the same time, the load compensation can be performed on the first scan line 30 through the second scan line 40, and further, the signal compensation can be performed on the position with the maximum load on the first scan line 30, so as to enhance the driving capability of the display panel 100.

Alternatively, fig. 8 is a cross-sectional view of a display panel provided in an embodiment of the present application, please refer to fig. 8, and referring to fig. 7, in which a first end 41 and a second end 42 of each second scan line 40 are electrically connected to a first shift register 61 and a second shift register 62 in the same shift register group, respectively;

the first scan line 30 and the second scan line 40 electrically connected to the same shift register group are electrically connected through a plurality of vias 70;

the distance between two adjacent vias 70 increases gradually along the direction of the first end 31 of the first scan line 30 at the first position 33 of the first scan line 30;

the distance between two adjacent vias 70 increases gradually along the direction of the second end 32 of the first scan line 30 at the first position 33 of the first scan line 30;

wherein a distance between the first position 33 of the first scan line 30 and the first end 31 of the first scan line 30 and a distance between the first position 33 of the first scan line 30 and the second end 32 of the first scan line 30 are equal within an error allowable range.

Specifically, as shown in fig. 7 and 8, the second scan line 40 in the present embodiment is also driven in double-sided mode, that is, the first end 41 and the second end 42 of the second scan line 40 are electrically connected to the first shift register 61 and the second shift register 62 in the same shift register group, and the first scan line 30 and the second scan line 40 electrically connected to the same shift register group are electrically connected through the via 70. Alternatively, the distance between two adjacent vias 70 increases in a direction pointing to the first end 31 of the first scan line 30 at the first position 33 of the first scan line 30, i.e., in the third direction D3 in fig. 8; as the distance between two adjacent vias 70 increases gradually along the direction of the second end 32 of the first scan line 30 at the first position 33 of the first scan line 30 (please refer to fig. 8), it can be understood that the vias 70 electrically connecting the first scan line 30 and the second scan line 40 concentrate in the middle position area of the first scan line 30, and the greater the density of the vias 70 located at the middle position, the smaller the density of the vias 70 located at the far from the middle position, i.e. L4 > L3 in fig. 8, the density of the vias 70 depends on the load size of the first scan line 30, and when in bilateral driving, the position with the largest load is located in the middle area of the first scan line 30, so that signal compensation is needed, and the signal compensation form of electrically connecting a plurality of vias 70 is adopted, so that the signal compensation in the area with the largest load of the first scan line 30 can be more sufficient, which is more beneficial to improving the driving capability of the display panel 100.

Optionally, as shown in fig. 1, a plurality of sub-pixels Pixel are further included, and a distance between two adjacent vias 70 is greater than a distance between two adjacent sub-pixels Pixel.

Specifically, as shown in fig. 1, the distance between two adjacent vias 70 in the present embodiment needs to be greater than the distance between two adjacent sub-pixels Pixel. When the distance between two adjacent vias 70 is too small, the requirements for the manufacturing process are higher, the difficulty is increased, and when the distance between two adjacent vias 70 is too large, the load of the first scanning line cannot be well compensated, and a good effect cannot be achieved.

Optionally, please continue to refer to fig. 8, and further include: a first metal layer 35 and a second metal layer 45;

the first scan line 30 is located on the first metal layer 35, and the second scan line 40 is located on the second metal layer 45.

An insulating layer 80 is further disposed between the first metal layer 35 and the second metal layer 45.

Specifically, referring to fig. 1, in this embodiment, the display panel 100 further includes a first metal layer 35 and a second metal layer 45, where the first metal layer 35 may be a gate layer or a source drain layer of a thin film transistor in the pixel driving circuit, and the second metal layer 45 is an added film layer, and is specially used for setting the second scan line 40, and the resistivity of the second metal layer 45 is smaller than that of the first metal layer 35, so that attenuation of scan signals when the second scan line 40 is set in other film layers can be effectively avoided, and the scan signals on the second scan line 40 can be more effectively transmitted to the first scan line 30.

Based on the same inventive concept, fig. 9 is a schematic structural diagram of the display device 200 according to the embodiment of the present application, and please refer to fig. 9, where the display device 200 includes a display panel 100, and the display panel 100 is the display panel 100 according to any of the embodiments of the present application.

It should be noted that, in the embodiment of the display device 200 provided in the embodiment of the present application, reference may be made to the embodiment of the display panel 100 described above, and the repetition is omitted. The display device 200 provided in the present application may be: any product or component with realistic functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

According to the embodiments, the beneficial effects of the application are as follows:

the display panel 100 and the display device 200 provided by the application adopt a mode of arranging the second scanning line 40 on the basis of arranging the first scanning line 30, wherein the second scanning line 40 is electrically connected with the position with the largest load in the first scanning line 30, the first scanning line 30 is electrically connected with the first signal output end Gout1 of the shift register 60, the second scanning line 40 is electrically connected with the second signal output end Gout2 of the shift register 60, and the first signal output end Gout1 and the second signal output end Gout2 synchronously output the first effective pulse signal at the same time, so that the second scanning line 40 compensates the position with the largest load in the first scanning line 30, the charging time of the first scanning line 30 is sufficient, the driving capability of the display panel 100 is enhanced, and the display effect of the display panel 100 is improved.

While the foregoing description illustrates and describes the preferred embodiments of the present application, it is to be understood that this application is not limited to the forms disclosed herein, but is not to be construed as an exclusive use of other embodiments, and is capable of many other combinations, modifications and environments, and adaptations within the scope of the inventive concept described herein, through the foregoing teachings or through the skill or knowledge of the relevant arts. And that modifications and variations which do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A display panel provided with a display area and a non-display area at least partially surrounding the display area, the display panel comprising:

the first scanning line comprises a first end and a second end, the second scanning line comprises a first end and a second end, the first scanning line and the second scanning line extend along a first direction and are distributed along a second direction; the second scanning line is electrically connected with the first scanning line, the electric connection part of the second scanning line and the first scanning line is the position with the largest load in the first scanning line, and the first direction is intersected with the second direction;

the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift registers, at least part of the shift registers comprise a first signal output end and a second signal output end, the first signal output end is electrically connected with the first scanning line, and the second signal output end is electrically connected with the second scanning line; the first signal output end and the second signal output end synchronously output a first effective pulse signal at the same time.

2. The display panel of claim 1, wherein the first scan line and the second scan line are located in different layers and are electrically connected through a via.

3. The display panel according to claim 2, wherein the gate driving circuit is a single-side driving;

the second end of the first scanning line is electrically connected with the second ends of the two scanning lines.

4. The display panel of claim 3, wherein the second end of the first scan line is electrically connected to the second end of the second scan line through a plurality of the vias;

and along the direction that the second end of the first scanning line points to the first end, the distance between two adjacent through holes is gradually increased.

5. The display panel of claim 2, wherein the gate driving circuit is a dual side driving;

the non-display area is also provided with a first frame area and a second frame area, the plurality of cascaded shift registers comprise a plurality of cascaded first shift registers positioned in the first frame area, and a plurality of cascaded second shift registers positioned in the second frame area, and at least part of the first shift registers or the second shift registers comprise the first signal output end and the second signal output end;

the first end and the second end of each first scanning line are respectively and electrically connected with one first shift register and one second shift register, and one first shift register and one second shift register which are electrically connected with one first scanning line form a shift register group.

6. The display panel according to claim 5, wherein a first end of the second scan line is electrically connected to the first shift register or the second shift register, and a second end of the second scan line electrically connected to the same shift register group is electrically connected to a first position of the first scan line, wherein a distance between the first position of the first scan line and the first end of the first scan line and a distance between the first position of the first scan line and the second end of the first scan line are equal within an error allowance range.

7. The display panel of claim 6, wherein the display panel comprises,

and in the two adjacent second scanning lines, the first end of one second scanning line is electrically connected with the first shift register, and the first end of the other second scanning line is electrically connected with the second shift register.

8. The display panel of claim 5, wherein the first end and the second end of each of the second scan lines are electrically connected to the first shift register and the second shift register in the same shift register group, respectively;

and a first position of the second scanning line of the same shift register group is electrically connected with a first position of the first scanning line, wherein the distance between the first position of the second scanning line and the first end of the second scanning line and the distance between the first position of the second scanning line and the second end of the second scanning line are equal within an error allowable range.

9. The display panel of claim 5, wherein the first end and the second end of each of the second scan lines are electrically connected to the first shift register and the second shift register in the same shift register group, respectively;

the first scanning line and the second scanning line which are electrically connected with the same shift register group are electrically connected through a plurality of through holes;

the distance between two adjacent through holes is gradually increased along the direction of pointing to the first end of the first scanning line at the first position of the first scanning line;

the distance between two adjacent through holes is gradually increased along the direction of pointing to the second end of the first scanning line at the first position of the first scanning line;

wherein a distance between a first position of the first scanning line and a first end of the first scanning line and a distance between the first position of the first scanning line and a second end of the first scanning line are equal within an error allowable range.

10. The display panel of claim 2, further comprising a plurality of sub-pixels, wherein a distance between two adjacent ones of the vias is greater than a distance between two adjacent ones of the sub-pixels.

11. The display panel of claim 1, further comprising: a first metal layer and a second metal layer;

the first scanning line is located on the first metal layer, and the second scanning line is located on the second metal layer.

12. A display device comprising a display panel according to any one of claims 1-11.