CN114283689B - Display module and driving method thereof - Google Patents
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- CN114283689B CN114283689B CN202111660368.7A CN202111660368A CN114283689B CN 114283689 B CN114283689 B CN 114283689B CN 202111660368 A CN202111660368 A CN 202111660368A CN 114283689 B CN114283689 B CN 114283689B
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Abstract
The application discloses a display module and a driving method thereof, which relate to the technical field of display and comprise the following steps: a display region and a non-display region at least partially surrounding the display region; a plurality of cascaded shift registers located in the non-display area; the first signal line is positioned in the non-display area and positioned at one side of the shift register close to the display area; the second signal line is positioned in the non-display area and is positioned at one side of the first signal line, which is close to the display area; the second signal line at least partially surrounds the display area; in the test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal; in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal. The application adopts a non-display area signal wiring multiplexing mode, which is beneficial to realizing the narrow frame design of the display module.
Description
Technical Field
The application relates to the technical field of display, in particular to a display module and a driving method thereof.
Background
From the CRT (Cathode Ray Tube) age to the liquid crystal age to the now-coming organic light-emitting age, the display industry has undergone decades of development to become more and more diverse. The display industry has been closely related to our lives, from traditional mobile phones, tablets, televisions and PCs, to current smart wearable devices and VR, etc., without the display technology.
The display module in the prior art comprises a testing stage and a display stage, and different signal wires are arranged in the testing stage and the display stage, and in general, partial signal wires are distributed and non-display areas exist, so that the narrow frame design of the display module is not facilitated; in addition, in the existing large-size display products, for example, in a large-size vehicle-mounted display module, in order to avoid the load difference, the signal lines are arranged more, and the narrow frame design of the display module is not facilitated; therefore, a display module for realizing a narrow bezel design is needed.
Disclosure of Invention
In view of this, the present application provides a display module and a driving method thereof, which adopts a non-display area signal routing multiplexing mode, and is beneficial to realizing a narrow frame design of the display module.
In order to solve the technical problems, the application has the following technical scheme:
in a first aspect, the present application provides a display module, including: a display region and a non-display region at least partially surrounding the display region;
a plurality of cascaded shift registers located in the non-display area;
the first signal line is positioned in the non-display area and positioned at one side of the shift register close to the display area;
the second signal line is positioned in the non-display area and is positioned at one side of the first signal line, which is close to the display area; the second signal line at least partially surrounds the display area;
In the test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal;
in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal.
In a second aspect, the present application further provides a driving method of a display module, where the driving method is used for the display module provided by the embodiment of the present application, and the display module includes: a display region and a non-display region at least partially surrounding the display region;
a plurality of cascaded shift registers located in the non-display area;
the first signal line is positioned in the non-display area and positioned at one side of the shift register close to the display area;
the second signal line is positioned in the non-display area and is positioned at one side of the first signal line, which is close to the display area; the second signal line at least partially surrounds the display area;
in the test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal;
in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal.
Compared with the prior art, the display panel and the display device provided by the application have the advantages that at least the following effects are realized:
according to the display module and the driving method thereof provided by the application, the narrow frame design of the display module is realized by adopting the mode that different signals are transmitted by the same signal line in stages; specifically, the display module comprises a plurality of cascaded shift registers, wherein the shift registers are positioned in a non-display area; the display module further comprises a first signal line and a second signal line which are both positioned in the non-display area, wherein the first signal line is positioned on one side of the shift register close to the display area, the second signal line is positioned on one side of the first signal line close to the display area, and the second signal line is at least partially arranged around the display area; it is understood that the second signal lines are at least partially arranged around the display area, the first signal lines are sequentially arranged at the periphery of the second signal lines, and the shift register is arranged at the periphery of the first signal lines; in the test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal; in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal; different signals are transmitted at different stages through the first signal wire and the second signal wire, and the first signal wire and the second signal wire are used in stages, so that the signal wires do not need to be arranged respectively corresponding to the test stage and the display stage, the number of the signal wires can be effectively reduced, the duty ratio of a non-display area is further reduced, and the narrow frame design of the display module is facilitated.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
fig. 1 is a schematic structural diagram of a display module according to an embodiment of the application;
fig. 2 is a schematic structural diagram of a display module according to an embodiment of the application;
FIG. 3 is a schematic diagram of a display module according to the prior art;
fig. 4 is a schematic structural diagram of a display module according to an embodiment of the application;
fig. 5 is a schematic diagram of a partial structure of a display module according to an embodiment of the application;
fig. 6 is a schematic diagram of a partial structure of a display module according to an embodiment of the application;
fig. 7 is a schematic diagram of another structure of a display module according to an embodiment of the application;
fig. 8 is a schematic diagram of another structure of a display module according to an embodiment of the application;
fig. 9 is a schematic workflow diagram of a driving method of a display module according to an embodiment of the application;
fig. 10 is a schematic diagram of another workflow of a driving method of a display module according to an embodiment of the application;
Fig. 11 is a schematic structural diagram of a driving circuit of a display module according to an embodiment of the application;
fig. 12 is a schematic workflow diagram of a driving method of a display module according to an embodiment of the application;
fig. 13 is a schematic workflow diagram of a driving method of a display module according to an embodiment of the application.
Detailed Description
Certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same component by different names. The description and claims do not take the form of an element differentiated by name, but rather by functionality. As used throughout the specification and claims, the word "comprise" is an open-ended term, and thus should be interpreted to mean "include, but not limited to. By "substantially" is meant that within an acceptable error range, a person skilled in the art is able to solve the technical problem within a certain error range, substantially achieving the technical effect. The description hereinafter sets forth a preferred embodiment for practicing the application, but is not intended to limit the scope of the application, as the description is given for the purpose of illustrating the general principles of the application. The scope of the application is defined by the appended claims. The same points between the embodiments are not described in detail.
The following detailed description refers to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic structural diagram of a display module according to an embodiment of the present application, fig. 2 is a schematic structural diagram of a display module according to an embodiment of the present application, please refer to fig. 2, and a display module 100 according to the present application includes: a display region 10 and a non-display region 20 at least partially surrounding the display region 10;
a plurality of cascaded shift registers 30 located in the non-display area 20;
the first signal line 40 is located in the non-display area 20 and located at one side of the shift register 30 near the display area 10;
the second signal line 50 is located in the non-display area 20 and located at one side of the first signal line 40 near the display area 10; the second signal line 50 at least partially surrounds the display area 10;
in the test phase, the first signal line 40 transmits a common voltage signal, and the second signal line 50 transmits a data signal;
in the display stage, the first signal line 40 transmits a pixel control signal, and the second signal line 50 transmits a common voltage signal.
It should be noted that, the embodiment shown in fig. 1 only schematically illustrates the schematic positional relationship of the non-display area 20 in the display area 10, and does not represent the actual size; the embodiment shown in fig. 2 only schematically shows the positional relationship of the display area 10, the first signal line 40, the second signal line 50, and the shift register 30, and does not represent the actual size.
Specifically, as shown in fig. 1 and 2, the display module 100 provided in this embodiment may be a LCD (Liquid Crystal Displayer) display module, where the display module 100 includes a display area 10 and a non-display area 20, optionally, the non-display area 20 is disposed around the display area 10, the display area 10 is used for displaying a picture, and the non-display area 20 is provided with at least part of a pixel driving circuit and a signal line, and the pixel driving circuit transmits a signal to the display area to make the display panel emit light; in general, the display module 100 manufactured needs to test the lighting condition of the display panel, and is put on the market for use after meeting the requirement, and it can be understood that the display module 100 includes a testing stage and a display stage, and in different stages, different signal lines are required to be used to make the display module 100 light.
In the related art, fig. 3 is a schematic structural diagram of a display module in the prior art, referring to fig. 3, a display module 300 includes a display area 310 and a non-display area 320, the non-display area 320 is provided with a cascaded shift register 330, the non-display area 320 is further provided with a common electrode signal wire 340, the common electrode signal wire 340 is located at one side of the cascaded shift register 330 near the display area 310, and the common electrode signal wire 340 is used for transmitting signals to a common electrode; the non-display area 320 further includes a plurality of test signal traces 350, the test signal traces 350 being used during a testing phase of the display module 300 for transmitting signals to the data lines 360 in the display area 310, wherein the test signal traces 350 are located on a side of the cascaded shift register 330 facing away from the display area 310. In order to reduce impedance, the signal wiring is generally set to be relatively wide; in addition, other signal lines are further disposed in the non-display area 320, so that a larger space is required for placing various signal lines in the non-display area 320, which makes the space occupation of the non-display area 320 larger and is not beneficial to realizing the narrow frame design of the display module.
In view of this, please continue to refer to fig. 1 and 2, in this embodiment, a manner of transmitting different signals by stages is adopted to realize the narrow frame design of the display module 100; specifically, the display module 100 in this embodiment includes a plurality of cascaded shift registers 30, where the shift registers 30 are located in the non-display area 20; the display module 100 further includes a first signal line 40 and a second signal line 50, both of which are located in the non-display area 20, the first signal line 40 is located at a side of the shift register 30 near the display area 10, the second signal line 50 is located at a side of the first signal line 40 near the display area 10, and the second signal line 50 is at least partially disposed around the display area 10; it is understood that the second signal lines 50 are at least partially arranged around the display area 10, the first signal lines 40 are sequentially arranged at the periphery of the second signal lines 50, and the shift register 30 is arranged at the periphery of the first signal lines 40; wherein, in the test phase, the first signal line 40 transmits a common voltage signal, and the second signal line 50 transmits a data signal; in the display stage, the first signal line 40 transmits a pixel control signal, and the second signal line 50 transmits a common voltage signal; optionally, the pixel control signal is a clock signal; different signals are transmitted at different stages through the first signal line 40 and the second signal line 50, and the first signal line 40 and the second signal line 50 are used in stages, so that the signal lines do not need to be arranged respectively corresponding to the test stage and the display stage, the number of the signal lines can be effectively reduced, the duty ratio of the non-display area 20 is further reduced, and the narrow frame design of the display module 100 is facilitated. In addition, in this embodiment, the first signal line 40 and the second signal line 50 used in the test stage are both disposed on the side of the shift register near the display area, so that the first signal line 40 and the second signal line 50 do not need to be provided with a line crossing portion to cross the shift register, and the impedance of the first signal line 40 and the second signal line 50 can be reduced, thereby simplifying the setting of the signal lines. In the detection phase, the display module can emit light without transmitting fine data signals and common voltage signals, and in the display phase, fine signals need to be transmitted to the display area row by row. The impedance value of the signal line affects the transmission amount and transmission speed of the signal, and the impedance value of the signal line is related to parameters such as width, length, resistivity and the like. Meanwhile, the signal amount of the data signal may be higher than that of the common voltage, and thus signal transmission may be achieved by setting the data signal line relatively wide. The signal transmission line based on different stages of the scheme can be adjusted, and only a part of signal lines are required to be wider under the condition of not affecting various signal transmission speeds, so that the narrow frame design of the display panel is facilitated. It will be appreciated that in the display phase, the second signal line 50 for transmitting the data line signal in the test phase is used to transmit the common voltage signal, and because the signal line for transmitting the data signal is relatively large in signal quantity and wide in signal quantity, the width of the second signal line 50 can meet the requirement of transmitting the relatively fine common voltage signal in the display phase, and the impedance can be effectively reduced, and the narrow frame arrangement can be realized through the reasonably phased signal lines without affecting the signal transmission.
With continued reference to fig. 2, in an alternative embodiment of the present application, the method further includes: a driving chip 60 located in the non-display area 20; the driving chip 60 is electrically connected to the first signal line 40 and the second signal line 50, respectively;
the data line D is located in the display area 10, extends along the first direction D1, and is arranged along the second direction D2; the first end D-1 of the data line D is electrically connected with the driving chip 60, and the second end D-2 of the data line D is electrically connected with the second signal line 50;
in the display stage, the driving chip 60 transmits a display data signal to the first terminal D-1 of the data line D.
It should be noted that, the embodiment of fig. 2 only schematically illustrates a structure in which the plurality of data lines D are disposed in the display area 10, and does not represent the actual number of the data lines D.
Specifically, as shown in fig. 2, the display module 100 in the present embodiment further includes a driving chip 60 located in the non-display area 20, optionally, the driving chip 60 is bound to the binding area of the display module 100, the driving chip 60 is used for driving the display module 100, and the driving chip 60 is electrically connected to the first signal line 40 and the second signal line 50 respectively; the driving chip 60 inputs different signals to the first signal line 40 and the second signal line 50 in the display stage, and it is also understood that the signal source in the display stage is the driving chip 60; the display module 100 in this embodiment further includes a data line D, where the data line D is located in the display area 10, extends along the first direction D1, and is arranged along the second direction D2, and optionally, the first direction D1 intersects the second direction D2; alternatively, the first direction D1 is perpendicular to the second direction D2; the first end D-1 of the data line D is electrically connected with the driving chip 60, and the second end D-2 of the data line D is electrically connected with the second signal line 50; it is understood that, during the display stage, the driving chip 60 transmits the display data signal to the first end D-1 of the data line D, and it is understood that the data signal during the display stage is provided by the driving chip 60 and transmitted to the data line D by the first end D-1 of the driving chip 60, so that the display module 100 emits light.
It should be further noted that, the display module 100 further includes a gate line extending along the second direction D2, arranged along the first direction D1, and insulated from the data line D in a crossing manner to define a pixel unit.
Fig. 4 is a schematic structural diagram of a display module according to an embodiment of the present application, and referring to fig. 4, in an alternative embodiment of the present application, the display module further includes: a test terminal 70 located in the non-display area 20, the test terminal 70 being electrically connected to the first signal line 40 and the second signal line 50, respectively;
in the test phase, the second signal line 50 transmits a data signal, which is a test data signal, to the second terminal D-2 of the data line D.
It should be noted that, the embodiment shown in fig. 4 only schematically illustrates a schematic positional relationship in which the test terminal 70 is electrically connected to the first signal line 40 and the second signal line 50, and does not represent actual dimensions of the test terminal 70, the first signal line 40 and the second signal line 50; the embodiment shown in fig. 4 only schematically illustrates the positional relationship between the test terminals and the driving chip, and does not represent the actual dimensions of the test terminals and the driving chip.
Specifically, as shown in fig. 4, the display module 100 in the present embodiment further includes a test terminal 70, where the test terminal 70 is located in the non-display area 20, and optionally, the test terminal 70 is located in a binding area of the display module 100; the test terminals 70 are electrically connected to the first signal lines 40 and the second signals, respectively; optionally, the test terminal 70 is externally connected with a test circuit board, and in the test stage, the test circuit board inputs different signals to the first signal line 40 and the second signal line 50 through the test terminal 70 respectively, which can also be understood as that the signal source in the test stage is the test circuit board; in the test phase, the second signal line 50 transmits a data signal to the second end D-2 of the data line D, where the data signal is a test data signal; specifically, the test circuit board transmits a test data signal to the second signal line 50, and the second signal line 50 is electrically connected to the second end D-2 of the data line D, and transmits the test data signal to the data line D, so that the display module 100 emits light.
It should be noted that, the display data signal is provided by the driving chip 60, and the test data signal is provided by the test circuit board; in the display stage and the test stage, the display module is required to emit light, only a display area is required to emit light in the test stage, and a too fine test data signal is not required, so that the display module can emit light simultaneously by a plurality of data lines D, and in the display stage, the display data signal requirement for realizing display is higher, and a series of pixel control circuits of a lower frame are required to finely regulate and control signals to provide different display data signals for different data lines D; in this way, the selection signal lines differentiated at different stages transmit signals according to the requirements for lighting the display region 10.
Fig. 5 is a schematic partial structure of a display module according to an embodiment of the present application, and referring to fig. 5, in an alternative embodiment of the present application, the display module further includes: a common electrode 110 located in the display area 10, the common electrode 110 being responsive to a common voltage signal;
the first signal wire 81 and the second signal wire 82, the first signal wire 81 and/or the second signal wire 82 being electrically connected to the common electrode 110; the end of the first signal wire 81 is electrically connected to the first signal wire 40, and the end of the second signal wire 82 is electrically connected to the second signal wire 50;
The first switch 91 and the second switch 92 are both positioned in the non-display area 20, the first switch 91 is connected in series in the first signal wire 81, and the second switch 92 is connected in series in the second signal wire 82; only one of the first switch 91 and the second switch 92 is turned on during the test phase or the display phase.
It should be noted that, in the embodiment shown in fig. 5, only schematic diagrams of positions where the first signal line 40 and the second signal line 50 are electrically connected to the first signal line 81 and the second signal line 82, respectively, are schematically shown, and the positions of the first switch 91 at the first signal line 81 and the positions of the second switch 92 at the second signal line 82 do not represent actual sizes.
Specifically, as shown in fig. 5, the display module 100 in the present embodiment further includes a common electrode 110, the common electrode 110 is located in the display area 10, and the common electrode 110 is cooperated with the pixel electrode to generate a voltage for driving the liquid crystal to deflect in response to the common voltage signal; the display module 100 in this embodiment further includes a first signal wire 81 and a second signal wire 82, where one end of the first signal wire 81 and/or one end of the second signal wire 82 are electrically connected to the common electrode 110, and optionally, the first signal wire 81 and/or the second signal wire 82 are directly in contact with and electrically connected to the common electrode 110; the other end of the first signal wire 81 is electrically connected to the first signal wire 40, and the other end of the second signal wire 82 is electrically connected to the second signal wire 50; it will be appreciated that the first signal line 40 and the second signal line 50 input signals to the first signal line 81 and the second signal line 82, respectively; in the test phase, the first signal line 40 transmits a common voltage signal to the common electrode 110, the second signal line 50 transmits a data signal, and in the display phase, the first signal line 40 transmits a pixel control signal, the second signal line 50 transmits a common voltage signal to the common electrode 110; it may also be understood that the first signal line 40 transmits a common voltage signal during a test phase, transmits a pixel control signal during a display phase, the second signal line 50 transmits a data signal during the test phase, transmits a common voltage signal during the display phase, the first signal line 40 and the second signal line 50 need to transmit different signals during the test phase and the display phase, and in order to avoid mutual interference of the signals during the test phase and the display phase, the first switch 91 and the second switch 92 need to be controlled by a switch, that is, the first switch 91 is connected in series to the first signal line 81, the second switch 92 is connected in series to the second signal line 82, and only one of the first switch 91 and the second switch 92 is in an on state during the test phase or the display phase, so that one of the first signal line 40 or the second signal line 50 transmits the common voltage signal to the common electrode 110, and the first signal line 40 and the second signal line 50 transmit different signals during different phases, thereby ensuring normal display of the display module 100.
It should be noted that, the first switch 91 and the second switch 92 are both switching transistors, the switching transistors include a P-type transistor and an N-type transistor, the P-type transistor is a PMOS transistor, the N-type transistor is an NMOS transistor or an oxide thin film transistor, and the embodiment is not limited thereto.
It should be noted that, the display module 100 in this embodiment includes an array substrate and a color film substrate disposed opposite to each other, and a liquid crystal disposed between the array substrate and the color film substrate; the display module 100 further includes pixel electrodes disposed corresponding to the common electrode 110, wherein different signals are input to the pixel electrodes and the common electrode 110 respectively, so that a voltage is generated between the pixel electrodes and the common electrode 110, and the liquid crystal can be driven to deflect, thereby realizing brightness adjustment of the display panel.
With continued reference to fig. 5, in an alternative embodiment of the present application, the first signal trace 81 and the second signal trace 82 are electrically connected to the common electrode 110, and the first signal trace 81 and the second signal trace 82 are respectively located at least partially in the display area 10 and at least partially in the non-display area 20.
Specifically, as shown in fig. 5, in this embodiment, the first signal trace 81 and the second signal trace 82 are arranged in parallel, the first signal trace 81 and the second signal trace 82 extend from the non-display area 20 to the display area 10, at least partially located in the non-display area 20 and at least partially located in the display area 10, and the first signal trace 81 and the second signal trace 82 are electrically connected with the common electrode 110 respectively, so that a common voltage signal is input to the common electrode 110 in a testing stage or a display stage, and effective signal transmission in the testing stage and the display stage is ensured.
Fig. 6 is a schematic diagram of a partial structure of a display module according to an embodiment of the application, and referring to fig. 6, in an alternative embodiment of the application, a first signal trace 81 is electrically connected to a common electrode 110, the first signal trace 81 is at least partially located in a display area 10, at least partially located in a non-display area 20, and a second signal trace 82 is located in the non-display area 20; one end of the second signal trace 82, which is close to the display area 10, is electrically connected to the first signal trace 81 through a via hole.
Specifically, as shown in fig. 6, the first signal trace 81 in the present embodiment is electrically connected to the common electrode 110, and the first signal trace 81 extends from the non-display area 20 to the display area 10, is at least partially located in the non-display area 20, is at least partially located in the display area 10, and is directly in contact with and electrically connected to the common electrode 110 in the display area 10; the second signal trace 82 is only located in the non-display area 20 and is electrically connected to the first signal trace 81, at this time, one end of the second signal trace 82, which is away from the display area 10, is electrically connected to the second signal trace 50, and one end of the second signal trace, which is close to the display area 10, is electrically connected to the first signal trace 81; optionally, the second signal trace 82 is electrically connected to the first signal trace 81 through a via hole, and the via hole is located in the non-display area 20; thus, the first signal traces 81 in the display area 10 are shared, so that the number of traces in the display area 10 can be reduced, and the manufacturing process of the display module 100 can be simplified.
With continued reference to fig. 5 and 6, in an alternative embodiment of the present application, the method further includes: the switch control signal line 90 is electrically connected to the first switch 91 and the second switch 92, and is used for controlling the on and off of the first switch 91 and the second switch 92.
Specifically, as shown in fig. 5 and 6, the display module 100 in this embodiment further includes a switch control signal line, where the switch control signal line 90 is electrically connected to the first switch 91 and the second switch 92, and optionally, when the first switch 91 and the second switch 92 are thin film transistors, the switch control signal line is electrically connected to a gate of the thin film transistor for controlling on and off of the thin film transistor; optionally, in this embodiment, the first switch 91 and the second switch 92 are thin film transistors with different types, that is, the first switch 91 is a P-type transistor, the second switch 92 is an N-type transistor, the first switch 91 is an N-type transistor, and the second switch 92 is a P-type transistor; thus, when the transistor control signal is transmitted on the switch control signal line 90, only one of the first switch 91 and the second switch 92 is turned on at the same time, so that the first signal line 40 and the second signal line 50 input the common voltage signal to the common electrode 110 at different stages, and the display module 100 emits light.
It should be noted that, the numbers of the first signal lines 40 and the second signal lines 50 in fig. 5 and other subsequent drawings are only schematic, and are not limited, and are not repeated in the following.
Fig. 7 is a schematic diagram of another structure of a display module provided in an embodiment of the present application, and referring to fig. 7, in an alternative embodiment of the present application, a non-display area 20 includes a first area i and a second area ii disposed opposite to each other, and a third area iii and a fourth area iv disposed opposite to each other;
the second signal line 50 is located in the first region i, the second region ii and the third region iii, respectively; the first signal lines 40 are respectively located in the first region i and the second region ii, and the shift register 30 is respectively located in the first region i and the second region ii.
It should be noted that, the embodiment shown in fig. 7 only schematically illustrates the positional relationship among the first area i, the second area ii, the third area iii, and the fourth area iv, and does not represent the actual manufacturing situation.
Specifically, as shown in fig. 7, in this embodiment, the non-display area 20 is divided into a first area i and a second area ii which are disposed opposite to each other, and a third area iii and a fourth area iv which are disposed opposite to each other; the second signal lines 50 are respectively arranged in the first area I, the second area II and the third area III, and the first signal lines 40 are respectively arranged in the first area I and the second area II; the cascaded shift registers 30 are respectively located in the first area I and the second area II; it can be understood that, in the present embodiment, the display module 100 is driven by a dual-side driving method, the first signal lines 40 are respectively located at two sides of the display area 10 along the second direction D2, and the second signal lines 50 are also located at two sides of the display area 10 along the second direction D2; on the one hand, by adopting the bilateral transmission signal, the loads of the first signal line 40 and the second signal line 50 can be effectively improved; on the other hand, the first signal line 40 and the second signal line 50 are both located between the display area 10 and the shift register 30, and no signal line is required to be disposed outside the shift register 30, so that the duty ratio of the non-display area 20 can be effectively reduced, which is beneficial to realizing the narrow frame design of the display module 100.
With continued reference to fig. 7, in an alternative embodiment of the present application, the method further includes: the clock signal line CKH is respectively positioned in the first area I, the second area II and the fourth area IV;
the first signal line 40 multiplexes the clock signal line CKH, and the pixel control signal is a clock signal.
Specifically, as shown in fig. 7, the display module 100 of the present embodiment further includes a clock signal line CKH, which is generally located at the lower border of the non-display area 20, i.e. the fourth area iv; in the detection stage, the display module can emit light without transmitting fine data signals and public voltage signals, and if the width of a public voltage signal line for transmitting the public voltage signals is wider, more non-display area space is occupied undoubtedly, so that the narrow frame arrangement is not facilitated. In this embodiment, the clock signal line CKH extends from the fourth region iv to the first region i and the second region ii, respectively, where the first signal line 40 multiplexes the clock signal lines CKH extending to the first region i and the second region ii; in the test stage, the common voltage signal is transmitted by using the portions of the clock signal lines CKH extending to the first and second regions i and ii, and at the same time, the clock signal lines CKH of the first and second regions i and ii may be set relatively thin, so that the reduction of the duty ratio of the non-display region 20 is advantageous for realizing the narrow frame design of the display module 100. In addition, in the display stage, the second signal line 50 transmitting the data line signal in the test stage is used to transmit the common voltage signal, and since the signal line transmitting the data signal is relatively large in signal quantity and wide in width, the width of the second signal line 50 can meet the requirement of transmitting the relatively fine common voltage signal in the display stage, and the impedance can be effectively reduced, and the narrow frame setting can be realized through reasonably multiplexing the signal lines without influencing the signal transmission.
Fig. 8 is a schematic diagram of another structure of a display module provided in an embodiment of the present application, referring to fig. 8, in an alternative embodiment of the present application, the display module further includes: a demultiplexer circuit 120, the demultiplexer circuit 120 being located in a fourth region iv;
the demultiplexer circuit 120 includes a plurality of transistors 121, and control terminals of the transistors in the same demultiplexer circuit 120 are electrically connected to different clock signal lines CKH, respectively, and output terminals of the transistors in the same demultiplexer circuit 120 are electrically connected to different data lines D, respectively.
It should be noted that, the embodiment shown in fig. 8 only schematically illustrates a schematic diagram in which one transistor is electrically connected to the clock signal line CKH and the data line D, respectively, and does not represent a practical situation.
Specifically, as shown in fig. 8, the display module 100 of the present embodiment further includes a demultiplexer, which is located in the fourth area iv of the non-display area 20; the demultiplexer comprises a plurality of transistors, the output ends of the transistors in the same demultiplexer are respectively and electrically connected with different data lines D, the input ends of the transistors in the same demultiplexer are respectively and electrically connected with the driving chip 60, and the control ends of the transistors in the same demultiplexer are respectively and electrically connected with different clock signal lines CKH; the driving chip 60 inputs different signals to the clock signal line CKH in different time periods to control the on and off of the transistor, and when the transistor is turned on, the driving chip 60 transmits the data signal to the data line D, so that the display module emits light.
Based on the same inventive concept, fig. 9 is a schematic workflow diagram of a driving method of a display module according to an embodiment of the present application, where the driving method is used to drive the display module 100 in the above embodiment, please refer to fig. 9, and in combination with fig. 2, the display module 100 includes: a display region 10 and a non-display region 20 at least partially surrounding the display region 10;
a plurality of cascaded shift registers 30 located in the non-display area 20;
the first signal line 40 is located in the non-display area 20 and located at one side of the shift register 30 near the display area 10;
the second signal line 50 is located in the non-display area 20 and located at one side of the first signal line 40 near the display area 10; the second signal line 50 at least partially surrounds the display area 10;
s101, in a test stage, the first signal line 40 transmits a common voltage signal, and the second signal line 50 transmits a data signal;
s102, in the display stage, the first signal line 40 transmits the pixel control signal, and the second signal line 50 transmits the common voltage signal.
Specifically, please continue to refer to fig. 9, and referring to fig. 5 and fig. 6, the driving method of the display module 100 provided in the present embodiment includes: a test stage driving and a display stage driving, wherein the test stage is used for eliminating bad display products, and in the test stage, the display area 10 only emits light; the display phase is used for displaying normal use of the product, and the display area 10 has high requirements for light emission during the display phase.
Further, in the testing stage, the first signal line 40 transmits a common voltage signal to the common electrode 110, the second signal line 50 transmits a data signal to the data line D, and provides a signal to the pixel electrode, so that a voltage is generated between the common electrode 110 and the pixel electrode, and the voltage drives the liquid crystal to deflect, and transmits light to the color film substrate, so that the display module emits light; in the display stage, the second signal line 50 transmits a common voltage signal to the common electrode 110, the driving chip 60 transmits a data signal to the data line D, and provides a signal to the pixel electrode, so that a voltage is generated between the common electrode 110 and the pixel electrode, and the voltage drives the liquid crystal to deflect, so that the display module emits light through light.
Fig. 10 is a schematic diagram of another workflow of a driving method of a display module according to an embodiment of the present application, fig. 11 is a schematic diagram of a structure of a driving circuit of a display module according to an embodiment of the present application, please refer to fig. 10 and 11, in an alternative embodiment of the present application, the display module 100 further includes:
the driving chip 60 is positioned in the non-display area 20, and the driving chip 60 is electrically connected with the first signal line 40 and the second signal line 50 respectively;
A test terminal 70 located in the non-display area 20, the test terminal 70 being electrically connected to the first signal line 40 and the second signal line 50, respectively;
a common electrode 110, the common electrode 110 being electrically connected to the first signal wiring 81 and/or the second signal wiring 82;
a data line D having a first end D-1 electrically connected to the driving chip 60 and a second end D-2 electrically connected to the second signal line 50;
the driving method further includes:
s201, in the test phase, the test terminal 70 transmits the first common voltage signal to the first signal line 40, and transmits the first common voltage signal to the common electrode 110 through the first signal line 81; the test terminal 70 transmits a test data signal to the second signal line 50, and the second signal line 50 transmits a test data signal to the second end D-2 of the data line D;
s202, in the display stage, the driving chip 60 transmits pixel control signals to the first signal line 40, and the first signal line 40 transmits pixel control signals to the display area 10; the driving chip 60 transmits a second common voltage signal to the second signal line 50, the second signal line 50 transmits the second common voltage signal to the common electrode 110 through the second signal trace 82, and the driving chip 60 transmits the display data signal to the first terminal D-1 of the data line D.
Specifically, please continue to refer to fig. 10 and 11, and the driving process of the testing stage and the display stage will be described in detail in this embodiment with reference to fig. 5 and 6;
s201, in a test stage, a first common voltage signal is input to a test terminal 70 arranged in a binding area by an external test circuit board, the first common voltage signal is transmitted to a common electrode 110 through a first signal wiring 81, the test terminal 70 transmits a test data signal to a second signal wire 50, the test data signal is provided to a pixel electrode 130, an electric field is formed between the pixel electrode 130 and the common electrode 110, and liquid crystal is driven to rotate; the second signal line 50 is required to be turned on by the gate of the thin film transistor to transmit the test data signal, so that the display module can be driven to emit light normally;
s202, in the display stage, the driving chip 60 transmits a second common voltage signal to the second signal line 50, the second common voltage signal is transmitted to the common electrode 110 through the second signal wiring 82, the driving chip 60 transmits a display data signal to the data line D, the display data signal is transmitted to the pixel electrode, an electric field is formed between the pixel electrode and the common electrode, and the liquid crystal is driven to rotate, wherein the data line transmits the display data signal to be conducted through the grid electrode of the thin film transistor, so that the display module can be driven to emit light; at this time, the first signal wiring 81 is used for transmitting a pixel control signal.
Fig. 12 is a schematic diagram of another workflow of a driving method of a display module according to an embodiment of the present application, fig. 13 is a schematic diagram of another workflow of a driving method of a display module according to an embodiment of the present application, please refer to fig. 12 and fig. 13, and fig. 5 and fig. 6 are combined, in an alternative embodiment of the present application, the display module 100 further includes: a first switch 91 and a second switch 92, the first switch 91 being connected in series in the first signal trace 81, the second switch 92 being connected in series in the second signal trace 82;
a switch control signal line 90, the switch control signal line 90 being electrically connected to the first switch 91 and the second switch 92, respectively;
in the test stage, a first potential signal is input to the switch control signal line 90, the first switch 91 is turned on, the second switch 92 is turned off, and the first signal line 40 inputs a first common voltage signal to the common electrode 110;
in the display stage, the second potential signal is input to the switch control signal line 90, the first switch 91 is turned off, the second switch 92 is turned on, and the second signal line 50 inputs the second common voltage signal to the common electrode 110.
Specifically, as shown in fig. 12 and 13, and referring to fig. 5 and 6, in the test stage of the present embodiment, a first potential signal is input to the switch control signal line 90, alternatively, the first potential signal is VGL, the first switch 91 is turned on, the second switch 92 is turned off, and the first signal line 40 inputs a first common voltage signal to the second end of the pixel electrode 130 through the first signal trace 81; in the display stage, a second potential signal is input to the switch control signal line 90, optionally, the second potential signal is VGH, the first switch 91 is turned off, the second switch 92 is turned on, and the second signal line 50 inputs a second common voltage signal to the second end of the pixel electrode 130 through the second signal trace 82; in this way, only one of the first switch 91 and the second switch 92 is turned on or off, so that different signals are further transmitted by the first signal line 40 and the second signal line 50 at different stages, the number of signal lines in the non-display area 20 can be reduced, and the narrow frame of the display module 100 is further facilitated.
In an alternative embodiment of the application, the first potential signal and the second potential signal are different.
Specifically, in this embodiment, the first potential signal is used in the test stage, the second potential signal is used in the display stage, and if only one of the first switch 91 and the second switch 92 is turned on, the first potential signal and the second potential signal are different, alternatively, the first potential signal is a low potential signal, and the second potential signal is a high potential signal; the first potential signal is a high potential signal, and then the first potential signal is a low potential signal; in this way, only one of the first switch 91 and the second switch 92 can be turned on or off effectively.
According to the above embodiments, the beneficial effects of the application are as follows:
according to the display module and the driving method thereof provided by the application, the narrow frame design of the display module is realized by adopting the mode that different signals are transmitted by the same signal line in stages; specifically, the display module comprises a plurality of cascaded shift registers, wherein the shift registers are positioned in a non-display area; the display module further comprises a first signal line and a second signal line which are both positioned in the non-display area, wherein the first signal line is positioned on one side of the shift register close to the display area, the second signal line is positioned on one side of the first signal line close to the display area, and the second signal line is at least partially arranged around the display area; it is understood that the second signal lines are at least partially arranged around the display area, the first signal lines are sequentially arranged at the periphery of the second signal lines, and the shift register is arranged at the periphery of the first signal lines; in the test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal; in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal; different signals are transmitted at different stages through the first signal wire and the second signal wire, and the first signal wire and the second signal wire are used in stages, so that the signal wires do not need to be arranged respectively corresponding to the test stage and the display stage, the number of the signal wires can be effectively reduced, the duty ratio of a non-display area is further reduced, and the narrow frame design of the display module is facilitated.
While the foregoing description illustrates and describes the preferred embodiments of the present application, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as limited to other embodiments, and is capable of numerous other combinations, modifications and environments and is capable of changes or modifications within the scope of the inventive concept as described herein, either as a result of the foregoing teachings or as a result of the knowledge or technology in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the application are intended to be within the scope of the appended claims.
Claims (13)
1. A display module, comprising: a display region and a non-display region at least partially surrounding the display region;
a plurality of cascaded shift registers located in the non-display area;
the first signal line is positioned in the non-display area and is positioned at one side of the shift register, which is close to the display area;
the second signal line is positioned in the non-display area and is positioned at one side of the first signal line, which is close to the display area; the second signal line at least partially surrounds the display area;
a common electrode located in the display area, the common electrode being responsive to a common voltage signal;
A first signal trace and a second signal trace, the first signal trace and/or the second signal trace being electrically connected to the common electrode; the end part of the first signal wire is electrically connected with the first signal wire, and the end part of the second signal wire is electrically connected with the second signal wire;
the first switch and the second switch are both positioned in the non-display area, the first switch is connected in series in the first signal wiring, and the second switch is connected in series in the second signal wiring;
in a test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal;
in a display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal;
only one of the first switch and the second switch is turned on during the test phase or the display phase.
2. The display module of claim 1, further comprising: the driving chip is positioned in the non-display area; the driving chip is electrically connected with the first signal line and the second signal line respectively;
the data line is positioned in the display area, extends along the first direction and is arranged along the second direction; the first end of the data line is electrically connected with the driving chip, and the second end of the data line is electrically connected with the second signal line;
In the display stage, the driving chip transmits a display data signal to a first end of the data line.
3. The display module of claim 2, further comprising: the test terminal is positioned in the non-display area and is electrically connected with the first signal line and the second signal line respectively;
in the test stage, the second signal line transmits the data signal to the second end of the data line, and the data signal is a test data signal.
4. The display module of claim 1, wherein the first signal trace and the second signal trace are each electrically connected to the common electrode, and the first signal trace and the second signal trace are each at least partially located in the display region and at least partially located in the non-display region.
5. The display module of claim 1, wherein the first signal trace is electrically connected to the common electrode, the first signal trace is at least partially located in the display region, at least partially located in the non-display region, and the second signal trace is located in the non-display region; one end of the second signal wire close to the display area is electrically connected with the first signal wire through a via hole.
6. The display module of claim 1, further comprising: and the switch control signal line is electrically connected with the first switch and the second switch respectively and is used for controlling the on and off of the first switch and the second switch.
7. The display module of claim 2, wherein the non-display area includes a first area and a second area disposed opposite each other, and a third area and a fourth area disposed opposite each other;
the second signal line is respectively positioned in the first area, the second area and the third area; the first signal line is respectively located in the first area and the second area, and the shift register is respectively located in the first area and the second area.
8. The display module assembly of claim 7, further comprising: a clock signal line located in the first region, the second region, and the fourth region, respectively;
the first signal line multiplexes the clock signal lines, and the pixel control signal is a clock signal.
9. The display module assembly of claim 8, further comprising: a demultiplexer circuit, said demultiplexer circuit being located in said fourth region iv;
The demultiplexer circuit comprises a plurality of transistors, wherein the control ends of the transistors in the same demultiplexer circuit are respectively and electrically connected with different clock signal lines, and the output ends of the transistors in the same demultiplexer circuit are respectively and electrically connected with different data lines.
10. A driving method of a display module, wherein the driving method is used for the display module according to any one of claims 1 to 9, the display module comprising: a display region and a non-display region at least partially surrounding the display region;
a plurality of cascaded shift registers located in the non-display area;
the first signal line is positioned in the non-display area and is positioned at one side of the shift register, which is close to the display area;
the second signal line is positioned in the non-display area and is positioned at one side of the first signal line, which is close to the display area; the second signal line at least partially surrounds the display area;
the common electrode is electrically connected with the first signal wiring and/or the second signal wiring;
the first switch is connected in series with the first signal wiring, and the second switch is connected in series with the second signal wiring;
In a test stage, the first signal line transmits a common voltage signal, and the second signal line transmits a data signal;
in the display stage, the first signal line transmits a pixel control signal, and the second signal line transmits a common voltage signal.
11. The driving method according to claim 10, wherein the display module further comprises:
the driving chip is positioned in the non-display area and is electrically connected with the first signal line and the second signal line respectively;
the test terminal is positioned in the non-display area and is electrically connected with the first signal line and the second signal line respectively;
the first end of the data wire is electrically connected with the driving chip, and the second end of the data wire is electrically connected with the second signal wire;
the driving method further includes:
in a test phase, the test terminal transmits a first common voltage signal to the first signal line and transmits the first common voltage signal to the common electrode through the first signal line; the test terminal transmits a test data signal to the second signal line, and the second signal line transmits the test data signal to the second end of the data line;
In a display stage, the driving chip transmits a pixel control signal to the first signal line, and the first signal line transmits the pixel control signal to the display area; the driving chip transmits a second common voltage signal to the second signal line, the second signal line transmits the second common voltage signal to the common electrode through the second signal line, and the driving chip transmits a display data signal to the first end of the data line.
12. The driving method according to claim 11, wherein the display module further comprises:
the switch control signal line is electrically connected with the first switch and the second switch respectively;
in a test stage, a first potential signal is input to the switch control signal line, the first switch is turned on, the second switch is turned off, and the first signal line inputs the first common voltage signal to the common electrode;
in the display stage, a second potential signal is input to the switch control signal line, the first switch is turned off, the second switch is turned on, and the second signal line inputs the second common voltage signal to the common electrode.
13. The driving method according to claim 12, wherein the first potential signal and the second potential signal are different.
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