JP2010102151A - Electrooptical device, electronic device, and driving method for electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a large voltage from being applied to both ends of a pixel selection transistor without deteriorating the image quality of a display image. <P>SOLUTION: In a common-reversal drive for periodically switching the potential LCCOM of the common electrode 1b of a liquid crystal element LC, a reset period (TB', TB'') for reducing a potential difference between a pixel electrode 1a and the common electrode 1b is arranged between a first writing period (T1) for gradation display and a switching period for switching the potential LCCOM of the common electrode 1b. After the reset period, the switching period TC for switching the potential of the common electrode 1b is arranged. In the reset period, a plurality of scanning lines WL are simultaneously driven, and also, a data potential for reducing the potential difference between the common electrode 1b and the pixel electrode 1a is supplied to the pixel electrode 1a of each of pixels. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electro-optical device (for example, a liquid crystal display device or an electrophoretic display device), an electronic apparatus, and a driving method of the electro-optical device.

  FIG. 17 is a diagram illustrating a configuration of a pixel circuit of a general liquid crystal display device. FIG. 18 is a perspective view showing a cross-sectional structure of the liquid crystal display device. The pixel circuit is provided corresponding to the intersection of the scanning line WL and the data line DL formed on the TFT (thin film transistor) substrate.

  The pixel circuit includes a pixel selection transistor M (NMOS transistor) whose on / off is controlled by a scanning voltage SEL of the scanning line WL, a storage capacitor C, and a liquid crystal element LC. The liquid crystal element LC includes a pixel electrode 1a, a common electrode 1b, and a liquid crystal that is an electro-optical material sandwiched between the pixel electrode 1a and the common electrode 1b.

  The liquid crystal element LC is connected between a common connection node PIX between the pixel selection transistor M and the pixel electrode 1a and the common line L1. In addition, the storage capacitor C is connected between the node PIX and the storage capacitor line L2.

  The holding capacitor C is provided to hold the potential written in the pixel. However, the holding capacitor C is omitted if it is not an essential component and can hold the potential written by the capacitance of the liquid crystal element LC itself. can do.

  The potential LCCOM of the common line L1 and the potential VCOM of the storage capacitor line L2 are generally set to the same potential. Further, although it is desirable to provide the common line L1 and the storage capacitor line L2 separately, both wirings can be shared. In a liquid crystal display device, generally, AC driving is performed in order to prevent the liquid crystal element LC from being burned.

The AC driving method for preventing the deterioration of the liquid crystal element LC in the liquid crystal display device can be broadly classified as follows. The potential LCCOM of the common electrode 1b is fixed, and the potential of the pixel electrode 1a is set to a positive voltage and a negative voltage with LCCOM as the center. And a second method (so-called common oscillation inversion method) in which the potential LCCOM of the common electrode 1b and the potential of the pixel electrode 1a are switched synchronously. The second method is described in Patent Document 1, for example. Note that subfield driving is described in, for example, Patent Document 2, and region division driving in subfield driving is described in, for example, Patent Document 3.
JP 2005-241741 A JP 2003-177723 A JP 2004-177930 A

  In the case of the first method in which the potential of the pixel electrode 1a is alternately switched between a positive voltage and a negative voltage with LCCOM as the center, a maximum voltage applied to the liquid crystal element LC (pixel) is applied to the source / drain of the pixel selection transistor M. A voltage twice as high as the voltage corresponding to the potential difference between the electrode 1a and the common electrode 1b is applied. For example, LCCOM is 0V, the positive write voltage is 5V, and the negative write voltage is −5V. When 5V is written to one pixel and then −5V is written to another row of pixels in the same column, the potential difference between the source and drain of the off-state pixel selection transistor in the one pixel is 10V. A voltage twice as high as the voltage applied to the liquid crystal element LC is applied. When a large voltage is applied to both ends of the pixel selection transistor, the pixel selection transistor is likely to be deteriorated. For example, a leakage current increases with time and power consumption may increase.

  In the case of the second method (so-called common oscillation inversion method) in which the potential LCCOM of the common electrode 1b and the potential of the pixel electrode 1a are switched in synchronization, the amplitude of the data potential written to each pixel via the data line. Is half of the first method. However, even when this second method is used, a voltage twice as high as the voltage applied to the liquid crystal element LC is instantaneously applied to the pixel selection transistor of one pixel. May contribute to the degradation of

  This problem will be described with reference to FIGS. 19 and 20 are diagrams for explaining voltages applied to both ends of the pixel selection transistor when the common swing inversion method is employed.

  As shown in FIG. 19A, it is assumed that a data potential of 5 V is written to the pixel P (1, 1). Next, as shown in FIG. 20, the potential LCCOM of the common line and the potential VCOM of the capacitor line are switched from 0V to 5V. At this time, the change in the potential VCOM of the capacitor line from 0 V to 5 V is transmitted to the node PIX via the storage capacitor C (or the capacitance of the liquid crystal element LC), and thus the potential of the node PIX is instantaneously changed. The voltage rises to 10 V (a voltage obtained by adding 5 V, which is a boost component due to capacitive coupling, to the write voltage 5 V). In this state, when the pixel selection transistor M of the pixel P (1,1) is turned off and subsequently a data potential of 0V is written to the pixel P (1,2), the pixel selection of the pixel P (1,1) is performed. A voltage of 10 V (a voltage twice the voltage applied to the liquid crystal element LC) is applied to both ends of the transistor M.

  The present invention has been made based on such consideration. According to at least one aspect of the present invention, for example, it is possible to prevent a large voltage from being applied to both ends of the pixel selection transistor without degrading the image quality of the display image.

  (1) One aspect of the electro-optical device of the present invention is provided corresponding to a plurality of scanning lines, a plurality of data lines, and an intersection of each of the plurality of scanning lines and each of the plurality of data lines. A scanning line driver having a plurality of pixels, a scanning line simultaneous driving circuit for simultaneously driving the plurality of scanning lines, a data line driver for driving the data line, and operations of the scanning line driver and the data line driver Each of the plurality of pixels includes a switching element whose on / off is controlled by one of the plurality of scanning lines, a pixel electrode, a common electrode, and the pixel An electro-optic element made of an electro-optic material sandwiched between an electrode and the common electrode, and when the common electrode is at a first potential as a period for writing data to each of the plurality of pixels In the picture A first writing period for supplying a data potential to one of the electrodes via one of the plurality of data lines; and the pixel electrode among the plurality of data lines when the common electrode is at a second potential. Between the first writing period and the second writing period for supplying the data potential via one of the first writing period and the second writing period. A potential switching period for switching to the second potential, and the control unit executes control to provide a reset period between the first writing period and the potential switching period. In the reset period, The scanning line driver is controlled to drive the plurality of scanning lines simultaneously by the scanning line simultaneous drive circuit, and the data line driver is controlled to control the image line in each of the plurality of pixels. The electrodes, to supply the data voltage for reducing the potential difference between the common electrode and the pixel electrode.

  In this aspect, before switching (reversing) the potential of the common electrode, a reset period is provided to bring the potential of the pixel electrode closer to the potential of the common electrode and reduce the potential difference between the two electrodes (most preferably the potential difference is zero). And). In this way, even when the potential of the pixel electrode is instantaneously boosted by capacitive coupling during the period of switching the potential of the common electrode, the increase in voltage is reduced compared to the prior art (between both electrodes by resetting). When the potential difference between the two is zero, the increase in voltage is ½). Therefore, the voltage applied to both ends of the pixel selection transistor is less than twice the maximum applied voltage to the liquid crystal element (when the potential difference between the two electrodes is zero by resetting, the maximum applied voltage to the liquid crystal element is The same voltage), and the deterioration of the characteristics of the pixel selection transistor is less likely to occur.

  Further, in this aspect, in the reset period, a plurality of scanning lines are simultaneously selected using a scanning line simultaneous drive circuit included in the scanning line driver, and the common electrode is simultaneously applied to each pixel electrode of the plurality of pixels. A data potential (hereinafter sometimes referred to as a reset potential) for reducing a potential difference between the pixel electrode and the pixel electrode is supplied. Thereby, it is possible to collectively reset each of the plurality of pixels, and the reset is completed in a very short period of time. For example, the period during which no voltage is applied between both electrodes is substantially only the potential switching period.

  If it takes a long time to write the reset potential to each pixel, this may cause a reduction in the image quality of the display image. For example, when the liquid crystal element is a normally white type and the reset potential is a potential corresponding to white data, the pixel electrode and the common electrode of the pixel after reset have the same potential, and the pixel displays white. (The state in which the transmittance of the liquid crystal element is increased). Therefore, when a long time is required for resetting, the transmittance of the liquid crystal element of each pixel is increased and the contrast of the display screen is lowered, so-called whitening phenomenon occurs, and the image quality may be lowered. In this aspect, as described above, since a plurality of scanning lines can be simultaneously selected and a reset potential can be simultaneously written to a plurality of pixels in one column, the reset period is very short, and a normally white liquid crystal element is used. Even if it is, whitening can be suppressed to such an extent that it hardly causes a problem.

  Further, the mechanism for simultaneously selecting a plurality of scanning lines can be realized relatively easily by changing the configuration of the output stage circuit of the scanning line driver, for example, and is easy to implement. Further, the circuit configuration can be further simplified and the space can be saved. Therefore, the present invention can be applied to a small electro-optical device.

  Further, in the driving method according to the present aspect in which the reset period is provided, the binary voltage is supplied to the pixel voltage for each of the plurality of subfields, and the transmittance of the liquid crystal element is controlled by the integrated applied voltage per unit time. Suitable for driving applications. Therefore, by applying the present invention, it is possible to suppress deterioration of element characteristics without degrading the image quality of a display image in a digital drive type electro-optical device.

  (2) In another aspect of the electro-optical device of the invention, the data potential for reducing the potential difference between the common electrode and the pixel electrode, which is the first potential, is the same potential as the first potential. Data potential.

  Thereby, the potential difference between the pixel electrode and the common electrode can be made zero by resetting. Therefore, even if the potential of the pixel electrode rises instantaneously by switching the potential of the common electrode, the voltage applied to both ends of the pixel selection transistor becomes the same voltage as the voltage applied to the liquid crystal element, and the characteristics of the pixel selection transistor Deterioration of is difficult to occur.

  (3) In another aspect of the electro-optical device according to the aspect of the invention, the electro-optical element is a normally white electro-optical element, and the control unit is configured to perform the reset after the end of the first writing period. Before the start of the period, each of the plurality of scanning lines is sequentially driven to execute control for providing a first black writing period for writing a black potential to each of the plurality of pixels, and after the potential switching period. In addition, before the start of the second writing period, the plurality of scanning lines are simultaneously driven by the scanning line simultaneous driving circuit of the scanning line driver, and the pixel electrodes in each of the plurality of pixels are simultaneously applied to the pixel electrodes. In addition, control for providing a second black writing period for writing a black potential is executed.

  As described above, the state in which the potential difference between the two electrodes is reduced (for example, the state in which no voltage is applied between the two electrodes) continues substantially in the potential switching period (which is necessary for switching the potential of the common electrode). Short time) only.

  However, since it is true that no voltage is applied to both electrodes during the potential switching period, in order to improve the image quality by reducing the influence of whitening of normally white liquid crystal during this period, In the aspect, the black writing period is provided before and after the reset period (that is, before the reset period and after the potential switching period). The reason for writing black not only before the reset period but also after the reset period is to align the black display time of the pixels in each row (so that there is no difference in the black display time of each row). This is to prevent the eyes from feeling uncomfortable.

  In the black writing period (first black writing period) before the reset period, each of the plurality of scanning lines is sequentially driven (including a line sequential driving of the scanning lines and a multiple sequential driving method in which a plurality of scanning lines are simultaneously selected). The black data potential is written to the pixel electrode of each pixel while selecting using.

  Further, in the black writing period (second black writing period) after the potential switching period, a plurality of scanning lines are driven all at once by the scanning line simultaneous driving circuit, and the pixel electrodes in each of the plurality of pixels are simultaneously applied. Write black data potential. Since the second black writing period ends in a very short period, writing of the next frame (second writing period) can be started immediately and efficient image display (image formation) is possible. is there.

  (4) In another aspect of the electro-optical device of the present invention, the first writing period or the second writing period is divided into a plurality of subfields on the time axis, and the floor to be displayed in each subfield. The sub-field driving type electro-optical device is configured to supply a binary data potential to each of the plurality of pixels according to the key and to control a voltage applied to the electro-optical element per unit time.

  As described above, the driving method for providing the reset period is a subfield driving in which a binary voltage is supplied to the pixel voltage for each of a plurality of subfields, and the transmittance of the liquid crystal element is controlled by the integrated applied voltage per unit time. Suitable for application to.

  When subfield driving is employed, for example, the following series of operations are executed. That is, in the first writing period for gradation expression, the data potential is written to each pixel for each of the plurality of subfields, and then the black potential is written in the final subfield. The scanning lines are selected all at once, and reset is executed so that the potential of the pixel electrode is the same as the potential of the common electrode. Next, the common electrode potential is switched (inverted), then all the scanning lines are simultaneously selected again to write the black potential to all the pixels, and in the next frame (second writing period). Transition. When such an operation is executed, the potential of the pixel electrode is substantially the same as the potential of the common electrode only in the time required for switching the potential of the common electrode, and a normally white liquid crystal element is used. Whitening is improved when there is. Therefore, by applying the present invention, it is possible to suppress the deterioration of the characteristics of the pixel selection transistor without reducing the image quality of the display image in the digital drive type electro-optical device.

  (5) In another aspect of the electro-optical device according to the aspect of the invention, the plurality of subfields may be weighted, and the plurality of scanning lines may be interlaced to scan at least two of the plurality of weighted subfields. Perform scanning of two subfields in parallel.

  In this aspect, the above driving method is applied to weighted subfield driving. In weighted subfield driving, so-called region division driving (a driving method in which scanning of a plurality of scanning lines is performed in a scanning manner and scanning of at least two of the weighted subfields is performed in parallel) is employed. In this case, each subfield scanning cycle is longer than in normal subfield driving (equal interval subfield driving). If simultaneous reset is not possible, the reset period becomes longer and white The float may become apparent. However, by applying the driving method of the present invention, simultaneous reset becomes possible, and the reset period is very short. Therefore, it becomes possible to reliably prevent the whitening from becoming obvious.

  (6) One aspect of the electronic apparatus of the invention includes any of the electro-optical devices described above.

  According to this aspect, for example, it is possible to provide an electronic device that has little change in display characteristics over time (deterioration with time), low power consumption, small size, and excellent display performance.

  (7) One aspect of the driving method of the electro-optical device according to the invention corresponds to a plurality of scanning lines, a plurality of data lines, and an intersection of each of the plurality of scanning lines and each of the plurality of data lines. Each of the plurality of pixels includes a switching element whose on / off is controlled by one of the plurality of scanning lines, a pixel electrode, a common electrode, An electro-optic device comprising an electro-optic material sandwiched between the pixel electrode and the common electrode, wherein the period of writing data to each of the plurality of pixels is A first writing period in which a data potential is supplied to the pixel electrode via one of the plurality of data lines when the common electrode is at a first potential; and when the common electrode is at a second potential. , The plurality of data on the pixel electrode Are provided between a second writing period for supplying a data potential via one of the first writing period, the first writing period, and the second writing period, and the potential of the common electrode is set to the first writing period. A potential switching period for switching from a potential to the second potential, and a reset period between the first writing period and the potential switching period. In the reset period, the plurality of scanning lines are provided. The data potential is driven all at once, and a data potential for reducing the potential difference between the common electrode and the pixel electrode, which is the first potential, is simultaneously supplied to the pixel electrodes in each of the plurality of pixels.

  According to the driving method of this aspect, even if the potential of the pixel electrode is instantaneously boosted by capacitive coupling by reducing the potential difference between the pixel electrode and the common electrode by resetting, the increase in voltage is not related to the prior art. Compared to this, the characteristics of the pixel selection transistor are hardly deteriorated. In addition, since a plurality of scanning lines can be selected simultaneously and a reset potential can be written to a plurality of pixels in one column at the same time, the reset period is very short, and even when a normally white liquid crystal element is used, white floating occurs. Can be suppressed to such an extent that it hardly causes a problem.

  (8) In another aspect of the driving method of the electro-optical device according to the aspect of the invention, the data potential for reducing the potential difference between the common electrode and the pixel electrode, which is the first potential, is the first potential. Each of the plurality of scanning lines is sequentially driven so that each of the plurality of pixels has the same data potential and is after the end of the first writing period and before the start of the reset period. A first black writing period for writing a black potential is provided, and the plurality of scanning lines are simultaneously driven after the potential switching period and before the start of the second writing period, A second black writing period for writing a black potential is provided to the pixel electrodes in each of the above.

  According to the driving method of this aspect, the potential difference between the pixel electrode and the common electrode can be made zero by resetting. Therefore, even if the potential of the pixel electrode rises instantaneously by switching the potential of the common electrode, the voltage applied to both ends of the pixel selection transistor becomes the same voltage as the voltage applied to the liquid crystal element, and the characteristics of the pixel selection transistor Degradation is less likely to occur.

  In addition, by providing a black writing period before and after the reset period (that is, before the reset period and after the potential switching period), the influence of whitening of the normally white liquid crystal is reduced and the image quality is further improved. be able to. The reason for writing black not only before the reset period but also after the reset period is to align the black display time of the pixels in each row (so that there is no difference in the black display time of each row). This is to prevent the eyes from feeling uncomfortable. In the black writing period (first black writing period) before the reset period, each of the plurality of scanning lines is sequentially driven (including a line sequential driving of the scanning lines and a multiple sequential driving method in which a plurality of scanning lines are simultaneously selected). The black data potential is written to the pixel electrode of each pixel while selecting using. Further, in the black writing period (second black writing period) after the potential switching period, a plurality of scanning lines are driven all at once by the scanning line simultaneous driving circuit, and the pixel electrodes in each of the plurality of pixels are simultaneously applied. Write black data potential. Since the second black writing period ends in a very short period, writing of the next frame (second writing period) can be started immediately and efficient image display (image formation) is possible. is there.

  As described above, according to at least one aspect of the present invention, for example, it is possible to prevent a large voltage from being applied to both ends of the pixel selection transistor without degrading the image quality of the display image.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

(First embodiment)
First, a liquid crystal driving method for providing a reset period will be described.

(Liquid crystal driving method with a reset period)
1A to 1C are diagrams for describing an example of a liquid crystal driving method for providing a reset period. FIG. 1A illustrates a state of the pixel circuit in the writing period TA. As shown in the figure, the scanning line WL is selected by the scanning signal SEL1, the pixel selection transistor M is turned on, and the data data potential DAT1 (5 V) is supplied to the pixel electrode 1a of the pixel circuit. The potential LCCOM of the common electrode 1b and the potential VCOM of the storage capacitor line are held at 0V.

  FIG. 1B shows a state of the pixel circuit in the reset period TB. With the scanning line WL selected by the scanning signal SEL1, the pixel electrode 1a of the pixel circuit has a data potential DAT2 (here, 0V) for reducing the potential difference between the pixel electrode 1a and the common electrode 1b. Supplied. The potential LCCOM of the common electrode 1b is held at 0V. Therefore, the potential difference between the pixel electrode 1a and the common electrode 1b becomes zero, and the liquid crystal element LC is not applied with a voltage (reset state). Note that even if the potential difference between the pixel circuit 1a and the common electrode 1b is not zero, the maximum voltage applied to both ends of the pixel selection transistor M is less than the maximum voltage 5V applied to the liquid crystal element LC. The effect of reducing the voltage is obtained. Therefore, the reset state includes a state in which the potential difference between the pixel circuit 1a and the common electrode 1b is reduced by the maximum applied voltage to the liquid crystal.

  FIG. 1C illustrates a state of the pixel circuit in the COM inversion period (potential switching period). In the COM inversion period (potential switching period), the potential LCCOM of the common electrode 1b (and the potential VCOM of the storage capacitor line) is switched from 5V to 0V (COM inversion). The COM inversion is performed, for example, periodically (for example, every frame) in order to prevent the liquid crystal element LC from being burned.

  Along with COM inversion, the potential of the pixel electrode 1a (potential of the node PIX) instantaneously increases from 0V to 5V due to capacitive coupling, but compared with 10V, which is the voltage increase in the prior art shown in FIG. 1/2. That is, the voltage level applied to both ends of the pixel selection transistor M can be set to the same level as the maximum applied voltage to the liquid crystal element LC. Therefore, deterioration of the characteristics of the pixel selection transistor M (for example, increase in leakage current over time, destruction of the pixel selection transistor M, etc.) is less likely to occur.

  FIG. 2 is a diagram illustrating changes in the scanning signal potential SEL1, the data potential DAT, the common electrode potential LCCOM, and the potential of the node PIX (PIX) in the writing period TA, the reset period TB, and the COM inversion period TC. The potential change shown is repeated periodically.

  However, if it takes a long time to write the reset potential to each pixel, this may cause a reduction in the image quality of the display image. For example, when the liquid crystal element LC is a normally white type and the reset potential (the data potential supplied to the pixel electrode 1b via the data line DL in the reset period TB) is a potential corresponding to white data, the reset is performed. The pixel electrode 1a and the common electrode 1b of the subsequent pixel are at the same potential, and the pixel is in a state of displaying white (a state in which the transmittance of the liquid crystal element LC is increased). Therefore, if a long time is required for resetting, the transmittance of the liquid crystal element LC of each pixel increases and the contrast of the display screen decreases, so-called whitening phenomenon occurs, and the image quality may deteriorate.

  Therefore, in the present embodiment, in the reset period, a plurality of scanning lines are selected at once using a scanning line simultaneous drive circuit included in the scanning line driver, and are shared by the pixel electrodes of the plurality of pixels all at once. A data potential (reset potential) for reducing the potential difference between the electrode and the pixel electrode is supplied. Thereby, it is possible to collectively reset each of the plurality of pixels, and the reset is completed in a very short period of time. For example, the period during which no voltage is applied between both electrodes is substantially only the potential switching period. Further, in the driving method of the present embodiment in which the reset period is provided, a binary voltage is supplied to the pixel voltage for each of the plurality of subfields, and the transmittance of the liquid crystal element is controlled by the integrated applied voltage per unit time. Suitable for field drive applications.

(Example of sub-field driving in which multiple scanning lines are simultaneously selected at reset)
FIG. 3 is a diagram for explaining an example of subfield driving in which a plurality of scanning lines are simultaneously selected at the time of resetting.

  FIG. 3A shows an operation of the liquid crystal display device in the case where the driving method provided with the reset period shown in FIGS. 1A to 1C is applied to subfield driving. In the driving method in FIG. 3A, the simultaneous driving method of the scanning lines is not adopted. The number of scanning lines in the display unit is n (for example, n = 1080). In addition, a normally white liquid crystal element is used.

  Here, one frame (16.6 ms) is divided into 18 subfields (SF), and 16 subfields are used for gradation expression. Here, one subfield is 0.2 ms, for example. A period from time t1 to t2 is a gradation expression period (first writing period) TA. For each subfield, a binary data potential of 1 (on) or 0 (off) is supplied to each pixel. The total applied voltage to the liquid crystal is determined by the ON / OFF time ratio of each pixel when viewed in the entire gradation expression period, thereby realizing a desired gradation display of each pixel. Note that in the gradation expression period TA, the potential LCCOM of the common electrode 1b is held at 0V.

  In each subfield (SF), n scanning lines are driven in a line sequential manner. The arrows in the figure indicate the scanning state (display state) of the pixels in each row. After the gradation expression period ends, reset is performed. A period from time t2 to t3 is a reset period TB. In the reset period TB, the scanning lines WL are scanned line-sequentially, and a white data potential (0 V) data potential is written into the pixel electrode 1a.

  Subsequently, COM inversion (switching between the common electrode potential LCCOM and the capacitance line potential VCOM) is performed. The period from time t3 to t4 is the COM inversion period TC. The COM inversion period TC is, for example, 0.05 ms. Subsequently, at time t4 to t5, the white data potential (0 V) is written to each pixel while scanning the scanning line from the n-th row to the first row in a line-sequential manner. Even after the reset period TC, the white data is written because the white display time of the pixels in each row is made uniform (the difference is not caused in the white display time of each row), and the user feels uncomfortable. This is to prevent it from occurring.

  However, in the driving method shown in (1) of FIG. 3, no voltage is applied to the liquid crystal element LC in the period from time t2 to time t5. Therefore, when aiming for a higher-definition display, The phenomenon of whitening and a decrease in contrast may be a problem.

  Therefore, in the present embodiment, as described above, a plurality of scanning lines are simultaneously selected, and a reset potential is simultaneously written to a plurality of pixels in one column. As a result, the reset period is very short, and even when a normally white liquid crystal element is used, whitening can be suppressed to such an extent that it hardly causes a problem.

  In (2) of FIG. 3, after the gradation expression period TA ends at time t2, all the scanning lines are selected at once and reset is executed. In the figure, the period TB 'is the all-scan line simultaneous selection reset period, and this period is very short. However, since it is true that no voltage is applied to both electrodes during the COM inversion period (potential switching period) TC, the effect of whitening of normally white liquid crystal during this period is reduced to further improve image quality. Therefore, it is preferable to provide a black writing period before and after the reset period (that is, before the reset period and after the COM inversion period).

  FIG. 3 (3) shows a driving example in which a black writing period is provided before and after the reset period. The reason for writing black not only before the reset period but also after the reset period is to align the black display time of the pixels in each row (so that there is no difference in the black display time of each row). This is to prevent the eyes from feeling uncomfortable.

  In (3) of FIG. 3, in the black writing period (first black writing period: time t2 to t3) before the reset period TC, each of the plurality of scanning lines is sequentially driven (line-sequential driving of scanning lines, a plurality of scanning lines). The black data potential is written to the pixel electrode of each pixel while selecting using a plurality of sequential driving methods for simultaneously selecting the scanning lines.

  Immediately after time t3, an all-scan line simultaneous selection reset period TB ″ is provided. This all-scan line simultaneous selection reset period TB ″ can be a short time. After the reset is completed, a COM inversion period TC is provided. Then, after the COM inversion is completed, black data is written again. That is, after completion of COM inversion, a black writing period TQ is provided by simultaneous driving of all scanning lines (time t4).

  In the black writing period (second black writing period: time t4) after the COM inversion period (potential switching period) TC, the plurality of scanning lines are driven all at once and the pixel electrodes in each of the plurality of pixels are simultaneously applied. Write black data potential. Since the second black writing period ends in a very short period, writing of the next frame (second writing period) can be started immediately (time t4), and efficient image display (image formation) Is possible. In the present embodiment, the driving method shown in (2) of FIG. 3 or (3) of FIG. 3 is adopted.

(Configuration example of a liquid crystal display device compatible with sub-field driving)
FIG. 4 is a diagram illustrating an example of a configuration of a liquid crystal display device corresponding to subfield driving. The liquid crystal display device includes a display unit (active matrix unit) 101, a control unit 200 including a timing signal generation circuit 201, an image processing unit 300 including a data coding circuit 301 and a field memory 310, and a scanning line simultaneous drive circuit 403. The scanning line driver 400 includes a data line driver 500. In the display unit (active matrix unit) 101, a plurality of pixels P (1,1) to P (n, n) are arranged in a matrix.

  The scanning line driver 400 drives (selects) the scanning line WL by the scanning signals SEL1 to SELn. The data line driver 500 supplies display voltages (binary data potentials for realizing display gradation) DAT1 to DATn to each pixel via the data line DL in a time division manner.

Binary data VID that is the basis for generating display voltages (binary data potentials) DAT1 to DATn
Is generated by a data coding circuit 301 provided in the image processing unit 300. The operation timing of each unit is controlled based on various timing signals output from the timing signal generation circuit 201 included in the control unit 200.

  The timing signal generation circuit 201 is connected to a polarity inversion signal FR, a data latch signal LAT, a data driver clock according to timing signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK supplied from a host device (not shown). CLX, data driver clock inversion signal CBX, and data driver start pulse SPX are generated and supplied to the data line driver 500. In addition, the timing signal generation circuit 201 generates a scan driver clock CLY, a scan driver clock inversion signal CBY, and a scan driver start pulse SPY and supplies the scan driver clock CLY to the scan line driver 400. The timing signal generation circuit 201 also supplies the scanning line driver 400 with a scanning line simultaneous drive control signal ALHIY for causing the scanning line simultaneous driving circuit 403 to perform simultaneous driving of a plurality of scanning lines. Further, the timing signal generation circuit 210 generates a subfield identification signal SF. The function of each signal will be described below.

  The polarity inversion signal FR is a signal whose polarity is inverted every field. The scan driver start pulse SPY is a pulse signal output at the beginning of each subfield, and when this is input to the scan line drive circuit 400, the scan line drive circuit 400 starts outputting the scan signals SEL1 to SELn. . The scanning driver clock CLY is a signal that defines the scanning speed (Y side), and the scanning signals SEL1 to SELn are sent for each scanning line in synchronization with the scanning driver clock CLY. The scan driver clock inversion signal CBY is a control signal for inverting the scan driver clock. The data latch signal LAT is a timing control signal for determining the timing at which data stored in a shift register provided in the data line driver 500 is output in parallel for the number of horizontal pixels.

  The data driver clock signal CLX is a clock signal for transferring data to the data line driver 500. The data driver start pulse SPX is a pulse signal output at the beginning of each subfield. The data driver clock inversion signal CBX is a control signal for inverting the data driver clock. Further, the subfield identification signal SF is for informing the data coding circuit 301 of what number the pulse (subfield) is.

  The data coding circuit 301 needs to recognize which subfield of one field when the display data is binarized. In the present embodiment, the timing signal generation circuit 201 counts the scan driver start pulse SPY and outputs the result as a subfield identification signal SF toward the data coding circuit 301. The data coding circuit 301 recognizes a subfield by the subfield identification signal SF.

  The field memory 310 connected to the data coding circuit 301 has a capacity for storing display data for two fields, for example. Here, the first field memory is a memory in which display data input from the outside is written, and the second field memory is a memory in which display data input one field before is stored. In the field memory 310, the display data of each pixel is read by the data coding circuit 301 accessing the second field memory while the display data manually input from the outside is written in the first field memory. It has become. The roles of the first field memory and the second field memory are exchanged for each field.

(Example of internal configuration of scanning line driver and data line driver)
FIG. 5 is a diagram illustrating an internal configuration example of the scanning line driver and the data line driver. The scan line driver 400 includes a shift register 401 and a scan line simultaneous drive circuit 403. The scanning line simultaneous drive circuit 403 is controlled by a scanning line simultaneous drive control signal ALHIY. The data line driver 500 includes a shift register 501, a first latch 502, and a second latch 503. Six columns of pixel data are sequentially stored in the first latch 502, and after the pixel data of all columns are stored, the pixel data is stored in the second latch 503 by the control signal LAT. In FIG. 5, the storage capacitor line for supplying VCOM and the common electrode line for supplying LCCOM are shown in common.

  6A and 6B are diagrams for explaining an example of a circuit configuration and an operation of a main part of the scanning line simultaneous driving circuit. 6A shows the configuration of the output stage circuit of each row of the scanning line simultaneous drive circuit, and FIG. 6B is a truth table showing the operation of the output stage circuit of each row of the scanning line simultaneous drive circuit. . SEL is a scanning signal, SROUT is an output signal of the shift register, and ALHIY is a scanning line simultaneous drive control signal. In FIG. 6A, M11, M13, and M14 are PMOS transistors, and M12, M15, and M16 are NMOS transistors. When the scanning line simultaneous drive control signal ALHIY is L (off), the PMOS transistor M13 is turned on, and the scanning signal SEL corresponding to the output signal SROUT of the shift register is obtained.

  When the scanning line simultaneous drive control signal ALHIY is H (on), the PMOS transistor M13 is turned off, the NMOS transistor M16 is turned on, and the output level of the first stage CMOS inverter composed of the transistors M11 and M12 is fixed to the L level. Is done. Therefore, the scanning signal SEL is fixed to the H level regardless of the output signal SROUT of the shift register. Therefore, when the scanning line simultaneous drive control signal ALHIY is set to H, for example, the scanning signals of all the rows can be forced to H, thereby enabling simultaneous selection of a plurality of scanning lines.

  FIG. 7 is a diagram showing the ON timing of the scanning line simultaneous drive control signal ALHIY in the subfield drive. The subfield driving method in FIG. 7 is the same as the driving method shown in (3) of FIG. As shown in the figure, the scanning line simultaneous drive control signal ALHIY is turned on at times t3 and t4.

  In the sub-field driving shown in FIG. 7, the data potential is written to each pixel for each of the plurality of sub-fields in the first writing period TA for gradation expression, and then black is applied in the final sub-field. The potential is written (period TS), and then all the scanning lines are simultaneously selected and reset is performed (period TB ″), so that the potential of the pixel electrode 1a is the same as the potential of the common electrode 1b. Next, switching (inversion) of the potential of the common electrode 1b is performed, and then all the scanning lines are simultaneously selected again to write the black potential to all the pixels (period TQ), and the next frame (second) (Time period t4). When such an operation is executed, the potential of the pixel electrode 1a becomes the same as the potential LCCOM of the common electrode 1b substantially only in the time required for switching the potential LCCOM of the common electrode 1b, and is normally white. The white floating in the case of using the liquid crystal element LC is improved. Therefore, by applying the present invention, it is possible to suppress the deterioration of the characteristics of the pixel selection transistor without reducing the image quality of the display image in the digital drive type electro-optical device.

(Second Embodiment)
In the present embodiment, the driving method of the present invention is applied to weighted subfield driving. In the weighting subfield drive of the present embodiment, weighting is performed on a plurality of subfields (that is, a plurality of subfields having different intervals are used instead of equally spaced subfields), and a plurality of scanning lines are interlaced and scanned. Thus, so-called region division driving is performed in which scanning of at least two of the weighted subfields is performed in parallel.

  In weighted subfield driving, so-called region division driving (a driving method in which scanning of a plurality of scanning lines is performed in a scanning manner and scanning of at least two of the weighted subfields is performed in parallel) is employed. In this case, each subfield scanning cycle is longer than in normal subfield driving (equal interval subfield driving). If simultaneous reset is not possible, the reset period becomes longer and white The float may become apparent. However, by applying the driving method of the present invention, simultaneous reset becomes possible, and the reset period is very short. Therefore, it becomes possible to reliably prevent the whitening from becoming obvious. This will be specifically described below.

(Subfield configuration)
FIG. 8 is a diagram illustrating a configuration example of subfields in weighted subfield driving. In the figure, the cycle of the data driver clock signal CLX is denoted as H. As shown, one field is provided with eight subfields (Sf1 to Sf8). The period of each subfield is not equal, but the interval is adjusted according to weighting. The period of one field is equally divided into four groups, and each group is further divided into two subfields (1, 2). The smallest subfield (Sf1, sf5, sf7) is a subfield having a higher resolution than the equally spaced subfields of the above-described embodiment, and therefore, a higher gradation display is possible.

  FIG. 9 is a diagram illustrating a configuration example (conversion example) of a data conversion table mounted on the data coding circuit. In the figure, when “1”, an on-voltage is applied to the liquid crystal element, and when “0”, an off-voltage is applied to the liquid crystal element.

  When the method of selecting the scanning lines in a line-sequential manner is employed, for example, it is necessary to finish scanning of all scanning lines (for example, 1080 scanning lines) within the period of the shortest subfield sf1. Circuit operation is required, which may be difficult to achieve. In the subfield sf1, if the period for scanning all the scanning lines can be made longer, the above problem is solved. Therefore, in this embodiment, the area division driving technique described in Japanese Patent Application Laid-Open No. 2004-177930 is adopted.

  When the area division driving method is adopted, for example, the scanning lines are the first line, the (n + 1) th line, the second line, the (n + 2) line, the third line, the (n + 3) line, and so on. In addition, the interlace scanning is performed according to a predetermined rule. For example, n = 100. The first subfield is written by scanning the first row, the second row, the third row,..., While the first row, the 102th row, the 103rd row,. A second subfield different from the subfield is written. In this case, the display area is divided into two, and the data of the first subfield and the second subfield are written in each area by time division. Since data of a plurality of fields is written in a time division manner while scanning over the scanning lines, if one subfield is viewed, the writing cycle becomes longer in proportion to the number of area divisions. Subfield driving can be realized.

  FIGS. 10A to 10C are diagrams showing the progress of scanning line selection in weighted subfield driving. FIG. 10A shows the progress of each subfield on the time axis. In the figure, the downward triangles painted in black indicate the timing of the start pulse SPY. FIG. 10B shows the progress of the subfield at timing T1, and FIG. 10C shows the progress of the subfield at timing T2. As is clear from FIGS. 10B and 10C, writing of a plurality of subfields proceeds in parallel.

  FIG. 11 is a diagram illustrating a main configuration example of a liquid crystal display device that performs weighted subfield driving. The basic configuration of the liquid crystal display device of FIG. 11 is the same as that of the liquid crystal display device shown in FIG. However, in FIG. 11, a control circuit 360, a memory 361, and a conversion table 363 as a data coding circuit are provided. In addition, an enable circuit 402 is provided in the scanning line driver 400 in order to perform interlace scanning. For example, by selecting simultaneously the shift register output corresponding to each of the plurality of scanning lines, and selecting and outputting one of them at a predetermined timing by the enable circuit 402, it is possible to perform interlace scanning of the scanning lines. Become.

  FIG. 12 is a diagram illustrating an internal configuration example of a scanning line driver and a data line driver in a liquid crystal display device that performs weighted subfield driving. The configuration shown in FIG. 12 is basically the same as the configuration shown in FIG. However, in FIG. 12, an enable circuit 402 is provided in the scanning line driver 400.

  13A and 13B are diagrams for explaining a configuration example and an operation of the output stage circuit in each row of the enable circuit. FIG. 13A shows the configuration of the output stage circuit in each row of the enable circuit 402, and FIG. 13B is a truth table showing the operation of the output stage circuit. ENBY is an enable control signal, EOUT is an enable signal output from the output stage circuit, and SROUT is an output signal of the shift register. In FIG. 13A, M20, M22, and M23 are PMOS transistors, and M21 and M24 are NMOS transistors. When the enable signal ENBY is H (off), the NMOS transistor M21 is turned on, and the enable signal EOUT corresponding to the output signal SROUT of the shift register is obtained. For example, the scanning signal SEL is generated by taking the logical product of the enable signal EOUT and the shift register output SROUT. Thereby, a desired single scanning line can be selected from the plurality of scanning lines.

  When the enable signal ENBY is L (on), the PMOS transistor M22 is turned on, the NMOS transistor M21 is turned off, and the output level of the first-stage CMOS inverter composed of the transistors M20 and M21 is fixed to the H level. Therefore, the enable signal EOUT is fixed at the L level regardless of the output signal SROUT of the shift register. Therefore, the non-selected scanning line can be maintained at the inactive level (L level).

  FIG. 14 is a diagram showing the ON timing of the scanning line simultaneous drive control signal ALHIY in the weighted subfield drive. The operation in the weighting subfield driving method of FIG. 14 is basically the same as the operation in the driving method shown in FIG. However, in the case of the weighted subfield drive of FIG. 14, the four subfields are advanced in parallel, so the write cycle of one subfield is four times.

  That is, in the case of the weighted subfield drive of FIG. 14, each subfield scanning cycle is longer than the normal subfield drive (equal interval subfield drive) shown in FIG. There is a case where the reset period becomes longer and whitening becomes apparent. However, as described above, by applying the driving method of the present invention, simultaneous reset becomes possible, and the reset period is very short. Therefore, it becomes possible to reliably prevent the whitening from becoming obvious. As shown in the figure, the scanning line simultaneous drive control signal ALHIY is turned on at times t3 and t4.

(Third embodiment)
15A and 15B are diagrams for explaining another example of the circuit configuration and operation of the main part of the scanning line simultaneous drive circuit. FIG. 15A shows the configuration of the output stage circuit in each row of the scanning line simultaneous drive circuit, and FIG. 15B is a truth table showing the operation in the output stage circuit in each row of the scanning line simultaneous drive circuit. .

  The output stage circuit shown in FIG. 15A is composed of a two-stage CMOS inverter. The scanning line simultaneous drive control signal (negative logic) / ALHIY is supplied as a power source for the PMOS transistor M30 constituting the first stage inverter. When / ALHIY is H, the first-stage inverter operates to obtain the scanning signal SEL corresponding to the shift register output SROUT. When / ALHIY is L, the output of the first-stage inverter is at L level, so that the scanning signal SEL is forcibly fixed to H. Therefore, simultaneous driving of a plurality of scanning lines is possible.

  The output stage circuit of FIG. 6 is composed of 6 elements, whereas the output stage circuit of FIG. 15 is composed of 4 elements. Therefore, the circuit configuration of the scanning line simultaneous drive circuit 403 can be simplified, and the area occupied by the circuit and the power consumption can be reduced.

(Fourth embodiment)
FIG. 16 is a perspective view showing an appearance of an example (mobile phone terminal) of an electronic apparatus equipped with the electro-optical device of the present invention. The cellular phone terminal 1300 includes a key operation unit 1302, an earpiece (speaker) 1304, a mouthpiece (microphone) 1306, and an electro-optical device (for example, a liquid crystal display device) 100 that includes the pixel circuit of the present invention. And having.

  By mounting the electro-optical device of the present invention, there is little change in display characteristics over time (deterioration with time) due to deterioration of the characteristics of the pixel transistor, excellent reliability, low leakage current (and hence low power consumption). ), It is possible to provide an electronic device that can cope with downsizing and has excellent display performance.

  As described above, according to at least one embodiment of the present invention, for example, it is possible to prevent a large voltage from being applied to both ends of the pixel selection transistor without degrading the image quality of the display image. .

  In addition, this invention is not limited to the above-mentioned embodiment. Those skilled in the art will readily appreciate that many variations are possible without substantially departing from the novel features and advantages of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configuration and operation of the pixel circuit are not limited to those described in the above embodiment, and various modifications and applications are possible.

1A to 1C are diagrams for explaining an example of a liquid crystal driving method in which a reset period is provided. The figure which shows the change of the scanning signal potential, the data potential, the potential of the common electrode, and the potential of the node PIX in the writing period, the reset period, and the COM inversion period. The figure for demonstrating the example of the subfield drive which performs simultaneous selection of several scanning lines at the time of reset The figure which shows an example of a structure of the liquid crystal display device corresponding to a subfield drive The figure which shows the internal structural example of a scanning line driver and a data line driver 6A and 6B are diagrams for explaining an example of a circuit configuration and an operation of a main part of the scanning line simultaneous driving circuit. The figure which shows the ON timing of the scanning line simultaneous drive control signal ALHIY in a subfield drive The figure which shows the structural example of the subfield in weighting subfield drive The figure which shows the structural example (conversion example) of the data conversion table mounted in a data coding circuit FIGS. 10A to 10C are diagrams showing the progress of scanning line selection in weighted subfield driving. The figure which shows the main structural examples of the liquid crystal display device which performs weighting subfield drive The figure which shows the internal structural example of a scanning line driver and a data line driver in the liquid crystal display device which performs weighting subfield drive 13A and 13B are diagrams for explaining a configuration example and operation of the output stage circuit in each row of the enable circuit. The figure which shows the ON timing of the scanning line simultaneous drive control signal ALHIY in weighting subfield drive 15A and 15B are diagrams for explaining another example of the circuit configuration and operation of the main part of the scanning line simultaneous driving circuit. The perspective view which shows the external appearance of an example (cellular-phone terminal) of the electronic device carrying the electro-optical apparatus of this invention The figure which shows the structure of the pixel circuit of a general liquid crystal display device The perspective view which shows the cross-section of a liquid crystal display device Diagram for explaining the voltage applied to both ends of the pixel selection transistor when the common oscillation inversion method is adopted Diagram for explaining the voltage applied to both ends of the pixel selection transistor when the common oscillation inversion method is adopted

Explanation of symbols

101 display unit (active matrix unit), 200 control unit,
201 timing signal generation circuit, 300 image processing unit,
301 data coding circuit, 310 field memory,
400 scan line driver, 403 scan line simultaneous drive circuit,
500 data line driver, TA gradation expression period,
TB (TB ′, TB ″) All-scan line simultaneous drive reset period,
White writing period by TS sequential scanning, Black writing period by TS 'sequential scanning,
TC COM inversion period (potential switching period),
TQ All scanning lines simultaneous drive black writing period

Claims (8)

A plurality of scan lines;
Multiple data lines,
A plurality of pixels provided corresponding to an intersection of each of the plurality of scanning lines and each of the plurality of data lines;
A scanning line driver having a scanning line simultaneous drive circuit that drives the plurality of scanning lines simultaneously;
A data line driver for driving the data line;
A control unit that controls operations of the scanning line driver and the data line driver, and each of the plurality of pixels includes a switching element that is controlled to be turned on / off by one of the plurality of scanning lines. A pixel electrode, a common electrode, and an electro-optic element made of an electro-optic material sandwiched between the pixel electrode and the common electrode,
In addition, as a period for writing data to each of the plurality of pixels, when the common electrode is at a first potential, a data potential is supplied to the pixel electrode via one of the plurality of data lines. A first writing period; a second writing period for supplying a data potential to the pixel electrode via one of the plurality of data lines when the common electrode is at a second potential; and A potential switching period for switching the potential of the common electrode from the first potential to the second potential is provided between the writing period and the second writing period,
The controller is
Executing a control for providing a reset period between the first writing period and the potential switching period;
In the reset period,
Controlling the scanning line driver to drive the plurality of scanning lines simultaneously by the scanning line simultaneous drive circuit;
Further, the data line driver is controlled so that a data potential for reducing a potential difference between the common electrode and the pixel electrode is supplied to the pixel electrode in each of the plurality of pixels. Electro-optic device. The electro-optical device according to claim 1,
The electro-optical device, wherein the data potential for reducing the potential difference between the common electrode and the pixel electrode, which is the first potential, is the same data potential as the first potential. The electro-optical device according to claim 1 or 2,
The electro-optic element is a normally white type electro-optic element,
The controller is
A first black writing period in which each of the plurality of scanning lines is sequentially driven to write a black potential to each of the plurality of pixels after the end of the first writing period and before the start of the reset period. Execute the control to provide
Further, after the potential switching period and before the start of the second writing period, the plurality of scanning lines are simultaneously driven by the scanning line simultaneous driving circuit of the scanning line driver, and An electro-optical device that performs a control for providing a second black writing period for writing a black potential simultaneously to the pixel electrodes in each of the pixel electrodes. The electro-optical device according to any one of claims 1 to 3,
The first writing period or the second writing period is divided into a plurality of subfields on a time axis, and in each subfield, a binary value is added to each of the plurality of pixels in accordance with a gradation to be displayed. An electro-optical device that is a sub-field drive type electro-optical device that supplies a data potential and controls a voltage applied to the electro-optical element per unit time. The electro-optical device according to claim 4,
The plurality of subfields are weighted, and the plurality of scanning lines are interlaced to perform scanning of at least two subfields of the weighted subfields in parallel. An electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 1. A plurality of scanning lines; a plurality of data lines; and a plurality of pixels provided corresponding to intersections of each of the plurality of scanning lines and each of the plurality of data lines. Each includes a switching element whose on / off is controlled by one of the plurality of scanning lines, a pixel electrode, a common electrode, and an electro-optical material sandwiched between the pixel electrode and the common electrode An electro-optic device comprising: an electro-optic element comprising:
As a period for writing data to each of the plurality of pixels, a first potential for supplying a data potential to the pixel electrode via one of the plurality of data lines when the common electrode is at a first potential. A writing period; a second writing period for supplying a data potential to the pixel electrode via one of the plurality of data lines when the common electrode is at a second potential; and the first writing. And a potential switching period for switching the potential of the common electrode from the first potential to the second potential, provided between the period and the second writing period,
A reset period is provided between the first writing period and the potential switching period,
In the reset period, the plurality of scanning lines are driven all at once, and the pixel electrodes in each of the plurality of pixels are simultaneously moved between the common electrode and the pixel electrode that are at the first potential. A driving method of an electro-optical device, characterized by supplying a data potential for reducing a potential difference. A method for driving an electro-optical device according to claim 7,
The data potential for reducing the potential difference between the common electrode and the pixel electrode that is the first potential is a data potential that is the same potential as the first potential, and
A first black writing period in which each of the plurality of scanning lines is sequentially driven to write a black potential to each of the plurality of pixels after the end of the first writing period and before the start of the reset period. Provided,
In addition, after the potential switching period and before the start of the second writing period, the plurality of scanning lines are driven all at once, and a black potential is simultaneously applied to the pixel electrodes in each of the plurality of pixels. An electro-optical device, wherein a second black writing period for writing is provided.

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