WO2016150037A1 - 一种移位寄存器、栅极驱动电路、显示面板及显示装置 - Google Patents

一种移位寄存器、栅极驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2016150037A1
WO2016150037A1 PCT/CN2015/084277 CN2015084277W WO2016150037A1 WO 2016150037 A1 WO2016150037 A1 WO 2016150037A1 CN 2015084277 W CN2015084277 W CN 2015084277W WO 2016150037 A1 WO2016150037 A1 WO 2016150037A1
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Prior art keywords
node
signal
module
output
switching transistor
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PCT/CN2015/084277
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English (en)
French (fr)
Inventor
黄飞
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/907,029 priority Critical patent/US9881576B2/en
Publication of WO2016150037A1 publication Critical patent/WO2016150037A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, a display panel, and a display device.
  • the gate driving circuit includes a plurality of shift registers, and each shift register corresponds to one gate line.
  • a plurality of shift registers are arranged in series, and a trigger signal is transmitted stepwise between adjacent shift registers. After receiving the trigger signal, each shift register outputs a gate line scan signal to the corresponding gate line, and supplies the trigger signal to the next stage unit circuit to implement the gate drive function.
  • Such a design can eliminate the need to separately set the gate driving chip in the frame area of the display panel, thereby facilitating the design of the narrow frame of the display panel, reducing the production cost of the related products, and improving the market competitiveness of the display product.
  • the circuit structure of the existing shift register is as shown in FIG. 1 , and the corresponding input and output timing diagram is shown in FIG. 2 .
  • FIG. 2 when the shift register is normally turned on, the potential of the first node PU is pulled high during the first time period, and is continuously pulled high during the second time period, thereby controlling the switching transistor T7 to be turned on, so that The scan signal output corresponds to the output scan signal.
  • the voltage signal output by the first node PU is noisy (as indicated by the area A labeled in FIG.
  • the capacitance C1 is The charging and discharging process is likely to cause a large noise of the scanning signal outputted from the output end of the scanning signal (as shown in the area B marked in FIG. 2), thereby causing a large power consumption of the shift register circuit and reducing the yield of the display panel.
  • a first aspect of the present disclosure provides a shift register, including: an input module, a reset module, a pull-up module, a first pull-down module, a second pull-down module, an output control module, and an output noise reduction module;
  • the input end of the input module is connected to the first reference signal end, the control end is connected to the signal input end, the output end is connected to the first node, and the input module is used for controlling the pull-down of the signal input end to the first The potential of the node;
  • the input end of the reset module is connected to the second reference signal end, the control end is connected to the reset signal end, the output end is connected to the first node, and the reset module is configured to pull down the control at the reset signal end The potential of the first node;
  • the input end and the control end of the pull-up module are respectively connected to the first clock signal end, and the output end is connected to the second node, and the pull-up module is configured to pull down the second at the control of the first clock signal end.
  • the input end of the first pull-down module is connected to the low-level signal end, the control end is connected to the second node, the output end is connected to the first node, and the first pull-down module is used to The control of the second node pulls down the potential of the first node;
  • the input end of the second pull-down module is connected to the low-level signal end, the control end is connected to the first node, the output end is connected to the second node, and the second pull-down module is used in the first The control of the node pulls down the potential of the second node;
  • the first input end of the output control module is connected to the low level signal end, the second input end is connected to the second clock signal end, the first control end is connected to the first node, and the second control end is connected
  • the second node is connected, and the output end is connected to the scan signal output end, and the output control module is configured to control the scan signal output end to select an output under the control of the first node and the second node a signal of the second clock signal end or a signal of the low level signal end;
  • the input end of the output noise reduction module is connected to the high level signal end, the control end is connected to the scan signal output end, the output end is connected to the first node, and the output noise reduction module is used for the scanning When the signal output end outputs the scan signal, the scan signal is fed back to the first control end of the output control module.
  • the output noise reduction module may include a first switching transistor.
  • the gate of the first switching transistor is connected to the output end of the scan signal, the source is connected to the high-level signal end, and the drain is connected to the first node.
  • the output noise reduction module may further comprise a transmission module.
  • the transmission module is connected to the high level signal end, the output end of the input module, and the reset module An output terminal, an output of the first pull-down module, a drain of the first switching transistor, and the first node, the transmission module is configured to be used for a drain of the first switching transistor The signal is filtered and noise reduced and then output to the first node.
  • the transmission module may comprise a second switching transistor.
  • the gate of the second switching transistor is connected to the high level signal terminal, the source is connected to the drain of the first switching transistor, and the drain is connected to the first node.
  • the output control module may include a first output control module and a second output control module
  • the first output control module is connected between the first node, the second clock signal end, and the scan signal output end, and the first output control module is used for control at the first node And controlling the scan signal output end to output the signal of the second clock signal end;
  • the second output control module is connected between the low level signal end, the second node, and the scan signal output end, and the second output control module is used for control at the second node And controlling the scan signal output end to output the signal of the low level signal end.
  • the first output control module may include a third switching transistor and a first capacitor; wherein
  • a gate of the third switching transistor is connected to the first node, a source is connected to the second clock signal end, and a drain is connected to the scan signal output end;
  • the first capacitor is connected between the first node and the scan signal output end.
  • the second output control module may include a fourth switching transistor and a fifth switching transistor; wherein
  • a gate of the fourth switching transistor is connected to the second node, a source is connected to the low-level signal end, and a drain is connected to the scan signal output end;
  • the gate of the fifth switching transistor is connected to the second node, and the source and the drain are respectively connected to the low-level signal end.
  • the second output control module may include a fourth switching transistor and a second capacitor; wherein
  • a gate of the fourth switching transistor is connected to the second node, a source is connected to the low-level signal end, and a drain is connected to the scan signal output end;
  • the second capacitor is coupled between the second node and the low level signal terminal.
  • the input module may include a sixth switching transistor.
  • a gate of the sixth switching transistor is connected to the signal input end, and a source is opposite to the first reference signal end
  • the drain is connected to the drain of the first switching transistor and the source of the second switching transistor, respectively.
  • the reset module may include a seventh switching transistor. a gate of the seventh switching transistor is connected to the reset signal terminal, a source is connected to the second reference signal terminal, and a drain is respectively connected to a drain of the first switching transistor and the second switching transistor The sources are connected.
  • the first pull down module may include an eighth switching transistor. a gate of the eighth switching transistor is connected to the second node, a source is connected to the low-level signal terminal, and a drain is respectively connected to a drain of the first switching transistor and the second switching transistor The sources are connected.
  • the pull up module may comprise a ninth switching transistor.
  • the gate and the source of the ninth switching transistor are respectively connected to the first clock signal end, and the drain is connected to the second node.
  • the second pull-down module may include a tenth switching transistor.
  • the gate of the tenth switching transistor is connected to the first node, the source is connected to the low level signal end, and the drain is connected to the second node.
  • a second aspect of the present disclosure provides a gate driving circuit comprising a plurality of the above-described shift registers provided by the first aspect of the present disclosure, wherein the first shift register and the last shift register are excluded
  • the scan signal output end of each of the remaining shift registers inputs a trigger signal to the signal input end of the next shift register adjacent thereto, and inputs a reset signal to the reset signal end of the previous shift register adjacent thereto;
  • the scan signal output end of the first shift register inputs a trigger signal to the signal input end of the second shift register;
  • the scan signal output end of the last shift register inputs a reset to itself and the reset signal end of the previous shift register. signal.
  • a third aspect of the present disclosure provides a display panel including the above-described gate driving circuit provided by the second aspect of the present disclosure.
  • a fourth aspect of the present disclosure provides a display device including the above display panel provided by the third aspect of the present disclosure.
  • Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel, and a display device, wherein the shift register includes an input module, a reset module, a pull-up module, a first pull-down module, and a second pull-down module.
  • An output control module, and an output noise reduction module wherein the input module is configured to pull down a potential of the first node at a signal input end; the reset module is used to The control of the bit signal terminal pulls down the potential of the first node; the pull-up module is used to pull down the potential of the second node at the control of the first clock signal; the first pull-down module is used to pull down the first node at the control of the second node The second pull-down module is configured to pull down the potential of the second node at the control of the first node; the output control module is configured to control the scan signal output terminal to select and output the second clock under the control of the first node and the second node Signal at the signal end or at the signal end of the low level signal.
  • the function of the shift register to output the scan signal is realized.
  • the scan signal is fed back to the first control end of the output control module, thereby reducing the signal noise of the first control end of the output control module, thereby reducing the output of the scan signal output end.
  • the noise of the scanned signal is enhanced, and the power consumption is reduced, thereby improving the yield of the display panel.
  • FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an example of an output noise reduction module in a shift register according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an example of a transmission module in a shift register according to an embodiment of the present disclosure
  • 6a and 6b are schematic structural diagrams showing an example of an output control module in a shift register according to an embodiment of the present disclosure
  • FIG. 7a and 7b are schematic structural diagrams of an example of a shift register provided by an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of input and output of a shift register according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • a shift register includes: an input module 01, a reset module 02, a pull-up module 03, a first pull-down module 04, a second pull-down module 05, an output control module 06, and an output noise reduction module 07. ;among them,
  • the input end of the input module 01 is connected to the first reference signal terminal CN, the control end is connected to the signal input terminal Input, the output end is connected to the first node P1, and the input module 01 is used to control the input of the signal input terminal Input to the first node.
  • the input end of the reset module 02 is connected to the second reference signal end CNB, the control end is connected to the reset signal end Reset, the output end is connected to the first node P1, and the reset module 02 is used to pull down the first node at the control of the reset signal end Reset. Potential of P1;
  • the input terminal and the control terminal of the pull-up module 03 are respectively connected to the first clock signal terminal CLK, the output terminal is connected to the second node P2, and the pull-up module 03 is used to pull down the second node P2 at the control of the first clock signal terminal CLK.
  • the input end of the first pull-down module 04 is connected to the low-level signal terminal VGL, the control end is connected to the second node P2, the output end is connected to the first node P1, and the first pull-down module 04 is used at the second node P2. Controlling the potential of the first node P1 to be pulled down;
  • the input end of the second pull-down module 05 is connected to the low-level signal terminal VGL, the control end is connected to the first node P1, the output end is connected to the second node P2, and the second pull-down module 05 is used for controlling the pull-down at the first node P1.
  • the first input end of the output control module 06 is connected to the low level signal end VGL, the second input end is connected to the second clock signal end CLKB, the first control end is connected to the first node P1, and the second control end is connected to the second node.
  • P2 is connected, the output end is connected to the scan signal output end Out, and the output control module 06 is configured to control the scan signal output end Out to select and output the signal of the second clock signal end CLKB under the control of the first node P1 and the second node P2 or a signal of a low level signal terminal VGL;
  • the input end of the output noise reduction module 07 is connected to the high level signal terminal VGH, the control end is connected to the scan signal output end Out, the output end is connected to the first node P1, and the output noise reduction module 07 is used for outputting at the scan signal output end Out.
  • the scan signal is fed back to the first control terminal of the output control module 06 when the signal is scanned.
  • the input module 01 is used to pull up the potential of the first node P1; the reset module 02 is used to pull down the potential of the first node P1; the pull-up module 03 is used to pull up the potential of the second node P2; the first pull-down module is used to pull down The potential of the first node P1; the second pull-down module is used to pull down the potential of the second node P2; the output control module 06 is configured to control the scan signal output terminal Out to select the signal of the second clock signal terminal CLKB or the low-level signal end VGL signal.
  • the arrangement realizes the function of the shift register outputting the scan signal.
  • the output noise reduction module 07 feeds back the scan signal to the first control end of the output control module 06, thereby reducing the signal noise of the first control end of the output control module 06, thereby reducing the scan.
  • the noise of the scan signal output from the signal output terminal Out is enhanced, and the power consumption is reduced, thereby improving the yield of the display panel.
  • the output noise reduction module 07 includes a first switching transistor T1.
  • the gate of the first switching transistor T1 is connected to the scan signal output terminal Out, the source is connected to the high level signal terminal VGH, and the drain is connected to the first node P1.
  • the first switch transistor T1 when the scan signal output terminal Out outputs the scan signal, the first switch transistor T1 is in an on state, and the turned-on first switch transistor T1 turns on the high level signal terminal VGH and the first node P1 to be turned on.
  • the potential of a node P1 that is, when the scan signal output terminal Out outputs a scan signal, the scan signal is fed back to the first control end of the output control module 06, thereby reducing the signal noise of the first control end of the output control module 06, thereby reducing the scan.
  • the noise of the scan signal output from the signal output terminal Out Such an arrangement enhances the lossless transmission of the signal and reduces power consumption, thereby increasing the yield of the display panel.
  • the output noise reduction module 07 further includes a transmission module 071.
  • the transmission module 071 is connected to the high-level signal terminal VGH, the output terminal of the input module 01, the output terminal of the reset module 02, the output terminal of the first pull-down module 04, the drain of the first switching transistor T1, and the first node P1. Between the transmission module 071 is for filtering and noise-reducing the signal of the drain of the first switching transistor T1 and then outputting it to the first node P1.
  • the transmission module 071 is in a normally open state under the control of the high level signal terminal VGH, and as a single tube transmission gate, transmits the scan signal fed back by the first switching transistor T1 to the first node P1, and the first switch The signal at the drain of transistor T1 is filtered to further reduce the noise of the signal.
  • the transmission module 071 also reduces the potential of the signal to avoid charging and discharging the first capacitor due to the excessive potential of the first node P1, thereby causing the problem that the scan signal output terminal Out outputs a noise signal.
  • the transmission module 071 includes a second switching transistor T2.
  • the gate of the second switching transistor T2 is connected to the high level signal terminal VGH, the source is connected to the drain of the first switching transistor T1, and the drain is connected to the first node P1.
  • the second switching transistor T2 Since the gate of the second switching transistor T2 is connected to the high level signal terminal VGH, The second switching transistor T2 is in a normally open state, and as a single-tube transmission gate, the signal of the drain of the first switching transistor T1 is filtered and noise-reduced. The second switching transistor T2 also simultaneously turns on the drain of the first switching transistor T1 and the first node P1, thereby filtering and noise-reducing the scan signal fed back by the first switching transistor T1 and then transferring it to the first node P1.
  • the output control module 06 includes a first output control module 061 and a second output control module 062;
  • the first output control module 061 is connected between the first node P1, the second clock signal terminal CLKB, and the scan signal output terminal Out.
  • the first output control module 061 is configured to control, by the control of the first node P1, the scan signal output terminal Out to output a signal of the second clock signal terminal CLKB;
  • the second output control module 062 is connected between the low level signal terminal VGL, the second node P2, and the scan signal output terminal Out, and the second output control module 062 is configured to control the scan signal output under the control of the second node P2.
  • the terminal Out outputs a signal of the low-level signal terminal VGL.
  • the first output control module 061 and the second output control module 062 respectively output the signal of the second clock signal terminal CLKB and the signal of the low-level signal terminal VGL under the control of the first node P1 and the second node P2, respectively. Therefore, the shift register can be caused to output a scan signal to the corresponding gate line in the corresponding time period, thereby driving the display panel to realize progressive scan.
  • the first output control module 061 includes a third switching transistor T3 and a first capacitor C1.
  • the gate of the third switching transistor T3 is connected to the first node P1, the source is connected to the second clock signal terminal CLKB, and the drain is connected to the scan signal output terminal Out; the first capacitor C1 is connected to the first node P1 and scanned. Between the signal outputs Out.
  • the third switching transistor T3 When the potential of the first node P1 is pulled high, the third switching transistor T3 is in an on state, and the turned-on third switching transistor T3 turns on the second clock signal terminal CLKB and the scan signal output terminal Out, and the first capacitor C1 acts as a bootstrap action on the potential of the first node P1 to further maintain the potential of the first node P1.
  • the second output control module 062 includes a fourth switching transistor T4 and a fifth switching transistor T5.
  • the gate of the fourth switching transistor T4 is connected to the second node P2
  • the source is connected to the low-level signal terminal VGL
  • the drain is connected to the scan signal output terminal Out
  • the gate of the fifth switching transistor T5 is connected to the second node.
  • P2 is connected, and the source and the drain are respectively connected to the low-level signal terminal VGL.
  • the fourth switching transistor T4 and the fifth switching crystal The tube T5 is in an on state, and the turned-on fourth switching transistor T4 turns on the low-level signal terminal VGL and the scan signal output terminal Out, and the turned-on fifth switching transistor T5 can be equivalent to a capacitor to further maintain the The potential of the two nodes P2, thereby reducing the noise of the voltage signal of the second node P2.
  • the second output control module 062 includes a fourth switching transistor T4 and a second capacitor C2.
  • the gate of the fourth switching transistor T4 is connected to the second node P2, the source is connected to the low-level signal terminal VGL, the drain is connected to the scan signal output terminal Out, and the second capacitor C2 is connected to the second node P2 and low. Between the level signal terminals VGL.
  • the fourth switching transistor T4 When the potential of the second node P2 is pulled high, the fourth switching transistor T4 is in an on state, and the turned-on fourth switching transistor T4 turns on the low-level signal terminal VGL and the scan signal output terminal Out, and the second capacitor C2 can further maintain the potential of the second node P2, thereby reducing the noise of the voltage signal of the second node P2.
  • the input module 01 includes a sixth switching transistor T6.
  • the gate of the sixth switching transistor T6 is connected to the signal input terminal Input, the source is connected to the first reference signal terminal CN, and the drain is connected to the drain of the first switching transistor T1 and the source of the second switching transistor T2, respectively.
  • the sixth switching transistor T6 When the signal input terminal inputs an input signal, the sixth switching transistor T6 is in an on state. The turned-on sixth switching transistor T6 turns on the first reference signal terminal CN and the source of the second switching transistor T2, and transmits the signal of the first reference signal terminal CN to the first node P1 through the second switching transistor T2.
  • the reset module 02 includes a seventh switching transistor T7.
  • the gate of the seventh switching transistor T7 is connected to the reset signal terminal Reset, the source is connected to the second reference signal terminal CNB, and the drain is connected to the drain of the first switching transistor T1 and the source of the second switching transistor T2, respectively.
  • the seventh switching transistor T7 When the reset signal terminal Reset input signal, the seventh switching transistor T7 is in an on state. The turned-on seventh switching transistor T7 turns on the second reference signal terminal CNB and the source of the second switching transistor T2, and transmits the signal of the second reference signal terminal CNB to the first node P1 through the second switching transistor T2.
  • the first pull-down module 04 includes an eighth switching transistor T8.
  • the gate of the eighth switching transistor T8 is connected to the second node P2, the source is connected to the low-level signal terminal VGL, and the drain is respectively connected to the first switching transistor
  • the drain of T1 is connected to the source of the second switching transistor T2.
  • the eighth switching transistor T8 When the potential of the second node P2 is pulled high, the eighth switching transistor T8 is in an on state. The turned-on eighth switching transistor T8 turns on the source of the second switching transistor T2 and the low-level signal terminal VGL, thereby pulling the potential of the source of the second switching transistor T2 low.
  • the pull-up module 03 includes a ninth switching transistor T9.
  • the gate and the source of the ninth switching transistor T9 are respectively connected to the first clock signal terminal CLK, and the drain is connected to the second node P2.
  • the ninth switching transistor T9 When the first clock signal terminal CLK inputs a high level signal, the ninth switching transistor T9 is in an on state, and the turned-on ninth switching transistor T9 turns on the first clock signal terminal CLK and the second node P2, thereby The potential of the two nodes P2 is pulled high.
  • the second pull-down module 05 includes a tenth switching transistor T10.
  • the gate of the tenth switching transistor T10 is connected to the first node P1, the source is connected to the low-level signal terminal VGL, and the drain is connected to the second node P2.
  • the tenth switching transistor T10 When the potential of the first node P1 is pulled high, the tenth switching transistor T10 is in an on state. The turned-on tenth switching transistor T10 turns on the second node P2 and the low-level signal terminal VGL, thereby pulling the potential of the second node P2 low.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor). Not limited.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the sources and drains of these transistors can be interchanged without specific distinction.
  • a thin film transistor will be described as an example in describing a specific embodiment.
  • the first reference signal terminal CN when the forward scan is initiated, the first reference signal terminal CN provides a high level signal, and the second reference signal terminal CNB provides a low level signal.
  • the first reference signal terminal CN provides a low level signal, and the second reference signal terminal CNB provides a high level signal.
  • the scan signal output terminal Out outputs a low level signal.
  • the turned-on tenth switching transistor T10 turns on the second node P2 and the low-level signal terminal VGL, thereby pulling down the potential of the second node P2.
  • the t1 phase is the charging phase.
  • the turned-on ninth switching transistor T9 turns on the first clock signal terminal CLK and the second node P2. Therefore, the potential of the second node P2 is pulled high. At this time, the fourth switching transistor T4 is in an on state. The turned-on fourth switching transistor T4 turns on the low-level signal terminal VGL and the scan signal output terminal Out, so the scan signal output terminal Out outputs a low-level signal.
  • the t3 phase is the non-scanning signal output phase.
  • the scan signal output terminal Out will always output a low level signal until the signal input terminal Input inputs a high level signal again for a certain period of time, then the shift register will repeat the above work.
  • a second aspect of the present disclosure provides a gate driving circuit including the above-described shift register provided by a plurality of cascaded embodiments of the present disclosure.
  • the scan signal output ends of each of the shift registers input a trigger signal to the signal input end of the next shift register adjacent thereto, and The reset signal end of the adjacent previous shift register inputs a reset signal;
  • the scan signal output end of the first shift register inputs a trigger signal to the signal input end of the second shift register;
  • the last shift register scan
  • the signal output terminal inputs a reset signal to itself and the reset signal terminal of the previous shift register.
  • FIG. 9 shows N shift registers, which are a first-stage shift register, a second-stage shift register, a third-stage shift register, a fourth-stage shift register, etc., N- 3-stage shift register, N-2th shift register, N-1th shift register, Nth shift register.
  • the signal output terminal Out of the N-1th shift register not only outputs a gate turn-on signal to the gate line connected thereto, but also outputs a reset signal to the N-2th shift register, and also to the Nth stage shift register.
  • the trigger signal is output.
  • each of the shift registers in the above-mentioned gate driving circuit is identical in function and structure to the above-described shift register provided by the present disclosure, and the repeated portions are not described again.
  • a third aspect of the present disclosure provides a display panel including the above-described gate driving circuit provided by an embodiment of the present disclosure. Since the principle of the display panel is similar to the above-mentioned gate driving circuit, the implementation of the display panel can be referred to the implementation of the above-mentioned gate driving circuit, and the repeated description is omitted.
  • a fourth aspect of the present disclosure provides a display device including the above display panel provided by an embodiment of the present disclosure.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of the display device is similar to that of the display panel, the implementation of the display device can be referred to the implementation of the above display panel, and the repeated description is omitted.
  • Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel, and a display device.
  • the shift register includes an input module, a reset module, a pull-up module, a first pull-down module, and a second pull-down module, and outputs a control module, and an output noise reduction module; wherein the input module is configured to pull down the potential of the first node at the signal input end; the reset module is configured to pull down the potential of the first node at the control of the reset signal end; the pull-up module is used for The control at the first clock signal end pulls down the potential of the second node; the first pull-down module is used to pull down the potential of the first node at the control of the second node; the second pull-down module is used to pull down the control at the first node The potential of the second node; the output control module is configured to, under the control of the first node and the second node, control the scan signal output end to select a signal outputting the second clock signal end or
  • the function of the shift register to output the scan signal is realized.
  • the output noise reduction module outputs the scan signal at the scan signal output end
  • the scan signal is fed back to the first control of the output control module.
  • the terminal end reduces the signal noise of the first control terminal of the output control module, thereby reducing the noise of the scan signal outputted by the scan signal output terminal. In this way, the lossless transmission of the signal is enhanced, and the power consumption is reduced, thereby improving the yield of the display panel.

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Abstract

一种移位寄存器、栅极驱动电路、显示面板及显示装置，该移位寄存器包括输入模块（01）、复位模块（02）、上拉模块（03）、第一下拉模块（04）、第二下拉模块（05）、输出控制模块（06），以及输出降噪模块（07）；输入模块（01）用于拉高第一节点（P1）的电位；复位模块（02）用于拉低第一节点（P1）的电位；上拉模块（03）用于拉高第二节点（P2）的电位；第一下拉模块（04）用于拉低第一节点（P1）的电位；第二下拉模块（05）用于拉低第二节点（P2）的电位；输出控制模块（06）用于控制扫描信号输出端选择输出第二时钟信号端（CLKB）的信号或低电平信号端（VGL）的信号；输出降噪模块（07）在扫描信号输出端输出扫描信号时，将扫描信号反馈给输出控制模块（06）的第一控制端，从而降低输出控制模块（06）的第一控制端的信号噪声，进而降低扫描信号输出端输出的扫描信号的噪声。

Description

一种移位寄存器、栅极驱动电路、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路、显示面板及显示装置。
背景技术
目前，随着液晶显示技术的发展，液晶面板业竞争越来越激烈，降低液晶显示面板的生产成本成为面板商提高竞争力的首选方案。为了降低显示面板的生产成本，一般地，相关技术领域的技术人员利用显示面板的边缘搭建栅极驱动电路。栅极驱动电路包括多个移位寄存器，每个移位寄存器对应一条栅线。多个移位寄存器采用串联设置，并且相邻两个移位寄存器之间有逐级传递的触发信号。每个移位寄存器在接收到触发信号后，向对应栅线输出栅线扫描信号，并把触发信号输送给下一级单元电路以实现栅极驱动的功能。这样的设计可以省去在显示面板的边框区域单独设置栅极驱动芯片的需要，因而有利于实现显示面板的窄边框设计，同时降低了相关产品的生产成本，提高了显示产品的市场竞争力。
一般地，现有的移位寄存器的电路结构如图1所示，其对应的输入输出时序图如图2所示。从图2可以看出，移位寄存器在正常开启工作时，第一节点PU的电位在第一时间段被拉高，并且在第二时间段被继续拉高，进而控制开关晶体管T7开启，使得扫描信号输出端对应输出扫描信号。然而由于第一节点PU输出的电压信号有噪声(如图2中标注的区域A所示)，且第一节点PU在第一次被拉高时产生的信号的电位较高，因此电容C1的充放电过程易造成扫描信号输出端输出的扫描信号有较大噪声(如图2中标注的区域B所示)，进而造成移位寄存器电路功耗较大，降低了显示面板的良率。
因此，如何降低移位寄存器输出的扫描信号的噪声，降低功耗，从而提高显示面板的良率，是本领域技术人员亟需解决的技术问题。
发明内容
本公开的一个目的在于提供一种移位寄存器、栅极驱动电路、显示面板及显示装置，其能够至少部分地缓解或消除以上提到的问题。
本公开的第一方面提供了一种移位寄存器，包括：输入模块、复位模块、上拉模块、第一下拉模块、第二下拉模块、输出控制模块，以及输出降噪模块；其中，
所述输入模块的输入端与第一参考信号端相连，控制端与信号输入端相连，输出端与第一节点相连，所述输入模块用于在所述信号输入端的控制下拉高所述第一节点的电位；
所述复位模块的输入端与第二参考信号端相连，控制端与复位信号端相连，输出端与所述第一节点相连，所述复位模块用于在所述复位信号端的控制下拉低所述第一节点的电位；
所述上拉模块的输入端和控制端分别与第一时钟信号端相连，输出端与第二节点相连，所述上拉模块用于在所述第一时钟信号端的控制下拉高所述第二节点的电位；
所述第一下拉模块的输入端与低电平信号端相连，控制端与所述第二节点相连，输出端与所述第一节点相连，所述第一下拉模块用于在所述第二节点的控制下拉低所述第一节点的电位；
所述第二下拉模块的输入端与低电平信号端相连，控制端与所述第一节点相连，输出端与所述第二节点相连，所述第二下拉模块用于在所述第一节点的控制下拉低所述第二节点的电位；
所述输出控制模块的第一输入端与所述低电平信号端相连，第二输入端与第二时钟信号端相连，第一控制端与所述第一节点相连，第二控制端与所述第二节点相连，输出端与所述扫描信号输出端相连，所述输出控制模块用于在所述第一节点和所述第二节点的控制下，控制所述扫描信号输出端选择输出所述第二时钟信号端的信号或所述低电平信号端的信号；
所述输出降噪模块的输入端与高电平信号端相连，控制端与所述扫描信号输出端相连，输出端与所述第一节点相连，所述输出降噪模块用于在所述扫描信号输出端输出扫描信号时将扫描信号反馈给所述输出控制模块的第一控制端。
根据一个实施例，所述输出降噪模块可以包括第一开关晶体管。所述第一开关晶体管的栅极与所述扫描信号输出端相连，源极与所述高电平信号端相连，漏极与所述第一节点相连。
根据另一实施例，所述输出降噪模块还可以包括传输模块。所述传输模块连接于所述高电平信号端、所述输入模块的输出端、所述复位模块的 输出端、所述第一下拉模块的输出端、所述第一开关晶体管的漏极，以及所述第一节点之间，所述传输模块用于对所述第一开关晶体管的漏极的信号进行滤波降噪并且然后将其输出到所述第一节点。
根据又一实施例，所述传输模块可以包括第二开关晶体管。所述第二开关晶体管的栅极与所述高电平信号端相连，源极与所述第一开关晶体管的漏极相连，漏极与所述第一节点相连。
根据再一实施例，所述输出控制模块可以包括第一输出控制模块和第二输出控制模块；其中，
所述第一输出控制模块连接于所述第一节点、所述第二时钟信号端，以及所述扫描信号输出端之间，所述第一输出控制模块用于在所述第一节点的控制下，控制所述扫描信号输出端输出所述第二时钟信号端的信号；
所述第二输出控制模块连接于所述低电平信号端、所述第二节点，以及所述扫描信号输出端之间，所述第二输出控制模块用于在所述第二节点的控制下，控制所述扫描信号输出端输出所述低电平信号端的信号。
在一个实施例中，所述第一输出控制模块可以包括第三开关晶体管和第一电容；其中，
所述第三开关晶体管的栅极与所述第一节点相连，源极与所述第二时钟信号端相连，漏极与所述扫描信号输出端相连；
所述第一电容连接于所述第一节点与所述扫描信号输出端之间。
根据另一实施例，所述第二输出控制模块可以包括第四开关晶体管和第五开关晶体管；其中，
所述第四开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极与所述扫描信号输出端相连；
所述第五开关晶体管的栅极与所述第二节点相连，源极和漏极分别与所述低电平信号端相连。
根据又一实施例，所述第二输出控制模块可以包括第四开关晶体管和第二电容；其中，
所述第四开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极与所述扫描信号输出端相连；
所述第二电容连接于所述第二节点和所述低电平信号端之间。
根据再一实施例，所述输入模块可以包括第六开关晶体管。所述第六开关晶体管的栅极与所述信号输入端相连，源极与所述第一参考信号端相 连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
根据实施例，所述复位模块可以包括第七开关晶体管。所述第七开关晶体管的栅极与所述复位信号端相连，源极与所述第二参考信号端相连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
根据另一实施例，所述第一下拉模块可以包括第八开关晶体管。所述第八开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
根据又一实施例，所述上拉模块可以包括第九开关晶体管。所述第九开关晶体管的栅极和源极分别与所述第一时钟信号端相连，漏极与所述第二节点相连。
根据再一实施例，所述第二下拉模块可以包括第十开关晶体管。所述第十开关晶体管的栅极与所述第一节点相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
本公开的第二方面提供了一种栅极驱动电路，包括级联的多个本公开的第一方面提供的上述移位寄存器，其中除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器的扫描信号输出端向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器的扫描信号输出端向自身以及上一个移位寄存器的复位信号端输入复位信号。
本公开的第三方面提供了一种显示面板，包括本公开的第二方面提供的上述栅极驱动电路。
本公开的第四方面提供了一种显示装置，包括本公开的第三方面提供的上述显示面板。
本公开的实施例提供了一种移位寄存器、栅极驱动电路、显示面板及显示装置，其中移位寄存器包括输入模块、复位模块、上拉模块、第一下拉模块、第二下拉模块，输出控制模块，以及输出降噪模块；其中，输入模块用于在信号输入端的控制下拉高第一节点的电位；复位模块用于在复 位信号端的控制下拉低第一节点的电位；上拉模块用于在第一时钟信号端的控制下拉高第二节点的电位；第一下拉模块用于在第二节点的控制下拉低第一节点的电位；第二下拉模块用于在第一节点的控制下拉低第二节点的电位；输出控制模块用于在第一节点和第二节点的控制下，控制扫描信号输出端选择输出第二时钟信号端的信号或低电平信号端的信号。通过这样的布置，实现了移位寄存器输出扫描信号的功能。同时，输出降噪模块在扫描信号输出端输出扫描信号时，将扫描信号反馈给输出控制模块的第一控制端，从而降低输出控制模块的第一控制端的信号噪声，进而降低扫描信号输出端输出的扫描信号的噪声。以此方式增强了信号的无损耗传输，降低了功耗，从而提高显示面板的良率。
附图说明
图1为现有技术中的移位寄存器的结构示意图；
图2为现有技术中的移位寄存器的输入输出时序图；
图3为本公开实施例提供的移位寄存器的结构示意图；
图4为本公开实施例提供的移位寄存器中输出降噪模块的示例结构示意图；
图5为本公开实施例提供的移位寄存器中传输模块的示例结构示意图；
图6a和图6b分别为本公开实施例提供的移位寄存器中输出控制模块的示例结构示意图；
图7a和图7b分别为本公开实施例提供的移位寄存器的示例结构示意图；
图8为本公开实施例提供的移位寄存器的输入输出时序图；
图9为本公开实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本公开实施例提供的移位寄存器，栅极驱动电路、显示面板及显示装置的具体实施方式进行详细地说明。
如图3所示，一种移位寄存器包括：输入模块01、复位模块02、上拉模块03、第一下拉模块04、第二下拉模块05、输出控制模块06，以及输出降噪模块07；其中，
输入模块01的输入端与第一参考信号端CN相连，控制端与信号输入端Input相连，输出端与第一节点P1相连，输入模块01用于在信号输入端Input的控制下拉高第一节点P1的电位；
复位模块02的输入端与第二参考信号端CNB相连，控制端与复位信号端Reset相连，输出端与第一节点P1相连，复位模块02用于在复位信号端Reset的控制下拉低第一节点P1的电位；
上拉模块03的输入端和控制端分别与第一时钟信号端CLK相连，输出端与第二节点P2相连，上拉模块03用于在第一时钟信号端CLK的控制下拉高第二节点P2的电位；
第一下拉模块04的输入端与低电平信号端VGL相连，控制端与第二节点P2相连，输出端与第一节点P1相连，第一下拉模块04用于在第二节点P2的控制下拉低第一节点P1的电位；
第二下拉模块05的输入端与低电平信号端VGL相连，控制端与第一节点P1相连，输出端与第二节点P2相连，第二下拉模块05用于在第一节点P1的控制下拉低第二节点P2的电位；
输出控制模块06的第一输入端与低电平信号端VGL相连，第二输入端与第二时钟信号端CLKB相连，第一控制端与第一节点P1相连，第二控制端与第二节点P2相连，输出端与扫描信号输出端Out相连，输出控制模块06用于在第一节点P1和第二节点P2的控制下，控制扫描信号输出端Out选择输出第二时钟信号端CLKB的信号或低电平信号端VGL的信号；
输出降噪模块07的输入端与高电平信号端VGH相连，控制端与扫描信号输出端Out相连，输出端与第一节点P1相连，输出降噪模块07用于在扫描信号输出端Out输出扫描信号时将扫描信号反馈给输出控制模块06的第一控制端。
在上述移位寄存器中，包括输入模块01、复位模块02、上拉模块03、第一下拉模块04、第二下拉模块05，输出控制模块06，以及输出降噪模块07；其中，输入模块01用于拉高第一节点P1的电位；复位模块02用于拉低第一节点P1的电位；上拉模块03用于拉高第二节点P2的电位；第一下拉模块用于拉低第一节点P1的电位；第二下拉模块用于拉低第二节点P2的电位；输出控制模块06用于控制扫描信号输出端Out选择输出第二时钟信号端CLKB的信号或低电平信号端VGL的信号。通过这样的 布置，实现了移位寄存器输出扫描信号的功能。同时，输出降噪模块07在扫描信号输出端Out输出扫描信号时，将扫描信号反馈给输出控制模块06的第一控制端，从而降低输出控制模块06的第一控制端的信号噪声，进而降低扫描信号输出端Out输出的扫描信号的噪声。以此方式增强了信号的无损耗传输，降低功耗，从而提高显示面板的良率。
在具体实施时，在上述移位寄存器中，如图4所示，输出降噪模块07包括第一开关晶体管T1。第一开关晶体管T1的栅极与扫描信号输出端Out相连，源极与高电平信号端VGH相连，漏极与第一节点P1相连。
具体地，在扫描信号输出端Out输出扫描信号时，第一开关晶体管T1处于导通状态，导通的第一开关晶体管T1将高电平信号端VGH与第一节点P1导通，拉高第一节点P1的电位，即在扫描信号输出端Out输出扫描信号时，将扫描信号反馈给输出控制模块06的第一控制端，从而降低输出控制模块06的第一控制端的信号噪声，进而降低扫描信号输出端Out输出的扫描信号的噪声。这样的布置增强了信号的无损耗传输，降低功耗，从而提高显示面板的良率。
在具体实施时，在上述移位寄存器中，如图5所示，输出降噪模块07还包括传输模块071。传输模块071连接于高电平信号端VGH、输入模块01的输出端、复位模块02的输出端、第一下拉模块04的输出端、第一开关晶体管T1的漏极，以及第一节点P1之间，传输模块071用于对第一开关晶体管T1的漏极的信号进行滤波降噪并且然后将其输出到第一节点P1。
具体地，传输模块071在高电平信号端VGH的控制下处于常开状态，并且作为单管传输门，将第一开关晶体管T1反馈的扫描信号传递到第一节点P1，并对第一开关晶体管T1漏极的信号进行滤波以进一步降低信号的噪声。传输模块071同时也降低了信号的电位，避免由于第一节点P1的电位过高而造成第一电容充放电，进而造成扫描信号输出端Out输出噪声信号的问题。
在具体实施时，在上述移位寄存器中，如图5所示，传输模块071包括第二开关晶体管T2。第二开关晶体管T2的栅极与高电平信号端VGH相连，源极与第一开关晶体管T1的漏极相连，并且漏极与第一节点P1相连。
由于第二开关晶体管T2的栅极与高电平信号端VGH相连，因此第 二开关晶体管T2处于常开状态，并且作为单管传输门，对第一开关晶体管T1的漏极的信号进行滤波降噪。第二开关晶体管T2同时还使第一开关晶体管T1的漏极与第一节点P1导通，从而对第一开关晶体管T1反馈的扫描信号进行滤波降噪并且然后将其传递到第一节点P1。
在具体实施时，在上述移位寄存器中，如图6a和图6b所示，输出控制模块06包括第一输出控制模块061和第二输出控制模块062；其中，
第一输出控制模块061连接于第一节点P1、第二时钟信号端CLKB，以及扫描信号输出端Out之间。第一输出控制模块061用于在第一节点P1的控制下，控制扫描信号输出端Out输出第二时钟信号端CLKB的信号；
第二输出控制模块062连接于低电平信号端VGL、第二节点P2，以及扫描信号输出端Out之间，第二输出控制模块062用于在第二节点P2的控制下，控制扫描信号输出端Out输出低电平信号端VGL的信号。
具体地，由于第一输出控制模块061和第二输出控制模块062分别在第一节点P1和第二节点P2的控制下对应输出第二时钟信号端CLKB的信号和低电平信号端VGL的信号，因此能够使得移位寄存器在对应时间段向对应栅线输出扫描信号，从而驱动显示面板实现逐行扫描。
在具体实施时，在上述移位寄存器中，如图6a和图6b所示，第一输出控制模块061包括第三开关晶体管T3和第一电容C1。其中，第三开关晶体管T3的栅极与第一节点P1相连，源极与第二时钟信号端CLKB相连，漏极与扫描信号输出端Out相连；第一电容C1连接于第一节点P1与扫描信号输出端Out之间。
当第一节点P1的电位被拉高时，第三开关晶体管T3处于导通状态，导通的第三开关晶体管T3将第二时钟信号端CLKB与扫描信号输出端Out导通，同时第一电容C1对第一节点P1的电位起到自举作用，以进一步保持第一节点P1的电位。
在具体实施时，在上述移位寄存器中，如图6a所示，第二输出控制模块062包括第四开关晶体管T4和第五开关晶体管T5。其中，第四开关晶体管T4的栅极与第二节点P2相连，源极与低电平信号端VGL相连，漏极与扫描信号输出端Out相连；第五开关晶体管T5的栅极与第二节点P2相连，源极和漏极分别与低电平信号端VGL相连。
当第二节点P2的电位被拉高时，第四开关晶体管T4和第五开关晶体 管T5处于导通状态，导通的第四开关晶体管T4将低电平信号端VGL与扫描信号输出端Out导通，同时导通的第五开关晶体管T5可以等效为电容，以进一步保持第二节点P2的电位，从而降低第二节点P2的电压信号的噪声。
在具体实施时，在上述移位寄存器中，如图6b所示，第二输出控制模块062包括第四开关晶体管T4和第二电容C2。其中，第四开关晶体管T4的栅极与第二节点P2相连，源极与低电平信号端VGL相连，漏极与扫描信号输出端Out相连；第二电容C2连接于第二节点P2和低电平信号端VGL之间。
当第二节点P2的电位被拉高时，第四开关晶体管T4处于导通状态，导通的第四开关晶体管T4将低电平信号端VGL与扫描信号输出端Out导通，同时第二电容C2可以进一步保持第二节点P2的电位，从而降低第二节点P2的电压信号的噪声。
在具体实施时，在上述移位寄存器中，如图7a和图7b所示，输入模块01包括第六开关晶体管T6。第六开关晶体管T6的栅极与信号输入端Input相连，源极与第一参考信号端CN相连，漏极分别与第一开关晶体管T1的漏极和第二开关晶体管T2的源极相连。
当信号输入端Input输入信号时，第六开关晶体管T6处于导通状态。导通的第六开关晶体管T6将第一参考信号端CN与第二开关晶体管T2的源极导通，通过第二开关晶体管T2将第一参考信号端CN的信号传递给第一节点P1。
在具体实施时，在上述移位寄存器中，如图7a和图7b所示，复位模块02包括第七开关晶体管T7。第七开关晶体管T7的栅极与复位信号端Reset相连，源极与第二参考信号端CNB相连，漏极分别与第一开关晶体管T1的漏极和第二开关晶体管T2的源极相连。
当复位信号端Reset输入信号时，第七开关晶体管T7处于导通状态。导通的第七开关晶体管T7将第二参考信号端CNB与第二开关晶体管T2的源极导通，并且通过第二开关晶体管T2将第二参考信号端CNB的信号传递给第一节点P1。
在具体实施时，在上述移位寄存器中，如图7a和图7b所示，第一下拉模块04包括第八开关晶体管T8。第八开关晶体管T8的栅极与第二节点P2相连，源极与低电平信号端VGL相连，漏极分别与第一开关晶体管 T1的漏极和所述第二开关晶体管T2的源极相连。
当第二节点P2的电位被拉高时，第八开关晶体管T8处于导通状态。导通的第八开关晶体管T8将第二开关晶体管T2的源极与低电平信号端VGL导通，进而将第二开关晶体管T2的源极的电位拉低。
在具体实施时，在上述移位寄存器中，如图7a和图7b所示，上拉模块03包括第九开关晶体管T9。第九开关晶体管T9的栅极和源极分别与第一时钟信号端CLK相连，漏极与第二节点P2相连。
当第一时钟信号端CLK输入高电平信号时，第九开关晶体管T9处于导通状态，导通的第九开关晶体管T9将第一时钟信号端CLK与第二节点P2导通，进而将第二节点P2的电位拉高。
在具体实施时，在上述移位寄存器中，如图7a和图7b所示，第二下拉模块05包括第十开关晶体管T10。第十开关晶体管T10的栅极与第一节点P1相连，源极与低电平信号端VGL相连，漏极与第二节点P2相连。
当第一节点P1的电位被拉高时，第十开关晶体管T10处于导通状态。导通的第十开关晶体管T10将第二节点P2与低电平信号端VGL导通，进而将第二节点P2的电位拉低。
需要说明的是，在本公开的上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。在具体实施中，这些晶体管的源极和漏极可以互换，不做具体区分。在描述具体实施例时以薄膜晶体管为例进行说明。
另外，由于在本公开的实施例中提供的上述移位寄存器中信号输入端Input和复位信号端Reset为对称设计，可以实现功能互换，因此本公开实施例提供的上述移位寄存器可以实现双向扫描。
一般地，在启动正向扫描时，第一参考信号端CN提供高电平信号，第二参考信号端CNB提供低电平信号。一般地，在反向扫描时，第一参考信号端CN提供低电平信号，第二参考信号端CNB提供高电平信号。
下面结合图7a所示的移位寄存器以及图8所示的图7a的输入输出时序图，以正向扫描为例对本公开实施例提供的移位寄存器的工作过程作以描述。具体地，选取如图8所示的输入输出时序图中的t1～t3三个阶段。下述描述中以1表示高电平信号，0表示低电平信号。
在t1阶段，Input＝1，CLKB＝0，CLK＝0，Reset＝0，CN＝1，CNB＝0。 由于Input＝1，因此第六开关晶体管T6导通。导通的第六开关晶体管T6将第一参考信号端CN与第二开关晶体管T2的源极导通，进而将第二开关晶体管T2的源极的电位拉高，。由于第二开关晶体管T2处于常开状态，因此第一节点P1的电位也被拉高，同时对第一电容C1充电。由于第一节点P1的电位被拉高，因此，第三开关晶体管T3和第十开关晶体管T10处于导通状态。导通的第三开关晶体管T3将第二时钟信号端CLKB与扫描信号输出端Out导通。由于此时CLKB＝0，因此扫描信号输出端Out输出低电平信号。导通的第十开关晶体管T10将第二节点P2与低电平信号端VGL导通，从而拉低第二节点P2的电位。t1阶段为充电阶段。
在t2阶段，Input＝0，CLKB＝1，CLK＝0，Reset＝0，CN＝1，CNB＝0。由于第一电容C1的自举作用，第一节点P1的电位进一步升高，因此第三开关晶体管T3仍处于导通状态。而此时CLKB＝1，因此，扫描信号输出端Out输出高电平信号。同时，第十开关晶体管T10仍处于导通状态，因此第二节点P2的电位继续被拉低。t2阶段为扫描信号输出阶段。
在t3阶段，Input＝0，CLKB＝0，CLK＝1，Reset＝1，CN＝1，CNB＝0。由于Reset＝1，因此第七开关晶体管T7导通。导通的第七开关晶体管T7将第二参考信号端CNB与第二开关晶体管T2的源极导通。由于CNB＝0，因此将第二开关晶体管T2的源极的电位拉低。由于第二开关晶体管T2处于常开状态，因此第一节点P1的电位也被拉低。由于第一节点P1的电位被拉低，因此，第三开关晶体管T3和第十开关晶体管T10处于截止状态。由于CLK＝1，因此第九开关晶体管T9导通。导通的第九开关晶体管T9将第一时钟信号端CLK与第二节点P2导通。因此，第二节点P2的电位被拉高。此时，第四开关晶体管T4处于导通状态。导通的第四开关晶体管T4将低电平信号端VGL与扫描信号输出端Out导通，因此扫描信号输出端Out输出低电平信号。t3阶段为非扫描信号输出阶段。
在后续时间段，扫描信号输出端Out将一直输出低电平信号，直到某个时间段信号输入端Input再次输入高电平信号时，则该移位寄存器将重复上述工作工程。
基于同一发明构思，本公开的第二方面提供了一种栅极驱动电路，包括级联的多个本公开实施例提供的上述移位寄存器，。其中除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与 其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器的扫描信号输出端向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器的扫描信号输出端向自身以及上一个移位寄存器的复位信号端输入复位信号。
为了方便说明，图9中示出了N个移位寄存器，分别为第1级移位寄存器、第2级移位寄存器、第3级移位寄存器、第4级移位寄存器……第N-3级移位寄存器、第N-2级移位寄存器、第N-1级移位寄存器、第N级移位寄存器。其中，第N-1级移位寄存器的信号输出端Out不仅向与其连接的栅线输出栅开启信号，还向第N-2级移位寄存器输出复位信号，同时还向第N级移位寄存器输出触发信号。
具体地，上述栅极驱动电路中的每个移位寄存器与本公开提供的上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
基于同一发明构思，本公开的第三方面提供了一种显示面板，包括本公开实施例提供的上述栅极驱动电路。由于该显示面板的原理与上述栅极驱动电路相似，因此该显示面板的实施可以参见上述栅极驱动电路的实施，重复之处不再赘述。
基于同一发明构思，本公开的第四方面提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置的原理与显示面板相似，因此该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
本公开实施例提供了一种移位寄存器、栅极驱动电路、显示面板及显示装置，该移位寄存器包括输入模块、复位模块、上拉模块、第一下拉模块、第二下拉模块，输出控制模块，以及输出降噪模块；其中，输入模块用于在信号输入端的控制下拉高第一节点的电位；复位模块用于在复位信号端的控制下拉低第一节点的电位；上拉模块用于在第一时钟信号端的控制下拉高第二节点的电位；第一下拉模块用于在第二节点的控制下拉低第一节点的电位；第二下拉模块用于在第一节点的控制下拉低第二节点的电位；输出控制模块用于在第一节点和第二节点的控制下，控制扫描信号输出端选择输出第二时钟信号端的信号或低电平信号端的信号。通过这样的布置，实现了移位寄存器输出扫描信号的功能。同时，输出降噪模块在扫描信号输出端输出扫描信号时，将扫描信号反馈给输出控制模块的第一控 制端，从而降低输出控制模块的第一控制端的信号噪声，进而降低扫描信号输出端输出的扫描信号的噪声。以此方式增强了信号的无损耗传输，降低功耗，从而提高显示面板的良率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种移位寄存器，包括：输入模块、复位模块、上拉模块、第一下拉模块、第二下拉模块、输出控制模块，以及输出降噪模块；其中，
    所述输入模块的输入端与第一参考信号端相连，控制端与信号输入端相连，输出端与第一节点相连，所述输入模块用于在所述信号输入端的控制下拉高所述第一节点的电位；
    所述复位模块的输入端与第二参考信号端相连，控制端与复位信号端相连，输出端与所述第一节点相连，所述复位模块用于在所述复位信号端的控制下拉低所述第一节点的电位；
    所述上拉模块的输入端和控制端分别与第一时钟信号端相连，输出端与第二节点相连，所述上拉模块用于在所述第一时钟信号端的控制下拉高所述第二节点的电位；
    所述第一下拉模块的输入端与低电平信号端相连，控制端与所述第二节点相连，输出端与所述第一节点相连，所述第一下拉模块用于在所述第二节点的控制下拉低所述第一节点的电位；
    所述第二下拉模块的输入端与低电平信号端相连，控制端与所述第一节点相连，输出端与所述第二节点相连，所述第二下拉模块用于在所述第一节点的控制下拉低所述第二节点的电位；
    所述输出控制模块的第一输入端与所述低电平信号端相连，第二输入端与第二时钟信号端相连，第一控制端与所述第一节点相连，第二控制端与所述第二节点相连，输出端与所述扫描信号输出端相连，所述输出控制模块用于在所述第一节点和所述第二节点的控制下，控制所述扫描信号输出端选择输出所述第二时钟信号端的信号或所述低电平信号端的信号；
    所述输出降噪模块的输入端与高电平信号端相连，控制端与所述扫描信号输出端相连，输出端与所述第一节点相连，所述输出降噪模块用于在所述扫描信号输出端输出扫描信号时将扫描信号反馈给所述输出控制模块的第一控制端。
  2. 如权利要求1所述的移位寄存器，其中，所述输出降噪模块包括第一开关晶体管，
    所述第一开关晶体管的栅极与所述扫描信号输出端相连，源极与所述高电平信号端相连，漏极与所述第一节点相连。
  3. 如权利要求2所述的移位寄存器，其中，所述输出降噪模块还包括传输模块，
    所述传输模块连接于所述高电平信号端、所述输入模块的输出端、所述复位模块的输出端、所述第一下拉模块的输出端、所述第一开关晶体管的漏极，以及所述第一节点之间，所述传输模块用于对所述第一开关晶体管的漏极的信号进行滤波降噪并且然后将其输出到所述第一节点。
  4. 如权利要求3所述的移位寄存器，其中，所述传输模块包括第二开关晶体管，
    所述第二开关晶体管的栅极与所述高电平信号端相连，源极与所述第一开关晶体管的漏极相连，漏极与所述第一节点相连。
  5. 如权利要求1所述的移位寄存器，其中，所述输出控制模块包括第一输出控制模块和第二输出控制模块；其中，
    所述第一输出控制模块连接于所述第一节点、所述第二时钟信号端，以及所述扫描信号输出端之间，所述第一输出控制模块用于在所述第一节点的控制下，控制所述扫描信号输出端输出所述第二时钟信号端的信号；
    所述第二输出控制模块连接于所述低电平信号端、所述第二节点，以及所述扫描信号输出端之间，所述第二输出控制模块用于在所述第二节点的控制下，控制所述扫描信号输出端输出所述低电平信号端的信号。
  6. 如权利要求5所述的移位寄存器，其中，所述第一输出控制模块包括：第三开关晶体管和第一电容；其中，
    所述第三开关晶体管的栅极与所述第一节点相连，源极与所述第二时钟信号端相连，漏极与所述扫描信号输出端相连；
    所述第一电容连接于所述第一节点与所述扫描信号输出端之间。
  7. 如权利要求5所述的移位寄存器，其中，所述第二输出控制模块包括第四开关晶体管和第五开关晶体管；其中，
    所述第四开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极与所述扫描信号输出端相连；
    所述第五开关晶体管的栅极与所述第二节点相连，源极和漏极分别与所述低电平信号端相连。
  8. 如权利要求5所述的移位寄存器，其中，所述第二输出控制模块包括第四开关晶体管和第二电容；其中，
    所述第四开关晶体管的栅极与所述第二节点相连，源极与所述低电平 信号端相连，漏极与所述扫描信号输出端相连；
    所述第二电容连接于所述第二节点和所述低电平信号端之间。
  9. 如权利要求4所述的移位寄存器，其中，所述输入模块包括第六开关晶体管，
    所述第六开关晶体管的栅极与所述信号输入端相连，源极与所述第一参考信号端相连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
  10. 如权利要求4所述的移位寄存器，其中，所述复位模块包括第七开关晶体管，
    所述第七开关晶体管的栅极与所述复位信号端相连，源极与所述第二参考信号端相连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
  11. 如权利要求4所述的移位寄存器，其中，所述第一下拉模块包括第八开关晶体管，
    所述第八开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极分别与所述第一开关晶体管的漏极和所述第二开关晶体管的源极相连。
  12. 如权利要求1-11任一项所述的移位寄存器，其中，所述上拉模块包括第九开关晶体管，
    所述第九开关晶体管的栅极和源极分别与所述第一时钟信号端相连，漏极与所述第二节点相连。
  13. 如权利要求1-11任一项所述的移位寄存器，其中，所述第二下拉模块包括第十开关晶体管，
    所述第十开关晶体管的栅极与所述第一节点相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
  14. 一种栅极驱动电路，包括级联的多个如权利要求1-13任一项所述的移位寄存器，其中除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器的扫描信号输出端向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器的扫描信号输出端向自身以及上一个移位寄存器的复位信号端输入复位信号。
  15. 一种显示面板，包括如权利要求14所述的栅极驱动电路。
  16. 一种显示装置，包括如权利要求15所述的显示面板。
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