WO2018233316A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018233316A1
WO2018233316A1 PCT/CN2018/077725 CN2018077725W WO2018233316A1 WO 2018233316 A1 WO2018233316 A1 WO 2018233316A1 CN 2018077725 W CN2018077725 W CN 2018077725W WO 2018233316 A1 WO2018233316 A1 WO 2018233316A1
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Prior art keywords
pull
node
control
clock signal
unit
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PCT/CN2018/077725
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English (en)
French (fr)
Inventor
黄飞
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/308,345 priority Critical patent/US11120718B2/en
Publication of WO2018233316A1 publication Critical patent/WO2018233316A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the embodiments of the present disclosure relate to the field of display driving technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • GOA Gate On Array
  • an embodiment of the present disclosure provides a shift register unit, including:
  • a starting unit which is respectively connected to the starting end and the pull-up node
  • a pull-up node control unit respectively connected to the pull-up node, the first clock signal input end, and the pull-down node;
  • a pull-down node control unit respectively connected to the first clock signal input end, the pull-down node, the start end, and the pull-up node;
  • a gate driving signal output unit which is respectively connected to the second clock signal input end, the pull-up node, the pull-down node, the low-level input end, and the gate driving signal output end;
  • a pull-up node noise reduction unit is respectively connected to the noise reduction control terminal, the pull-up node and the low-level input terminal, and is configured to control the pull-up node and the Connect or disconnect between low level inputs.
  • the shift register unit further includes:
  • the second capacitor unit is connected between the pull-down node and the low-level input terminal for controlling the potential of the pull-down node.
  • the gate driving signal output unit is specifically configured to control the gate driving signal output end and the second under the control of the pull-up node and the pull-down node.
  • a clock signal input terminal or the low level input terminal is connected;
  • the shift register unit further includes:
  • a start signal output unit respectively connected to the second clock signal input end, the pull-up node, the pull-down node, the low-level input end, and the start signal output end, for Controlling, by the node and the pull-down node, the start signal output end to be connected to the second clock signal input end or the low level input end;
  • the third capacitor unit is connected between the pull-up node and the start signal output end.
  • the noise reduction control terminal is connected to the pull-down node;
  • the pull-up node noise reduction unit comprises: a pull-up node noise reduction transistor, and the gate is connected to the noise reduction control terminal
  • the first pole is connected to the pull-up node, and the second pole is connected to the low-level input terminal.
  • the gate driving signal output unit includes:
  • a first gate driving signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input end, and a second pole connected to the gate driving signal output end;
  • a second gate driving signal output transistor a gate connected to the pull-down node, a first pole connected to the gate driving signal output end, and a second pole connected to the low level input end;
  • the start signal output unit includes:
  • a first start signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input end, and a second pole connected to the start signal output end;
  • a second start signal output transistor a gate connected to the pull-down node, a first pole connected to the start signal output end, and a second pole connected to the low level input end;
  • the second capacitor unit includes:
  • the first end is coupled to the gate of the second start signal output transistor, and the second end is coupled to the low level input.
  • the pull-up node control unit includes a pull-up control node; the pull-up node control unit is further connected to a high-level input terminal and the low-level input terminal, respectively, for Controlling the pull-up control node to be connected to the low-level input terminal when the first clock signal input terminal inputs a high level, and controlling the pull-up control node and the ground when the potential of the pull-down node is a high level
  • the low-level input terminal is connected, and the pull-up control node is controlled to be connected to the pull-up node under the control of the high-level input terminal.
  • the pull-up node control unit includes:
  • a first pull-up node control transistor a gate connected to the first clock signal input end, a first pole connected to the pull-up control node, and a second pole connected to the low-level input end;
  • a second pull-up node control transistor a gate connected to the pull-down node, a first pole connected to the pull-up control node, and a second pole connected to the low-level input terminal;
  • the third pull-up node controls the transistor, the gate is connected to the high-level input terminal, the first pole is connected to the pull-up node, and the second pole is connected to the pull-up control node.
  • the starting unit is configured to control a potential of the pull-up node to be a high level when the starting end inputs a high level;
  • the pull-down node control unit includes a pull-down control node; the pull-down node control unit is further connected to the high-level input terminal and the low-level input terminal, and is configured to control the device when the potential of the pull-up node is high
  • the pull-down node is connected to the low-level input terminal, and when the start-end terminal inputs a high level, the pull-down node is controlled to be connected to the low-level input terminal, when the first clock signal input terminal inputs a high level Controlling the potential of the pull-down control node to a high level, and controlling the pull-down control node to be connected to the pull-down node under the control of the high-level input terminal.
  • the pull-down node control unit includes:
  • a first pull-down node controls a transistor, a gate is connected to the pull-up control node, a first pole is connected to the pull-down node, and a second pole is connected to the low-level input terminal;
  • the second pull-down node controls the transistor, the gate is connected to the start end, the first pole is connected to the pull-down node, and the second pole is connected to the low-level input end;
  • a third pull-down node controls the transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole is connected to the pull-down control node;
  • the fourth pull-down node controls the transistor, the gate is connected to the high-level input terminal, the first pole is connected to the pull-down control node, and the second pole is connected to the pull-down node.
  • the shift register unit further includes: a reset unit, respectively connected to the reset end and the pull-down control node, configured to control the pull-down control node under the control of the reset end Potential.
  • an embodiment of the present disclosure further provides a driving method of a shift register unit, which is applied to the shift register unit described above, the driving method includes: in each display period,
  • the start unit controls the pull-up node to be connected with the start end, thereby
  • the beginning end charges the first capacitor unit such that the potential of the pull-up node is at a high level; under the control of the start end and the pull-up node, the pull-down node control unit controls the potential of the pull-down node to be a low level
  • the gate driving signal output unit controls the gate driving signal output end to be connected to the second clock signal input end under the control of the pull-up node, so that the gate driving signal output end outputs a low level;
  • the pull-up node noise reduction unit controls disconnection between the pull-up node and the low-level input terminal;
  • the first clock signal input terminal inputs a low level
  • the second clock signal input terminal inputs a high level
  • the first capacitor unit bootstraps the potential of the pull-up node
  • the pull-down node control unit continues to control such that the potential of the pull-down node is a low level
  • the gate drive signal output unit controls the gate under the control of the pull-up node
  • the pole drive signal output end is connected to the second clock signal input end, so that the gate drive signal output end outputs a high level
  • the pull-up node noise reduction unit controls Disconnecting between the pull-up node and the low-level input terminal;
  • the first clock signal input end and the second clock signal input end both input a low level, since the second clock signal input end becomes an input low level, due to the first capacitance
  • the function of the unit is such that the potential of the pull-up node jumps to the potential of the pull-up node in the first phase, and the potential of the pull-up node is still at a high level; under the control of the pull-up node, The pull-down node control unit continues to control such that the potential of the pull-down node is low; the gate drive signal output unit controls the gate drive signal output end and the first control under the control of the pull-up node
  • the two clock signal input ends are connected such that the gate drive signal output end outputs a low level; under the control of the noise reduction control end, the pull-up node noise reduction unit controls the pull-up node and the low Disconnected between level inputs;
  • the pull-up node control unit controls the The pull-up node control unit controls the potential of the pull-down node to be a high level, and the gate drive signal output unit controls the gate under the control of the pull-down node
  • the driving signal output end is connected to the low level input end, and the pull-up node noise reduction unit controls the pull-up node to be connected to the low level input end under the control of the noise reduction control end;
  • the first clock signal input end is input with a low level and a high level.
  • the pull-up node control unit continuously controls the potential of the pull-up node to be a low level
  • the pull-down node control unit continuously controls the potential of the pull-down node to a high level
  • the gate driving signal output unit is at the Under the control of the pull-down node
  • the gate drive signal output end is continuously connected to the low-level input end
  • the pull-up node noise reduction unit controls the pull-up node under the control of the noise reduction control end Connected to the low level input.
  • each display period further includes a reset phase before the first phase
  • the driving method further includes:
  • the reset terminal In the reset phase, the reset terminal inputs a high level, and the first clock signal input end and the second clock signal input end both input a low level, and under the control of the reset end, the reset unit controls the
  • the pull-down node is connected to the reset terminal such that the potential of the pull-down node is at a high level, and the pull-up node control unit controls the potential of the pull-up node to be low under the control of the pull-down node
  • the gate driving signal output end controls the gate driving signal output end to be connected to the second clock signal input end under the control of the pull-up node, so that the gate driving signal output end output is low a level
  • the pull-up node noise reduction unit controls the pull-up node to be connected to the low-level input terminal under the control of the noise reduction control terminal.
  • the period of the first clock signal input by the first clock signal input terminal and the period of the second clock signal input by the second clock signal input terminal are both T
  • the duty ratios of the first clock signal and the second clock signal are both 1/4
  • the first clock signal is delayed by T/2 from the second clock signal.
  • an embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units; except for the first stage of the shift register unit In addition, the start end of each stage of the shift register unit is connected to the gate drive signal output end of the shift register unit adjacent to the previous stage; or
  • the gate driving circuit includes a plurality of cascaded shift register units; in addition to the shift stage unit of the first stage, the start end of the shift register unit of each stage and the adjacent upper level The start signal output of the shift register unit is connected.
  • an embodiment of the present disclosure further provides a display device including the above-described gate driving circuit.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • 3A is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 3B is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram of a specific embodiment of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 is a timing chart showing the operation of this embodiment of the shift register unit according to the embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the main purpose of the embodiments of the present disclosure is to provide a shift register unit, a driving method, a gate driving circuit, and a display device, which can solve the problem that the existing shift register unit cannot properly pull up the node and the gate driving signal.
  • the terminal performs noise reduction, so that the technical problem of stable and effective output of the gate drive signal cannot be achieved.
  • the shift register unit of the embodiment of the present disclosure includes:
  • the starting unit 11 is respectively connected to the starting end STV and the pull-up node PU;
  • the pull-up node control unit 12 is respectively connected to the pull-up node PU, the first clock signal input terminal inputting the first clock signal CKB, and the pull-down node PD;
  • a pull-down node control unit 13 respectively connected to the first clock signal input end of the input first clock signal CKB, the pull-down node PD, the start end STV and the pull-up node PU;
  • the gate driving signal output unit 14 is respectively connected to the second clock signal input terminal of the second clock signal CK, the pull-up node PU, the pull-down node PD, the gate driving signal output terminal OUT, and the input low level VSS. Low level input connection;
  • the pull-up node noise reduction unit 15 is respectively connected to the noise reduction control terminal NC, the pull-up node PU, and the low-level input terminal of the input low level VSS, for control of the noise reduction control terminal NC And controlling connection or disconnection between the pull-up node PU and the low-level input terminal;
  • the first capacitor unit 16 is connected between the pull-up node PU and the gate drive signal output terminal OUT.
  • the first capacitor unit 16 is used to control the potential of the pull-up node PU.
  • the shift register unit of the embodiment of the present disclosure adopts a pull-up node noise reduction unit 15 to control whether the pull-up node PU is connected to the low-level input terminal under the control of the noise reduction control terminal NC.
  • the noise reduction is performed on the pull-up node under the control of the noise reduction control terminal NC.
  • the shift register unit described in the embodiments of the present disclosure has the advantages of low noise and good stability, and can greatly improve the panel yield.
  • the start signal is supplied to the adjacent lower stage shift register unit through the gate drive signal output terminal OUT.
  • the shift register unit of the embodiment of the present disclosure may further include:
  • the second capacitor unit 17 is connected between the pull-down node PD and the low-level input terminal of the input low level VSS.
  • Another difference between the shift register unit described in the embodiments of the present disclosure and the prior art is that, in addition to the first capacitor unit 16, another capacitor unit, that is, the second capacitor unit 17, is connected to the The pull-down node PD is between the low-level input terminal; the second capacitor unit 17 is for maintaining the potential of the pull-down node PD.
  • the gate driving signal output unit is specifically configured to control the gate driving signal output end and the second clock signal input end or under control of the pull-up node and the pull-down node The low level input is connected.
  • the shift register unit further includes:
  • a start signal output unit connected to the second clock signal input end, the pull-up node, the pull-down node, the low-level input end, and the start signal output end, respectively, for Controlling, by the node and the pull-down node, the start signal output end to be connected to the second clock signal input end or the low level input end;
  • the third capacitor unit is connected to the pull-up node and connected to the start signal output end.
  • the shift register unit of another embodiment of the present disclosure further includes:
  • the start signal output unit 18 is respectively connected to the second clock signal input terminal of the input second clock signal CK, the pull-up node PU, the pull-down node PD, the low-level input terminal of the input low level VSS, and a start signal output terminal STV_OUT connected to control the start signal output terminal STV_OUT and the second clock signal input terminal and/or the control under the control of the pull-up node PU and the pull-down node PD Low level input connection; and,
  • the third capacitor unit 19 is connected to the pull-up node PU and connected to the start signal output terminal STV_OUT.
  • a start signal output unit 18 is added, and the start signal is provided to the adjacent next stage shift register unit through the start signal output terminal STV_OUT, and the shift is enhanced.
  • the third capacitor unit 19 is for further maintaining the potential of the pull-up node PU.
  • the noise reduction control terminal NC may be connected to the pull-down node PD.
  • the pull-up node noise reduction unit 15 includes: a pull-up node noise reduction transistor T12, a gate connected to the noise reduction control terminal NC, a first pole connected to the pull-up node PU, and a second pole and an input low-power The low level input of the flat VSS is connected.
  • the pull-up node noise reduction transistor T12 may be an n-type transistor, but is not limited thereto.
  • the noise reduction control terminal may also be connected to other terminals, and the noise reduction control terminal only needs to be able to output a corresponding noise reduction control signal to control the noise reduction of the pull-up node in a corresponding period of time.
  • the noise reduction control terminal can also be connected to the first clock signal input terminal.
  • the period of the first clock signal and the period of the second clock signal may both be T, and the duty ratio of the first clock signal and the second clock signal may both be 1/4, and the second clock signal ratio is The first clock signal is delayed by T/2 as shown in FIG.
  • the gate driving signal output unit may include:
  • a first gate driving signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input end, and a second pole connected to the gate driving signal output end;
  • the second gate driving signal output transistor has a gate connected to the pull-down node, a first pole connected to the gate driving signal output end, and a second pole connected to the low level input end.
  • start signal output unit may include:
  • a first start signal output transistor a gate connected to the pull-up node, a first pole connected to the second clock signal input end, and a second pole connected to the start signal output end;
  • a second start signal output transistor the gate is connected to the pull-down node, the first pole is connected to the start signal output end, and the second pole is connected to the low level input end.
  • the second capacitor unit may include:
  • the first end is coupled to the gate of the second start signal output transistor, and the second end is coupled to the low level input.
  • the pull-up node control unit 12 may include a pull-up control node (not shown in FIG. 4).
  • the pull-up node control unit 12 is further connected to a high-level input terminal inputting a high-level VDD and a low-level input terminal inputting a low-level VSS, respectively, for inputting the first clock signal CKB Controlling the pull-up control node (not shown in FIG. 4) and the low-level input terminal of the input low level VSS when a clock signal input terminal inputs a high level, when the potential of the pull-down node PD is high Normally controlling the pull-up control node (not shown in FIG.
  • the pull-up control node (not shown in FIG. 4) is connected to the pull-up node PU.
  • the pull-up node control unit may include:
  • a first pull-up node control transistor a gate connected to the first clock signal input end, a first pole connected to the pull-up control node, and a second pole connected to the low-level input end;
  • a second pull-up node control transistor a gate connected to the pull-down node, a first pole connected to the pull-up control node, and a second pole connected to the low-level input terminal;
  • the third pull-up node controls the transistor, the gate is connected to the high-level input terminal, the first pole is connected to the pull-up node, and the second pole is connected to the pull-up control node.
  • the pull-up node control unit 12 may include:
  • the first pull-up node controls the transistor T3, the gate is connected to the first clock signal input end of the input first clock signal CKB, the drain is connected to the pull-up control node PUCN, and the source and the input low level VSS low level input connection;
  • the second pull-up node controls the transistor T4, the gate is connected to the pull-down node PD, the drain is connected to the pull-up control node PUCN, and the source is connected to the low-level input terminal of the input low level VSS; ,
  • the third pull-up node controls the transistor T7, the gate is connected to the high-level input terminal of the input high-level VDD, the drain is connected to the pull-up node PU, and the source is connected to the pull-up control node PUCN.
  • T3, T4, and T7 are both n-type transistors will be described.
  • T3 When the first clock signal CKB is high, T3 is turned on to enable the pull-up control node PUCN to be connected to the low level VSS; when the first clock signal CKB is low, T3 is turned off, so that the pull-up is performed
  • the control node PUCN is not electrically connected to the low level input terminal of the input low level VSS;
  • T4 When the potential of the pull-down node PD is high level, T4 is turned on, so that the pull-up control node PU is connected to the low level VSS; when the potential of the pull-down node PD is low level, T4 is turned off, so that The pull-up control node PUCN is not electrically connected to the low-level input terminal of the input low level VSS;
  • V7 Since the gate of T7 is connected to the high level VDD, V7 is normally open, so that the pull-up node PU and the pull-up control node PUCN are electrically connected.
  • the starting unit may be configured to control a potential of the pull-up node to be a high level when the start end inputs a high level;
  • the pull-down node control unit may include a pull-down control node; the pull-down node control unit is further connected to the high-level input terminal and the low-level input terminal, and is configured to control when the potential of the pull-up node is high level
  • the pull-down node is connected to the low-level input terminal, and when the start-end terminal inputs a high level, the pull-down node is controlled to be connected to the low-level input end, and when the first clock signal input end is input with high power
  • the potential of the pull-down control node is normally controlled to be a high level, and the pull-down control node is controlled to be connected to the pull-down node under the control of the high-level input terminal.
  • the start unit 11 is configured to control the potential of the pull-up node PU to be high when the start terminal STV inputs a high level. Level.
  • the pull-down node control unit 13 may include a pull-down control node PDCN (not shown in FIG. 6).
  • the pull-down node control unit 13 is further connected to the high-level input terminal of the input high-level VDD and the low-level input terminal of the input low-level VSS, for when the potential of the pull-up node PU is
  • the pull-down node PD is connected to the low level input end of the input low level VSS, and when the start end STV is input high level, the pull-down node PD and the input low level VSS are controlled.
  • a low-level input terminal is connected to control a potential of the pull-down control node PDCN (not shown in FIG.
  • the pull-down control node PDCN (not shown in FIG. 6) is controlled to be connected to the pull-down node PD under the control of the high-level input of the input high level VDD.
  • the pull-down node control unit may include:
  • a first pull-down node controls a transistor, a gate is connected to the pull-up node, a first pole is connected to the pull-down node, and a second pole is connected to the low-level input terminal;
  • the second pull-down node controls the transistor, the gate is connected to the start end, the first pole is connected to the pull-down node, and the second pole is connected to the low-level input end;
  • a third pull-down node controls the transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole is connected to the pull-down control node;
  • the fourth pull-down node controls the transistor, the gate is connected to the high-level input terminal, the first pole is connected to the pull-down control node, and the second pole is connected to the pull-down node.
  • the pull-down node control unit 13 includes:
  • the first pull-down node controls the transistor T8, the gate is connected to the pull-up node PU, the drain is connected to the pull-down node PD, and the source is connected to the low-level input terminal of the input low level VSS;
  • the second pull-down node controls the transistor T6, the gate is connected to the start terminal STV, the drain is connected to the pull-down node PD, and the source is connected to the low-level input terminal of the input low level VSS;
  • the fourth pull-down node controls the transistor T11, the gate is connected to the high-level input terminal of the input high-level VDD, the drain is connected to the pull-down control node PDCN, and the source is connected to the pull-down node PD.
  • an N-type transistor is illustrated as an example of T8, T6, T10, and T11.
  • T8 When the potential of the pull-up node PU is high level, T8 is turned on, so that the pull-down node PD is connected to VSS; when the potential of the pull-up node PU is low level, T8 is turned off to disconnect the pull-down node PD and a connection between low level inputs;
  • T6 When the start terminal STV is input to a high level, T6 is turned on, so that the pull-down node PD is connected to the low level VSS; when the start terminal STV is input with a low level, T6 is turned off to disconnect the pull-down node PD and the low level.
  • T10 When the first clock signal CKB is at a high level, T10 is turned on, so that the first clock signal input terminal is connected to the pull-down control node PDCN, so that the potential of the pull-down control node PDCN is at a high level; when the first clock When the signal CKB is low, T10 is turned off to disconnect the connection between the first clock signal input terminal and the pull-down control node PDCN;
  • T11 Since the gate of T11 is connected to the high level input terminal, T11 is normally open, so that the electrical connection between the pull-down control node PDCN and the pull-down node PD is electrically connected.
  • the shift register unit according to the embodiment of the present disclosure further includes: a reset unit 110, and a reset end Reset and the pull-down control, respectively.
  • a node PDCN connection is used to control the potential of the pull-down control node PDCN under the control of the reset terminal Reset.
  • the reset unit 110 can be controlled by the reset terminal Reset to control the potential of the pull-down control node PDCN.
  • a specific embodiment of the shift register unit of the present disclosure includes a start unit, a pull-up node control unit, a pull-down node control unit, a gate drive signal output unit, and a pull-up node.
  • the starting unit comprises: a starting transistor T1, the gate and the drain are both connected to the starting end STV, and the source is connected to the pull-up control node PUCN.
  • the noise reduction control terminal includes a pull-down node PD.
  • the pull-up node noise reduction unit comprises: a pull-up node noise reduction transistor T12, a gate connected to the pull-down node PD, a drain connected to the pull-up node PU, and a low-level input of the source and the input low level VSS End connection.
  • the gate drive signal output unit includes:
  • a first gate driving signal outputting transistor T13 a gate connected to the pull-up node PU, a drain connected to a second clock signal input end of the input second clock signal CK, a source and the gate driving signal output end OUT connection;
  • the second gate driving signal output transistor T14 has a gate connected to the pull-down node PD, a drain connected to the gate driving signal output terminal OUT, and a source connected to the low-level input terminal of the input low level VSS.
  • the start signal output unit includes:
  • a first start signal output transistor T15 a gate connected to the pull-up node PU, a drain connected to the second clock signal input end of the input second clock signal CK, a source and the start signal output terminal STV_OUT Connect;
  • the second start signal output transistor T16 has a gate connected to the pull-down node PD, a drain connected to the start signal output terminal STV_OUT, and a source connected to the low-level input terminal of the input low level VSS.
  • the first capacitor unit includes a storage capacitor C1, the first end is connected to the pull-up node PU, and the second end is connected to the gate drive signal output end OUT.
  • the second capacitor unit includes:
  • a first output capacitor C3 the first end is connected to the gate of the second gate driving signal outputting transistor T14, and the second end is connected to the low level input end of the input low level VSS;
  • the second output capacitor C4 has a first end connected to the gate of the second start signal output transistor T16, and a second end connected to the low level input terminal of the input low level VSS.
  • the third capacitor unit includes: a starting capacitor C2, the first end is connected to the pull-up node PU, and the second end is connected to the start signal output terminal STV_OUT.
  • the pull-up node control unit includes:
  • the first pull-up node controls the transistor T3, the gate is connected to the first clock signal input terminal of the input first clock signal CKB, the drain is connected to the pull-up control node PUCN, and the source and the input low level VSS are low.
  • the second pull-up node controls the transistor T4, the gate is connected to the pull-down node PD, the drain is connected to the pull-up control node PUCN, and the source is connected to the low-level input terminal of the input low level VSS; ,
  • the third pull-up node controls the transistor T7, the gate is connected to the high-level input terminal of the input high-level VDD, the drain is connected to the pull-up node PU, and the source is connected to the pull-up control node PUCN.
  • the pull-down node control unit includes:
  • the first pull-down node controls the transistor T8, the gate is connected to the pull-up control node PUCN, the drain is connected to the pull-down node PD, and the source is connected to the low-level input terminal of the input low level VSS;
  • the second pull-down node controls the transistor T6, the gate is connected to the start terminal STV, the drain is connected to the pull-down node PD, and the source is connected to the low-level input terminal of the input low level VSS;
  • the fourth pull-down node controls the transistor T11, the gate is connected to the high-level input terminal of the input high-level VDD, the drain is connected to the pull-down control node PDCN, and the source is connected to the pull-down node PD.
  • the reset unit includes a reset transistor T9, the gate and the drain are both connected to the reset terminal Reset, and the source is connected to the pull-down control node PDCN.
  • all of the transistors are NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) tubes, but in actual operation, the shift register unit is used.
  • the transistor can also be P-type, and the type of transistor is not limited herein.
  • a reset signal is input by the reset terminal Reset, and the reset signal resets the shift register unit by giving a high level for a certain period of time before the start of each frame scan. The rest of the time is low; T7 and T11 are normally open; VDD is a DC high level signal, VSS is a DC low level signal, and STV_OUT provides a start signal for the adjacent next stage shift register unit.
  • the specific embodiment of the shift register unit shown in FIG. 9 is composed of 14 NMOS transistors and 4 capacitors, which can effectively reduce noise, thereby improving the performance and stability of the gate drive of the display.
  • the shift register unit shown in FIG. 9 reduces the noise of the signal path and the noise of the output of the gate drive signal by adding a normally open NMOS transistor (ie, T7 and T11) as a single-tube transmission gate, and enhancing the signal. Lossless transmission.
  • the specific embodiment of the shift register unit shown in FIG. 9 of the present disclosure adds four capacitors so that the voltage of the pull-up node PU and the voltage of the pull-down node PD are more stable and effective, ensuring a stable and effective output of the gate drive signal.
  • the specific embodiment of the shift register unit shown in FIG. 9 of the present disclosure is in operation, during each display period (ie, each frame display time).
  • Reset inputs a high level
  • STV inputs a low level
  • CK and CKB are both low
  • T9 is turned on
  • T11 is turned on
  • PD is connected to Reset, so that the potential of the PD is high
  • T4 is turned on. So that the PUCN is connected to VSS, T7 is turned on, so that the PU is connected to the PUCN, and the PU is also connected to the VSS.
  • both T14 and T16 are turned on, the OUT output is low, and the STV_OUT is also output low; and due to the potential of the PD High level, T12 is turned on to denoise the PU;
  • both Reset and STV input a low level, and CK and CKB are both low. Since CK goes low, the potential of the PU returns to the potential of the first stage S1, but the potential of the PU is still High level, the potential of PD is still low level, T13 and T15 are both open, T14 and T16 are both closed, OUT is connected with the second clock signal input terminal, OUT and STV_OUT both output low level;
  • the CK interval is a high level and a low level
  • the CKB interval is a low level and a high level.
  • T3 is turned on, so that PUCN is connected to the low-level input of input VSS, and the potential of PUCN is low. Since T7 is normally open, the potential of PU is also low; when CKB is When high level, T10 is turned on, so PDCN is connected with the first clock signal input end of input CKB, and the potential of PDCN is high level. Since T11 is normally open, the potential of PD is high level, T12 is turned on, so that PU and The low-level input of the input VSS is connected to denoise the PU.
  • the potential of the PD is low, T12 is disconnected, and the pull-up node noise reduction unit controls the PU to be disconnected from the low-level input of the input low level VSS. open.
  • T12 When CKB is high level, T12 operates as a single-tube transmission gate to better lower the potential of the PU and the gate drive signal.
  • the potential of the gate drive signal outputted by the output terminal OUT is used to denoise the PU terminal and the OUT terminal to improve the stability of the gate drive signal output.
  • C1 and C2 function as potentials of the bootstrap PU
  • C3 and C4 function to stabilize the potential of the PD and reduce the noise of the PD.
  • T12 is used as a single-tube transmission gate to mainly transmit a high level during operation.
  • T12 is an NMOS ( N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor tubes, there is a certain threshold loss in NMOS single-tube transmission gates. Therefore, in order to reduce the threshold loss, a PMOS (P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor) single-tube transfer gate can be used instead, or CMOS (Complementary Metal Oxide Semiconductor) can be used to eliminate the threshold loss.
  • the three embodiments of the shift register unit function to filter and shape the signal using the parasitic capacitance of the transfer gate.
  • T12 can be a PMOS transistor, in which case the gate of T12 is connected to the third clock signal input terminal, and the third clock signal is inverted from the first clock signal CKB.
  • the noise reduction control terminal may include a first clock signal input terminal and a third clock signal input terminal; and the pull-up node reduces noise.
  • the unit may include: a first pull-up node noise reduction transistor, a gate connected to the first clock signal input end, a first pole connected to the pull-up node, and a second pole connected to the low-level input end; And a second pull-up node noise reduction transistor, the gate is connected to the third clock signal income end, the first pole is connected to the low level input terminal, and the second pole is connected to the pull-up node;
  • the first pull-up node noise reduction transistor is an NMOS transistor
  • the second pull-up node noise reduction transistor is a PMOS transistor; a first clock signal input by the first clock signal input end and a first clock signal input end input by the third clock signal input end The three clock signals are inverted.
  • the noise reduction control terminal may include a pull-down node and a third clock signal input terminal; and the pull-up node noise reduction unit includes: a pull-up node noise reduction transistor, a gate connected to the pull-down node, a first pole connected to the pull-up node, a second pole connected to the low-level input terminal, and a second pull-up node noise reduction a transistor, a gate connected to the third clock signal income end, a first pole connected to the low level input terminal, a second pole connected to the pull up node, and the first pull-up node noise reduction transistor being
  • the NMOS transistor, the second pull-up node noise reduction transistor is a PMOS transistor; the first clock signal input by the first clock signal input terminal is inverted with the third clock signal input by the third clock signal input terminal.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is applied to the shift register unit described above, and the driving method includes:
  • the start unit controls the pull-up node to be connected with the start end, thereby
  • the beginning end charges the first capacitor unit such that the potential of the pull-up node is at a high level; under the control of the start end and the pull-up node, the pull-down node control unit controls the potential of the pull-down node to be a low level
  • the gate driving signal output unit controls the gate driving signal output end to be connected to the second clock signal input end under the control of the pull-up node, so that the gate driving signal output end outputs a low level;
  • the pull-up node noise reduction unit controls disconnection between the pull-up node and the low-level input terminal;
  • the first clock signal input terminal inputs a low level
  • the second clock signal input terminal inputs a high level
  • the first capacitor unit bootstraps the potential of the pull-up node
  • the pull-down node control unit continues to control such that the potential of the pull-down node is low
  • the gate driving signal output unit controls the gate driving under the control of the pull-up node
  • the signal output end is connected to the second clock signal input end, so that the gate drive signal output end outputs a high level
  • the pull-up node noise reduction unit controls the Disconnecting between the pull-up node and the low-level input terminal;
  • the first clock signal input end and the second clock signal input end both input a low level, since the second clock signal input end becomes an input low level, due to the first capacitance
  • the function of the unit is such that the potential of the pull-up node jumps to the potential of the pull-up node in the first phase, and the potential of the pull-up node is still at a high level; under the control of the pull-up node, The pull-down node control unit continues to control such that the potential of the pull-down node is low; the gate drive signal output unit controls the gate drive signal output end and the first control under the control of the pull-up node
  • the two clock signal input ends are connected such that the gate drive signal output end outputs a low level; under the control of the noise reduction control end, the pull-up node noise reduction unit controls the pull-up node and the low Disconnected between level inputs;
  • the pull-up node control unit is under the control of the first clock signal input end Controlling a potential of the pull-up node to a low level
  • the pull-down node control unit controls a potential of the pull-down node to be a high level
  • the gate drive signal output unit controls the control under the control of the pull-down node
  • the gate driving signal output end is connected to the low level input end
  • the pull-up node noise reduction unit controls the pull-up node to be connected to the low level input end under the control of the noise reduction control end;
  • the first clock signal input end is input with a low level and a high level.
  • the pull-up node control unit continuously controls the potential of the pull-up node to be a low level
  • the pull-down node control unit continuously controls the potential of the pull-down node to a high level
  • the gate driving signal output unit is at the Under the control of the pull-down node
  • the gate drive signal output end is continuously connected to the low-level input end
  • the pull-up node noise reduction unit controls the pull-up node under the control of the noise reduction control end Connected to the low level input.
  • the driving method of the shift register unit according to the embodiment of the present disclosure adopts the pull-up node noise reduction unit under the control of the noise reduction control end at all times after the fourth stage and the fourth stage of each display period
  • the noise reduction of the pull-up node is performed at a partial time, so that the shift register unit described in the embodiment of the present disclosure has the advantages of low noise and good stability, and the panel yield can be greatly improved.
  • the pull-up in the first phase, the second phase, and the third phase of each display cycle, the pull-up is controlled under the control of the noise reduction control terminal
  • the node noise reduction unit controls the disconnection between the pull-up node and the low-level input terminal of the input low level to avoid making the potential of the pull-up node high.
  • each display period further includes a reset phase before the first phase
  • the driving method of the shift register unit in the embodiment of the present disclosure further includes:
  • the reset terminal In the reset phase, the reset terminal inputs a high level, and the first clock signal input end and the second clock signal input end both input a low level, and under the control of the reset end, the reset unit controls the pull-down a node is connected to the reset end such that a potential of the pull-down node is at a high level, and the pull-up node control unit controls a potential of the pull-up node to be a low level under the control of the pull-down node.
  • the gate driving signal output end controls the gate driving signal output end to be connected to the second clock signal input end under the control of the pull-up node, so that the gate driving signal output end outputs a low level
  • the pull-up node noise reduction unit controls the pull-up node to be connected to the low-level input terminal under the control of the noise reduction control end, thereby performing noise reduction on the pull-up node.
  • a period of the first clock signal input by the first clock signal input end and a period of the second clock signal input by the second clock signal input end are both T, the first clock signal and the The duty ratio of the second clock signal is 1/4, and the first clock signal is delayed by T/2 from the second clock signal, as shown in FIG.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded shift register units; in addition to the first stage shift register unit, each stage of the shift register unit The start end is connected to the gate drive signal output end of the shift register unit adjacent to the upper stage; or
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded shift register units described above; a start end of the shift register unit of each stage except the first stage shift register unit Connected to the start signal output of the adjacent upper stage shift register unit.
  • the display device described in the embodiments of the present disclosure includes the above-described gate driving circuit.
  • the display device may specifically include a liquid crystal display device, for example, the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

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Abstract

本公开文本实施例提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元包括：起始单元(11)；上拉节点控制单元(12)；下拉节点控制单元(13)；栅极驱动信号输出单元(14)；第一电容单元(16)；以及，上拉节点降噪单元(15)，分别与降噪控制端(NC)、所述上拉节点(PU)和所述低电平输入端(VSS)连接，用于在所述降噪控制端(NC)的控制下控制所述上拉节点(PU)与所述低电平输入端(VSS)之间连接或断开。本公开文本实施例可以实现栅极驱动信号的稳定输出。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2017年6月21日在中国提交的中国专利申请号No.201710474351.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本实施例涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
目前随着液晶面板业竞争趋于激烈，降低面板成本成为面板厂商的首选方法。其中GOA(Gate On Array，设置在阵列基板上的栅极驱动)电路的采用可以减少IC(Integrated Circuit，集成电路)使用量，因此成为降低成本的一个直接的方法。噪声降低是GOA电路设计的一个考虑重点，这是因为现有的GOA电路存在输出噪声高、稳定性差等技术问题。
发明内容
在第一方面中，本公开文本实施例提供了一种移位寄存器单元，包括：
起始单元，分别与起始端和上拉节点连接；
上拉节点控制单元，分别与所述上拉节点、第一时钟信号输入端和下拉节点连接；
下拉节点控制单元，分别与所述第一时钟信号输入端、所述下拉节点、所述起始端和所述上拉节点连接；
栅极驱动信号输出单元，分别与第二时钟信号输入端、所述上拉节点、所述下拉节点、低电平输入端和栅极驱动信号输出端连接；
第一电容单元，连接于所述上拉节点和所述栅极驱动信号输出端之间；以及，
上拉节点降噪单元，分别与降噪控制端、所述上拉节点和所述低电平输 入端连接，用于在所述降噪控制端的控制下，控制所述上拉节点与所述低电平输入端之间连接或断开。
根据本公开文本的一个可行实施例，所述的移位寄存器单元还包括：
第二电容单元，连接于所述下拉节点和所述低电平输入端之间，用于控制维持下拉节点的电位。
根据本公开文本的一个可行实施例，所述栅极驱动信号输出单元具体用于在所述上拉节点和所述下拉节点的控制下，控制所述栅极驱动信号输出端与所述第二时钟信号输入端或所述低电平输入端连接；
所述移位寄存器单元还包括：
起始信号输出单元，分别与所述第二时钟信号输入端、所述上拉节点、所述下拉节点、所述低电平输入端和起始信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下，控制所述起始信号输出端与所述第二时钟信号输入端或所述低电平输入端连接；以及，
第三电容单元，连接于所述上拉节点与所述起始信号输出端之间。
根据本公开文本的一个可行实施例，所述降噪控制端与所述下拉节点连接；所述上拉节点降噪单元包括：上拉节点降噪晶体管，栅极与所述降噪控制端连接，第一极与所述上拉节点连接，第二极与所述低电平输入端连接。
根据本公开文本的一个可行实施例，所述栅极驱动信号输出单元包括：
第一栅极驱动信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动信号输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述低电平输入端连接；
所述起始信号输出单元包括：
第一起始信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述起始信号输出端连接；以及，
第二起始信号输出晶体管，栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述低电平输入端连接；
所述第二电容单元包括：
第一输出电容，第一端与所述第二栅极驱动信号输出晶体管的栅极连接， 第二端与所述低电平输入端连接；以及，
第二输出电容，第一端与所述第二起始信号输出晶体管的栅极连接，第二端与所述低电平输入端连接。
根据本公开文本的一个可行实施例，所述上拉节点控制单元包括上拉控制节点；所述上拉节点控制单元还分别与高电平输入端和所述低电平输入端连接，用于当所述第一时钟信号输入端输入高电平时控制所述上拉控制节点与所述低电平输入端连接，当所述下拉节点的电位为高电平时控制所述上拉控制节点与所述低电平输入端连接，并在所述高电平输入端的控制下控制所述上拉控制节点与所述上拉节点连接。
根据本公开文本的一个可行实施例，所述上拉节点控制单元包括：
第一上拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；
第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；以及，
第三上拉节点控制晶体管，栅极与所述高电平输入端连接，第一极与所述上拉节点连接，第二极与所述上拉控制节点连接。
根据本公开文本的一个可行实施例，所述起始单元用于当所述起始端输入高电平时控制所述上拉节点的电位为高电平；
所述下拉节点控制单元包括下拉控制节点；所述下拉节点控制单元还与高电平输入端和所述低电平输入端连接，用于当所述上拉节点的电位为高电平时控制所述下拉节点与所述低电平输入端连接，当所述起始端输入高电平时控制所述下拉节点与所述低电平输入端连接，当所述第一时钟信号输入端输入高电平时控制所述下拉控制节点的电位为高电平，并在所述高电平输入端的控制下控制所述下拉控制节点与所述下拉节点连接。
根据本公开文本的一个可行实施例，所述下拉节点控制单元包括：
第一下拉节点控制晶体管，栅极与所述上拉控制节点连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
第二下拉节点控制晶体管，栅极与所述起始端连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
第三下拉节点控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉控制节点连接；以及，
第四下拉节点控制晶体管，栅极与所述高电平输入端连接，第一极与所述下拉控制节点连接，第二极与所述下拉节点连接。
根据本公开文本的一个可行实施例，所述的移位寄存器单元还包括：复位单元，分别与复位端和所述下拉控制节点连接，用于在所述复位端的控制下控制所述下拉控制节点的电位。
在第二方面中，本公开文本实施例还提供了一种移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：在每一显示周期内，
在第一阶段，第一时钟信号输入端和第二时钟信号输入端都输入低电平，在起始端的控制下，起始单元控制上拉节点与所述起始端连接，从而通过所述起始端为第一电容单元充电，使得所述上拉节点的电位为高电平；在所述起始端和所述上拉节点的控制下，下拉节点控制单元控制使得下拉节点的电位为低电平；栅极驱动信号输出单元在所述上拉节点的控制下控制栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在降噪控制端的控制下，上拉节点降噪单元控制所述上拉节点与低电平输入端之间断开；
在第二阶段，所述第一时钟信号输入端输入低电平，所述第二时钟信号输入端输入高电平，所述第一电容单元自举拉升所述上拉节点的电位；在所述上拉节点的控制下，所述下拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出高电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
在第三阶段，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，由于所述第二时钟信号输入端变为输入低电平，由于所述第一电容单元的作用，使得所述上拉节点的电位跳变到所述上拉节点在第一阶段的电位，所述上拉节点的电位仍为高电平；在所述上拉节点的控制下，所述下 拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
在第四阶段，所述第一时钟信号输入端输入高电平，所述第二时钟信号输入端输入低电平，在所述第一时钟信号输入端的控制下，上拉节点控制单元控制所述上拉节点的电位为低电平，所述下拉节点控制单元控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控制下控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接；
在第四阶段结束后，所述第一时钟信号输入端间隔输入低电平、高电平，当所述第一时钟信号输入端输入高电平时，在该第一时钟信号输入端的控制下，所述上拉节点控制单元持续控制所述上拉节点的电位为低电平，所述下拉节点控制单元持续控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控制下持续控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接。
根据本公开文本的一个可行实施例，当所述移位寄存器单元还包括复位单元时，每一显示周期在所述第一阶段之前还包括复位阶段；
所述驱动方法还包括：
在所述复位阶段，复位端输入高电平，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，在所述复位端的控制下，所述复位单元控制所述下拉节点与所述复位端连接，从而使得所述下拉节点的电位为高电平，所述上拉节点控制单元在所述下拉节点的控制下控制所述上拉节点的电位为低电平，所述栅极驱动信号输出端在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平，在所述降噪控制端的控制下，所述上拉节点降噪单 元控制所述上拉节点与所述低电平输入端连接。
根据本公开文本的一个可行实施例，由所述第一时钟信号输入端输入的第一时钟信号的周期和由所述第二时钟信号输入端输入的第二时钟信号的周期都为T，所述第一时钟信号和所述第二时钟信号的占空比都为1/4，所述第一时钟信号比所述第二时钟信号延迟T/2。
在第三方面中，本公开文本实施例还提供了一种栅极驱动电路，所述栅极驱动电路包括多个级联的上述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻上一级所述移位寄存器单元的栅极驱动信号输出端连接；或者，
所述栅极驱动电路包括多个级联的上述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻上一级所述移位寄存器单元的起始信号输出端连接。
在第四方面中，本公开文本实施例还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开文本实施例所述的移位寄存器单元的结构图；
图2是本公开文本另一实施例所述的移位寄存器单元的结构图；
图3A是本公开文本又一实施例所述的移位寄存器单元的结构图；
图3B是本公开文本另一实施例所述的移位寄存器单元的结构图；
图4是本公开文本再一实施例所述的移位寄存器单元的结构图；
图5是本公开文本另一实施例所述的移位寄存器单元的结构图；
图6是本公开文本又一实施例所述的移位寄存器单元的结构图；
图7是本公开文本再一实施例所述的移位寄存器单元的结构图；
图8是本公开文本又一实施例所述的移位寄存器单元的结构图；
图9是本公开文本实施例所述的移位寄存器单元的一具体实施方式的电路图；以及
图10是本公开文本实施例所述的移位寄存器单元的该具体实施方式的工作时序图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
下面将结合本公开文本实施例中的附图，对本公开文本实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开文本一部分实施例，而不是全部的实施例。基于本公开文本中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开文本保护的范围。
本公开文本所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开文本实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开文本实施例的主要目的在于提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置，解决现有的移位寄存器单元无法很好的对上拉节点和栅极驱动信号输出端进行降噪，从而无法实现栅极驱动信号的稳定有效输出的技术问题。
如图1所示，本公开文本实施例所述的移位寄存器单元包括：
起始单元11，分别与起始端STV和上拉节点PU连接；
上拉节点控制单元12，分别与所述上拉节点PU、输入第一时钟信号CKB的第一时钟信号输入端和下拉节点PD连接；
下拉节点控制单元13，分别与所述输入第一时钟信号CKB的第一时钟信号输入端、所述下拉节点PD、所述起始端STV和所述上拉节点PU连接；
栅极驱动信号输出单元14，分别与输入第二时钟信号CK的第二时钟信 号输入端、所述上拉节点PU、所述下拉节点PD、栅极驱动信号输出端OUT和输入低电平VSS的低电平输入端连接；
上拉节点降噪单元15，分别与降噪控制端NC、所述上拉节点PU和所述输入低电平VSS的低电平输入端连接，用于在所述降噪控制端NC的控制下，控制所述上拉节点PU与所述低电平输入端之间连接或断开；以及，
第一电容单元16，连接于所述上拉节点PU和所述栅极驱动信号输出端OUT之间。
在如图1所示的实施例中，所述第一电容单元16用于控制维持上拉节点PU的电位。
本公开文本实施例所述的移位寄存器单元采用了上拉节点降噪单元15，在所述降噪控制端NC的控制下控制所述上拉节点PU是否与所述低电平输入端连接，在降噪控制端NC的控制下对上拉节点进行降噪。本公开文本实施例所述的移位寄存器单元具有噪声低、稳定性好的优点，可以大大提高面板良率。
在本公开文本如图1所示的实施例中，通过栅极驱动信号输出端OUT为相邻下一级移位寄存器单元提供起始信号。
如图2所示，在图1所示的移位寄存器单元的实施例的基础上，本公开文本实施例所述的移位寄存器单元还可以包括：
第二电容单元17，连接于所述下拉节点PD与所述输入低电平VSS的低电平输入端之间。
本公开文本实施例所述的移位寄存器单元与现有技术的另一个区别在于，除了包含第一电容单元16之外还采用了另一个电容单元，即第二电容单元17，连接于所述下拉节点PD与所述低电平输入端之间；第二电容单元17用于维持下拉节点PD的电位。
在实际操作时，所述栅极驱动信号输出单元具体用于在所述上拉节点和所述下拉节点的控制下，控制所述栅极驱动信号输出端与所述第二时钟信号输入端或所述低电平输入端连接。
另外，所述移位寄存器单元还包括：
起始信号输出单元，分别与所述第二时钟信号输入端、所述上拉节点、 所述下拉节点、所述低电平输入端和起始信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下，控制所述起始信号输出端与所述第二时钟信号输入端或所述低电平输入端连接；以及，
第三电容单元，连接于所述上拉节点与所述起始信号输出端连接。
如图3A所示，在本公开文本如图2所示的移位寄存器单元的实施例的基础上，本公开文本另一实施例所述的移位寄存器单元还包括：
起始信号输出单元18，分别与所述输入第二时钟信号CK的第二时钟信号输入端、所述上拉节点PU、所述下拉节点PD、输入低电平VSS的低电平输入端和起始信号输出端STV_OUT连接，用于在所述上拉节点PU和所述下拉节点PD的控制下，控制所述起始信号输出端STV_OUT与所述第二时钟信号输入端和/或所述低电平输入端连接；以及，
第三电容单元19，连接于所述上拉节点PU与所述起始信号输出端STV_OUT连接。
在如图3A所示的移位寄存器单元的实施例中，增设了起始信号输出单元18，通过起始信号输出端STV_OUT为相邻下一级移位寄存器单元提供起始信号，增强了移位寄存器单元的驱动能力。所述第三电容单元19用于进一步维持上拉节点PU的电位。
根据另一种具体实施方式，在图3A所示的移位寄存器单元的实施例的基础上，如图3B所示，所述降噪控制端NC可以与所述下拉节点PD连接。
所述上拉节点降噪单元15包括：上拉节点降噪晶体管T12，栅极与所述降噪控制端NC连接，第一极与所述上拉节点PU连接，第二极与输入低电平VSS的低电平输入端连接。这里，所述上拉节点降噪晶体管T12可以为n型晶体管，但是并不以此为限。
在实际操作时，所述降噪控制端也可以与其他端子连接，所述降噪控制端只需能够输出相应的降噪控制信号，以在相应的时间段能够控制对上拉节点进行降噪即可。例如，所述降噪控制端也可以与第一时钟信号输入端连接。
在实际操作时，第一时钟信号的周期和第二时钟信号的周期可以都为T，第一时钟信号和第二时钟信号的占空比可以都为1/4，所述第二时钟信号比所述第一时钟信号延迟T/2，如图10所示。
在实际操作时，所述栅极驱动信号输出单元可以包括：
第一栅极驱动信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动信号输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述低电平输入端连接。
另外，所述起始信号输出单元可以包括：
第一起始信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述起始信号输出端连接；以及，
第二起始信号输出晶体管，栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述低电平输入端连接。
另外，所述第二电容单元可以包括：
第一输出电容，第一端与所述第二栅极驱动信号输出晶体管的栅极连接，第二端与所述低电平输入端连接；以及，
第二输出电容，第一端与所述第二起始信号输出晶体管的栅极连接，第二端与所述低电平输入端连接。
在具体实施时，如图5所示，在图3所示的移位寄存器单元的实施例的基础上，所述上拉节点控制单元12可以包括上拉控制节点(图4中未示出).所述上拉节点控制单元12还分别与输入高电平VDD的高电平输入端和输入低电平VSS的低电平输入端连接，用于当所述输入第一时钟信号CKB的第一时钟信号输入端输入高电平时控制所述上拉控制节点(图4中未示出)与所述输入低电平VSS的低电平输入端，当所述下拉节点PD的电位为高电平时控制所述上拉控制节点(图4中未示出)与所述输入低电平VSS的低电平输入端连接，并在所述输入高电平VDD的高电平输入端的控制下控制所述上拉控制节点(图4中未示出)与所述上拉节点PU连接。
根据一种具体实施方式，所述上拉节点控制单元可以包括：
第一上拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；
第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；以及，
第三上拉节点控制晶体管，栅极与所述高电平输入端连接，第一极与所述上拉节点连接，第二极与所述上拉控制节点连接。
如图5所示，在如图4所示的移位寄存器单元的基础上，所述上拉节点控制单元12可以包括：
第一上拉节点控制晶体管T3，栅极与所述输入第一时钟信号CKB的第一时钟信号输入端连接，漏极与所述上拉控制节点PUCN连接，源极与所述输入低电平VSS的低电平输入端连接；
第二上拉节点控制晶体管T4，栅极与所述下拉节点PD连接，漏极与所述上拉控制节点PUCN连接，源极与所述输入低电平VSS的低电平输入端连接；以及，
第三上拉节点控制晶体管T7，栅极与所述输入高电平VDD的高电平输入端连接，漏极与所述上拉节点PU连接，源极与所述上拉控制节点PUCN连接。
在图5所示的实施例中，以T3、T4和T7都为n型晶体管为例说明。
本公开文本如图5所示的移位寄存器单元的实施例在工作时，
当第一时钟信号CKB为高电平时，T3打开，以使得所述上拉控制节点PUCN接入低电平VSS；当第一时钟信号CKB为低电平时，T3关闭，以使得所述上拉控制节点PUCN不与所述输入低电平VSS的低电平输入端电导通连接；
当所述下拉节点PD的电位为高电平时，T4打开，以使得所述上拉控制节点PU接入低电平VSS；当所述下拉节点PD的电位为低电平时，T4关闭，以使得所述上拉控制节点PUCN不与所述输入低电平VSS的低电平输入端电导通连接；
由于T7的栅极接入高电平VDD，因此V7常开，使得上拉节点PU与上拉控制节点PUCN之间电导通连接。
在具体实施时，所述起始单元可以用于当所述起始端输入高电平时控制所述上拉节点的电位为高电平；
所述下拉节点控制单元可以包括下拉控制节点；所述下拉节点控制单元还与高电平输入端和所述低电平输入端连接，用于当所述上拉节点的电位为 高电平时控制所述下拉节点与所述低电平输入端连接，当所述起始端输入高电平时控制所述下拉节点与所述低电平输入端连接，当所述第一时钟信号输入端输入高电平时控制所述下拉控制节点的电位为高电平，并在所述高电平输入端的控制下控制所述下拉控制节点与所述下拉节点连接。
如图6所示，在如图3所示的移位寄存器单元的基础上，所述起始单元11用于当所述起始端STV输入高电平时控制所述上拉节点PU的电位为高电平。
如图7所示，所述下拉节点控制单元13可以包括下拉控制节点PDCN(图6中未示出)。所述下拉节点控制单元13还与所述输入高电平VDD的高电平输入端和所述输入低电平VSS的低电平输入端连接，用于当所述上拉节点PU的电位为高电平时控制所述下拉节点PD与所述输入低电平VSS的低电平输入端连接，当所述起始端STV输入高电平时控制所述下拉节点PD与所述输入低电平VSS的低电平输入端连接，当所述输入第一时钟信号CKB的第一时钟信号输入端输入高电平时控制所述下拉控制节点PDCN(图6中未示出)的电位为高电平，并在所述输入高电平VDD的高电平输入端的控制下控制所述下拉控制节点PDCN(图6中未示出)与所述下拉节点PD连接。
根据一种具体实施方式，所述下拉节点控制单元可以包括：
第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
第二下拉节点控制晶体管，栅极与所述起始端连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
第三下拉节点控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉控制节点连接；以及，
第四下拉节点控制晶体管，栅极与所述高电平输入端连接，第一极与所述下拉控制节点连接，第二极与所述下拉节点连接。
如图7所示，在如图6所示的移位寄存器单元的基础上，所述下拉节点控制单元13包括：
第一下拉节点控制晶体管T8，栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极与所述输入低电平VSS的低电平输入端连接；
第二下拉节点控制晶体管T6，栅极与所述起始端STV连接，漏极与所述下拉节点PD连接，源极与所述输入低电平VSS的低电平输入端连接；
第三下拉节点控制晶体管T10，栅极和漏极都与所述输入第一时钟信号CKB的第一时钟信号输入端连接，源极与所述下拉控制节点PDCN连接；以及，
第四下拉节点控制晶体管T11，栅极与所述输入高电平VDD的高电平输入端连接，漏极与所述下拉控制节点PDCN连接，源极与所述下拉节点PD连接。
在图7所示的实施例中，以T8、T6、T10和T11都为n型晶体管为例说明。
本公开文本如图7所示的移位寄存器单元的实施例在工作时，
当所述上拉节点PU的电位为高电平时，T8打开，以使得下拉节点PD接入VSS；当所述上拉节点PU的电位为低电平时，T8关闭，以断开下拉节点PD与低电平输入端之间的连接；
当所述起始端STV输入高电平时，T6打开，以使得下拉节点PD接入低电平VSS；当所述起始端STV输入低电平时，T6关闭，以断开下拉节点PD与低电平输入端之间的连接；
当所述第一时钟信号CKB为高电平时，T10打开，以使得第一时钟信号输入端与下拉控制节点PDCN连接，从而使得下拉控制节点PDCN的电位为高电平；当所述第一时钟信号CKB为低电平时，T10关闭，以断开第一时钟信号输入端与下拉控制节点PDCN之间的连接；
由于T11的栅极与高电平输入端连接，因此T11常开，使得下拉控制节点PDCN与下拉节点PD之间电导通连接。
如图8所示，在如图7所示的移位寄存器单元的基础上，本公开文本实施例所述的移位寄存器单元还包括：复位单元110，分别与复位端Reset和所述下拉控制节点PDCN连接，用于在所述复位端Reset的控制下控制所述下拉控制节点PDCN的电位。
在实际操作时，当需要控制下拉节点PD的电位为低电平时，可以通过复位端Reset控制复位单元110，控制所述下拉控制节点PDCN的电位来实现。
下面通过一具体实施例来说明本公开文本所述的移位寄存器单元。如图1至图9所示，本公开文本所述的移位寄存器单元的一具体实施例包括起始单元、上拉节点控制单元、下拉节点控制单元、栅极驱动信号输出单元、上拉节点降噪单元、第一电容单元、第二电容单元、起始信号输出单元、第三电容单元、复位单元、栅极驱动信号输出端OUT和起始信号输出端STV_OUT。
所述起始单元包括：起始晶体管T1，栅极和漏极都与起始端STV连接，源极与上拉控制节点PUCN连接。
降噪控制端包括下拉节点PD。
所述上拉节点降噪单元包括：上拉节点降噪晶体管T12，栅极与所述下拉节点PD连接，漏极与上拉节点PU连接，源极与输入低电平VSS的低电平输入端连接。
所述栅极驱动信号输出单元包括：
第一栅极驱动信号输出晶体管T13，栅极与所述上拉节点PU连接，漏极与输入第二时钟信号CK的第二时钟信号输入端连接，源极与所述栅极驱动信号输出端OUT连接；以及，
第二栅极驱动信号输出晶体管T14，栅极与所述下拉节点PD连接，漏极与所述栅极驱动信号输出端OUT连接，源极与输入低电平VSS的低电平输入端连接。
所述起始信号输出单元包括：
第一起始信号输出晶体管T15，栅极与所述上拉节点PU连接，漏极与所述输入第二时钟信号CK的第二时钟信号输入端连接，源极与所述起始信号输出端STV_OUT连接；以及，
第二起始信号输出晶体管T16，栅极与所述下拉节点PD连接，漏极与所述起始信号输出端STV_OUT连接，源极与所述输入低电平VSS的低电平输入端连接。
所述第一电容单元包括：存储电容C1，第一端与所述上拉节点PU连接，第二端与所述栅极驱动信号输出端OUT连接。
所述第二电容单元包括：
第一输出电容C3，第一端与所述第二栅极驱动信号输出晶体管T14的栅 极连接，第二端与所述输入低电平VSS的低电平输入端连接；以及，
第二输出电容C4，第一端与所述第二起始信号输出晶体管T16的栅极连接，第二端与所述输入低电平VSS的低电平输入端连接。
所述第三电容单元包括：起始电容C2，第一端与所述上拉节点PU连接，第二端与所述起始信号输出端STV_OUT连接。
所述上拉节点控制单元包括：
第一上拉节点控制晶体管T3，栅极与输入第一时钟信号CKB的第一时钟信号输入端连接，漏极与上拉控制节点PUCN连接，源极与所述输入低电平VSS的低电平输入端连接；
第二上拉节点控制晶体管T4，栅极与所述下拉节点PD连接，漏极与所述上拉控制节点PUCN连接，源极与所述输入低电平VSS的低电平输入端连接；以及，
第三上拉节点控制晶体管T7，栅极与输入高电平VDD的高电平输入端连接，漏极与所述上拉节点PU连接，源极与所述上拉控制节点PUCN连接。
所述下拉节点控制单元包括：
第一下拉节点控制晶体管T8，栅极与所述上拉控制节点PUCN连接，漏极与所述下拉节点PD连接，源极与输入低电平VSS的低电平输入端连接；
第二下拉节点控制晶体管T6，栅极与所述起始端STV连接，漏极与所述下拉节点PD连接，源极与输入低电平VSS的低电平输入端连接；
第三下拉节点控制晶体管T10，栅极和漏极都与所述输入第一时钟信号CKB的第一时钟信号输入端连接，源极与所述下拉控制节点PDCN连接；以及，
第四下拉节点控制晶体管T11，栅极与所述输入高电平VDD的高电平输入端连接，漏极与所述下拉控制节点PDCN连接，源极与所述下拉节点PD连接。
所述复位单元包括：复位晶体管T9，栅极和漏极都与复位端Reset连接，源极与下拉控制节点PDCN连接。
在如图9所示的具体实施例中，所有的晶体管都为NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)管，但是在实际 操作时，移位寄存器单元中采用的晶体管也可以为P型，在此不对晶体管的类型进行限定。
在图9所示的移位寄存器单元的具体实施例中，由复位端Reset输入复位信号，该复位信号在每一帧扫描开始前给出一定时间的高电平对移位寄存器单元进行复位，其余时间为低电平；T7和T11常开；VDD为直流高电平信号，VSS为直流低电平信号，STV_OUT为相邻下一级移位寄存器单元提供起始信号。
本公开文本如图9所示的移位寄存器单元的具体实施例由14个NMOS管和4个电容构成，可以有效降低噪声，从而提升显示器栅极驱动的性能及稳定性。本公开文本如图9所示的移位寄存器单元通过增加常开的NMOS管(也即T7和T11)作为单管传输门来降低信号通路的噪声及栅极驱动信号输出端的噪声，增强信号的无损传输。并且，本公开文本如图9所示的移位寄存器单元的具体实施例加入4个电容使得上拉节点PU的电压和下拉节点PD的电压更加稳定有效，确保栅极驱动信号的稳定有效输出。
如图10所示，本公开文本如图9所示的移位寄存器单元的具体实施例在工作时，在每一显示周期(也即每一帧显示时间)内，
在复位阶段S0，Reset输入高电平，STV输入低电平，CK和CKB都为低电平，T9打开，T11打开，从而PD与Reset连接，以使得PD的电位为高电平，T4打开，以使得PUCN接入VSS，T7打开，以使得PU与PUCN连接，PU也接入VSS，此时T14和T16都打开，OUT输出低电平，STV_OUT也输出低电平；并由于PD的电位为高电平，T12打开，以对PU进行降噪；
在第一阶段S1，Reset输入低电平，STV输入高电平，CK为低电平，CKB为低电平，T1打开，PUCN与STV连接，以使得PUCN的电位为高电平，T7打开，STV通过T7给C1和C2充电，以使得T13和T15逐渐打开，PU的电位被拉高为高电平，T6和T8打开，将PD的电位拉低为低电平，T13和T15都打开，T14和T16都关闭，OUT与第二时钟信号输入端连接，OUT和STV_OUT都输出低电平；
在第二阶段S2，Reset和STV都输入低电平，CK为高电平，CKB为低电平，由于C1和C2的自举作用，PU的电位进一步升高，T7打开，从而PUCN 的电位也为高电平，T8打开，从而将PD的电位拉低为低电平，T13和T15都打开，T14和T16都关闭，OUT与第二时钟信号输入端连接，OUT和STV_OUT都输出高电平；
在第三阶段S3，Reset和STV都输入低电平，CK和CKB都为低电平，由于CK变为低电平，PU的电位回到第一阶段S1的电位，但是PU的电位仍为高电平，PD的电位仍为低电平，T13和T15都打开，T14和T16都关闭，OUT与第二时钟信号输入端连接，OUT和STV_OUT都输出低电平；
在第四阶段S4，Reset和STV都输入低电平，CK为低电平，CKB为高电平，T3、T4、T10和T12都打开，PD的电位被拉高，PU的电位被拉低，对PU进行降噪；T13和T15都关闭，T14和T16都打开，OUT与低电平输入端连接，OUT和STV_OUT都输出低电平；
在所述第四阶段S4结束后，CK间隔为高电平、低电平，CKB间隔为低电平、高电平。当CKB为高电平时，T3打开，从而使得PUCN与输入VSS的低电平输入端连接，PUCN的电位为低电平，由于T7常开，因此PU的电位也为低电平；当CKB为高电平时，T10打开，从而PDCN与输入CKB的第一时钟信号输入端连接，PDCN的电位为高电平，由于T11常开，所以PD的电位为高电平，T12打开，以使得PU与输入VSS的低电平输入端连接，对PU进行降噪。
在第一阶段S1、第二阶段S2和第三阶段S3，PD的电位为低电平，T12断开，上拉节点降噪单元控制PU与输入低电平VSS的低电平输入端之间断开。
本公开文本如图9所示的移位寄存器单元的具体实施例增加了T12，在CKB为高电平时，T12作为单管传输门工作，以更好的拉低PU的电位以及栅极驱动信号输出端OUT输出的栅极驱动信号的电位，以对PU端和OUT端进行降噪，提高栅极驱动信号输出的稳定性。
在本公开文本如图9所示的移位寄存器单元的具体实施例中，C1、C2起到自举PU的电位的作用，C3、C4起到稳定PD的电位并降低PD的噪声的作用。
在本公开文本如图9所示的移位寄存器单元的具体实施例中，T12作为 单管传输门在工作过程中主要是用来传输高电平，在该具体实施例中，T12为NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)管，NMOS单管传输门会存在一定的阈值损失。因此为了减小阈值损失，可用PMOS(P-Metal-Oxide-Semiconductor，P型金属-氧化物-半导体)单管传输门来代替，或者为了消除阈值损失可以使用CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)传输门代替，在移位寄存器单元中这三种实施方案作用功能都是利用传输门的寄生电容对信号进行滤波整形保持。
在具体实施时，T12可以为PMOS管，此时T12的栅极与第三时钟信号输入端连接，第三时钟信号与第一时钟信号CKB反相。
当采用CMOS传输门来进行降噪时，由于CMOS传输门包括NMOS管和PMOS管，所以降噪控制端可以包括第一时钟信号输入端和第三时钟信号输入端；所述上拉节点降噪单元可以包括：第一上拉节点降噪晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述低电平输入端连接；以及，第二上拉节点降噪晶体管，栅极与所述第三时钟信号收入端连接，第一极与所述低电平输入端连接，第二极与所述上拉节点连接；所述第一上拉节点降噪晶体管为NMOS管，所述第二上拉节点降噪晶体管为PMOS管；由第一时钟信号输入端输入的第一时钟信号与由第三时钟信号输入端输入的第三时钟信号反相。
当采用CMOS传输门来进行降噪时，由于CMOS传输门包括NMOS管和PMOS管，所以降噪控制端可以包括下拉节点和第三时钟信号输入端；所述上拉节点降噪单元包括：第一上拉节点降噪晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述低电平输入端连接；以及，第二上拉节点降噪晶体管，栅极与所述第三时钟信号收入端连接，第一极与所述低电平输入端连接，第二极与所述上拉节点连接；所述第一上拉节点降噪晶体管为NMOS管，所述第二上拉节点降噪晶体管为PMOS管；由第一时钟信号输入端输入的第一时钟信号与由第三时钟信号输入端输入的第三时钟信号反相。
本公开文本实施例所述的移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：
在每一显示周期内，
在第一阶段，第一时钟信号输入端和第二时钟信号输入端都输入低电平，在起始端的控制下，起始单元控制上拉节点与所述起始端连接，从而通过所述起始端为第一电容单元充电，使得所述上拉节点的电位为高电平；在所述起始端和所述上拉节点的控制下，下拉节点控制单元控制使得下拉节点的电位为低电平；栅极驱动信号输出单元在所述上拉节点的控制下控制栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在降噪控制端的控制下，上拉节点降噪单元控制所述上拉节点与低电平输入端之间断开；
在第二阶段，所述第一时钟信号输入端输入低电平，所述第二时钟信号输入端输入高电平，第一电容单元自举拉升所述上拉节点的电位；在所述上拉节点的控制下，所述下拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出高电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
在第三阶段，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，由于所述第二时钟信号输入端变为输入低电平，由于所述第一电容单元的作用，使得所述上拉节点的电位跳变到所述上拉节点在第一阶段的电位，所述上拉节点的电位仍为高电平；在所述上拉节点的控制下，所述下拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
在第四阶段，所述第一时钟信号输入端输入高电平，所述第二时钟信号输入端输入低电平，在所述第一时钟信号输入端的控制下，所述上拉节点控制单元控制所述上拉节点的电位为低电平，所述下拉节点控制单元控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控 制下控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接；
在第四阶段结束后，所述第一时钟信号输入端间隔输入低电平、高电平，当所述第一时钟信号输入端输入高电平时，在该第一时钟信号输入端的控制下，所述上拉节点控制单元持续控制所述上拉节点的电位为低电平，所述下拉节点控制单元持续控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控制下持续控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接。
本公开文本实施例所述的移位寄存器单元的驱动方法采用了上拉节点降噪单元在降噪控制端的控制下在所述第四阶段和每一显示周期的第四阶段结束后的所有时刻或部分时刻对上拉节点进行降噪，从而使得本公开文本实施例所述的移位寄存器单元具有噪声低、稳定性好的优点，可以大大提高面板良率。
在本公开文本实施例所述的移位寄存器单元的驱动方法中，在每一显示周期的第一阶段、第二阶段和第三阶段，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与输入低电平的低电平输入端之间断开，以免不能使得上拉节点的电位为高电平。
具体的，当所述移位寄存器单元还包括复位单元时，每一显示周期在所述第一阶段之前还包括复位阶段；
相应的，本公开文本实施例所述的移位寄存器单元的驱动方法还包括：
在所述复位阶段，复位端输入高电平，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，在所述复位端的控制下，复位单元控制所述下拉节点与所述复位端连接，从而使得所述下拉节点的电位为高电平，所述上拉节点控制单元在所述下拉节点的控制下控制所述上拉节点的电位为低电平，所述栅极驱动信号输出端在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平，在所述降噪控制端的控制下，所述上拉节点降噪单元控 制所述上拉节点与所述低电平输入端连接，从而对所述上拉节点进行降噪。
具体的，由所述第一时钟信号输入端输入的第一时钟信号的周期和由所述第二时钟信号输入端输入的第二时钟信号的周期都为T，所述第一时钟信号和所述第二时钟信号的占空比都为1/4，所述第一时钟信号比所述第二时钟信号延迟T/2，如图10所示。
本公开文本实施例所述的栅极驱动电路，包括多个级联的上述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻上一级所述移位寄存器单元的栅极驱动信号输出端连接；或者，
本公开文本实施例所述的栅极驱动电路包括多个级联的上述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻所述上一级移位寄存器单元的起始信号输出端连接。
另外，本公开文本实施例所述的显示装置包括上述的栅极驱动电路。在本公开文本实施例中，该显示装置具体可以包括液晶显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种移位寄存器单元，包括：
    起始单元，分别与起始端和上拉节点连接；
    上拉节点控制单元，分别与所述上拉节点、第一时钟信号输入端和下拉节点连接；
    下拉节点控制单元，分别与所述第一时钟信号输入端、所述下拉节点、所述起始端和所述上拉节点连接；
    栅极驱动信号输出单元，分别与第二时钟信号输入端、所述上拉节点、所述下拉节点、低电平输入端和栅极驱动信号输出端连接；
    第一电容单元，连接于所述上拉节点和所述栅极驱动信号输出端之间；以及，
    上拉节点降噪单元，分别与降噪控制端、所述上拉节点和所述低电平输入端连接，用于在所述降噪控制端的控制下，控制所述上拉节点与所述低电平输入端之间连接或断开。
  2. 如权利要求1所述的移位寄存器单元，还包括：
    第二电容单元，连接于所述下拉节点和所述低电平输入端之间，用于控制维持下拉节点的电位。
  3. 如权利要求1或2所述的移位寄存器单元，其中，所述栅极驱动信号输出单元具体用于在所述上拉节点和所述下拉节点的控制下，控制所述栅极驱动信号输出端与所述第二时钟信号输入端或所述低电平输入端连接；
    所述移位寄存器单元还包括：
    起始信号输出单元，分别与所述第二时钟信号输入端、所述上拉节点、所述下拉节点、所述低电平输入端和起始信号输出端连接，用于在所述上拉节点和所述下拉节点的控制下，控制所述起始信号输出端与所述第二时钟信号输入端或所述低电平输入端连接；以及，
    第三电容单元，连接于所述上拉节点与所述起始信号输出端之间。
  4. 如权利要求1至3中任一项权利要求所述的移位寄存器单元，其中，所述降噪控制端与所述下拉节点连接；所述上拉节点降噪单元包括：上拉节 点降噪晶体管，其栅极与所述降噪控制端连接，第一极与所述上拉节点连接，第二极与所述低电平输入端连接。
  5. 如权利要求3所述的移位寄存器单元，其中，所述栅极驱动信号输出单元包括：
    第一栅极驱动信号输出晶体管，其栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
    第二栅极驱动信号输出晶体管，其栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述低电平输入端连接；
    所述起始信号输出单元包括：
    第一起始信号输出晶体管，其栅极与所述上拉节点连接，第一极与所述第二时钟信号输入端连接，第二极与所述起始信号输出端连接；以及，
    第二起始信号输出晶体管，其栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述低电平输入端连接；
    所述第二电容单元包括：
    第一输出电容，其第一端与所述第二栅极驱动信号输出晶体管的栅极连接，第二端与所述低电平输入端连接；以及，
    第二输出电容，其第一端与所述第二起始信号输出晶体管的栅极连接，第二端与所述低电平输入端连接。
  6. 如权利要求1至5中任一项权利要求所述的移位寄存器单元，其中，所述上拉节点控制单元包括上拉控制节点；所述上拉节点控制单元还分别与高电平输入端和所述低电平输入端连接，用于当所述第一时钟信号输入端输入高电平时控制所述上拉控制节点与所述低电平输入端连接，当所述下拉节点的电位为高电平时控制所述上拉控制节点与所述低电平输入端连接，并在所述高电平输入端的控制下控制所述上拉控制节点与所述上拉节点连接。
  7. 如权利要求6所述的移位寄存器单元，其中，所述上拉节点控制单元包括：
    第一上拉节点控制晶体管，其栅极与所述第一时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；
    第二上拉节点控制晶体管，其栅极与所述下拉节点连接，第一极与所述上拉控制节点连接，第二极与所述低电平输入端连接；以及，
    第三上拉节点控制晶体管，其栅极与所述高电平输入端连接，第一极与所述上拉节点连接，第二极与所述上拉控制节点连接。
  8. 如权利要求1至7中任一项权利要求所述的移位寄存器单元，其中，所述起始单元用于当所述起始端输入高电平时控制所述上拉节点的电位为高电平；
    所述下拉节点控制单元包括下拉控制节点；所述下拉节点控制单元还与高电平输入端和所述低电平输入端连接，用于当所述上拉节点的电位为高电平时控制所述下拉节点与所述低电平输入端连接，当所述起始端输入高电平时控制所述下拉节点与所述低电平输入端连接，当所述第一时钟信号输入端输入高电平时控制所述下拉控制节点的电位为高电平，并在所述高电平输入端的控制下控制所述下拉控制节点与所述下拉节点连接。
  9. 如权利要求8所述的移位寄存器单元，其中，所述下拉节点控制单元包括：
    第一下拉节点控制晶体管，栅极与所述上拉控制节点连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
    第二下拉节点控制晶体管，栅极与所述起始端连接，第一极与所述下拉节点连接，第二极与所述低电平输入端连接；
    第三下拉节点控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述下拉控制节点连接；以及，
    第四下拉节点控制晶体管，栅极与所述高电平输入端连接，第一极与所述下拉控制节点连接，第二极与所述下拉节点连接。
  10. 如权利要求8或9所述的移位寄存器单元，还包括：复位单元，分别与复位端和所述下拉控制节点连接，用于在所述复位端的控制下控制所述下拉控制节点的电位。
  11. 一种移位寄存器单元的驱动方法，应用于如权利要求1至10中任一项权利要求所述的移位寄存器单元，所述驱动方法包括：在每一显示周期内，
    在第一阶段，第一时钟信号输入端和第二时钟信号输入端都输入低电平， 在起始端的控制下，起始单元控制上拉节点与所述起始端连接，从而通过所述起始端为第一电容单元充电，使得所述上拉节点的电位为高电平；在所述起始端和所述上拉节点的控制下，下拉节点控制单元控制使得下拉节点的电位为低电平；栅极驱动信号输出单元在所述上拉节点的控制下控制栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在降噪控制端的控制下，上拉节点降噪单元控制所述上拉节点与低电平输入端之间断开；
    在第二阶段，所述第一时钟信号输入端输入低电平，所述第二时钟信号输入端输入高电平，所述第一电容单元自举拉升所述上拉节点的电位；在所述上拉节点的控制下，所述下拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出高电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
    在第三阶段，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，由于所述第二时钟信号输入端变为输入低电平，由于所述第一电容单元的作用，使得所述上拉节点的电位跳变到所述上拉节点在第一阶段的电位，所述上拉节点的电位仍为高电平；在所述上拉节点的控制下，所述下拉节点控制单元继续控制使得所述下拉节点的电位为低电平；所述栅极驱动信号输出单元在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平；在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端之间断开；
    在第四阶段，所述第一时钟信号输入端输入高电平，所述第二时钟信号输入端输入低电平，在所述第一时钟信号输入端的控制下，上拉节点控制单元控制所述上拉节点的电位为低电平，所述下拉节点控制单元控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控制下控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连 接；
    在第四阶段结束后，所述第一时钟信号输入端间隔输入低电平、高电平，当所述第一时钟信号输入端输入高电平时，在该第一时钟信号输入端的控制下，所述上拉节点控制单元持续控制所述上拉节点的电位为低电平，所述下拉节点控制单元持续控制所述下拉节点的电位为高电平，所述栅极驱动信号输出单元在所述下拉节点的控制下持续控制所述栅极驱动信号输出端与所述低电平输入端连接，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接。
  12. 如权利要求11所述的移位寄存器单元的驱动方法，其中，当所述移位寄存器单元还包括复位单元时，每一显示周期在所述第一阶段之前还包括复位阶段；
    所述驱动方法还包括：
    在所述复位阶段，复位端输入高电平，所述第一时钟信号输入端和所述第二时钟信号输入端都输入低电平，在所述复位端的控制下，所述复位单元控制所述下拉节点与所述复位端连接，从而使得所述下拉节点的电位为高电平，所述上拉节点控制单元在所述下拉节点的控制下控制所述上拉节点的电位为低电平，所述栅极驱动信号输出端在所述上拉节点的控制下控制所述栅极驱动信号输出端与所述第二时钟信号输入端连接，从而使得所述栅极驱动信号输出端输出低电平，在所述降噪控制端的控制下，所述上拉节点降噪单元控制所述上拉节点与所述低电平输入端连接。
  13. 如权利要求11或12所述的移位寄存器单元的驱动方法，其中，由所述第一时钟信号输入端输入的第一时钟信号的周期和由所述第二时钟信号输入端输入的第二时钟信号的周期都为T，所述第一时钟信号和所述第二时钟信号的占空比都为1/4，所述第一时钟信号比所述第二时钟信号延迟T/2。
  14. 一种栅极驱动电路，其中，所述栅极驱动电路包括多个级联的如权利要求1至10中任一项权利要求所述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻上一级所述移位寄存器单元的栅极驱动信号输出端连接；或者，
    所述栅极驱动电路包括多个级联的如权利要求3至10中任一项权利要求 所述的移位寄存器单元；除了第一级所述移位寄存器单元之外，每一级所述移位寄存器单元的起始端与相邻上一级所述移位寄存器单元的起始信号输出端连接。
  15. 一种显示装置，包括如权利要求14所述的栅极驱动电路。
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