CN106486075B - Goa电路 - Google Patents
Goa电路 Download PDFInfo
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- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
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- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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Abstract
本发明涉及一种GOA电路。该GOA电路包括级联的多个GOA电路单元,其中第n级GOA电路单元包括:第一薄膜晶体管(T1),第二薄膜晶体管(T2),第三薄膜晶体管(T3),第四薄膜晶体管(T4),第五薄膜晶体管(T5),第六薄膜晶体管(T6),第七薄膜晶体管(T7),第八薄膜晶体管(T8),第九薄膜晶体管(T9),第十薄膜晶体管(T10),第一电容(C1)及第二电容(C2)。本发明的GOA电路在现有的GOA电路基础上增加T9、T10,2个TFT,无需D2U和U2D控制信号的配合就可以实现正反向扫描功能,这对于更窄边框的设计起到一定的帮助作用;同时该GOA电路对应的驱动时序简单,可以降低IC成本。
Description
技术领域
本发明涉及液晶显示器领域,尤其涉及一种GOA电路。
背景技术
阵列基板行驱动(Gate Driver On Array,简称GOA)技术是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在阵列基板上,实现对栅极逐行扫描的驱动方式的一项技术。
在GOA电路设计都需要具有正反向扫描功能,而现在的普遍做法就是在GOA电路单元中增加U2D和D2U正反向扫描单元:正向扫描时,正向扫描控制信号U2D为高电平,反向扫描控制信号D2U为低电平;反向扫描时,反向扫描控制信号D2U为高电平,正向扫描控制信号U2D为低电平。而这种方式就需要芯片(IC)具有输出该信号的功能,对IC的可选择性有一定的限制,同时由于D2U和U2D的存在,在布局(Layout)设计时对更窄边框的设计也存在一定的限制作用,同时这种电路架构对应的IC成本相对较高。
参见图1,其为现有的GOA电路示意图,可用于LTPS面板。现有的GOA电路包括级联的多个GOA电路单元,其中输出第n级水平扫描信号的第n级GOA电路单元包括:薄膜晶体管T1,其栅极连接第n-2级GOA电路单元的信号输出点Gn-2,源极和漏极分别连接节点H和输入正向扫描控制信号U2D;薄膜晶体管T2,其栅极连接节点Q,源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV1;薄膜晶体管T3,其栅极连接第n+2级GOA电路单元的信号输出点Gn+2,源极和漏极分别连接节点H和输入反向扫描控制信号D2U;薄膜晶体管T4,其栅极连接节点P,源极和漏极分别连接信号输出点Gn和恒压低电位VGL;薄膜晶体管T5,其栅极连接恒压高电位VGH,源极和漏极分别连接节点H和节点Q;薄膜晶体管T6,其栅极连接节点P,源极和漏极分别连接节点H和恒压低电位VGL;薄膜晶体管T7,其栅极连接节点H,源极和漏极分别连接节点P和恒压低电位VGL;薄膜晶体管T8,其栅极输入时钟信号CKV3,源极和漏极分别连接节点P和恒压高电位VGH;电容C1,其两端分别连接节点Q和信号输出点Gn;电容C2,其两端分别连接节点P和恒压低电位VGL。节点Q为用于控制栅极驱动信号输出的点;节点P为用于维持Q点及Gn点低电平的稳定点。图1中虚线框部分即为GOA电路的正反向扫描单元。
参见图2,其为图1的GOA电路正向扫描时序示意图,现结合图1,对电路的具体工作过程(正向扫描)介绍如下:
正向扫描时:U2D为高电平,D2U为低电平;
阶段1,预充电:Gn-2与U2D同时为高电平,T1导通,H点被预充电。当H点为高电平时,T5处于导通状态,Q点被预充电。当H点为高电平时,T7处于导通状态,P点被拉低;
阶段2,Gn输出高电平:在阶段1中,Q点被预充电,C1对电荷具有一定的保持作用,T2处于导通状态,CKV1的高电平输出到Gn端;
阶段3,Gn输出低电平:C1对Q点的高电平具有保持作用,而此时CKV1的低电平将Gn点拉低;
阶段4,Q点拉低到VGL:当Gn+2为高电平,此时D2U为低电平,T3处于导通的状态,那么Q点被拉低到VGL;
阶段5,Q点及Gn点低电平维持阶段:当Q点变为低电平后,T7处于截止状态,当CKV3跳变为高电平时T8导通,P点被充电,那么T4和T6均处于导通的状态,可以保证Q点及Gn点低电平的稳定,同时C2对P点的高电平具有一定的保持作用。
参见图3,其为图1的GOA电路反向扫描时序示意图,现结合图1,对电路的具体工作过程(反向扫描)介绍如下:
反向扫描时:D2U为高电平,U2D为低电平;
阶段1,预充电:Gn+2与D2U同时为高电平,T3导通,H点被预充电。当H点为高电平时,T5处于导通状态,Q点被预充电。当H点为高电平时,T7处于导通状态,P点被拉低;
阶段2,Gn输出高电平:在阶段1中,Q点被预充电,C1对电荷具有一定的保持作用,T2处于导通状态,CKV1的高电平输出到Gn端;
阶段3,Gn输出低电平:C1对Q点的高电平具有保持作用,而此时CKV1的低电平将Gn点拉低;
阶段4,Q点拉低到VGL:当Gn-2为高电平时,此时U2D为低电平,T1处于导通的状态,那么Q点被拉低到VGL;
阶段5,Q点及Gn点低电平维持阶段:当Q点变为低电平后,T7处于截止状态,当CKV3跳变为高电平时T8导通,P点被充电,那么T4和T6均处于导通的状态,可以保证Q点及Gn点低电平的稳定,同时C2对P点的高电平具有一定的保持作用。
发明内容
本发明的目的在于提供一种GOA电路,实现正反向扫描功能而无需D2U和U2D控制信号的配合。
为实现上述目的,本发明提供了一种GOA电路,包括级联的多个GOA电路单元,其中第n级GOA电路单元包括:
第一薄膜晶体管,其栅极连接恒压高电位,第一源极/漏极连接第n-2级GOA电路单元的信号输出点,第二源极/漏极连接第九薄膜晶体管的第一源极/漏极;
第九薄膜晶体管,其栅极连接第n-2级GOA电路单元的信号输出点,第二源极/漏极连接第三节点;
第三薄膜晶体管,其栅极连接恒压高电位,第一源极/漏极连接第n+2级GOA电路单元的信号输出点,第二源极/漏极连接第十薄膜晶体管的第一源极/漏极;
第十薄膜晶体管,其栅极连接第n+2级GOA电路单元的信号输出点,第二源极/漏极连接第三节点;
第七薄膜晶体管,其栅极连接第三节点,源极和漏极分别连接第二节点和恒压低电位;
第六薄膜晶体管,其栅极连接第二节点,源极和漏极分别连接第三节点和恒压低电位;
第五薄膜晶体管,其栅极连接恒压高电位,源极和漏极分别连接第三节点和第一节点;
第八薄膜晶体管,其栅极输入第二时钟信号,源极和漏极分别连接第二节点和恒压高电位;
第二薄膜晶体管,其栅极连接第一节点,源极和漏极分别连接第n级GOA电路单元的信号输出点和输入第一时钟信号;
第一电容,其两端分别连接第一节点和第n级GOA电路单元的信号输出点;
第四薄膜晶体管,其栅极连接第二节点,源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位;
第二电容,其两端分别连接第二节点和恒压低电位。
其中,该第一时钟信号和第二时钟信号为占空比为0.25的矩形波,该第一时钟信号和第二时钟信号的相位相差二分之一周期。
其中,对于第1级GOA电路单元,正向扫描开始时,该第n-2级GOA电路单元的信号输出点输入高电平信号作为启动信号。
其中,对于第2级GOA电路单元,正向扫描开始时,该第n-2级GOA电路单元的信号输出点输入高电平信号作为启动信号。
其中,对于倒数第1级GOA电路单元,反向扫描开始时,该第n+2级GOA电路单元的信号输出点输入高电平信号作为启动信号。
其中,对于倒数第2级GOA电路单元,反向扫描开始时,该第n+2级GOA电路单元的信号输出点输入高电平信号作为启动信号。
其中,其为LTPS面板的GOA电路。
其中,其为OLED面板的GOA电路。
综上,本发明的GOA电路无需D2U和U2D控制信号的配合就可以实现正反向扫描功能,这对于更窄边框的设计起到一定的帮助作用;同时该GOA电路对应的驱动时序简单,可以降低IC成本。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为现有的GOA电路示意图;
图2为图1的GOA电路正向扫描时序示意图;
图3为图1的GOA电路反向扫描时序示意图;
图4为本发明的GOA电路示意图;
图5为图4的GOA电路正向扫描时序示意图;
图6为图4的GOA电路反向扫描时序示意图。
具体实施方式
参见图4,其为本发明的GOA电路示意图,可用于LTPS面板。该GOA电路包括级联的多个GOA电路单元,其中输出第n级水平扫描信号的第n级GOA电路单元包括:薄膜晶体管T1,其栅极连接恒压高电位VGH,第一源极/漏极连接第n-2级GOA电路单元的信号输出点Gn-2,第二源极/漏极连接薄膜晶体管T9的第一源极/漏极;薄膜晶体管T2,其栅极连接节点Q,源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV1;薄膜晶体管T3,其栅极连接恒压高电位VGH,第一源极/漏极连接第n+2级GOA电路单元的信号输出点Gn+2,第二源极/漏极连接薄膜晶体管T10的第一源极/漏极;薄膜晶体管T4,其栅极连接节点P,源极和漏极分别连接信号输出点Gn和恒压低电位VGL;薄膜晶体管T5,其栅极连接恒压高电位VGH,源极和漏极分别连接节点H和节点Q;薄膜晶体管T6,其栅极连接节点P,源极和漏极分别连接节点H和恒压低电位VGL;薄膜晶体管T7,其栅极连接节点H,源极和漏极分别连接节点P和恒压低电位VGL;薄膜晶体管T8,其栅极输入时钟信号CKV3,源极和漏极分别连接节点P和恒压高电位VGH;薄膜晶体管T9,其栅极连接第n-2级GOA电路单元的信号输出点Gn-2,第二源极/漏极连接节点H;薄膜晶体管T10,其栅极连接第n+2级GOA电路单元的信号输出点Gn+2,第二源极/漏极连接节点H;电容C1,其两端分别连接节点Q和信号输出点Gn;电容C2,其两端分别连接节点P和恒压低电位VGL。
参见图5,其为图4的GOA电路正向扫描时序示意图。现结合图4,对电路的具体工作过程(正向扫描)介绍如下:
阶段1,预充电:Gn-2为高电平,T1、T9均导通,H点被预充电。当H点为高电平时,T5处于导通状态,Q点被预充电。当H点为高电平时,T7处于导通状态,P点被拉低;
阶段2,Gn输出高电平:在阶段1中,Q点被预充电,C1对电荷具有一定的保持作用,T2处于导通状态,CKV1的高电平输出到Gn端;
阶段3,Gn输出低电平:C1对Q点的高电平具有保持作用,而此时CKV1的低电平将Gn点拉低;
阶段4,Q点拉低到VGL:当CKV3为高电平时,T8导通,P点被充电,T6导通,Q点被拉低;
阶段5,Q点及Gn点低电平维持阶段:当Q点变为低电平后,T7处于截止状态,当CKV3跳变为高电平时T8导通,P点被充电,那么T4和T6均处于导通的状态,可以保证Q点及Gn点低电平的稳定,同时C2对P点的高电平具有一定的保持作用。
同时,该电路对应的充电单元具有降低Q点漏电功能。具体说明在低电平维持阶段,由于T1与T3栅极接VGH,均处于打开的状态,此时Gn-2与Gn+2均为低电平,Vds=0V。那么T9与T10均处于Vds=0V状态,那么一定程度上可以降低Q点漏电的发生。
参见图6,其为图4的GOA电路反向扫描时序示意图。现结合图4,对电路的具体工作过程(反向扫描)介绍如下:
阶段1,预充电:Gn+2为高电平,T3、T10均导通,H点被预充电。当H点为高电平时,T5处于导通状态,Q点被预充电。当H点为高电平时,T7处于导通状态,P点被拉低;
阶段2,Gn输出高电平:在阶段1中,Q点被预充电,C1对电荷具有一定的保持作用,T2处于导通状态,CKV1的高电平输出到Gn端;
阶段3,Gn输出低电平:C1对Q点的高电平具有保持作用,而此时CKV1的低电平将Gn点拉低;
阶段4,Q点拉低到VGL:当CKV3为高电平时,T8导通,P点被充电,T6导通,Q点被拉低;
阶段5,Q点及Gn点低电平维持阶段:当Q点变为低电平后,T7处于截止状态,当CKV3跳变为高电平时T8导通,P点被充电,那么T4和T6均处于导通的状态,可以保证Q点及Gn点低电平的稳定,同时C2对P点的高电平具有一定的保持作用。
同时,该电路对应的充电单元具有降低Q点漏电功能。具体说明在低电平维持阶段,由于T3与T1栅极接VGH,均处于打开的状态,此时Gn+2与Gn-2均为低电平,Vds=0V。那么T9与T10均处于Vds=0V状态,那么一定程度上可以降低Q点漏电的发生。
由图5和图6可见,时钟信号CKV1和时钟信号CKV3为占空比为0.25的矩形波,时钟信号CKV1和时钟信号CKV3的相位相差二分之一周期。
对于初始的第1级和第2级GOA电路单元,正向扫描开始时,在该第n-2级GOA电路单元的信号输出点Gn-2输入高电平信号作为启动信号。
对于倒数第1级和倒数第2级GOA电路单元,反向扫描开始时,该第n+2级GOA电路单元的信号输出点Gn+2输入高电平信号作为启动信号。
本发明提出了一种新的基于LTPS的GOA电路设计方法,详见图4,图5和图6:如图4虚线框部分所示,在现有的GOA电路基础上增加T9、T102个TFT,此时该GOA电路在无需D2U和U2D控制信号的配合就可以实现正反向扫描功能,这对于更窄边框的设计起到一定的帮助作用。同时该GOA电路对应的驱动时序简单,可以降低IC成本。
本发明的GOA电路已知和潜在的技术/产品应用领域及其应用方式如下:1、集成在阵列基板上的液晶显示器行扫描(Gate)驱动电路;2、应用于手机,显示器,电视的栅极驱动领域;3、可涵盖LCD和OLED的行业先进技术;4、本电路的稳定性适用于高解析度的面板设计当中。
综上,本发明的GOA电路无需D2U和U2D控制信号的配合就可以实现正反向扫描功能,这对于更窄边框的设计起到一定的帮助作用;同时该GOA电路对应的驱动时序简单,可以降低IC成本。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (8)
1.一种GOA电路,包括级联的多个GOA电路单元,其中第n级GOA电路单元包括:第一薄膜晶体管(T1)、第九薄膜晶体管(T9)、第三薄膜晶体管(T3)、第十薄膜晶体管(T10)、第七薄膜晶体管(T7)、第六薄膜晶体管(T6)、第五薄膜晶体管(T5)、第八薄膜晶体管(T8)、第二薄膜晶体管(T2)、第一电容(C1)、第四薄膜晶体管(T4)、第二电容(C2);
其特征在于,所述第一薄膜晶体管(T1),其栅极连接恒压高电位(VGH),第一源极/漏极连接第n-2级GOA电路单元的信号输出点(Gn-2),第二源极/漏极连接第九薄膜晶体管(T9)的第一源极/漏极;
所述第九薄膜晶体管(T9),其栅极连接第n-2级GOA电路单元的信号输出点(Gn-2),第二源极/漏极连接第三节点(H);
所述第三薄膜晶体管(T3),其栅极连接恒压高电位(VGH),第一源极/漏极连接第n+2级GOA电路单元的信号输出点(Gn+2),第二源极/漏极连接第十薄膜晶体管(T10)的第一源极/漏极;
所述第十薄膜晶体管(T10),其栅极连接第n+2级GOA电路单元的信号输出点(Gn+2),第二源极/漏极连接第三节点(H);
所述第七薄膜晶体管(T7),其栅极连接第三节点(H),源极和漏极分别连接第二节点(P)和恒压低电位(VGL);
所述第六薄膜晶体管(T6),其栅极连接第二节点(P),源极和漏极分别连接第三节点(H)和恒压低电位(VGL);
所述第五薄膜晶体管(T5),其栅极连接恒压高电位(VGH),源极和漏极分别连接第三节点(H)和第一节点(Q);
所述第八薄膜晶体管(T8),其栅极输入第二时钟信号(CKV3),源极和漏极分别连接第二节点(P)和恒压高电位(VGH);
所述第二薄膜晶体管(T2),其栅极连接第一节点(Q),源极和漏极分别连接第n级GOA电路单元的信号输出点(Gn)和输入第一时钟信号(CKV1);
所述第一电容(C1),其两端分别连接第一节点(Q)和第n级GOA电路单元的信号输出点(Gn);
所述第四薄膜晶体管(T4),其栅极连接第二节点(P),源极和漏极分别连接第n级GOA电路单元的信号输出点(Gn)和恒压低电位(VGL);
所述第二电容(C2),其两端分别连接第二节点(P)和恒压低电位(VGL)。
2.如权利要求1所述的GOA电路,其特征在于,该第一时钟信号(CKV1)和第二时钟信号(CKV3)为占空比为0.25的矩形波,该第一时钟信号(CKV1)和第二时钟信号(CKV3)的相位相差二分之一周期。
3.如权利要求1所述的GOA电路,其特征在于,对于第1级GOA电路单元,正向扫描开始时,该第n-2级GOA电路单元的信号输出点(Gn-2)输入高电平信号作为启动信号。
4.如权利要求1所述的GOA电路,其特征在于,对于第2级GOA电路单元,正向扫描开始时,该第n-2级GOA电路单元的信号输出点(Gn-2)输入高电平信号作为启动信号。
5.如权利要求1所述的GOA电路,其特征在于,对于倒数第1级GOA电路单元,反向扫描开始时,该第n+2级GOA电路单元的信号输出点(Gn+2)输入高电平信号作为启动信号。
6.如权利要求1所述的GOA电路,其特征在于,对于倒数第2级GOA电路单元,反向扫描开始时,该第n+2级GOA电路单元的信号输出点(Gn+2)输入高电平信号作为启动信号。
7.如权利要求1所述的GOA电路,其特征在于,其为LTPS面板的GOA电路。
8.如权利要求1所述的GOA电路,其特征在于,其为OLED面板的GOA电路。
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