WO2017156850A1 - 移位寄存器及驱动方法、驱动电路、阵列基板及显示装置 - Google Patents

移位寄存器及驱动方法、驱动电路、阵列基板及显示装置 Download PDF

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Publication number
WO2017156850A1
WO2017156850A1 PCT/CN2016/081645 CN2016081645W WO2017156850A1 WO 2017156850 A1 WO2017156850 A1 WO 2017156850A1 CN 2016081645 W CN2016081645 W CN 2016081645W WO 2017156850 A1 WO2017156850 A1 WO 2017156850A1
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Prior art keywords
pull
module
control
control module
turned
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PCT/CN2016/081645
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English (en)
French (fr)
Inventor
孙拓
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京东方科技集团股份有限公司
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Priority to US15/528,030 priority Critical patent/US10403210B2/en
Publication of WO2017156850A1 publication Critical patent/WO2017156850A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to display technologies, and more particularly to a shift register and a driving method, a gate driving circuit, an array substrate, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • AMLCD active matrix liquid crystal display
  • FIG. 1 is a schematic circuit diagram of a shift register of an AMOLED in the prior art.
  • the scan line shift register commonly used in the prior art includes 7 transistors and 2 capacitors (7T2C), which are complicated in structure and require many signals for operation.
  • Embodiments of the present invention provide a shift register and a driving method, a gate driving circuit, an array substrate, and a display device.
  • the circuit structure is simplified and can be applied to a narrow bezel or an ultra-high resolution screen.
  • a shift register comprising: a pull-up control module, a pull-up module, a pull-down control module, a pull-down module, and an output.
  • the pull-up control module is connected to the pull-up module, and the pull-up control module is configured to control the pull-up of the pull-up module for the level of the output.
  • the pull-up module is connected to the output, and the pull-up module is configured to perform the level on the output.
  • Pull The pull-down control module is connected to the pull-down module, and the pull-down control module is configured to control the pull-down of the pull-down module to the level of the output.
  • the pull-down module is connected to the output, and the pull-down module is configured to pull down the level of the output.
  • the pull up control module includes a control end, a first end, and a second end.
  • the pull-up module includes a control end, a first end, and a second end.
  • the pull-down control module includes a control end, a first end, and a second end.
  • the pull-down module includes a control end, a first end, and a second end.
  • the control end of the pull-up control module is connected to the clock signal end, the first end is connected to the first input end, and the second end is connected to the control end of the pull-up module.
  • the first end of the pull-up module is connected to the first voltage end, and the second end is connected to the output end.
  • the control end of the pull-down control module is connected to the second end of the pull-up control module, the first end is connected to the second input end, and the second end is connected to the control end of the pull-down module.
  • the first end of the pull-down module is connected to the second voltage end, and the second end is connected to the output end.
  • the second voltage terminal is coupled to the clock signal terminal.
  • the pull up control module includes a first transistor.
  • the control end of the first transistor is a control end of the pull-up control module
  • the first end of the first transistor is a first end of the pull-up control module
  • the second end of the first transistor is a second end of the pull-up control module.
  • the pull up module includes a second transistor and a first capacitor.
  • the control end of the second transistor is connected to the control terminal of the pull-up module, the first end of the second transistor is the first end of the pull-up module, and the second end of the second transistor is the second end of the pull-up module.
  • the first capacitor is coupled between the control terminal of the second transistor and the first terminal.
  • the pull down control module includes a third transistor.
  • the control end of the third transistor is a control terminal of the pull-down control module
  • the first end of the third transistor is a first end of the pull-down control module
  • the second end of the third transistor is a second end of the pull-down control module.
  • the pull down module includes a fourth transistor and a second capacitor.
  • the control end of the fourth transistor is the control end of the pull-down module
  • the first end of the fourth transistor is the first end of the pull-down module
  • the second end of the fourth transistor is the second end of the pull-down module.
  • the second capacitor is coupled between the control terminal and the second terminal of the fourth transistor.
  • a gate driving circuit comprising a plurality of cascaded shift registers, the output of the shift register being configured to provide a corresponding pixel circuit For the gate drive signal.
  • the pull-up control module and the output end of the shift register of the first stage are connected to the shift register of the next stage.
  • the pull up control module includes a control end, a first end, and a second end.
  • the pull-up module includes a control end, a first end, and a second end.
  • the pull-down control module includes a control end, a first end, and a second end.
  • the pull-down module includes a control end, a first end, and a second end.
  • the control end of the pull-up control module is connected to the clock signal end, the first end is connected to the first input end, and the second end is connected to the control end of the pull-up module.
  • the first end of the pull-up module is connected to the first voltage end, and the second end is connected to the output end.
  • the control end of the pull-down control module is connected to the second end of the pull-up control module, the first end is connected to the second input end, and the second end is connected to the control end of the pull-down module.
  • the first end of the pull-down module is connected to the second voltage end, and the second end is connected to the output end.
  • the second end of the pull-up control module of the one-stage shift register is connected to the first input end of the shift register of the next stage, the output end of the shift register of one stage and the shift register of the next stage The second input is connected.
  • an array substrate comprising the above-described gate drive circuit.
  • a display device comprising the above array substrate.
  • a method for driving a shift register for driving the shift register includes: a first stage, wherein the pull-up control module is turned on, the pull-up module is turned on, and the pull-down control module is Turn on, the pull-down module is cut off. The output outputs a high level.
  • the pull-up control module is turned off, the pull-up module is turned on, the pull-down control module is turned on, and the pull-down module is turned off.
  • the output outputs a high level.
  • the pull-up control module is turned off, the pull-up module is turned on, the pull-down control module is turned on, and the pull-down module is turned on.
  • the output outputs a high level.
  • the pull-up control module is turned on, the pull-up module is turned off, the pull-down control module is turned off, and the pull-down module is turned on.
  • the output outputs a low level.
  • the pull-up control module is turned off, the pull-up module is turned off, the pull-down control module is turned off, and the pull-down module is turned on.
  • the output outputs a high level.
  • the pull-up control module is turned off, the pull-up module is turned off, the pull-down control module is turned off, and the pull-down module is turned on. The output outputs a high level.
  • the pull up control module includes a control end, a first end, and a second end.
  • the pull-up module includes a control end, a first end, and a second end.
  • the pull-down control module includes a control end, first End and second end.
  • the pull-down module includes a control end, a first end, and a second end.
  • the control end of the pull-up control module is connected to the clock signal end, the first end is connected to the first input end, and the second end is connected to the control end of the pull-up module.
  • the first end of the pull-up module is connected to the first voltage end, and the second end is connected to the output end.
  • the control end of the pull-down control module is connected to the second end of the pull-up control module, the first end is connected to the second input end, and the second end is connected to the control end of the pull-down module.
  • the first end of the pull-down module is connected to the second voltage end, and the second end is connected to the output end.
  • the signal at the first input is valid, the signal at the second input is inactive, the signal at the clock signal is active, the first voltage terminal is high, and the second voltage terminal is low.
  • the signal at the first input is valid, the signal at the second input is inactive, the signal at the clock signal is inactive, the first voltage terminal is high, and the second voltage terminal is high.
  • the signal at the first input is invalid, the signal at the second input is valid, the signal at the clock signal is invalid, the first voltage terminal is high, and the second voltage terminal is high.
  • the signal at the first input is invalid, the signal at the second input is invalid, the signal at the clock signal is valid, the first voltage terminal is high, and the second voltage terminal is low.
  • the signal at the first input is invalid, the signal at the second input is invalid, the signal at the clock signal is invalid, the first voltage terminal is high, and the second voltage terminal is high.
  • the signal of the first input terminal is valid, the signal of the second input terminal is invalid, the signal of the clock signal end is invalid, the first voltage terminal is a high level, and the second voltage terminal is a high level.
  • the shift register and the driving method, the gate driving circuit, the array substrate, and the display device according to the embodiments of the present invention simplify the circuit structure, and can realize a narrow bezel or an ultra-high resolution screen.
  • FIG. 1 is a schematic circuit diagram of a shift register of an AMOLED in the prior art
  • Figure 2 is a block diagram of a shift register in accordance with a first embodiment of the present invention
  • Figure 3 is a schematic circuit diagram of the shift register shown in Figure 2;
  • FIG. 4 is a timing chart of the shift register shown in FIG. 3;
  • Figure 5 is a schematic structural view of a gate driving circuit according to a second embodiment of the present invention.
  • Fig. 6 is a timing chart of the gate driving circuit shown in Fig. 5.
  • the shift register 10 includes a pull-up control module 1, a pull-up module 2, a pull-down control module 3, a pull-down module 4, and an output terminal OP.
  • the pull-up control module 1 is connected to the pull-up module 2, and the pull-up control module 1 is configured to control the pull-up of the level of the pull-up module 2 for the output OP.
  • the pull-up module 2 is connected to the output OP, and the pull-up module 2 is configured to pull up the level of the output OP.
  • the pull-down control module 3 is connected to the pull-down module 4, which is configured to control the pull-down of the level of the pull-down module 4 for the output OP.
  • the pull-down module 4 is connected to the output OP, which is configured to pull down the level of the output OP.
  • the shift register is implemented by using the pull-up control module 1, the pull-up module 2, the pull-down control module 3, the pull-down module 4, and the output terminal OP, which simplifies the circuit structure.
  • FIG. 3 is a schematic circuit diagram of the shift register shown in FIG.
  • the pull-up control module 1 includes a control end, a first end, and a second end.
  • the pull-up control module 1 includes a first transistor T1.
  • the control terminal of the first transistor T1 is the control terminal of the pull-up control module 1.
  • the first terminal of the first transistor T1 is the first end of the pull-up control module 1, and the second terminal of the first transistor T1 is the pull-up control module 1.
  • the pull-up module 2 includes a control end, a first end, and a second end. Specifically, the pull-up module 2 includes a second transistor T2 and a first capacitor C1.
  • the control terminal of the second transistor T2 is the control terminal of the pull-up module 2
  • the first terminal of the second transistor T2 is the first terminal of the pull-up module 2
  • the second transistor T2 The second end of the pull-up module 2 is the second end.
  • the first capacitor C1 is connected between the control terminal of the second transistor T2 and the first terminal.
  • the pull-down control module 3 includes a control end, a first end, and a second end. Specifically, the pull-down control module 3 includes a third transistor T3. The control end of the third transistor T3 is the control end of the pull-down control module 3, the first end of the third transistor T3 is the first end of the pull-down control module 3, and the second end of the third transistor T3 is the second end of the pull-down control module 3. end.
  • the pull-down module 4 includes a control end, a first end, and a second end. Specifically, the pull-down module 4 includes a fourth transistor T4 and a second capacitor C2.
  • the control terminal of the fourth transistor T4 is the control terminal of the pull-down module 4
  • the first terminal of the fourth transistor T4 is the first terminal of the pull-down module 4
  • the second terminal of the fourth transistor T4 is the second terminal of the pull-down module 4.
  • the second capacitor C2 is connected between the control terminal and the second terminal of the fourth transistor T4.
  • control terminal of the pull-up control module 1 is connected to the clock signal terminal CK, the first terminal is connected to the first input terminal STV1, and the second terminal is connected to the control terminal of the pull-up module 2.
  • the first end of the pull-up module 2 is connected to the first voltage terminal VGH, and the second end is connected to the output terminal OP.
  • the control end of the pull-down control module 3 is connected to the second end of the pull-up control module 1, the first end is connected to the second input terminal STV2, and the second end is connected to the control end of the pull-down module 4.
  • the first end of the pull-down module 4 is connected to the second voltage terminal VGL, and the second end is connected to the output terminal OP.
  • the pull-up control module 1, the pull-up module 2, the pull-down control module 3, and the pull-down module 4 are implemented using transistors, so that the circuit structure is simplified.
  • the driving method of the shift register comprises:
  • the signal of the first input terminal STV1 is valid
  • the signal of the second input terminal STV2 is invalid
  • the signal of the clock signal terminal CK is valid
  • the first voltage terminal VGH is a high level
  • the second voltage terminal VGL is a low level.
  • the pull-up control module 1 is turned on
  • the pull-up module 2 is turned on
  • the pull-down control module 3 is turned on
  • the pull-down module 4 is turned off.
  • the voltage of the first node A is valid
  • the voltage of the second node B is invalid.
  • the output OP outputs a high level.
  • the first node A is a connection point of the second end of the pull-up control module 1 and the control end of the pull-up module 2
  • the second node B is a connection of the second end of the pull-down control module 3 and the control end of the pull-down module 4. point.
  • the signal of the first input terminal STV1 is valid
  • the signal of the second input terminal STV2 is invalid
  • the signal of the clock signal terminal CK is invalid
  • the first voltage terminal VGH is high level
  • the second voltage terminal VGL is high level.
  • the pull-up control module 1 is turned off
  • the pull-up module 2 is turned on
  • the pull-down control module 3 is turned on
  • the pull-down module 4 is turned off.
  • the voltage of the first node A is valid
  • the voltage of the second node B is invalid.
  • the output OP outputs a high level.
  • the signal of the first input terminal STV1 is invalid
  • the signal of the second input terminal STV2 is valid
  • the signal of the clock signal terminal CK is invalid
  • the first voltage terminal VGH is high level
  • the second voltage terminal VGL is high level.
  • the pull-up control module 1 is turned off, the pull-up module 2 is turned on, the pull-down control module 3 is turned on, and the pull-down module 4 is turned on.
  • the voltage of the first node A is valid, and the voltage of the second node B is valid.
  • the output OP outputs a high level.
  • the second voltage terminal VGL is made high level, and the output terminal OP outputs a high level.
  • the signal of the first input terminal STV1 is invalid
  • the signal of the second input terminal STV2 is invalid
  • the signal of the clock signal terminal CK is valid
  • the first voltage terminal VGH is a high level
  • the second voltage terminal VGL is a low level.
  • the pull-up control module 1 is turned on
  • the pull-up module 2 is turned off
  • the pull-down control module 3 is turned off
  • the pull-down module 4 is turned on.
  • the voltage of the first node A is invalid
  • the voltage of the second node B is valid.
  • the output OP outputs a low level.
  • the pull-down module 4 has been fully turned on, and, in the case of including the second capacitor C2, due to the bootstrap action of the second capacitor C2, the second node B is the absolute voltage of the control terminal of the pull-down module 4.
  • the value is much larger than the absolute value of the turn-on threshold voltage of the pull-down module 4, and the conduction state of the pull-down module 4 can be well ensured. Therefore, in the embodiment of the present invention, in the fourth stage, the second voltage terminal VGL is made low level, and the output terminal OP outputs low level.
  • the signal of the first input terminal STV1 is invalid
  • the signal of the second input terminal STV2 is invalid
  • the signal of the clock signal terminal CK is invalid
  • the first voltage terminal VGH is a high level
  • the second voltage terminal VGL is a high level.
  • the pull-up control module 1 is turned off
  • the pull-up module 2 is turned off
  • the pull-down control module 3 is turned off
  • the pull-down module 4 is turned on.
  • the voltage of the first node A is invalid
  • the voltage of B is valid.
  • the output OP outputs a high level.
  • the signal of the first input terminal STV1 is valid
  • the signal of the second input terminal STV2 is invalid
  • the signal of the clock signal terminal CK is invalid
  • the first voltage terminal VGH is high level
  • the second voltage terminal VGL is high level.
  • the pull-up control module 1 is turned off
  • the pull-up module 2 is turned off
  • the pull-down control module 3 is turned off
  • the pull-down module 4 is turned on.
  • the voltage of the first node A is invalid
  • the voltage of the second node B is valid.
  • the output OP outputs a high level.
  • the output terminal OP outputs a low-level pulse signal, but this is not a limitation of the present invention.
  • the shift register provided according to an embodiment of the present invention can provide a different signal to the pixel circuit without changing the circuit configuration.
  • the signal/voltage "valid” means that when the signal/voltage is applied to the control terminal of the corresponding module in the shift register, the module can be turned on, and the signal/voltage "invalid” means the signal/voltage. When applied to the control terminal of the corresponding module in the shift register, the module can be turned off.
  • the transistor in the module of the shift register is a P-type transistor as an example.
  • the effective signal/voltage is a low-level signal.
  • the invalid signal/voltage is a high level signal/voltage, but this is not a limitation of the present invention.
  • the transistor in the module of the shift register may also be an N-type transistor.
  • the effective signal/voltage is a high level signal/voltage
  • the invalid signal/voltage is a low level signal/voltage. Therefore, according to the shift register provided by the embodiment of the present invention, different types of transistors can be used without changing the circuit configuration.
  • the second voltage terminal VGL since the state of the second voltage terminal VGL is the same as the clock signal terminal CK, the second voltage terminal VGL can be connected to the clock signal terminal CK. This further simplifies the circuit structure.
  • Fig. 5 is a schematic structural view of a gate driving circuit according to a second embodiment of the present invention.
  • the gate drive circuit includes a plurality of cascaded shift registers 10 as described above, and the output OP of the shift register 10 is configured to provide a gate drive signal to the corresponding pixel circuit. Among them, level one
  • the pull-up control module 1 and the output OP of the shift register 10 are connected to the shift register 10 of the next stage.
  • the first node A of the shift register 10 of the first stage is connected to the first input terminal STV1 of the shift register of the next stage, and the output OP of the shift register 10 of the first stage is shifted with the next stage.
  • the second input terminal STV2 of the register 10 is connected.
  • Fig. 6 is a timing chart of the gate driving circuit shown in Fig. 5.
  • three clock signals are respectively applied to the clock signal terminals CK1, CK2, and CK3 of three cascaded shift registers 10 (represented by G1, G2, and G3).
  • the signal waveforms of the three clock signals are the same. It differs by 1/3 clock cycle in timing.
  • the required clock signals are identical to the clock signals received by CK1, CK2, and CK3.
  • three clock signals can satisfy the needs of all shift registers in the gate drive circuit.
  • the three clock signals can come from the same clock source, and different timings are obtained through the delay circuit. It can be understood that the number of clock sources can also be greater than one in order to avoid excessive clock source load.
  • an array substrate is also provided, including the gate drive circuit described above.
  • a display device comprising the above array substrate.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种移位寄存器及驱动方法、栅极驱动电路、阵列基板以及显示装置，所述移位寄存器（10）包括：上拉控制模块（1）、上拉模块（2）、下拉控制模块（3）、下拉模块（4）和输出端（OP）。上拉控制模块（1）与上拉模块（2）连接，上拉控制模块（1）被配置为控制上拉模块（2）对于输出端（OP）的电平的上拉。上拉模块（2）与输出端（OP）连接，上拉模块（2）被配置为对于输出端（OP）的电平进行上拉。下拉控制模块（3）与下拉模块（4）连接，下拉控制模块（3）被配置为控制下拉模块（4）对于输出端（OP）的电平的下拉。下拉模块（4）与输出端（OP）连接，下拉模块（4）被配置为对于输出端（OP）的电平进行下拉。该移位寄存器（10）及驱动方法、栅极驱动电路、阵列基板以及显示装置，对于电路结构进行了简化，可以应用于窄边框或者超高分辨率的屏幕中。

Description

移位寄存器及驱动方法、驱动电路、阵列基板及显示装置
本申请要求2016年3月16日递交的中国专利申请第201610151132.3号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术，尤其涉及移位寄存器及驱动方法、栅极驱动电路、阵列基板以及显示装置。
背景技术
使用了主动矩阵有机发光二极体(Active Matrix Organic Light Emitting Diode，AMOLED)的像素电路的驱动需求与传统主动矩阵液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)中的像素电路的驱动需求不同，在具有补偿功能的AMOLED像素电路中，至少需要一个移位寄存器用于控制数据信号写入像素电路的过程。
图1是现有技术中的AMOLED的移位寄存器的示意性的电路图。如图1所示，现有技术中通常使用的扫描线移位寄存器包括7个晶体管和2个电容(7T2C)，其结构复杂且工作所需的信号较多。
发明内容
本发明的实施例提供了移位寄存器及驱动方法、栅极驱动电路、阵列基板以及显示装置，对于电路结构进行了简化，可以应用于窄边框或者超高分辨率的屏幕中。
根据本发明的第一个方面，提供了一种移位寄存器，包括：上拉控制模块、上拉模块、下拉控制模块、下拉模块和输出端。上拉控制模块与上拉模块连接，上拉控制模块被配置为控制上拉模块对于输出端的电平的上拉。上拉模块与输出端连接，上拉模块被配置为对于输出端的电平进行上 拉。下拉控制模块与下拉模块连接，下拉控制模块被配置为控制下拉模块对于输出端的电平的下拉。下拉模块与输出端连接，下拉模块被配置为对于输出端的电平进行下拉。
在本发明的实施例中，上拉控制模块包括控制端、第一端和第二端。上拉模块包括控制端、第一端和第二端。下拉控制模块包括控制端、第一端和第二端。下拉模块包括控制端、第一端和第二端。上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与上拉模块的控制端连接。上拉模块的第一端与第一电压端连接，第二端与输出端连接。下拉控制模块的控制端与上拉控制模块的第二端连接，第一端与第二输入端连接，第二端与下拉模块的控制端连接。下拉模块的第一端与第二电压端连接，第二端与输出端连接。
在本发明的实施例中，第二电压端与时钟信号端连接。
在本发明的实施例中，上拉控制模块包括第一晶体管。第一晶体管的控制端为上拉控制模块的控制端，第一晶体管的第一端为上拉控制模块的第一端，第一晶体管的第二端为上拉控制模块的第二端。
在本发明的实施例中，上拉模块包括第二晶体管和第一电容。第二晶体管的控制端为上拉模块的控制端连接，第二晶体管的第一端为上拉模块的第一端，第二晶体管的第二端为上拉模块的第二端。第一电容连接在第二晶体管的控制端和第一端之间。
在本发明的实施例中，下拉控制模块包括第三晶体管。第三晶体管的控制端为下拉控制模块的控制端，第三晶体管的第一端为下拉控制模块的第一端，第三晶体管的第二端为下拉控制模块的第二端。
在本发明的实施例中，下拉模块包括第四晶体管和第二电容。第四晶体管的控制端为下拉模块的控制端，第四晶体管的第一端为下拉模块的第一端，第四晶体管的第二端为下拉模块的第二端。第二电容连接在第四晶体管的控制端和第二端之间。
根据本发明的第二方面，提供了一种栅极驱动电路，包括多个级联的上述的移位寄存器，移位寄存器的输出端被配置为向相对应的像素电路提 供栅极驱动信号。其中，一级的移位寄存器的上拉控制模块和输出端与下一级的移位寄存器连接。
在本发明的实施例中，上拉控制模块包括控制端、第一端和第二端。上拉模块包括控制端、第一端和第二端。下拉控制模块包括控制端、第一端和第二端。下拉模块包括控制端、第一端和第二端。上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与上拉模块的控制端连接。上拉模块的第一端与第一电压端连接，第二端与输出端连接。下拉控制模块的控制端与上拉控制模块的第二端连接，第一端与第二输入端连接，第二端与下拉模块的控制端连接。下拉模块的第一端与第二电压端连接，第二端与输出端连接。其中，一级的移位寄存器的上拉控制模块的第二端与下一级的移位寄存器的第一输入端连接，一级的移位寄存器的输出端与下一级的移位寄存器的第二输入端连接。
根据本发明的第三个方面，提供了一种阵列基板，包括上述的栅极驱动电路。
根据本发明的第四个方面，一种显示装置，包括上述的阵列基板。
根据本发明的第五个方面，一种移位寄存器的驱动方法，用于驱动上述的移位寄存器，包括：第一阶段，使得上拉控制模块导通，上拉模块导通，下拉控制模块导通，下拉模块截止。输出端输出高电平。第二阶段，使得上拉控制模块截止，上拉模块导通，下拉控制模块导通，下拉模块截止。输出端输出高电平。第三阶段，使得上拉控制模块截止，上拉模块导通，下拉控制模块导通，下拉模块导通。输出端输出高电平。第四阶段，使得上拉控制模块导通，上拉模块截止，下拉控制模块截止，下拉模块导通。输出端输出低电平。第五阶段，使得上拉控制模块截止，上拉模块截止，下拉控制模块截止，下拉模块导通。输出端输出高电平。第六阶段，使得上拉控制模块截止，上拉模块截止，下拉控制模块截止，下拉模块导通。输出端输出高电平。
在本发明的实施例中，上拉控制模块包括控制端、第一端和第二端。上拉模块包括控制端、第一端和第二端。下拉控制模块包括控制端、第一 端和第二端。下拉模块包括控制端、第一端和第二端。上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与上拉模块的控制端连接。上拉模块的第一端与第一电压端连接，第二端与输出端连接。下拉控制模块的控制端与上拉控制模块的第二端连接，第一端与第二输入端连接，第二端与下拉模块的控制端连接。下拉模块的第一端与第二电压端连接，第二端与输出端连接。在第一阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号有效，第一电压端是高电平，第二电压端是低电平。在第二阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平。在第三阶段，第一输入端的信号无效，第二输入端的信号有效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平。在第四阶段，第一输入端的信号无效，第二输入端的信号无效，时钟信号端的信号有效，第一电压端是高电平，第二电压端是低电平。在第五阶段，第一输入端的信号无效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平。在第六阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平。
根据本发明的实施例的移位寄存器及驱动方法、栅极驱动电路、阵列基板以及显示装置，对于电路结构进行了简化，可以实现窄边框或者超高分辨率的屏幕中。
附图说明
为了更清楚地说明本发明的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本发明的一些实施例，而非对本发明的限制，其中：
图1是现有技术中的AMOLED的移位寄存器的示意性的电路图；
图2是根据本发明的第一实施例的移位寄存器的框图；
图3是图2所示的移位寄存器的示意性的电路图；
图4是图3所示的移位寄存器的时序图；
图5是根据本发明的第二实施例的栅极驱动电路的示意性的结构图；
图6是图5所示的栅极驱动电路的时序图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本发明保护的范围。
图2是根据本发明的第一实施例的移位寄存器的框图。如图2所示，在本发明的实施例中，移位寄存器10包括：上拉控制模块1、上拉模块2、下拉控制模块3、下拉模块4和输出端OP。上拉控制模块1与上拉模块2连接，上拉控制模块1被配置为控制上拉模块2对于输出端OP的电平的上拉。上拉模块2与输出端OP连接，上拉模块2被配置为对于输出端OP的电平进行上拉。下拉控制模块3与下拉模块4连接，下拉控制模块3被配置为控制下拉模块4对于输出端OP的电平的下拉。下拉模块4与输出端OP连接，下拉模块4被配置为对于输出端OP的电平进行下拉。
在本发明的实施例中，使用上拉控制模块1、上拉模块2、下拉控制模块3、下拉模块4和输出端OP实现移位寄存器，简化了电路结构。
图3是图2所示的移位寄存器的示意性的电路图。在本发明的实施例中，上拉控制模块1包括控制端、第一端和第二端。具体的，上拉控制模块1包括第一晶体管T1。第一晶体管T1的控制端为上拉控制模块1的控制端，第一晶体管T1的第一端为上拉控制模块1的第一端，第一晶体管T1的第二端为上拉控制模块1的第二端。
上拉模块2包括控制端、第一端和第二端。具体的，上拉模块2包括第二晶体管T2和第一电容C1。第二晶体管T2的控制端为上拉模块2的控制端，第二晶体管T2的第一端为上拉模块2的第一端，第二晶体管T2 的第二端为上拉模块2的第二端。第一电容C1连接在第二晶体管T2的控制端和第一端之间。
下拉控制模块3包括控制端、第一端和第二端。具体的，下拉控制模块3包括第三晶体管T3。第三晶体管T3的控制端为下拉控制模块3的控制端，第三晶体管T3的第一端为下拉控制模块3的第一端，第三晶体管T3的第二端为下拉控制模块3的第二端。
下拉模块4包括控制端、第一端和第二端。具体的，下拉模块4包括第四晶体管T4和第二电容C2。第四晶体管T4的控制端为下拉模块4的控制端，第四晶体管T4的第一端为下拉模块4的第一端，第四晶体管T4的第二端为下拉模块4的第二端。第二电容C2连接在第四晶体管T4的控制端和第二端之间。
此外，上拉控制模块1的控制端与时钟信号端CK连接，第一端与第一输入端STV1连接，第二端与上拉模块2的控制端连接。上拉模块2的第一端与第一电压端VGH连接，第二端与输出端OP连接。下拉控制模块3的控制端与上拉控制模块1的第二端连接，第一端与第二输入端STV2连接，第二端与下拉模块4的控制端连接。下拉模块4的第一端与第二电压端VGL连接，第二端与输出端OP连接。
在本发明的实施例中，上拉控制模块1、上拉模块2、下拉控制模块3和下拉模块4使用晶体管实现，使得电路结构得到了简化。
图4是图3所示的移位寄存器的时序图。在本发明的实施例中，移位寄存器的驱动方法包括：
在第一阶段，第一输入端STV1的信号有效，第二输入端STV2的信号无效，时钟信号端CK的信号有效，第一电压端VGH是高电平，第二电压端VGL是低电平。使得上拉控制模块1导通，上拉模块2导通，下拉控制模块3导通，下拉模块4截止。第一节点A的电压有效，第二节点B的电压无效。输出端OP输出高电平。第一节点A是上拉控制模块1的第二端与上拉模块2的控制端连接的连接点，第二节点B是下拉控制模块3的第二端与下拉模块4的控制端连接的连接点。
在第二阶段，第一输入端STV1的信号有效，第二输入端STV2的信号无效，时钟信号端CK的信号无效，第一电压端VGH是高电平，第二电压端VGL是高电平。使得上拉控制模块1截止，上拉模块2导通，下拉控制模块3导通，下拉模块4截止。第一节点A的电压有效，第二节点B的电压无效。输出端OP输出高电平。
在第三阶段，第一输入端STV1的信号无效，第二输入端STV2的信号有效，时钟信号端CK的信号无效，第一电压端VGH是高电平，第二电压端VGL是高电平。使得上拉控制模块1截止，上拉模块2导通，下拉控制模块3导通，下拉模块4导通。第一节点A的电压有效，第二节点B的电压有效。输出端OP输出高电平。
在第三阶段，下拉模块4由截止变为导通时，会存在不完全导通的过渡阶段，如果在该阶段使得输出端OP输出低电平，将不能得到预期的输出信号。因此，在本发明的实施例中，在第三阶段，使得第二电压端VGL是高电平，输出端OP输出高电平。
在第四阶段，第一输入端STV1的信号无效，第二输入端STV2的信号无效，时钟信号端CK的信号有效，第一电压端VGH是高电平，第二电压端VGL是低电平。使得上拉控制模块1导通，上拉模块2截止，下拉控制模块3截止，下拉模块4导通。第一节点A的电压无效，第二节点B的电压有效。输出端OP输出低电平。
在第四阶段，下拉模块4已经完全导通，并且，在包括第二电容C2的情况下，由于第二电容C2的自举作用，使得第二节点B即下拉模块4的控制端的电压的绝对值远大于下拉模块4的导通阈值电压的绝对值，能够很好的保证下拉模块4的导通状态。因此，在本发明的实施例中，在第四阶段，使得第二电压端VGL是低电平，输出端OP输出低电平。
在第五阶段，第一输入端STV1的信号无效，第二输入端STV2的信号无效，时钟信号端CK的信号无效，第一电压端VGH是高电平，第二电压端VGL是高电平。使得上拉控制模块1截止，上拉模块2截止，下拉控制模块3截止，下拉模块4导通。第一节点A的电压无效，第二节点 B的电压有效。输出端OP输出高电平。
在第六阶段，第一输入端STV1的信号有效，第二输入端STV2的信号无效，时钟信号端CK的信号无效，第一电压端VGH是高电平，第二电压端VGL是高电平。使得上拉控制模块1截止，上拉模块2截止，下拉控制模块3截止，下拉模块4导通。第一节点A的电压无效，第二节点B的电压有效。输出端OP输出高电平。
在本发明的实施例中，为了描述方便，以输出端OP输出低电平脉冲信号进行了说明，但是这并不是对于本发明的限制。例如，如果在每个阶段都将第一电压端VGH以及第二电压端VGL的电平进行反向，输出端OP就可以输出相反的高电平的脉冲信号。因此，根据本发明的实施例提供的移位寄存器，在不改变电路结构的情况下，可以向像素电路提供不同的信号。
上述描述中，信号/电压“有效”是指该信号/电压被施加到移位寄存器中的对应模块的控制端时，能够使得该模块导通，信号/电压“无效”是指该信号/电压被施加到移位寄存器中的对应模块的控制端时，能够使得该模块截止。如图3所示，在本发明的实施例中，为了描述方便，以移位寄存器的模块中的晶体管为P型晶体管为例进行了说明，此时，有效信号/电压是低电平的信号/电压，无效信号/电压是高电平的信号/电压，但是这并不是对于本发明的限制。例如，移位寄存器的模块中的晶体管也可以是N型的晶体管，此时，有效信号/电压是高电平的信号/电压，无效信号/电压是低电平的信号/电压。因此，根据本发明的实施例提供的移位寄存器，在不改变电路结构的情况下，可以使用不同类型的晶体管。
此外，在本发明的实施例中，由于第二电压端VGL的状态与时钟信号端CK相同，因此，第二电压端VGL可以与时钟信号端CK连接。这样进一步的简化了电路结构。
图5是根据本发明的第二实施例的栅极驱动电路的示意性的结构图。栅极驱动电路，包括多个级联的上述的移位寄存器10，移位寄存器10的输出端OP被配置为向相对应的像素电路提供栅极驱动信号。其中，一级 的移位寄存器10的上拉控制模块1和输出端OP与下一级的移位寄存器10连接。
具体而言，一级的移位寄存器10的第一节点A与下一级的移位寄存器的第一输入端STV1连接，一级的移位寄存器10的输出端OP与下一级的移位寄存器10的第二输入端STV2连接。
图6是图5所示的栅极驱动电路的时序图。如图6所示，3个时钟信号分别施加到三个级联的移位寄存器10(以G1、G2和G3表示)的时钟信号端CK1、CK2和CK3。3个时钟信号的信号波形相同，在时序上相差1/3个时钟周期。对于进一步级联的移位寄存器10(例如，G4、G5、G6……)，所需要的时钟信号与CK1、CK2和CK3接收的时钟信号完全相同。因此，在本发明的实施例中，3个时钟信号可以满足栅极驱动电路中所有移位寄存器的需要。3个时钟信号可以来自同一个时钟源，通过延时电路得到不同的时序。可以理解的是，为了避免时钟源负载过大，时钟源的个数也可以大于1。
在本发明的实施例中，还提供了一种阵列基板，包括上述的栅极驱动电路。
在本发明的实施例中，还提供了一种显示装置，包括上述的阵列基板。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

  1. 一种移位寄存器，包括：上拉控制模块、上拉模块、下拉控制模块、下拉模块和输出端；
    所述上拉控制模块与所述上拉模块连接，所述上拉控制模块被配置为控制所述上拉模块对于所述输出端的电平的上拉；
    所述上拉模块与所述输出端连接，所述上拉模块被配置为对于所述输出端的电平进行上拉；
    所述下拉控制模块与所述下拉模块连接，所述下拉控制模块被配置为控制所述下拉模块对于所述输出端的电平的下拉；
    所述下拉模块与所述输出端连接，所述下拉模块被配置为对于所述输出端的电平进行下拉。
  2. 根据权利要求1所述的移位寄存器，其中，所述上拉控制模块包括控制端、第一端和第二端；所述上拉模块包括控制端、第一端和第二端；所述下拉控制模块包括控制端、第一端和第二端；所述下拉模块包括控制端、第一端和第二端；
    所述上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与所述上拉模块的控制端连接；
    所述上拉模块的第一端与第一电压端连接，第二端与所述输出端连接；
    所述下拉控制模块的控制端与所述上拉控制模块的第二端连接，第一端与第二输入端连接，第二端与所述下拉模块的控制端连接；
    所述下拉模块的第一端与第二电压端连接，第二端与所述输出端连接。
  3. 根据权利要求2所述的移位寄存器，其中，所述第二电压端与所述时钟信号端连接。
  4. 根据权利要求2所述的移位寄存器，其中，所述上拉控制模块包括第一晶体管；所述第一晶体管的控制端为所述上拉控制模块的控制端，所述第一晶体管的第一端为所述上拉控制模块的第一端，所述第一晶体管的第二端为所述上拉控制模块的第二端。
  5. 根据权利要求2所述的移位寄存器，其中，所述上拉模块包括第二晶体管和第一电容；所述第二晶体管的控制端为所述上拉模块的控制端，所述第二晶体管的第一端为所述上拉模块的第一端，所述第二晶体管的第二端为所述上拉模块的第二端；所述第一电容连接在所述第二晶体管的控制端和第一端之间。
  6. 根据权利要求2所述的移位寄存器，其中，所述下拉控制模块包括第三晶体管；所述第三晶体管的控制端为所述下拉控制模块的控制端，所述第三晶体管的第一端为所述下拉控制模块的第一端，所述第三晶体管的第二端为所述下拉控制模块的第二端。
  7. 根据权利要求2所述的移位寄存器，其中，所述下拉模块包括第四晶体管和第二电容；所述第四晶体管的控制端为所述下拉模块的控制端，所述第四晶体管的第一端为所述下拉模块的第一端，所述第四晶体管的第二端为所述下拉模块的第二端；所述第二电容连接在所述第四晶体管的控制端和第二端之间。
  8. 一种栅极驱动电路，包括多个级联的如权利要求1所述的移位寄存器，所述移位寄存器的所述输出端被配置为向相对应的像素电路提供栅极驱动信号；其中，一级的所述移位寄存器的所述上拉控制模块和所述输出端与下一级的所述移位寄存器连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述上拉控制模块包括控制端、第一端和第二端；所述上拉模块包括控制端、第一端和第二端；所述下拉控制模块包括控制端、第一端和第二端；所述下拉模块包括控制端、第一端和第二端；
    所述上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与所述上拉模块的控制端连接；
    所述上拉模块的第一端与第一电压端连接，第二端与所述输出端连接；
    所述下拉控制模块的控制端与所述上拉控制模块的第二端连接，第一端与第二输入端连接，第二端与所述下拉模块的控制端连接；
    所述下拉模块的第一端与第二电压端连接，第二端与所述输出端连接；
    其中，一级的所述移位寄存器的所述上拉控制模块的第二端与下一级的所述移位寄存器的第一输入端连接，一级的所述移位寄存器的所述输出端与下一级的所述移位寄存器的第二输入端连接。
  10. 一种阵列基板，包括如权利要求8至9中任一项所述的栅极驱动电路。
  11. 一种显示装置，包括如权利要求10所述的阵列基板。
  12. 一种移位寄存器的驱动方法，用于驱动如权利要求1所述的移位寄存器，包括：
    第一阶段，使得上拉控制模块导通，上拉模块导通，下拉控制模块导通，下拉模块截止；输出端输出高电平；
    第二阶段，使得上拉控制模块截止，上拉模块导通，下拉控制模块导通，下拉模块截止；输出端输出高电平；
    第三阶段，使得上拉控制模块截止，上拉模块导通，下拉控制模块导通，下拉模块导通；输出端输出高电平；
    第四阶段，使得上拉控制模块导通，上拉模块截止，下拉控制模块截止，下拉模块导通；输出端输出低电平；
    第五阶段，使得上拉控制模块截止，上拉模块截止，下拉控制模块截止，下拉模块导通；输出端输出高电平；
    第六阶段，使得上拉控制模块截止，上拉模块截止，下拉控制模块截止，下拉模块导通；输出端输出高电平。
  13. 根据权利要求12所述的驱动方法，其中，所述上拉控制模块包括控制端、第一端和第二端；所述上拉模块包括控制端、第一端和第二端；所述下拉控制模块包括控制端、第一端和第二端；所述下拉模块包括控制端、第一端和第二端；
    所述上拉控制模块的控制端与时钟信号端连接，第一端与第一输入端连接，第二端与所述上拉模块的控制端连接；
    所述上拉模块的第一端与第一电压端连接，第二端与所述输出端连接；
    所述下拉控制模块的控制端与所述上拉控制模块的第二端连接，第一 端与第二输入端连接，第二端与所述下拉模块的控制端连接；
    所述下拉模块的第一端与第二电压端连接，第二端与所述输出端连接；
    在第一阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号有效，第一电压端是高电平，第二电压端是低电平；
    在第二阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平；
    在第三阶段，第一输入端的信号无效，第二输入端的信号有效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平；
    在第四阶段，第一输入端的信号无效，第二输入端的信号无效，时钟信号端的信号有效，第一电压端是高电平，第二电压端是低电平；
    在第五阶段，第一输入端的信号无效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平；
    在第六阶段，第一输入端的信号有效，第二输入端的信号无效，时钟信号端的信号无效，第一电压端是高电平，第二电压端是高电平。
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