WO2020019527A1 - Goa电路及显示装置 - Google Patents

Goa电路及显示装置 Download PDF

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Publication number
WO2020019527A1
WO2020019527A1 PCT/CN2018/109665 CN2018109665W WO2020019527A1 WO 2020019527 A1 WO2020019527 A1 WO 2020019527A1 CN 2018109665 W CN2018109665 W CN 2018109665W WO 2020019527 A1 WO2020019527 A1 WO 2020019527A1
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WIPO (PCT)
Prior art keywords
terminal
switch tube
electrically connected
switch
tube
Prior art date
Application number
PCT/CN2018/109665
Other languages
English (en)
French (fr)
Inventor
张鑫
肖军城
管延庆
田超
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/349,625 priority Critical patent/US10714044B1/en
Publication of WO2020019527A1 publication Critical patent/WO2020019527A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display, and in particular to a GOA circuit and a display device which can be used in liquid crystal display technology.
  • liquid crystal display devices Liquid Crystal Display
  • GOA Gate Driver on Array
  • the GOA circuit mainly uses the Array process of thin film transistor (TFT) liquid crystal display.
  • TFT thin film transistor
  • the gate line scan drive signal circuit is fabricated on the Array substrate to achieve progressive scan of the pixel transistor's gate. Drive way.
  • the technology based on low temperature polysilicon can be divided into NMOS type, PMOS type, and CMOS type including NMOS and PMOS according to the type of thin film transistor used in the panel.
  • GOA circuits can also be divided into NMOS circuits, PMOS circuits, and CMOS circuits.
  • NMOS circuits can omit P-type doped photomasks and processes, which are helpful for improving yield and reducing costs. Therefore, the development of stable NMOS circuits has industrial demand.
  • NMOS TFTs are electrons
  • the mobility of electrons is higher than that of holes. Therefore, NMOS devices are more likely to be damaged than PMOS devices (carriers are holes).
  • ITP In-cell Touch Panel
  • split screen is more likely to occur at the TP pause level. This is because TFT is not an ideal switching device. Even in the OFF state, there will still be a certain leakage current. For example, the TP pause level needs to be maintained. A longer period of high potential will reduce the level of stability of GOA.
  • GOA circuits have tried to solve the above problems by blocking the electric leakage pathway in the past, there is still room for improvement.
  • An object of the present invention is to provide a GOA circuit, which can avoid the failure of the GOA circuit caused by the leakage current of the transistor, so as to improve the level stability.
  • Another object of the present invention is to provide a display device, which can improve the level stability of the GOA circuit and improve the reliability of the product.
  • an aspect of the present invention provides a GOA circuit, which includes a cascaded multi-level sub-circuit, and an n-th sub-circuit in the multi-level sub-circuit includes: a control module, Electrically connected to a positive scan control terminal, a negative scan control terminal, a (n-2) th scan terminal, a (n + 2) th scan terminal, a (n + 1) th clock terminal, a first (n-1) level clock end, a high-end end and a low-end end; an output module electrically connected to the high-end end, the low-end end, an n-th clock end, an n-th scan end, and an Control terminal; a pull-up supplementary module, including a supplementary switch tube and an auxiliary switch tube, the supplementary switch tube is electrically connected to the auxiliary switch tube, the high-end terminal, the control module, and the output module; The auxiliary switch tube is electrically connected to the supplementary switch tube, the
  • a control terminal of the supplementary switch tube is electrically connected to a first end of the auxiliary switch tube and the control module, a first end of the supplementary switch tube and the control module.
  • a control terminal of the auxiliary switch tube is electrically connected to the high-end terminal, and a second terminal of the supplementary switch tube is electrically connected to a second terminal of the auxiliary switch tube and the output module.
  • a control terminal of the leakage switch tube is electrically connected to the control module and the output module, and a first terminal of the leakage switch tube is electrically connected to the auxiliary switch.
  • a first end of the tube or a second end of the auxiliary switching tube, and a second end of the leakage switching tube is electrically connected to the lower end.
  • the relay unit includes a seventh switch, a control terminal of the seventh switch is electrically connected to the high-end terminal, and a first terminal of the seventh switch
  • the second node is electrically connected to the first node, and a second terminal of the seventh switch is electrically connected to the pull-up unit.
  • the pull-up unit includes an eighth switch tube, a control terminal of the eighth switch tube is electrically connected to the relay unit, and a first of the eighth switch tube is A terminal is electrically connected to the n-th clock terminal, and a second terminal of the eighth switch is electrically connected to the n-th scanning terminal.
  • the pull-down unit includes a ninth switch tube, a control terminal of the ninth switch tube is electrically connected to the second node, and a first terminal of the ninth switch tube.
  • the n-th scanning end is electrically connected, and a second end of the ninth switching tube is electrically connected to the lower end.
  • the detection unit includes a tenth switch tube, an eleventh switch tube, and a twelfth switch tube.
  • a control terminal of the tenth switch tube is electrically connected to the control terminal.
  • a first end of a tenth switch tube and a control end of the eleventh switch tube, a second end of the tenth switch tube is electrically connected to the n-th scan terminal, and the eleventh switch
  • a first end of the tube is electrically connected to the second node
  • a second end of the eleventh switch tube is electrically connected to the lower end
  • a control end of the twelfth switch tube is electrically connected to the second node.
  • a first terminal of the twelfth switch tube is electrically connected to the n-th scanning terminal
  • a second terminal of the twelfth switch tube is electrically connected to the lower terminal.
  • a GOA circuit including a cascaded multi-stage sub-circuit, and an n-th sub-circuit in the multi-stage sub-circuit may include: a control module , Is electrically connected to a positive scanning control terminal, a negative scanning control terminal, a (n-2) -level scanning terminal, a (n + 2) -level scanning terminal, a (n + 1) -level clock terminal, a An (n-1) th clock end, a high end and a low end; an output module electrically connected to the high end, the low end, an nth clock end, an nth scan end, and an Controllable end; a pull-up supplementary module including a supplementary switch tube and an auxiliary switch tube, the supplementary switch tube is electrically connected to the auxiliary switch tube, the high-end terminal, the control module, and the output module, The auxiliary switch tube is electrically connected to the supplementary switch tube, the high-end
  • a control terminal of the supplementary switch tube is electrically connected to a first end of the auxiliary switch tube and the control module, a first end of the supplementary switch tube and the control module.
  • a control terminal of the auxiliary switch tube is electrically connected to the high-end terminal, and a second terminal of the supplementary switch tube is electrically connected to a second terminal of the auxiliary switch tube and the output module.
  • a control terminal of the leakage switch tube is electrically connected to the control module and the output module, and a first terminal of the leakage switch tube is electrically connected to the auxiliary switch.
  • a first end of the tube or a second end of the auxiliary switching tube, and a second end of the leakage switching tube is electrically connected to the lower end.
  • the control module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube.
  • the first switch tube is electrically connected to the (n-2) th scanning terminal, the positive scan control terminal, the second switch tube, the sixth switch tube, the supplementary switch tube, and the An auxiliary switch tube
  • the second switch tube is electrically connected to the (n + 2) -th scan terminal, the negative scan control terminal, the first switch tube, the sixth switch tube, and the supplementary switch
  • the auxiliary switch tube the third switch tube is electrically connected to the positive scan control terminal, the (n + 1) th clock terminal, the fourth switch tube and the fifth switch tube
  • the fourth switch tube is electrically connected to the negative scanning control terminal, the (n-1) th clock terminal, the third switch tube and the fifth switch tube, and the fifth switch tube is electrically connected.
  • the high-end terminal, the third switch tube, the fourth switch tube, the sixth switch tube, the leakage switch tube, and the output module are connected, and the sixth switch tube is electrically Connected to the low end, the first switch tube, the second switch tube, the fifth switch tube, the supplementary switch tube, the auxiliary switch tube, the output module, and the leakage switch tube .
  • the output module includes a relay unit, a pull-up unit, a pull-down unit, a detection unit, a first energy storage element and a second energy storage element.
  • the relay unit is electrically connected to the high end, the supplementary switch tube, the auxiliary switch tube and the pull-up unit, and the relay unit, the supplementary switch tube and the auxiliary switch tube are connected together to form a first A node, the pull-up unit is electrically connected to the relay unit, the n-th clock terminal and the n-th scan terminal, and the pull-down unit is electrically connected to the n-th scan terminal, the The low end, the leakage switch and the control module, and the detection unit is electrically connected to the n-th scanning end, the low end, the controllable end, the pull-down unit, the leakage Circuit switch tube and the control module, the pull-down unit, the detection unit, the leakage switch tube and the control module are connected together to form a second node, and the first energy storage element is electrically connected
  • the relay unit includes a seventh switch, a control terminal of the seventh switch is electrically connected to the high-end terminal, and a first terminal of the seventh switch
  • the second node is electrically connected to the first node, and a second terminal of the seventh switch is electrically connected to the pull-up unit.
  • the pull-up unit includes an eighth switch tube, a control terminal of the eighth switch tube is electrically connected to the relay unit, and a first of the eighth switch tube is A terminal is electrically connected to the n-th clock terminal, and a second terminal of the eighth switch is electrically connected to the n-th scanning terminal.
  • the pull-down unit includes a ninth switch tube, a control terminal of the ninth switch tube is electrically connected to the second node, and a first terminal of the ninth switch tube.
  • the n-th scanning end is electrically connected, and a second end of the ninth switching tube is electrically connected to the lower end.
  • the detection unit includes a tenth switch tube, an eleventh switch tube, and a twelfth switch tube.
  • a control terminal of the tenth switch tube is electrically connected to the control terminal.
  • a first end of a tenth switch tube and a control end of the eleventh switch tube, a second end of the tenth switch tube is electrically connected to the n-th scan terminal, and the eleventh switch
  • a first end of the tube is electrically connected to the second node
  • a second end of the eleventh switch tube is electrically connected to the lower end
  • a control end of the twelfth switch tube is electrically connected to the second node.
  • a first terminal of the twelfth switch tube is electrically connected to the n-th scanning terminal
  • a second terminal of the twelfth switch tube is electrically connected to the lower terminal.
  • another aspect of the present invention provides a display device including an array substrate and the GOA circuit as described above, the GOA circuit being disposed on the array substrate.
  • the GOA circuit and display device of the present invention are provided with the pull-up supplementary module. If the leakage switch tube reduces the potential of the first node due to a certain leakage current during the touch period, then At the same time, since the supplementary switch tube of the pull-up supplementary module also has a certain leakage current to increase the potential of the first node, the effect of the leakage of the leakage switch tube on the potential of the first node is slowed down, thereby increasing the circuit current. The marginal range of the touch period makes the circuit work normally and improves the reliability of the circuit.
  • FIG. 1 is a schematic diagram of a GOA circuit according to a first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a GOA circuit according to a second embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present invention without a pull-up supplementary module.
  • an aspect of the present invention includes a GOA circuit, which can be used to control a display panel based on low temperature polysilicon (LTPS) technology.
  • the display panel can use a thin film transistor (TFT) type as an NMOS transistor.
  • TFT thin film transistor
  • the switch can have a control terminal (such as the gate of a transistor), a first terminal (such as one of the source and the drain of a transistor), and a second terminal (such as the source and the drain of a transistor). another).
  • the GOA circuit may include cascaded multi-level sub-circuits.
  • n may be a positive
  • An integer is used to represent one of the cascaded multi-level sub-circuits, and the sub-circuits of the other levels are the same as those of the n-th level, which can be understood by those skilled in the art, and will not be repeated here.
  • the n-th sub-circuit in the multi-level sub-circuit may include: a control module 1, an output module 2, a pull-up supplementary module 3, and a leakage switch tube 4. The following illustrates the implementation of the GOA circuit according to an embodiment of the present invention, but is not limited thereto.
  • the control module 1 can be electrically connected to a positive scanning control terminal U2D, a negative scanning control terminal D2U, a (n-2) -level scanning terminal G (n-2), and a first (n + 2) -stage scanning terminal G (n + 2), (n + 1) -stage clock terminal CK (n + 1), (n-1) -stage clock terminal CK (n-1), one A high-end VGH and a low-end VGL;
  • the output module 2 can be electrically connected to the high-end VGH, the low-end VGL, an n-th clock terminal CK (n), and an n-th scan terminal G (n )
  • the pull-up supplementary module 3 may include a supplementary switch tube Ta and an auxiliary switch tube Tb, and the supplementary switch tube Ta is electrically connected to the auxiliary switch tube Tb and the high-end VGH ,
  • the control module 1 and the output module 2 is electrically connected to the
  • the positive scanning control terminal U2D and the negative scanning control terminal D2U can be used for input signals to control the progressive scanning sequence.
  • the positive scanning control terminal U2D inputs a constant voltage high potential signal and the negative scanning
  • the control terminal D2U inputs a constant voltage low potential signal, and scans from top to bottom progressively;
  • the positive scanning control terminal U2D inputs a constant voltage low potential signal and the negative scanning control terminal D2U inputs a constant voltage high potential signal, Scan from bottom to top.
  • the (n-2) th scanning end G (n-2) and the (n + 2) th scanning end G (n + 2) can be used to input the (n-2), (n + 2) th Signal output from the scanning end of the first stage sub-circuit; the (n + 1) th clock end CK (n + 1), the nth clock end CK (n), the (n-1) th clock end CK (n -1) Can input clock signals for (n + 1), n, (n-1) -level sub-circuits; the n-th scan end G (n) can be used to output an n-th scan signal for each The gate level of the pixel transistor is scanned in line; the high-side VGH and low-side VGL can be used to input a constant voltage high-potential signal and a constant voltage low-potential signal, and the voltage value can be adjusted according to the manufacture of the transistor; the controllable end GAS2 can be used to input a control signal, such as a pulse signal, to cooperate with a TP
  • the control module 1 may include a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a fifth switch.
  • the control terminal of the first switching tube T1 is electrically connected to the (n-2) th stage scanning terminal G (n-2).
  • a first terminal is electrically connected to the positive scanning control terminal U2D, and a second terminal of the first switching transistor T1 is electrically connected to a second terminal of the second switching transistor T2 and a control terminal of the sixth switching transistor T6.
  • the control terminal of the third switch tube T3 is electrically connected to the positive scan Control terminal U2D, the third switch T
  • the first terminal of 3 is electrically connected to the (n + 1) th clock terminal CK (n + 1), the second terminal of the third switching tube T3, the second terminal of the fourth switching tube T4, and all
  • the control terminal of the fifth switch T5 is electrically connected to the negative scanning control terminal D2U, and the first terminal of the fourth switch T
  • the first terminal of the fifth switch tube T5 is electrically connected. Connected to the high end, the second end of the fifth switch T5 is electrically connected to the first end of the sixth switch T6, the control end of the leakage switch 4 and the output module 2;
  • the control terminal of the sixth switch tube T6 is electrically connected to the second terminal of the first switch tube T1, the second terminal of the second switch tube T2, the control terminal of the supplementary switch tube Ta, and the auxiliary switch.
  • the first end of the tube Tb, the sixth switch A first terminal of T6 is electrically connected to a second terminal of the fifth switch tube, a control terminal of the output module 2 and the leakage switch tube 4, and a second terminal of the sixth switch tube T6 is electrically connected. The low end.
  • the output module 2 may include a relay unit 21, a pull-up unit 22, a pull-down unit 23, a detection unit 24, a first energy storage member 25 and A second energy storage member 26, the relay unit 21 is electrically connected to the high-end VGH, the supplementary switch tube Ta, the auxiliary switch tube Tb, and the pull-up unit 22, and the relay unit 21
  • the supplementary switching tube Ta and the auxiliary switching tube Tb are connected together to form a first node Q;
  • the pull-up unit 22 is electrically connected to the relay unit 21 and the n-th clock terminal CK (n) And the n-th scanning terminal G (n);
  • the pull-down unit 23 is electrically connected to the n-th scanning terminal G (n), the low-level terminal VGL, the leakage switch 4 and the control Module 4;
  • the detection unit 24 is electrically connected to the n-th scanning end G (n), the low-end VGL, the controllable end GAS2, the pull-down unit 23, and the leakage switch 4 And the control module
  • the relay unit 21 may include a seventh switch T7, and a control terminal of the seventh switch T7 is electrically connected to the high-end VGH, and the seventh switch T7 The first terminal of is electrically connected to the first node Q, and the second terminal of the seventh switch T7 is electrically connected to the pull-up unit 22.
  • the pull-up unit 22 may include an eighth switch T8, and a control terminal of the eighth switch T8 is electrically connected to the relay unit 21 (such as the seventh switch). Second end of the tube T7), the first end of the eighth switching tube T8 is electrically connected to the n-th clock terminal CK (n), and the second end of the eighth switching tube T8 is electrically connected to the The n-th scanning end G (n).
  • the pull-down unit 23 may include a ninth switch T9, and a control terminal of the ninth switch T9 is electrically connected to the second node P, and the ninth switch T9 The first terminal of is electrically connected to the n-th scanning terminal G (n), and the second terminal of the ninth switching tube T9 is electrically connected to the lower terminal VGL.
  • the detection unit 24 may include a tenth switch tube T10, an eleventh switch tube T11, and a twelfth switch tube T12.
  • the control terminal of the tenth switch tube T10 The first end of the tenth switching tube T10 and the control end of the eleventh switching tube T11 are electrically connected, and the second end of the tenth switching tube T10 is electrically connected to the n-th scanning terminal G ( n), a first terminal of the eleventh switching transistor T11 is electrically connected to the second node P, a second terminal of the eleventh switching transistor T11 is electrically connected to the lower terminal VGL, and the first The control terminal of the twelve switch transistor T12 is electrically connected to the controllable terminal GAS2, and the first terminal of the twelfth switch transistor T12 is electrically connected to the n-th scan terminal G (n), and the twelfth switch The second terminal of the switching tube T12 is electrically connected to the low-level terminal VGL.
  • the control terminal of the supplementary switch tube Ta of the pull-up supplementary module 3 is electrically connected to the first end of the auxiliary switch tube Tb and the control module 1.
  • the first transistor T1, the first terminal of the supplementary switching tube Ta and the control terminal of the auxiliary switching tube Tb are electrically connected to the high-end terminal VGH, and the second terminal of the supplementary switching tube Ta is electrically connected to the auxiliary The second end of the switching tube Tb, the relay unit 21 and the first energy storage element 25 of the output module 2; in addition, the control end of the leakage switching tube 4 is electrically connected to the first end of the control module 1
  • Five switch tubes T5, sixth switch tube T6, the pull-down unit 23, the detection unit 24, and the second energy storage member 26 of the output module 2 the first end of the leakage switch tube 4 is electrically The first terminal (as shown in FIG. 1) or the second terminal (as shown in FIG. 2) of the auxiliary switch tube Tb is connected, and the second terminal of the leakage switch tube
  • the following illustrates the operation of the GOA circuit described above. Taking the ITP panel as an example, it is necessary to insert several touch periods (TP Term) within the display time of one frame.
  • the The signals input from the positive scanning control terminal U2D and the negative scanning control terminal D2U control the progressive scanning sequence, in cooperation with the (n-2) th scanning terminal G (n-2) and the (n + 2) th scanning terminal G ( n + 2), (n + 1) th clock terminal CK (n + 1), nth clock terminal CK (n), (n-1) th clock terminal CK (n-1), controllable terminal GAS2, high-end VGH and low-end VGL input signals required for operation can output the n-th scan signal at the n-th scan terminal G (n) for progressive scanning; during the touch period,
  • the first node Q can maintain a potential required for the operation of the circuit to ensure that the circuit works normally.
  • the characteristics that the GOA circuit is provided with the pull-up supplementary module 3 are specifically explained
  • the GAS1 signal (the signal at the gate of the eleventh switching transistor T11) is a normal low potential (Low) in normal operation.
  • the controllable terminal GAS2 jumps from a normal low potential (Low) to a high potential (High) during a touch period.
  • the current ITP panel needs to insert several TP Term within one frame of the screen display time to implement the touch function.
  • the GOA circuit of the NMOS must be held (cascaded) through the first energy storage device 25.
  • the required high potential (High) because the NMOS TFT is not an ideal switching device, there will still be a certain leakage current even in the OFF state, such as the long duration of TP Term , The time for which the TP pause stage needs to be maintained at a high potential will be long, and the leakage current will reduce the stability of the GOA stage.
  • the first terminal of the leakage switch tube 4 is electrically connected to the auxiliary switch tube Tb.
  • the leakage switch 4 is OFF, and the leakage
  • there is a certain leakage current (from the first node Q to the low-end VGL) of the circuit switching tube 4 to reduce the potential of the first node Q it should be noted that at this time, the complementary switching tube Ta is also turned off.
  • the auxiliary switching tube Tb operates as a normally-on TFT, but even in an on state, the resistance of the TFT can reach a megohm level, which can partially reduce the leakage current of the leakage switching tube 4.
  • the potential on the left side of the auxiliary switch Tb is theoretically slightly higher than the right, and the voltage on the left side of the auxiliary switch Tb is the control terminal (gate) of the supplementary switch Ta.
  • Voltage which is conducive to the leakage of the supplementary switching tube Ta to the first node Q, so that the first node Q is maintained at a high potential to ensure the normal operation of the circuit.
  • the leakage switch tube 4 still has leakage current and will lower the Q potential of the first node
  • the present invention is different from the prior art GOA circuit in the way of blocking electric leakage.
  • the leakage is different.
  • the electric leakage path of the circuit switch tube 4 is not blocked.
  • the pull-up supplementary module 3 uses the leakage current characteristic of the supplementary switch tube Ta to supplement the electrical energy of the first energy storage element 25 in time to slow down.
  • the leakage current of the leakage switch tube 4 substantially maintains the potential of the first node Q to ensure that the circuit works normally and avoids the screen splitting phenomenon on the panel of the display device.
  • the GOA circuit according to the second embodiment of the present invention is also provided with the above-mentioned pull-up supplementary module 3 (such as the first terminal of the leakage switch tube 4 electrically connected to the first terminal of the auxiliary switch tube Tb). (Two ends).
  • the advantage of this embodiment is that it is more conducive to the stage transmission.
  • the first switch T1 can quickly improve the sixth switch T6.
  • An embodiment is lower, so that the GOA circuit still maintains normal functions even after experiencing TP term, and avoids split screen phenomenon on the panel of the display device.
  • the driving structure of the GOA circuit may be an interlace or a dual-drive type; the phase number of the GOA circuit may be 4CK, or 6CK or 8CK. Taking 4CK as an example, two GOA circuits are used as a cycle. Two identical GOA circuits can be used as a first GOA circuit and a second GOA circuit, and four clock signals (CK1, CK2, CK3, CK4) ) Input to the GOA circuit and a second GOA circuit. For example, as shown in FIG. 1 and FIG.
  • CK1 may be input to the n-th clock terminal CK (n) of the first GOA circuit
  • CK2 and CK4 may be input to the first GOA circuit
  • the (n + 1) th clock terminal CK (n + 1), the (n-1) th clock terminal CK (n-1) of the second GOA circuit, and CK3 is input to the The n-th stage clock terminal CK (n) of the second GOA circuit can be understood by those skilled in the art, and will not be described again here.
  • the display device including an array substrate and the GOA circuit as described above, and the GOA circuit is disposed on the array substrate.
  • the display device may be configured as one of the following items: liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital camera, navigator and any other product with a display function Or, the display device can solve the same problems and produce the same effects as the GOA circuit described above.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及显示装置，所述GOA电路中的一第n级子电路包括：一控制模块（1）；一输出模块（2）；一上拉补充模块（3），包括一补充开关管（Ta）及一辅助开关管（Tb），所述补充开关管（Ta）耦接所述辅助开关管（Tb）、所述控制模块（1）及所述输出模块（2），所述辅助开关管（Tb）耦接所述补充开关管（Ta）、所述控制模块（1）及所述输出模块（2）；及一漏路开关管，耦接所述控制模块（1）、所述输出模块（2）、所述补充开关管（Ta）及所述辅助开关管（Tb）。

Description

GOA电路及显示装置 技术领域
本发明涉及显示领域，特别是有涉及一种可用于液晶显示技术的GOA电路及显示装置。
 背景技术
目前，液晶显示装置(Liquid Crystal Display)已广泛应用于各种电子产品，在液晶显示装置中的一个重要组成部分是GOA(Gate Driver on Array)电路，GOA电路主要利用薄膜晶体管(TFT)液晶显示器的Array制程，将栅极(Gate)行扫描驱动信号电路制作于在Array基板上，以实现对像素晶体管的栅极逐行扫描的驱动方式。
在显示面板技术中，基于低温多晶硅（LTPS）的技术根据面板内采用的薄膜晶体管类型，可区分为NMOS型、PMOS型以及含有NMOS和PMOS的CMOS型。类似地，GOA电路也可区分为NMOS电路、PMOS电路及CMOS电路。其中，由于NMOS电路与CMOS电路相比可省去P型掺杂的光罩及工序，对于提高良率及降低成本皆有助益，所以开发稳定的NMOS电路具有产业需求性。
但是，由于NMOS型TFT的载流子为电子，电子的迁移率较高于空穴，因此，NMOS元件比PMOS元件(载流子为空穴)容易损伤，表现在面板上就是产品的高温信赖度不足，容易出现GOA电路失效，使面板出现分屏现象，尤其是In-cell Touch Panel(ITP)，在TP暂停级更容易出现分屏现象，这是因为TFT并非理想开关器件，即使在关态(OFF)情况下，依然会存在一定的漏电流，如TP暂停级需要维持高电位的时间较长，将会降低GOA的级传稳定性。以往虽有GOA电路阻绝电泄途径而试图解决上述问题，但仍有待改善。
有鉴于此，有必要提供一种新的GOA电路及显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的一目的在于提供一种GOA电路，可避免晶体管的漏电流造成GOA电路失效，以提高级传稳定性。
本发明的另一目的在于提供一种显示装置，可提高GOA电路的级传稳定性，以提高产品信赖度。
 技术解决方案
为了达成本发明的前述目的，本发明的一方面提供一种GOA电路，其包括级联的多级子电路，在所述多级子电路中的一第n级子电路包括：一控制模块，电性连接一正扫控端、一负扫控端、一第(n-2)级扫描端、一第(n+2)级扫描端、一第(n+1)级时钟端、一第(n-1)级时钟端、一高位端及一低位端；一输出模块，电性连接所述高位端、所述低位端、一第n级时钟端、一第n级扫描端及一可控端；一上拉补充模块，包括一补充开关管及一辅助开关管，所述补充开关管电性连接所述辅助开关管、所述高位端、所述控制模块及所述输出模块，所述辅助开关管电性连接所述补充开关管、所述高位端、所述控制模块及所述输出模块；及一漏路开关管，电性连接所述控制模块、所述输出模块、所述补充开关管、所述辅助开关管及所述低位端；其中，所述控制模块包括一第一开关管、一第二开关管、一第三开关管、一第四开关管、一第五开关管及一第六开关管，所述第一开关管电性连接所述第(n-2)级扫描端、所述正扫控端、所述第二开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第二开关管电性连接所述第(n+2)级扫描端、所述负扫控端、所述第一开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第三开关管电性连接所述正扫控端、所述第(n+1)级时钟端、所述第四开关管及所述第五开关管，所述第四开关管电性连接所述负扫控端、所述第(n-1)级时钟端、所述第三开关管及所述第五开关管，所述第五开关管电性连接所述高位端、所述第三开关管、所述第四开关管、所述第六开关管、所述漏路开关管及所述输出模块，所述第六开关管电性连接所述低位端、所述第一开关管、所述第二开关管、所述第五开关管、所述补充开关管、所述辅助开关管、所述输出模块及所述漏路开关管；所述输出模块包括一中继单元、一上拉单元、一下拉单元、一侦测单元、一第一储能件及一第二储能件，所述中继单元电性连接所述高位端、所述补充开关管、所述辅助开关管及所述上拉单元，所述中继单元、所述补充开关管及所述辅助开关管共同连接形成一第一节点，所述上拉单元电性连接所述中继单元、所述第n级时钟端及所述第n级扫描端，所述下拉单元电性连接所述第n级扫描端、所述低位端、所述漏路开关管及所述控制模块，所述侦测单元电性连接所述第n级扫描端、所述低位端、所述可控端、所述下拉单元、所述漏路开关管及所述控制模块，所述下拉单元、所述侦测单元、所述漏路开关管及所述控制模块共同连接形成一第二节点，所述第一储能件电性连接于所述第一节点与所述低位端之间，所述第二储能件电性连接于所述第二节点与所述低位端之间。
在本发明的一实施例中，所述补充开关管的一控制端电性连接所述辅助开关管的一第一端及所述控制模块，所述补充开关管的一第一端及所述辅助开关管的一控制端电性连接所述高位端，所述补充开关管的一第二端电性连接所述辅助开关管的一第二端及所述输出模块。
在本发明的一实施例中，所述漏路开关管的一控制端电性连接所述控制模块及所述输出模块，所述漏路开关管的一第一端电性连接所述辅助开关管的第一端或所述辅助开关管的第二端，所述漏路开关管的一第二端电性连接所述低位端。
在本发明的一实施例中，所述中继单元包括一第七开关管，所述第七开关管的一控制端电性连接所述高位端，所述第七开关管的一第一端电性连接所述第一节点，所述第七开关管的一第二端电性连接所述上拉单元。
在本发明的一实施例中，所述上拉单元包括一第八开关管，所述第八开关管的一控制端电性连接所述中继单元，所述第八开关管的一第一端电性连接所述第n级时钟端，所述第八开关管的一第二端电性连接所述第n级扫描端。
在本发明的一实施例中，所述下拉单元包括一第九开关管，所述第九开关管的一控制端电性连接所述第二节点，所述第九开关管的一第一端电性连接所述第n级扫描端，所述第九开关管的一第二端电性连接所述低位端。
在本发明的一实施例中，所述侦测单元包括一第十开关管、一第十一开关管及一第十二开关管，所述第十开关管的一控制端电性连接所述第十开关管的一第一端及所述第十一开关管的一控制端，所述第十开关管的一第二端电性连接所述第n级扫描端，所述第十一开关管的一第一端电性连接所述第二节点，所述第十一开关管的一第二端电性连接所述低位端，所述第十二开关管的一控制端电性连接所述可控端，所述第十二开关管的一第一端电性连接所述第n级扫描端，所述第十二开关管的一第二端电性连接所述低位端。
为了达成本发明的前述目的，本发明的另一方面提供一种GOA电路，包括级联的多级子电路，在所述多级子电路中的一第n级子电路可包括：一控制模块，电性连接一正扫控端、一负扫控端、一第(n-2)级扫描端、一第(n+2)级扫描端、一第(n+1)级时钟端、一第(n-1)级时钟端、一高位端及一低位端；一输出模块，电性连接所述高位端、所述低位端、一第n级时钟端、一第n级扫描端及一可控端；一上拉补充模块，包括一补充开关管及一辅助开关管，所述补充开关管电性连接所述辅助开关管、所述高位端、所述控制模块及所述输出模块，所述辅助开关管电性连接所述补充开关管、所述高位端、所述控制模块及所述输出模块；及一漏路开关管，电性连接所述控制模块、所述输出模块、所述补充开关管、所述辅助开关管及所述低位端。
在本发明的一实施例中，所述补充开关管的一控制端电性连接所述辅助开关管的一第一端及所述控制模块，所述补充开关管的一第一端及所述辅助开关管的一控制端电性连接所述高位端，所述补充开关管的一第二端电性连接所述辅助开关管的一第二端及所述输出模块。
在本发明的一实施例中，所述漏路开关管的一控制端电性连接所述控制模块及所述输出模块，所述漏路开关管的一第一端电性连接所述辅助开关管的第一端或所述辅助开关管的第二端，所述漏路开关管的一第二端电性连接所述低位端。
在本发明的一实施例中，所述控制模块包括一第一开关管、一第二开关管、一第三开关管、一第四开关管、一第五开关管及一第六开关管，所述第一开关管电性连接所述第(n-2)级扫描端、所述正扫控端、所述第二开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第二开关管电性连接所述第(n+2)级扫描端、所述负扫控端、所述第一开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第三开关管电性连接所述正扫控端、所述第(n+1)级时钟端、所述第四开关管及所述第五开关管，所述第四开关管电性连接所述负扫控端、所述第(n-1)级时钟端、所述第三开关管及所述第五开关管，所述第五开关管电性连接所述高位端、所述第三开关管、所述第四开关管、所述第六开关管、所述漏路开关管及所述输出模块，所述第六开关管电性连接所述低位端、所述第一开关管、所述第二开关管、所述第五开关管、所述补充开关管、所述辅助开关管、所述输出模块及所述漏路开关管。
在本发明的一实施例中，所述输出模块包括一中继单元、一上拉单元、一下拉单元、一侦测单元、一第一储能件及一第二储能件，所述中继单元电性连接所述高位端、所述补充开关管、所述辅助开关管及所述上拉单元，所述中继单元、所述补充开关管及所述辅助开关管共同连接形成一第一节点，所述上拉单元电性连接所述中继单元、所述第n级时钟端及所述第n级扫描端，所述下拉单元电性连接所述第n级扫描端、所述低位端、所述漏路开关管及所述控制模块，所述侦测单元电性连接所述第n级扫描端、所述低位端、所述可控端、所述下拉单元、所述漏路开关管及所述控制模块，所述下拉单元、所述侦测单元、所述漏路开关管及所述控制模块共同连接形成一第二节点，所述第一储能件电性连接于所述第一节点与所述低位端之间，所述第二储能件电性连接于所述第二节点与所述低位端之间。
在本发明的一实施例中，所述中继单元包括一第七开关管，所述第七开关管的一控制端电性连接所述高位端，所述第七开关管的一第一端电性连接所述第一节点，所述第七开关管的一第二端电性连接所述上拉单元。
在本发明的一实施例中，所述上拉单元包括一第八开关管，所述第八开关管的一控制端电性连接所述中继单元，所述第八开关管的一第一端电性连接所述第n级时钟端，所述第八开关管的一第二端电性连接所述第n级扫描端。
在本发明的一实施例中，所述下拉单元包括一第九开关管，所述第九开关管的一控制端电性连接所述第二节点，所述第九开关管的一第一端电性连接所述第n级扫描端，所述第九开关管的一第二端电性连接所述低位端。
在本发明的一实施例中，所述侦测单元包括一第十开关管、一第十一开关管及一第十二开关管，所述第十开关管的一控制端电性连接所述第十开关管的一第一端及所述第十一开关管的一控制端，所述第十开关管的一第二端电性连接所述第n级扫描端，所述第十一开关管的一第一端电性连接所述第二节点，所述第十一开关管的一第二端电性连接所述低位端，所述第十二开关管的一控制端电性连接所述可控端，所述第十二开关管的一第一端电性连接所述第n级扫描端，所述第十二开关管的一第二端电性连接所述低位端。
为了达成本发明的前述目的，本发明的另一方面提供一种显示装置，包括一阵列基板及如上所述的GOA电路，所述GOA电路设置于所述阵列基板。
 有益效果
与现有技术相比较，本发明的GOA电路及显示装置设有所述上拉补充模块，如所述漏路开关管在触控期因为存在一定的漏电流而使第一节点降低电位，则在同时，由于所述上拉补充模块的补充开关管也存在一定的漏电流以使第一节点提高电位，因而减缓所述漏路开关管漏电对第一节点电位的影响，进而增大电路在触控期的边际范围，使电路正常工作，提高电路可靠度。
 附图说明
图1是本发明第一实施例的GOA电路的示意图。
图2是本发明第二实施例的GOA电路的示意图。
图3是本发明实施例的GOA电路还未设置上拉补充模块的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1所示，本发明的一方面包括一种GOA电路，可用于控制基于低温多晶硅(LTPS)技术的显示面板，所述显示面板采用的薄膜晶体管（TFT）类型可为NMOS晶体管，后述的开关管可具有一控制端(如晶体管的栅极)、一第一端(如晶体管的源极与汲极中的一个)及一第二端(如晶体管的源极与汲极中的另一个)。
请再参阅图1所示，所述GOA电路可包括级联(cascade)的多级子电路(sub-circuits)，在此仅以一第n级子电路为例说明，例如n可为一正整数，用以代表级联的多级子电路中的一个，其余级别的子电路与第n级子电路相同，这是本领域技术人员可以理解的，在此不另赘述。在所述多级子电路中的第n级子电路可包括：一控制模块1、一输出模块2、一上拉补充模块3及一漏路开关管4。以下举例说明本发明一实施例的GOA电路的实施态样，但不以此为限。
请再参阅图1所示，所述控制模块1可电性连接一正扫控端U2D、一负扫控端D2U、一第(n-2)级扫描端G(n-2)、一第(n+2)级扫描端G(n+2)、一第(n+1)级时钟端CK(n+1)、一第(n-1)级时钟端CK(n-1)、一高位端VGH及一低位端VGL；所述输出模块2可电性连接所述高位端VGH、所述低位端VGL、一第n级时钟端CK(n)、一第n级扫描端G(n)及一可控端GAS2；所述上拉补充模块3可包括一补充开关管Ta及一辅助开关管Tb，所述补充开关管Ta电性连接所述辅助开关管Tb、所述高位端VGH、所述控制模块1及所述输出模块2，所述辅助开关管Tb电性连接所述补充开关管Ta、所述高位端VGH、所述控制模块1及所述输出模块2；所述漏路开关管4可电性连接所述控制模块1、所述输出模块2、所述补充开关管Ta、所述辅助开关管Tb及所述低位端VGL。
应被理解的是，所述正扫控端U2D及负扫控端D2U可用于输入信号控制逐行扫描顺序，例如：所述正扫控端U2D输入一恒压高电位信号且所述负扫控端D2U输入一恒压低电位信号，则由上向下逐行扫描；所述正扫控端U2D输入一恒压低电位信号且所述负扫控端D2U输入一恒压高电位信号，则由下向上逐行扫描。
此外，所述第(n-2)级扫描端G(n-2)及第(n+2)级扫描端G(n+2)可用于输入第(n-2)、(n+2)级子电路的扫描端输出的信号；所述第(n+1)级时钟端CK(n+1)、第n级时钟端CK(n)、第(n-1)级时钟端CK(n-1)可输入用于第(n+1)、n、(n-1)级子电路的时钟信号；第n级扫描端G(n)可用于输出一第n级扫描信号，用以逐行扫描像素晶体管的栅级；所述高位端VGH及低位端VGL可用于输入一恒压高电位信号及一恒压低电位信号，其电压值可配合晶体管制成进行调整；所述可控端GAS2可用于输入一控制信号，例如一脉波信号，用以配合一触控期维持(TP term Holding)状态，例如：所述控制信号在一触控期内为高电位，其余为低电位，这是本领域技术人员可以理解的，不再赘述于此。
在一实施例中，如图1所示，所述控制模块1可包括一第一开关管T1、一第二开关管T2、一第三开关管T3、一第四开关管T4、一第五开关管T5及一第六开关管T6，所述第一开关管T1的控制端电性连接所述第(n-2)级扫描端G(n-2)，所述第一开关管T1的第一端电性连接所述正扫控端U2D，所述第一开关管T1的第二端电性连接所述第二开关管T2的第二端、所述第六开关管T6的控制端、所述补充开关管Ta的控制端及所述辅助开关管Tb的第一端；所述第二开关管T2的控制端电性连接所述第(n+2)级扫描端G(n+2)，所述第二开关管T2的第一端电性连接所述负扫控端D2U，所述第二开关管T2的第二端电性连接所述第一开关管T1的第二端、所述第六开关管T6的控制端、所述补充开关管Ta的控制端及所述辅助开关管Tb的第一端；所述第三开关管T3的控制端电性连接所述正扫控端U2D，所述第三开关管T3的第一端电性连接所述第(n+1)级时钟端CK(n+1)，所述第三开关管T3的第二端所述第四开关管T4的第二端及所述第五开关管T5的控制端；所述第四开关管T4的控制端电性连接所述负扫控端D2U，所述第四开关管T4的第一端电性连接所述第(n-1)级时钟端CK(n-1)，所述第四开关管T4的第二端电性连接所述第三开关管T3的第二端及所述第五开关管T5的控制端；所述第五开关管T5的控制端电性连接所述第三开关管T3的第二端及所述第四开关管T4的第二端，所述第五开关管T5的第一端电性连接所述高位端，所述第五开关管T5的第二端电性连接所述第六开关管T6的第一端、所述漏路开关管4的控制端及所述输出模块2；所述第六开关管T6的控制端电性连接所述第一开关管T1的第二端、所述第二开关管T2的第二端、所述补充开关管Ta的控制端及所述辅助开关管Tb的第一端，所述第六开关管T6的第一端电性连接所述第五开关管的第二端、所述输出模块2及所述漏路开关管4的控制端，所述第六开关管T6的第二端电性连接所述低位端。
在一实施例中，如图1所示，所述输出模块2可包括一中继单元21、一上拉单元22、一下拉单元23、一侦测单元24、一第一储能件25及一第二储能件26，所述中继单元21电性连接所述高位端VGH、所述补充开关管Ta、所述辅助开关管Tb及所述上拉单元22，所述中继单元21、所述补充开关管Ta及所述辅助开关管Tb共同连接形成一第一节点Q；所述上拉单元22电性连接所述中继单元21、所述第n级时钟端CK(n)及所述第n级扫描端G(n)；所述下拉单元23电性连接所述第n级扫描端G(n)、所述低位端VGL、所述漏路开关管4及所述控制模块4；所述侦测单元24电性连接所述第n级扫描端G(n)、所述低位端VGL、所述可控端GAS2、所述下拉单元23、所述漏路开关管4及所述控制模块1，所述下拉单元23、所述侦测单元24、所述漏路开关管4及所述控制模块1共同连接形成一第二节点P；所述第一储能件25(如电容器)电性连接于所述第一节点Q与所述低位端VGL之间，所述第二储能件26(如电容器)电性连接于所述第二节点P与所述低位端VGL之间。
具体地，如图1所示，所述中继单元21可包括一第七开关管T7，所述第七开关管T7的控制端电性连接所述高位端VGH，所述第七开关管T7的第一端电性连接所述第一节点Q，所述第七开关管T7的第二端电性连接所述上拉单元22。
具体地，如图1所示，所述上拉单元22可包括一第八开关管T8，所述第八开关管T8的控制端电性连接所述中继单元21(如所述第七开关管T7的第二端)，所述第八开关管T8的第一端电性连接所述第n级时钟端CK(n)，所述第八开关管T8的第二端电性连接所述第n级扫描端G(n)。
具体地，如图1所示，所述下拉单元23可包括一第九开关管T9，所述第九开关管T9的控制端电性连接所述第二节点P，所述第九开关管T9的第一端电性连接所述第n级扫描端G(n)，所述第九开关管T9的第二端电性连接所述低位端VGL。
具体地，如图1所示，所述侦测单元24可包括一第十开关管T10、一第十一开关管T11及一第十二开关管T12，所述第十开关管T10的控制端电性连接所述第十开关管T10的第一端及所述第十一开关管T11的控制端，所述第十开关管T10的第二端电性连接所述第n级扫描端G(n)，所述第十一开关管T11的第一端电性连接所述第二节点P，所述第十一开关管T11的一第二端电性连接所述低位端VGL，所述第十二开关管T12的控制端电性连接所述可控端GAS2，所述第十二开关管T12的第一端电性连接所述第n级扫描端G(n)，所述第十二开关管T12的第二端电性连接所述低位端VGL。
在一些实施例中，如图1及图2所示，所述上拉补充模块3的补充开关管Ta的控制端电性连接所述辅助开关管Tb的第一端及所述控制模块1的第一晶体管T1，所述补充开关管Ta的第一端及所述辅助开关管Tb的控制端电性连接所述高位端VGH，所述补充开关管Ta的第二端电性连接所述辅助开关管Tb的第二端、所述输出模块2的所述中继单元21及第一储能件25；此外，所述漏路开关管4的控制端电性连接所述控制模块1的第五开关管T5、第六开关管T6及所述输出模块2的所述下拉单元23、所述侦测单元24及第二储能件26，所述漏路开关管4的第一端电性连接所述辅助开关管Tb的第一端(如图1所示)或第二端(如图2所示)，所述漏路开关管4的第二端电性连接所述低位端VGL。
以下举例说明上述GOA电路运作时的态样，以ITP的面板为例，需要在一帧画面的显示时间内插入若干个触控期(TP Term)，在所述显示时间内，可经由所述正扫控端U2D及负扫控端D2U输入的信号控制逐行扫描顺序，配合所述第(n-2)级扫描端G(n-2)、第(n+2)级扫描端G(n+2)、第(n+1)级时钟端CK(n+1)、第n级时钟端CK(n)、第(n-1)级时钟端CK(n-1)、可控端GAS2、高位端VGH及低位端VGL输入工作所需的信号，可于所述第n级扫描端G(n)输出第n级扫描信号，用于逐行扫描；在所述触控期内，所述第一节点Q可以维持电路运作所需的电位，以确保电路工作正常。以下特别说明所述GOA电路设有所述上拉补充模块3所能达成的特点。
首先，观察还未设置所述上拉补充模块的GOA电路(如图3所示)，其中GAS1信号(位于第十一开关管T11栅极的信号)在正常工作情况为常态低电位(Low)，所述可控端GAS2在触控期由常态显示(Normal Display)时的常态低电位(Low)跳变为高电位(High)。通常，当前ITP的面板需要在一帧画面显示时间内插入若干个TP Term，用于实现Touch功能，此时，NMOS的GOA电路须通过第一储能件25维持(Holding)级传(cascaded)所需要的高电位(High)，但是，由于NMOS TFT并不是理想开关器件，即使在关闭状态(OFF)的情况下，依然会存在一定的漏电流(leakage current)，如TP Term持续时间较长，则TP暂停级需要维持高电位的时间就会很长，所述漏电流将会降低GOA的级传稳定性。
另一方面，在GOA电路设置上述上拉补充模块3后，以第一实施例为例，如图1所示，所述漏路开关管4的第一端电性连接所述辅助开关管Tb的第一端，当第一节点Q处于高电位(High)的级传Holding状态时，尤其是处于TP Term的Holding状态时，所述漏路开关管4是关态(OFF)，所述漏路开关管4虽会存在一定的漏电流(由第一节点Q到低位端VGL)，以使第一节点Q降低电位，但需注意的是，此时，所述补充开关管Ta也是处于关闭状态，也会存在一定的漏电流(由高位端VGH到第一节点Q)，以使第一节点Q提高电位，因而减缓所述漏路开关管4漏电对所述第一节点Q电位的影响，进而增大电路在TP Term的边际范围(Margin)，使电路正常工作，提高电路可靠度。
此外，所述辅助开关管Tb工作为常开型TFT，但是即使是开态(ON)，TFT的电阻也可以达到兆欧级别，能够辅助所述漏路开关管4的漏电流部分地降低。另外，如图1所示，所述辅助开关管Tb左侧的电位理论上要稍高于右边，所述辅助开关管Tb左侧电压，又是所述补充开关管Ta的控制端(栅极)电压，有利于所述补充开关管Ta往所述第一节点Q漏电，使所述第一节点Q维持高电位，以确保电路正常工作。
需被注意的是，所述漏路开关管4虽仍存在漏电流而会降低第一节点Q电位，但是，本发明与现有技术的GOA电路阻绝电泄途径方式不同的是，所述漏路开关管4的电泄途径并未被阻绝，替代地，所述上拉补充模块3利用所述补充开关管Ta的漏电流特性，对第一储能件25即时性地补充电能，以减缓所述漏路开关管4漏电的影响，进而大致地维持第一节点Q的电位，以确保电路工作正常，避免显示装置的面板出现分屏现象。
此外，如图2所示，本发明第二实施例的GOA电路也设有上述上拉补充模块3(如所述漏路开关管4的第一端电性连接所述辅助开关管Tb的第二端)，相较于第一实施例，此实施例的好处在于更有利于级传的进行，在进行级传时，所述第一开关管T1可以迅速的提升所述第六开关管T6的控制端(栅极)的电压，进而迅速关闭所述漏路开关管4，完成级传的功能，相应的对所述第一开关管T1的控制端(栅极)的电位要求会比第一实施例低一些，使得GOA电路即使经历TP term仍然保持正常的功能，避免显示装置的面板出现分屏现象。
应被理解的是，上述GOA电路的驱动架构可以采用交错式(Interlace)或者双驱式；所述GOA电路的相阶(Phase)数可以使用4CK，也可以是6CK或8CK。以4CK为例，以两个GOA电路为一个循环，可以采用两个相同的上述GOA电路作为一第一GOA电路及一第二GOA电路，并将四个时钟信号(CK1、CK2、CK3、CK4)输入到所述GOA电路及一第二GOA电路。例如：如图1及图2所示，可将CK1输入到所述第一GOA电路的所述第n级时钟端CK(n)，另将CK2、CK4分别输入到所述第一GOA电路及所述第二GOA电路的所述第(n+1)级时钟端CK(n+1)、所述第(n-1)级时钟端CK(n-1)，另将CK3输入到所述第二GOA电路的所述第n级时钟端CK(n)，这是本领域技术人员可以理解的，不再赘述于此。
本发明的另一方面提供一种显示装置，包括一阵列基板及如上所述的GOA电路，所述GOA电路设置于所述阵列基板上。所述显示装置可以被配置成以下项目中的其中一种：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或部件，所述显示装置能与上述GOA电路解决同样的问题及产生同样的效果。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (17)

  1. 一种GOA电路，其包括级联的多级子电路，在所述多级子电路中的一第n级子电路包括：
    一控制模块，电性连接一正扫控端、一负扫控端、一第(n-2)级扫描端、一第(n+2)级扫描端、一第(n+1)级时钟端、一第(n-1)级时钟端、一高位端及一低位端；
    一输出模块，电性连接所述高位端、所述低位端、一第n级时钟端、一第n级扫描端及一可控端；
    一上拉补充模块，包括一补充开关管及一辅助开关管，所述补充开关管电性连接所述辅助开关管、所述高位端、所述控制模块及所述输出模块，所述辅助开关管电性连接所述补充开关管、所述高位端、所述控制模块及所述输出模块；及
    一漏路开关管，电性连接所述控制模块、所述输出模块、所述补充开关管、所述辅助开关管及所述低位端；
    其中，所述控制模块包括一第一开关管、一第二开关管、一第三开关管、一第四开关管、一第五开关管及一第六开关管，所述第一开关管电性连接所述第(n-2)级扫描端、所述正扫控端、所述第二开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第二开关管电性连接所述第(n+2)级扫描端、所述负扫控端、所述第一开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第三开关管电性连接所述正扫控端、所述第(n+1)级时钟端、所述第四开关管及所述第五开关管，所述第四开关管电性连接所述负扫控端、所述第(n-1)级时钟端、所述第三开关管及所述第五开关管，所述第五开关管电性连接所述高位端、所述第三开关管、所述第四开关管、所述第六开关管、所述漏路开关管及所述输出模块，所述第六开关管电性连接所述低位端、所述第一开关管、所述第二开关管、所述第五开关管、所述补充开关管、所述辅助开关管、所述输出模块及所述漏路开关管；
    所述输出模块包括一中继单元、一上拉单元、一下拉单元、一侦测单元、一第一储能件及一第二储能件，所述中继单元电性连接所述高位端、所述补充开关管、所述辅助开关管及所述上拉单元，所述中继单元、所述补充开关管及所述辅助开关管共同连接形成一第一节点，所述上拉单元电性连接所述中继单元、所述第n级时钟端及所述第n级扫描端，所述下拉单元电性连接所述第n级扫描端、所述低位端、所述漏路开关管及所述控制模块，所述侦测单元电性连接所述第n级扫描端、所述低位端、所述可控端、所述下拉单元、所述漏路开关管及所述控制模块，所述下拉单元、所述侦测单元、所述漏路开关管及所述控制模块共同连接形成一第二节点，所述第一储能件电性连接于所述第一节点与所述低位端之间，所述第二储能件电性连接于所述第二节点与所述低位端之间。
  2. 如权利要求1所述的GOA电路，其中，所述补充开关管的一控制端电性连接所述辅助开关管的一第一端及所述控制模块，所述补充开关管的一第一端及所述辅助开关管的一控制端电性连接所述高位端，所述补充开关管的一第二端电性连接所述辅助开关管的一第二端及所述输出模块。
  3. 如权利要求2所述的GOA电路，其中，所述漏路开关管的一控制端电性连接所述控制模块及所述输出模块，所述漏路开关管的一第一端电性连接所述辅助开关管的第一端或所述辅助开关管的第二端，所述漏路开关管的一第二端电性连接所述低位端。
  4. 如权利要求1所述的GOA电路，其中，所述中继单元包括一第七开关管，所述第七开关管的一控制端电性连接所述高位端，所述第七开关管的一第一端电性连接所述第一节点，所述第七开关管的一第二端电性连接所述上拉单元。
  5. 如权利要求1所述的GOA电路，其中，所述上拉单元包括一第八开关管，所述第八开关管的一控制端电性连接所述中继单元，所述第八开关管的一第一端电性连接所述第n级时钟端，所述第八开关管的一第二端电性连接所述第n级扫描端。
  6. 如权利要求1所述的GOA电路，其中，所述下拉单元包括一第九开关管，所述第九开关管的一控制端电性连接所述第二节点，所述第九开关管的一第一端电性连接所述第n级扫描端，所述第九开关管的一第二端电性连接所述低位端。
  7. 如权利要求1所述的GOA电路，其中，所述侦测单元包括一第十开关管、一第十一开关管及一第十二开关管，所述第十开关管的一控制端电性连接所述第十开关管的一第一端及所述第十一开关管的一控制端，所述第十开关管的一第二端电性连接所述第n级扫描端，所述第十一开关管的一第一端电性连接所述第二节点，所述第十一开关管的一第二端电性连接所述低位端，所述第十二开关管的一控制端电性连接所述可控端，所述第十二开关管的一第一端电性连接所述第n级扫描端，所述第十二开关管的一第二端电性连接所述低位端。
  8. 一种GOA电路，其包括级联的多级子电路，在所述多级子电路中的一第n级子电路包括：
    一控制模块，电性连接一正扫控端、一负扫控端、一第(n-2)级扫描端、一第(n+2)级扫描端、一第(n+1)级时钟端、一第(n-1)级时钟端、一高位端及一低位端；
    一输出模块，电性连接所述高位端、所述低位端、一第n级时钟端、一第n级扫描端及一可控端；
    一上拉补充模块，包括一补充开关管及一辅助开关管，所述补充开关管电性连接所述辅助开关管、所述高位端、所述控制模块及所述输出模块，所述辅助开关管电性连接所述补充开关管、所述高位端、所述控制模块及所述输出模块；及
    一漏路开关管，电性连接所述控制模块、所述输出模块、所述补充开关管、所述辅助开关管及所述低位端。
  9. 如权利要求8所述的GOA电路，其中，所述补充开关管的一控制端电性连接所述辅助开关管的一第一端及所述控制模块，所述补充开关管的一第一端及所述辅助开关管的一控制端电性连接所述高位端，所述补充开关管的一第二端电性连接所述辅助开关管的一第二端及所述输出模块。
  10. 如权利要求9所述的GOA电路，其中，所述漏路开关管的一控制端电性连接所述控制模块及所述输出模块，所述漏路开关管的一第一端电性连接所述辅助开关管的第一端或所述辅助开关管的第二端，所述漏路开关管的一第二端电性连接所述低位端。
  11. 如权利要求8所述的GOA电路，其中，所述控制模块包括一第一开关管、一第二开关管、一第三开关管、一第四开关管、一第五开关管及一第六开关管，所述第一开关管电性连接所述第(n-2)级扫描端、所述正扫控端、所述第二开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第二开关管电性连接所述第(n+2)级扫描端、所述负扫控端、所述第一开关管、所述第六开关管、所述补充开关管及所述辅助开关管，所述第三开关管电性连接所述正扫控端、所述第(n+1)级时钟端、所述第四开关管及所述第五开关管，所述第四开关管电性连接所述负扫控端、所述第(n-1)级时钟端、所述第三开关管及所述第五开关管，所述第五开关管电性连接所述高位端、所述第三开关管、所述第四开关管、所述第六开关管、所述漏路开关管及所述输出模块，所述第六开关管电性连接所述低位端、所述第一开关管、所述第二开关管、所述第五开关管、所述补充开关管、所述辅助开关管、所述输出模块及所述漏路开关管。
  12. 如权利要求8所述的GOA电路，其中，所述输出模块包括一中继单元、一上拉单元、一下拉单元、一侦测单元、一第一储能件及一第二储能件，所述中继单元电性连接所述高位端、所述补充开关管、所述辅助开关管及所述上拉单元，所述中继单元、所述补充开关管及所述辅助开关管共同连接形成一第一节点，所述上拉单元电性连接所述中继单元、所述第n级时钟端及所述第n级扫描端，所述下拉单元电性连接所述第n级扫描端、所述低位端、所述漏路开关管及所述控制模块，所述侦测单元电性连接所述第n级扫描端、所述低位端、所述可控端、所述下拉单元、所述漏路开关管及所述控制模块，所述下拉单元、所述侦测单元、所述漏路开关管及所述控制模块共同连接形成一第二节点，所述第一储能件电性连接于所述第一节点与所述低位端之间，所述第二储能件电性连接于所述第二节点与所述低位端之间。
  13. 如权利要求12所述的GOA电路，其中，所述中继单元包括一第七开关管，所述第七开关管的一控制端电性连接所述高位端，所述第七开关管的一第一端电性连接所述第一节点，所述第七开关管的一第二端电性连接所述上拉单元。
  14. 如权利要求12所述的GOA电路，其中，所述上拉单元包括一第八开关管，所述第八开关管的一控制端电性连接所述中继单元，所述第八开关管的一第一端电性连接所述第n级时钟端，所述第八开关管的一第二端电性连接所述第n级扫描端。
  15. 如权利要求12所述的GOA电路，其中，所述下拉单元包括一第九开关管，所述第九开关管的一控制端电性连接所述第二节点，所述第九开关管的一第一端电性连接所述第n级扫描端，所述第九开关管的一第二端电性连接所述低位端。
  16. 如权利要求12所述的GOA电路，其中，所述侦测单元包括一第十开关管、一第十一开关管及一第十二开关管，所述第十开关管的一控制端电性连接所述第十开关管的一第一端及所述第十一开关管的一控制端，所述第十开关管的一第二端电性连接所述第n级扫描端，所述第十一开关管的一第一端电性连接所述第二节点，所述第十一开关管的一第二端电性连接所述低位端，所述第十二开关管的一控制端电性连接所述可控端，所述第十二开关管的一第一端电性连接所述第n级扫描端，所述第十二开关管的一第二端电性连接所述低位端。
  17. 一种显示装置，包括一阵列基板，还包括如权利要求8所述的GOA电路，所述GOA电路设置于所述阵列基板。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979407B (zh) * 2019-04-22 2020-06-16 深圳市华星光电半导体显示技术有限公司 一种goa电路、tft基板及显示装置
CN111477153A (zh) * 2020-05-08 2020-07-31 武汉华星光电技术有限公司 Goa电路和显示面板
CN111477181B (zh) 2020-05-22 2021-08-27 京东方科技集团股份有限公司 栅极驱动电路、显示基板、显示装置和栅极驱动方法
CN111627402B (zh) * 2020-06-01 2021-09-24 武汉华星光电技术有限公司 Goa电路、显示面板以及显示装置
CN111681625A (zh) * 2020-06-23 2020-09-18 武汉华星光电技术有限公司 驱动电路、显示面板及显示装置
CN115602124A (zh) * 2021-07-08 2023-01-13 乐金显示有限公司（Kr） 选通驱动器及包括其的显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261343A (zh) * 2015-11-24 2016-01-20 武汉华星光电技术有限公司 一种goa驱动电路
CN107093412A (zh) * 2017-06-29 2017-08-25 京东方科技集团股份有限公司 显示基板、显示器件和像素电极驱动方法
WO2018016178A1 (ja) * 2016-07-20 2018-01-25 三菱電機株式会社 シフトレジスタ回路および表示パネル
US20180151593A1 (en) * 2016-11-29 2018-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011111529A1 (en) * 2010-03-12 2011-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN202677790U (zh) * 2012-04-13 2013-01-16 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN202905121U (zh) * 2012-09-13 2013-04-24 北京京东方光电科技有限公司 移位寄存器单元电路、移位寄存器、阵列基板及显示设备
CN104091577B (zh) * 2014-07-15 2016-03-09 深圳市华星光电技术有限公司 应用于2d-3d信号设置的栅极驱动电路
CN105047168B (zh) * 2015-09-01 2018-01-09 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN105427829B (zh) * 2016-01-12 2017-10-17 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105679262B (zh) * 2016-01-12 2017-08-29 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105976781B (zh) * 2016-07-14 2018-08-14 武汉华星光电技术有限公司 Goa电路
KR102607402B1 (ko) * 2016-10-31 2023-11-30 엘지디스플레이 주식회사 게이트 구동 회로와 이를 이용한 표시장치
CN108010495B (zh) * 2017-11-17 2019-12-13 武汉华星光电技术有限公司 一种goa电路
CN108091308B (zh) * 2017-12-08 2019-03-22 武汉华星光电技术有限公司 一种goa电路
US10339887B1 (en) 2017-12-08 2019-07-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit
US10614313B2 (en) * 2017-12-12 2020-04-07 International Business Machines Corporation Recognition and valuation of products within video content

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261343A (zh) * 2015-11-24 2016-01-20 武汉华星光电技术有限公司 一种goa驱动电路
WO2018016178A1 (ja) * 2016-07-20 2018-01-25 三菱電機株式会社 シフトレジスタ回路および表示パネル
US20180151593A1 (en) * 2016-11-29 2018-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device
CN107093412A (zh) * 2017-06-29 2017-08-25 京东方科技集团股份有限公司 显示基板、显示器件和像素电极驱动方法

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