WO2020001603A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020001603A1
WO2020001603A1 PCT/CN2019/093627 CN2019093627W WO2020001603A1 WO 2020001603 A1 WO2020001603 A1 WO 2020001603A1 CN 2019093627 W CN2019093627 W CN 2019093627W WO 2020001603 A1 WO2020001603 A1 WO 2020001603A1
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Prior art keywords
reset
terminal
transistor
control
output
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PCT/CN2019/093627
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English (en)
French (fr)
Inventor
刘帅南
王立冬
包欢
唐建业
项得胜
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/623,541 priority Critical patent/US11302242B2/en
Publication of WO2020001603A1 publication Critical patent/WO2020001603A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the GOA Gate On Array
  • the present disclosure provides a shift register unit, which includes a reset circuit and a reset control circuit.
  • the reset circuit is connected to a pull-up node for resetting the potential of the pull-up node in a reset phase;
  • the reset control circuit is connected to the reset circuit, and is configured to maintain a potential of the pull-up node at a first voltage in an output stage of each display cycle.
  • the reset circuit includes a reset transistor, a gate of the reset transistor is connected to a reset control terminal, a first pole of the reset transistor is connected to a pull-up node, and a second pole of the reset transistor is connected to a reset voltage.
  • Terminal connection, the first and second electrodes are a source and a drain, respectively;
  • the reset control circuit is connected to the reset control terminal and the reset voltage terminal, and controls the potential of the reset control terminal and / or the potential of the reset voltage terminal to control the reset transistor in the output stage. To the locked state.
  • the reset control circuit under the control of the reverse lock control terminal, turns on the connection between the reset control terminal and the reset voltage terminal to control the gate-source voltage of the reset transistor to be a predetermined voltage.
  • a predetermined voltage Within the voltage range
  • the reset control circuit disconnects the reset control terminal from the reset voltage terminal under the control of the reverse lock control terminal.
  • the reset transistor is an n-type transistor, and the predetermined voltage range is less than or equal to 0V; or, the reset transistor is a p-type transistor, and the predetermined voltage range is greater than or equal to 0V.
  • the reverse lock control terminal includes a first reverse lock control terminal and a second reverse lock control terminal; the first reverse lock control terminal is connected to the pull-up node, and the second reverse lock control terminal Connected to the clock control terminal to the lock control terminal;
  • the reset control circuit includes a first lock transistor and a second lock transistor, wherein:
  • a gate of the first lock transistor is connected to the pull-up node, and a first pole of the first lock transistor is connected to the reset voltage terminal;
  • the gate of the second lock transistor is connected to the clock signal terminal, the first pole of the second lock transistor is connected to the second pole of the first lock transistor, and the second pole of the second lock transistor And connected to the reset control terminal.
  • the shift register unit further includes an output circuit
  • the output circuit is respectively connected to the pull-up node, the clock signal terminal and the gate drive signal output terminal, and is used to control the clock signal terminal in the input phase and the output phase under the control of the pull-up node.
  • the output clock signal is written into the gate driving signal output terminal;
  • the reset circuit is also connected to the gate drive signal output terminal, and is used to control the reset voltage output from the reset voltage terminal to be written into the gate drive signal under the control of the reset control terminal during the reset phase.
  • the output circuit includes an output transistor, and the reset circuit further includes an output reset transistor, wherein:
  • a gate of the output transistor is connected to the pull-up node, a first pole of the output transistor is connected to the clock signal terminal, and a second pole of the output transistor is connected to a gate drive signal output terminal;
  • the gate of the output reset transistor is connected to the reset control terminal, the first pole of the output reset transistor is connected to the gate drive signal output terminal, and the second pole of the output reset transistor is connected to the reset voltage. ⁇ ⁇ End connection.
  • the shift register unit according to the present disclosure further includes:
  • An input circuit connected to the input terminal and the pull-up node, respectively, for controlling the potential of the pull-up node under the control of the input terminal in the input stage;
  • the storage circuit is connected to the pull-up node, and is configured to maintain a potential of the pull-up node in an input stage, and pull up the potential of the pull-up node by bootstrapping in an output stage.
  • the input circuit includes an input transistor, a gate of the input transistor and a first pole of the input transistor are both connected to the input terminal, and a second pole of the input transistor is connected to the pull-up node connection;
  • the storage circuit includes a storage capacitor, a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to a gate driving signal output terminal.
  • the present disclosure also provides a driving method of a shift register unit for driving the above-mentioned shift register unit.
  • the driving method of the shift register unit includes: in an output stage of each display cycle, through the reset control The circuit maintains the potential of the pull-up node at a first voltage.
  • the reset circuit includes a reset transistor, a gate of the reset transistor is connected to a reset control terminal, a first pole of the reset transistor is connected to a pull-up node, and a second pole of the reset transistor is connected to a reset voltage. Terminal connection; the maintaining the potential of the pull-up node at a first voltage by the reset control circuit includes:
  • the reset control circuit controls the potential of the reset control terminal and / or the potential of the reset voltage terminal during the output stage to place the reset transistor in a reverse lock state.
  • the reset control circuit controlling the potential of the reset control terminal and / or the potential of the reset voltage terminal to place the reset transistor in a reverse lock state during the output stage includes:
  • the reset control circuit under the control of the reverse lock control terminal, turns on the connection between the reset control terminal and the reset voltage terminal to control the gate-source voltage of the reset transistor to be within a predetermined voltage range Inside;
  • the reset transistor is an n-type transistor, and the predetermined voltage range is less than or equal to 0V; or the reset transistor is a p-type transistor, and the predetermined voltage range is greater than or equal to 0V.
  • the display cycle further includes a reset phase;
  • the driving method includes:
  • the reset control circuit is controlled to open the connection between the reset control terminal and the reset voltage terminal under the control of the reverse lock control terminal.
  • the reverse lock control terminal includes a first reverse lock control terminal and a second reverse lock control terminal; the first reverse lock control terminal is connected to the pull-up node, and the second reverse lock control terminal Connected to the lock control terminal and the clock signal terminal; the driving method includes:
  • the reset control circuit turns on the connection between the reset voltage terminal and the reset control terminal under the control of the pull-up node and the clock signal terminal to control the reset transistor.
  • the gate-source voltage is within a predetermined voltage range
  • the reset control circuit disconnects the connection between the reset voltage terminal and the reset control terminal under the control of the clock signal terminal.
  • the method for driving the shift register unit further includes:
  • the reset circuit controls the potential of the pull-up node to a reset voltage, and the reset circuit controls the gate drive signal output terminal to output the reset voltage;
  • the reset voltage is a voltage input from the reset voltage terminal.
  • the display cycle further includes an input phase and an output cut-off hold phase
  • the driving method of the shift register unit further includes:
  • the reset control circuit disconnects the connection between the reset control terminal and the reset voltage terminal, so that the gate-source voltage of the reset transistor is at the predetermined Within the voltage range
  • a reset control circuit disconnects the connection between the reset control terminal and the reset voltage terminal, so that the gate-source voltage of the reset transistor is at Within the predetermined voltage range.
  • the present disclosure also provides a gate driving circuit including a plurality of stages of the above-mentioned shift register units; the shift register unit further includes a gate driving signal output terminal and an input terminal;
  • each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent previous-stage shift register unit;
  • the reset control terminal of each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent next-stage shift register unit.
  • the present disclosure also provides a display device including the above gate driving circuit.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of an embodiment of a shift register unit according to the present disclosure.
  • FIG. 4 is a schematic diagram of a cascade connection of two-stage shift register units included in a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 5 is an operation timing diagram of the two-stage shift register unit shown in FIG. 4.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the main purpose of the present disclosure is to provide a shift register unit, a driving method, a gate driving circuit, and a display device, which solve the related art because carriers are generated by the reset transistor in the shift register unit due to light.
  • the leakage current is large, so that the potential of the pull-up node is pulled down during the output stage, so that the shift register unit cannot stably output the gate driving signal, and the problem of abnormal display occurs.
  • the shift register unit according to the embodiment of the present disclosure includes a reset circuit, and the reset circuit is connected to the pull-up node for resetting the pull-up node in a reset phase.
  • the shift register unit further includes a reset control circuit;
  • the reset control circuit is connected to the reset circuit, and is configured to control to reduce a leakage current of the reset circuit in an output stage, so as to maintain a potential of the pull-up node to a first voltage.
  • the output stage is the stage where the clock signal terminal outputs the gate driving signal to the gate driving signal output terminal through the output circuit.
  • the first voltage may be a high voltage, but is not limited thereto.
  • the reset control circuit reduces the leakage current of the reset circuit by controlling to maintain the potential of the pull-up node PU. Is the first voltage, so that the output circuit included in the shift register unit connected to the pull-up node PU can normally output a gate driving signal, and the corresponding row of pixel units receives the gate driving signal, and the corresponding row of pixel units The included switching transistor is turned on to write the data voltage on the corresponding column data line into the corresponding column pixel unit in the corresponding row to enable normal display.
  • the reset circuit may include a reset transistor, a gate of the reset transistor is connected to a reset control terminal, a first pole of the reset transistor is connected to a pull-up node, and a second pole of the reset transistor is connected to a reset Voltage terminal connection;
  • the reset control circuit is connected to the reset control terminal and / or the reset voltage terminal, and is configured to control the voltage of the reset control terminal and / or the potential of the reset voltage terminal in the output stage to control the voltage reduction.
  • the leakage current of the reset transistor is reduced.
  • a reset control circuit is added to control the reset control in an output stage (the output stage is a stage in which the shift register unit outputs a corresponding gate driving signal). And / or the potential of the reset voltage terminal, so as to reduce the leakage current of the reset transistor included in the reset circuit on the basis of not changing the existing timing, to achieve the control of the leakage current of the reset transistor, and to avoid The influence of the leakage current of the reset transistor on the output of the gate driving signal will not affect the display.
  • the reset control circuit may control the potential of the reset control terminal during the output stage, or control the potential of the reset control terminal and the potential of the reset voltage terminal to make the reset circuit
  • the gate-source voltage of the included reset transistor is within a predetermined voltage range, so that the reset transistor is in a reverse lock (ie, the transistor is off) state, thereby reducing the leakage current of the reset transistor in the output stage;
  • the reset transistor is an n-type transistor, and the predetermined voltage range is less than or equal to 0V; or, the reset transistor is a p-type transistor, and the predetermined voltage range is greater than or equal to 0V.
  • the gate-source voltage of the reset transistor is a positive voltage, and even if the gate-source voltage is less than the threshold voltage of the reset transistor, a leakage due to backlight illumination will occur.
  • the current phenomenon makes the output of the gate driving circuit unstable, and the display module generates an abnormal display.
  • the embodiments of the present disclosure need to ensure that the reset transistor is in a reverse lock state during the output stage, that is, when the reset transistor is an n-type transistor
  • the gate-source voltage of the reset transistor is less than or equal to 0; when the reset transistor is a p-type transistor, the gate-source voltage of the reset transistor is greater than or equal to 0, so that the leakage current of the reset transistor is kept at a minimum state, Does not affect the normal display of the display module.
  • the reset control circuit may reduce a leakage current of the reset transistor by controlling a potential of the reset voltage terminal in an output stage.
  • the potential of the reset voltage terminal may be set to a first voltage, so that the potential of the source of the reset transistor and the potential of the drain of the reset transistor are the same to reduce the leakage current of the reset transistor.
  • the reset control circuit may be used to control the connection between the reset control terminal and the reset voltage terminal under the control of the reverse lock control terminal in the output stage to control the reset.
  • the gate-source voltage of the transistor is within a predetermined voltage range
  • the reset control circuit may be further configured to control the disconnection between the reset control terminal and the reset voltage terminal under the control of the reverse lock control terminal in the reset phase, so that the reset circuit includes The reset transistor can reset the pull-up node under the control of the reset control terminal, so that the reset circuit included in the shift register unit can pull down the potential of the gate driving signal;
  • the reset transistor is an n-type transistor, and the predetermined voltage range is less than or equal to 0V; or, the reset transistor is a p-type transistor, and the predetermined voltage range is greater than or equal to 0V.
  • the reverse lock control terminal may include a first reverse lock control terminal and a second reverse lock control terminal, and the first reverse lock control terminal may be connected to the pull-up node, and the first The two reverse lock control terminals can be connected to the clock signal terminal, but not limited to this.
  • the reset control circuit may include a first lock transistor and a second lock transistor, wherein:
  • a gate of the first lock transistor is connected to the pull-up node, and a first pole of the first lock transistor is connected to the reset voltage terminal;
  • the gate of the second lock transistor is connected to the clock signal terminal, the first pole of the second lock transistor is connected to the second pole of the first lock transistor, and the second pole of the second lock transistor And connected to the reset control terminal.
  • the shift register unit may further include an output circuit
  • the output circuit is respectively connected to the pull-up node, the clock signal terminal and the gate drive signal output terminal, and is used to control the clock in the input phase and the output phase under the control of the pull-up node.
  • a clock signal output from a signal terminal is written into the gate driving signal output terminal;
  • the reset circuit is also connected to the gate drive signal output terminal, and is used to control the gate drive signal output terminal to be connected to the reset voltage terminal under the control of the reset control terminal during the reset phase to The voltage at the output terminal of the gate driving signal is reset.
  • the shift register unit may further include:
  • An input circuit connected to the input terminal and the pull-up node, respectively, for controlling the potential of the pull-up node under the control of the input terminal in the input stage;
  • the storage circuit is connected to the pull-up node, and is configured to maintain a potential of the pull-up node in an input stage, and pull up the potential of the pull-up node by bootstrapping in an output stage.
  • the input circuit may include an input transistor, a gate of the input transistor and a first pole of the input transistor are both connected to the input terminal, and a second pole of the input transistor is connected to the pull-up Node connection
  • the storage circuit includes a storage capacitor, a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to a gate driving signal output terminal.
  • the shift register unit, the driving method, the gate driving circuit, and the display device described in the present disclosure are additionally provided with a reset control circuit.
  • the reset control circuit reduces the leakage current of the reset circuit by controlling to maintain the reset current.
  • the switching transistor included in the unit is turned on to write the data voltage on the corresponding column data line into the corresponding row pixel unit to enable normal display.
  • the shift register unit includes an input circuit 11, a reset circuit 12, an output circuit 13, a storage circuit 14, and a reset control circuit 15, wherein:
  • the input circuit 11 is respectively connected to an input terminal INPUT and a pull-up node PU, and is used to control the connection between the input terminal INPUT and the pull-up node PU during the input phase under the control of the input terminal INPUT.
  • the first voltage may be a high voltage, but not limited to this;
  • the reset circuit 12 is respectively connected to a reset control terminal RESET, a reset voltage terminal EN1, the pull-up node PU, and a gate drive signal output terminal OUTPUT, and is used for resetting under the control of the reset control terminal RESET, Controls writing the reset voltage output from the reset voltage terminal EN1 to the pull-up node PU to reset the potential of the pull-up node PU, and is used to control the reset voltage output from the reset voltage terminal EN1 during the reset phase. Writing to the gate driving signal output terminal OUTPUT to reset the potential of the gate driving signal output from the gate driving signal output terminal OUTPUT;
  • the output circuit 13 is respectively connected to the pull-up node PU, a clock signal terminal CLK, and a gate drive signal output terminal OUTPUT, and is configured to control the clock signal during the input phase under the control of the pull-up node PU.
  • the clock signal output from the terminal CLK is written into the gate driving signal output terminal OUTPUT, so that the gate driving signal output terminal OUTPUT outputs an invalid level (the invalid level refers to the gate and The level of the switching transistor connected to the output terminal of the gate driving signal is turned off), and the output circuit 13 is further configured to control the clock signal output from the clock signal terminal CLK under the control of the pull-up node PU in the output stage Write into the gate drive signal output terminal OUTPUT, so that the gate drive signal output terminal OUTPUT outputs a gate drive signal (the gate drive signal is capable of enabling a gate included in a pixel unit and the gate drive signal (The signal that the switching transistor connected to the output OUTPUT is turned on);
  • a first end of the storage circuit 14 is connected to the pull-up node PU, and a second end of the storage circuit 14 is connected to the gate drive signal output terminal OUTPUT; the storage circuit 14 is used to maintain the input stage The potential of the pull-up node PU is pulled up in the output stage by a bootstrap;
  • the reset circuit 12 includes a reset transistor (not shown in FIG. 1), a gate of the reset transistor is connected to a reset control terminal RESET, a first pole of the reset transistor is connected to a pull-up node PU, and the reset transistor The second electrode is connected to the reset voltage terminal EN1;
  • the reset control circuit 15 is respectively connected to a reset control terminal RESET, a clock signal terminal CLK, the pull-up node PU, and the reset voltage terminal EN1, and is used to output the clock signal terminal CLK and the Under the control of the pull node PU, the reset control terminal RESET is controlled to be connected to the reset voltage terminal EN1 so that the gate-source voltage of the reset transistor (not shown in FIG.
  • a reverse level to the reset transistor refers to: When the reset transistor is an n-type transistor, and the threshold voltage of the reset transistor is a positive voltage, the gate-source voltage of the reset transistor is controlled to be less than or equal to 0V; when the reset transistor is a p-type transistor, the threshold voltage of the reset transistor A negative voltage, controlling the gate-source voltage of the reset transistor to be greater than or equal to 0V;
  • the reset control circuit 15 is further configured to disconnect the connection between the reset control terminal RESET and the reset voltage terminal EN1 during the reset phase under the control of the clock signal terminal CLK, so that the reset In this stage, the reset transistor can be turned on to reset the potential of the pull-up node PU.
  • the shift register unit is provided with a reset control circuit 15 to control the reset control terminal RESET in an output stage (the output stage is a stage in which the shift register unit outputs a corresponding gate driving signal). It is electrically connected to the reset voltage terminal EN1, thereby realizing the management and control of the leakage current of the reset transistor (not shown in FIG. 1, which will be described later in the embodiment) included in the reset circuit 12 without changing the existing timing. In order to avoid the influence of the leakage current of the reset transistor on the output of the gate driving signal, the display is not affected.
  • the reset control circuit 15 turns on the connection between the reset control terminal RESET and the reset voltage terminal EN1.
  • EN1 inputs a low voltage
  • the gate of the reset transistor included in the reset circuit is connected to RESET, Therefore, the gate of the reset transistor is also connected to a low level, so that the reset transistor is in a reverse lock state, thereby avoiding the phenomenon that it is easy to generate a large leakage current when the reset transistor is illuminated;
  • the reset control circuit 15 disconnects the connection between the reset control terminal RESET and the reset voltage terminal EN1, and during the reset phase, RESET outputs a high level, so that the reset transistor can be turned on during the reset phase, so that The reset transistor included in the reset circuit 12 can discharge the pull-up node PU and pull down the potential of the gate driving signal correctly.
  • each display cycle may include an input phase, an output phase, a reset phase, and an output cut-off hold phase in sequence.
  • the clock signal terminal CLK outputs an invalid level.
  • the input circuit 11 controls the potential of the pull-up node PU to be raised, and the storage circuit 14 controls the pull-up node to be maintained.
  • the potential of PU; the output circuit 13 turns on the connection between the gate drive signal output terminal OUTPUT and the clock signal terminal CLK under the control of the pull-up node PU, so that the gate drive signal output terminal OUTPUT outputs Inactive level
  • the clock signal terminal CLK outputs an active level
  • the storage circuit 14 bootstraps the potential of the pull-up node PU
  • the output circuit 13 turns on the gate under the control of the pull-up node PU.
  • the reset control circuit 15 is under the control of the pull-up node PU and the clock signal terminal CLK
  • the connection between the reset voltage terminal EN1 and the reset control terminal RESET is turned on, so that the gate of the reset transistor included in the reset circuit 12 is connected to the low voltage input of the EN1, so that the reset transistor is in a reverse lock state to improve the The leakage phenomenon of the reset transistor included in the reset circuit 12 is described;
  • the reset circuit 12 turns on the connection between the pull-up node PU and the reset voltage terminal EN1 to control the potential of the pull-up node PU.
  • the output circuit 13 disconnects the connection between the gate drive signal output terminal OUTPUT and the clock signal terminal CLK; under the control of the reset control terminal RESET, all The reset circuit 12 turns on the connection between the gate driving signal output terminal OUTPUT and the reset voltage terminal EN1, so that the gate driving signal output terminal OUTPUT outputs a reset voltage (the reset voltage is the reset Voltage input from the voltage terminal); under the control of the clock signal terminal CLK, the reset control circuit 15 disconnects the connection between the reset voltage terminal EN1 and the reset control terminal RESET, so that the reset is performed during the reset phase
  • the reset transistor included in the circuit 12 can be turned on to discharge the pull-up node PU and pull down the potential of the gate drive signal;
  • the reset control circuit 15 disconnects the connection between the reset control terminal RESET and the reset voltage terminal EN1, and the pull-up node PU Under the control of the reset control terminal RESET, the output circuit 13 controls a potential for maintaining a gate driving signal; the gate driving signal is a signal output from the gate driving signal output terminal OUTPUT.
  • the reset control circuit 15 includes a first lock transistor T6 and a second lock transistor T5:
  • a gate of the first lock transistor T6 is connected to the pull-up node PU, and a drain of the first lock transistor T6 is connected to the reset voltage terminal EN1;
  • the gate of the second lock transistor T5 is connected to the clock signal terminal CLK, and the drain of the second lock transistor T5 is connected to the source of the first lock transistor T6.
  • a source is connected to the reset control terminal RESET;
  • the reset circuit 12 includes a reset transistor T3 and an output reset transistor T4;
  • the gate of the reset transistor T3 is connected to the reset control terminal RESET, the drain of the reset transistor T3 is connected to the pull-up node PU, and the source of the reset transistor T3 is connected to the reset voltage terminal EN1. ;
  • the gate of the output reset transistor T4 is connected to the reset control terminal RESET, the drain of the output reset transistor T4 is connected to the gate drive signal output terminal OUTPUT, and the source of the output reset transistor T4 is connected to all The reset voltage terminal EN1 is connected.
  • T6, T5, T3, and T4 are all n-type transistors, but not limited thereto.
  • both T6 and T5 are turned on to turn on the connection between RESET and EN1, and EN1 is input to a low level so that the gate of T3
  • the source voltage is the reverse voltage, and the reverse voltage is locked to T3, so that the leakage current of T3 is kept at the minimum state, which does not affect the normal display of the module.
  • the embodiment of the present disclosure as shown in FIG. 2 can realize reverse voltage lock of T3 through the use of T5 and T6 during operation.
  • T5 is controlled by CLK, so that EN1 controls T3 only in the output stage.
  • CLK outputs a low level and T5 is turned off.
  • T6 is continuously turned on due to the role of the PU, EN1 can no longer act on T3 and can discharge the potential of the PU.
  • the embodiment of the present disclosure can realize the control of the leakage current of T3 without changing the existing display timing, and avoid the influence of the leakage current on the normal display.
  • some embodiments of the shift register unit include an input circuit 11, a reset circuit 12, an output circuit 13, a storage circuit 14, and a reset control circuit 15, wherein:
  • the input circuit 11 includes an input transistor T1.
  • the gate of the input transistor T1 and the drain of the input transistor T1 are both connected to the input terminal INPUT.
  • the source of the input transistor T1 is connected to the pull-up node. PU connection;
  • the reset circuit 12 includes a reset transistor T3 and an output reset transistor T4.
  • the gate of the reset transistor T3 is connected to the reset control terminal RESET, the drain of the reset transistor T3 is connected to the pull-up node PU, and the source of the reset transistor T3 is connected to the reset voltage terminal EN1. ;
  • the gate of the output reset transistor T4 is connected to the reset control terminal RESET, the drain is connected to the gate drive signal output terminal OUTPUT, and the source is connected to the reset voltage terminal EN1;
  • the output circuit 13 includes an output transistor T2.
  • the gate of the output transistor T2 is connected to the pull-up node PU.
  • the drain of the output transistor T2 is connected to the clock signal terminal CLK.
  • a source is connected to the gate drive signal output terminal OUTPUT;
  • the storage circuit 14 includes a storage capacitor C1, a first end of which is connected to the pull-up node PU, and a second end of which is connected to a gate drive signal output terminal OUTPUT;
  • the reset control circuit 15 includes a first lock transistor T6 and a second lock transistor T5:
  • a gate of the first lock transistor T6 is connected to the pull-up node PU, and a drain of the first lock transistor T6 is connected to the reset voltage terminal EN1;
  • the gate of the second lock transistor T5 is connected to the clock signal terminal CLK, and the drain of the second lock transistor T5 is connected to the source of the first lock transistor T6.
  • a source is connected to the reset control terminal RESET.
  • all the transistors are n-type transistors, but not limited thereto.
  • the principle of the influence of the leakage current of T3 on the display is: During the input phase, the input signal input by INPUT charges C1, and the input signal returns to zero potential after charging is completed. During the output phase, C1 bootstraps to raise the potential of PU to ensure that The output of the gate drive signal; in the output stage, RESET has no signal input, and RESET maintains a zero potential state.
  • T3 When T3 is illuminated, if T3 is not locked by the reverse voltage, T3 will likely have a large leakage current.
  • the input of EN1 is low, which causes a leakage current flowing from the PU to EN1 through T3, which causes the potential of the PU to drop.
  • T2 cannot maintain an effective on state, resulting in unstable gate drive signal output, and OUTPUT cannot perform pixel operation. Effective charging causes the module to display abnormally.
  • INPUT In the input stage, INPUT is input high level, RESET is input low level, T1 is turned on, INPUT charges C1 through T1, so that the potential of PU is high level, CLK outputs low level, T2 is turned on, and OUTPUT outputs low level. Level; T5 is off, so there is no communication between RESET and EN1;
  • the reset voltage input by EN1 is low level, so that reverse voltage lock is performed on T3, so that the leakage current of T3 is kept to a minimum, which does not affect the normal display of the module; and because the gate of T4 is also connected to RESET , Then in the output stage, T4 is also reverse voltage locked to reduce the leakage current of T4 so as not to affect the gate drive signal output by OUTPUT;
  • INPUT input is low level
  • RESET input is high level
  • CLK is output low level
  • T5 is turned off to disconnect the connection between RESET and EN1
  • T3 is turned on to discharge the potential of the PU to make the PU
  • the potential becomes low and T4 is turned on, so that OUTPUT is connected to EN1 and OUTPUT outputs a low level
  • both INPUT and RESET are input low level, the potential of the PU is maintained at low level, T6 is turned off to disconnect the connection between RESET and EN1, and OUTPUT continues to output low level.
  • the driving method of the shift register unit is used to drive the above-mentioned shift register unit.
  • the driving method of the shift register unit includes: in the output stage of each display cycle, through the reset control The circuit maintains the potential of the pull-up node at a first voltage.
  • the first voltage may be a high voltage, but is not limited thereto.
  • the reset control circuit reduces the leakage current of the reset circuit by controlling to maintain the potential of the pull-up node to be the first A voltage, so that the output circuit included in the shift register unit connected to the pull-up node can normally output a gate drive signal, the corresponding row pixel unit receives the gate drive signal, and the switch included in the corresponding row pixel unit The transistor is turned on to write the data voltage on the corresponding column data line to the pixel unit in the corresponding row of the corresponding row to enable normal display.
  • the reset circuit may include a reset transistor, a gate of the reset transistor is connected to a reset control terminal, a first pole of the reset transistor is connected to a pull-up node, and a second pole of the reset transistor is connected to a reset The voltage terminal is connected; wherein the potential of the pull-up node is maintained at a first voltage by the reset control circuit includes:
  • the reset control circuit controls the potential of the reset control terminal and / or the potential of the reset voltage terminal during the output stage to place the reset transistor in a reverse lock state.
  • the driving method of the shift register unit controls the reset control through a reset control circuit in an output stage (the output stage is a stage in which the shift register unit outputs a corresponding gate driving signal). And / or the potential of the reset voltage terminal, so as to reduce the leakage current of the reset transistor included in the reset circuit on the basis of not changing the existing timing, to achieve the control of the leakage current of the reset transistor, and to avoid The influence of the leakage current of the reset transistor on the output of the gate driving signal will not affect the display.
  • the reset control circuit may control the potential of the reset control terminal during the output stage, or control the potential of the reset control terminal and the potential of the reset voltage terminal to make the reset circuit
  • the gate-source voltage of the included reset transistor is within a predetermined voltage range, so that the reset transistor is in a reverse lock state, thereby eliminating or reducing a leakage current that may occur during the output stage of the reset transistor;
  • the reset transistor is an n-type transistor, and the predetermined voltage range is less than or equal to 0V; or, the reset transistor is a p-type transistor, and the predetermined voltage range is greater than or equal to 0V.
  • the reset transistor is an n-type transistor
  • the gate-source voltage of the reset transistor is a positive voltage
  • the gate-source voltage is less than the threshold voltage of the reset transistor
  • the backlight-induced The leakage current phenomenon makes the output of the gate driving circuit unstable and the display module produces an abnormal display.
  • the embodiments of the present disclosure need to ensure that the reset transistor is in a reverse lock state during the output stage, that is, when the reset transistor is an n-type transistor When the reset source transistor is less than or equal to 0; when the reset transistor is a p-type transistor, the reset source transistor ’s source voltage is greater than or equal to 0, so that the leakage current of the reset transistor is kept at a minimum state , Does not affect the normal display of the display module.
  • the reset control circuit may reduce a leakage current of the reset transistor by controlling a potential of the reset voltage terminal in an output stage.
  • the potential of the reset voltage terminal may be set to a first voltage, so that the potential of the source of the reset transistor and the potential of the drain of the reset transistor are the same to reduce the leakage current of the reset transistor.
  • the display cycle further includes a reset phase;
  • the driving method of the shift register unit includes:
  • the reset control circuit controls the connection between the reset control terminal and the reset voltage terminal under the control of the reverse lock control terminal to control the gate-source voltage of the reset transistor at Within a predetermined voltage range;
  • the reset control circuit is controlled to open the connection between the reset control terminal and the reset voltage terminal under the control of the reverse lock control terminal.
  • the reverse lock control terminal may include a first reverse lock control terminal and a second reverse lock control terminal; the first reverse lock control terminal is connected to the pull-up node, and the second The reverse lock control terminal is connected to the clock signal terminal; the driving method of the shift register unit includes:
  • the reset control circuit turns on the connection between the reset voltage terminal and the reset control terminal under the control of the pull-up node and the clock signal terminal to control the reset transistor.
  • the gate-source voltage is within a predetermined voltage range
  • the repeated bit control circuit disconnects the reset voltage terminal and the reset control terminal under the control of the clock signal terminal.
  • the method for driving the shift register unit may further include:
  • the reset circuit controls the potential of the pull-up node to a reset voltage, and the reset circuit controls the gate drive signal output terminal to output the reset voltage;
  • the reset voltage is a voltage input from the reset voltage terminal.
  • the display cycle further includes an input phase and an output cut-off hold phase
  • the driving method of the shift register unit further includes:
  • the reset control circuit disconnects the connection between the reset control terminal and the reset voltage terminal, so that the gate-source voltage of the reset transistor is at the predetermined Within the voltage range
  • a reset control circuit disconnects the connection between the reset control terminal and the reset voltage terminal, so that the gate-source voltage of the reset transistor is at Within the predetermined voltage range.
  • the gate driving circuit according to the embodiment of the present disclosure includes multiple stages of the above-mentioned shift register unit; the shift register unit further includes a gate driving signal output terminal and an input terminal;
  • each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent previous-stage shift register unit;
  • the reset control terminal of each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent next-stage shift register unit.
  • n is a positive integer
  • reference numeral T1-n is an input transistor included in the n-th stage shift register unit
  • reference numeral T2-n is an output transistor included in the n-th stage shift register unit
  • T3-n is an n-th stage
  • the reset transistor included in the shift register unit is labeled as T4-n as the output reset transistor included in the n-th shift register unit
  • the reference transistor T5-n is the second lock transistor included in the n-th shift register unit.
  • T6-n is a first lock transistor included in the n-th stage shift register unit
  • reference numeral C1-n is a storage capacitor included in the n-th stage shift register unit;
  • the reference transistor T1-n + 1 is an input transistor included in the shift register unit of the n + 1th stage, and the reference symbol T2-n + 1 is the output transistor included in the shift register unit of the n + 1th stage, T3-n + 1 is the reset transistor included in the shift register unit of the (n + 1) th stage, the reference number T4-n + 1 is the output reset transistor included in the shift register unit of the n + 1th stage, and the number is T5-n + 1.
  • the second lock transistor included in the n + 1 stage shift register unit, T6-n + 1 is the first lock transistor included in the n + 1 stage shift register unit; the reference numeral C1-n is the n stage shift register
  • the input terminal labeled INPUTn is the n-th input terminal
  • the label labeled RESETn is the n-th reset terminal
  • the label labeled Pun is the n-th pull-up node
  • the label EN1-n is n-th reset Voltage terminal
  • CLKn is the n-th clock signal terminal
  • OUTPUTn is the n-th gate drive signal output terminal
  • INPUTn + 1 is the n + 1-th input terminal
  • RESETn + 1 is the first The n + 1 level reset terminal
  • the Pun + 1 is the n + 1th level pull-up node
  • the EN1-n + 1 is the n + 1th level reset voltage terminal
  • the CLKn + 1 is the nth level. + 1-level clock signal terminal
  • the label labeled OUTPUTn + 1 is the n + 1-th gate drive signal output terminal;
  • OUTPUTn is connected to INPUTn + 1
  • OUTPUTn + 1 is connected to RESETn.
  • all transistors are n-type transistors, but not limited to this; EN1-n and EN-n + 1 are all input low level.
  • STV is a start signal
  • STV is a start signal connected to an input terminal of a first-stage shift register unit included in a gate driving circuit
  • SZ is a frame display time
  • the nth The row grid lines remain on, the pixels in the nth row begin to receive data signals, and the pixels in the nth row on the display screen can be displayed normally; T5-n and T6-n are both turned on, so that T3-n is in the reverse level lock state, Maintain the leakage current of T3-n at a minimum level to ensure that the high voltage of PU-n is maintained, to avoid the abnormal display of OUTPUTn due to the leakage current of T3-n that cannot normally output a high level. Pixels in line n are displayed normally;
  • the nth output stage Sn2 is also the n + 1th input stage.
  • INPUTn + 1 is input high level
  • RESETn + 1 is input low level
  • T1-n + 1 is turned on to control Pun.
  • C1-n + 1 maintains the potential of Pun + 1, CLKn + 1 inputs low level
  • T2-n + 1 turns on
  • OUTPUTn + 1 outputs low level;
  • the nth reset stage Sn3 is the n + 1 output stage.
  • both Inputn + 1 and RESETn + 1 are input low level
  • CLKn + 1 is input high level
  • C1-n + 1 Bootstrap pulls up the potential of PU-n + 1, T2-n + 1 turns on
  • OUTPUTn + 1 outputs a high level.
  • the gate line of the n + 1th row remains turned on, and the pixel of the n + 1th row starts receiving data signals ,
  • the n + 1th row of pixels on the display screen can be displayed normally; T5-n + 1 and T6-n + 1 are both turned on, so that T3-n + 1 is in the reverse level lock state, and T3-n + 1
  • the leakage current is maintained at a minimum level to ensure that the high voltage of PU-n + 1 is maintained, to avoid the abnormal display phenomenon caused by OUTPUTn + 1 not outputting high level due to the leakage current of T3-n + 1. To ensure that the n + 1th row of pixels are displayed properly.
  • the display device includes the gate driving circuit described above.
  • the display device may be, for example, an electronic paper, an OLED (Organic Light-Emitting Diode) display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital direction frame, a navigator, or any other device having a display function. Products or parts.
  • OLED Organic Light-Emitting Diode

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Abstract

本公开提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元包括复位电路和复位控制电路，所述复位电路与上拉节点连接，用于在复位阶段对上拉节点的电位进行复位；所述复位控制电路与所述复位电路连接，用于在每个显示周期的输出阶段将所述上拉节点的电位保持在第一电压。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2018年6月29日在中国提交的中国专利申请号No.201810695672.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
相关技术的窄边框显示模组中，背光两侧无遮光胶带，背光直接照射背光两侧的GOA(Gate On Array，设置于阵列基板上的栅极驱动)，这种条件下，GOA包括的移位寄存器单元中的复位晶体管因光照产生载流子，从而该复位晶体管的漏电流较大，从而会在输出阶段拉低上拉节点的电位，从而导致移位寄存器单元不能稳定输出栅极驱动信号，使得栅极驱动电压下降，模组产生异常显示。
发明内容
本公开提供了一种移位寄存器单元，包括复位电路和复位控制电路，所述复位电路与上拉节点连接，用于在复位阶段对上拉节点的电位进行复位；
所述复位控制电路与所述复位电路连接，用于每个显示周期的输出阶段将所述上拉节点的电位保持在第一电压。
可选的，所述复位电路包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体管的第二极与复位电压端连接，所述第一极和第二极分别为源极和漏极；
所述复位控制电路与所述复位控制端和所述复位电压端连接，通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态。
可选的，在输出阶段，复位控制电路在反向锁定控制端的控制下，导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
可选的，在复位阶段，复位控制电路在反向锁定控制端的控制下，断开所述复位控制端与所述复位电压端之间的连接。
所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
可选的，所述反向锁定控制端包括第一反向锁定控制端与第二反向锁定控制端；所述第一反向锁定控制端与所述上拉节点连接，所述第二反向锁定控制端与时钟信号端连接；
所述复位控制电路包括第一锁定晶体管和第二锁定晶体管，其中，
所述第一锁定晶体管的栅极与所述上拉节点连接，所述第一锁定晶体管的第一极与所述复位电压端连接；
所述第二锁定晶体管的栅极与所述时钟信号端连接，所述第二锁定晶体管的第一极与所述第一锁定晶体管的第二极连接，所述第二锁定晶体管的第二极与所述复位控制端连接。
可选的，所述移位寄存器单元还包括输出电路；
所述输出电路分别与所述上拉节点、时钟信号端和栅极驱动信号输出端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，控制将所述时钟信号端输出的时钟信号写入所述栅极驱动信号输出端；
所述复位电路还与所述栅极驱动信号输出端连接，用于在复位阶段，在所述复位控制端的控制下，控制将所述复位电压端输出的复位电压写入所述栅极驱动信号输出端，以对所述栅极驱动信号输出端的电压进行复位。
可选的，所述输出电路包括输出晶体管，所述复位电路还包括输出复位晶体管，其中，
所述输出晶体管的栅极与所述上拉节点连接，所述输出晶体管的第一极与所述时钟信号端连接，所述输出晶体管的第二极与栅极驱动信号输出端连接；
所述输出复位晶体管的栅极与所述复位控制端连接，所述输出复位晶体 管的第一极与所述栅极驱动信号输出端连接，所述输出复位晶体管的第二极与所述复位电压端连接。
可选的，本公开所述的移位寄存器单元还包括：
输入电路，分别与输入端和上拉节点连接，用于在输入阶段，在所述输入端的控制下，控制所述上拉节点的电位；以及，
存储电路，与所述上拉节点连接，用于在输入阶段维持所述上拉节点的电位，在输出阶段自举拉升所述上拉节点的电位。
可选的，所述输入电路包括输入晶体管，所述输入晶体管的栅极和所述输入晶体管的第一极都与所述输入端连接，所述输入晶体管的第二极与所述上拉节点连接；
所述存储电路包括存储电容，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与栅极驱动信号输出端连接。
本公开还提供了一种移位寄存器单元的驱动方法，用于驱动上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：在每个显示周期的输出阶段，通过所述复位控制电路将所述上拉节点的电位保持在第一电压。
可选的，所述复位电路包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体管的第二极与复位电压端连接；所述通过所述复位控制电路将所述上拉节点的电位保持在第一电压包括：
所述复位控制电路通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态。
可选的，所述复位控制电路通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态包括：
在输出阶段，所述复位控制电路在反向锁定控制端的控制下，导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
其中所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
可选的，所述显示周期还包括复位阶段；所述驱动方法包括：
在所述复位阶段，所述复位控制电路在所述反向锁定控制端的控制下，控制断开通所述复位控制端与所述复位电压端之间的连接。
可选的，所述反向锁定控制端包括第一反向锁定控制端与第二反向锁定控制端；所述第一反向锁定控制端与所述上拉节点连接，所述第二反向锁定控制端与时钟信号端连接；所述驱动方法包括：
在所述输出阶段，所述复位控制电路在所述上拉节点和所述时钟信号端的控制下导通所述复位电压端与所述复位控制端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
在所述复位阶段，所述复位控制电路在所述时钟信号端的控制下，断开所述复位电压端与所述复位控制端之间的连接。
可选的，所述移位寄存器单元的驱动方法还包括：
在所述复位阶段，在所述复位控制端的控制下，复位电路控制所述上拉节点的电位为复位电压，所述复位电路控制栅极驱动信号输出端输出复位电压；
所述复位电压为所述复位电压端输入的电压。
可选的，所述显示周期还包括输入阶段和输出截止保持阶段，所述移位寄存器单元的驱动方法还包括：
在所述输入阶段，在所述时钟信号端的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内；
在所述输出截止保持阶段，在所述上拉节点的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元；所述移位寄存器单元还包括栅极驱动信号输出端和输入端；
除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位控制 端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开又一实施例所述的移位寄存器单元的结构图；
图3是本公开所述的移位寄存器单元的实施例的电路图；
图4是本公开实施例所述的栅极驱动电路包括的两级移位寄存器单元的级联示意图；
图5是图4所示的两级移位寄存器单元的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开的主要目的在于提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置，解决相关技术中由于移位寄存器单元中的复位晶体管因光照产生载流子，从而该复位晶体管的漏电流较大，从而会在输出阶段拉低上拉节点的电位，从而导致移位寄存器单元不能稳定输出栅极驱动信号，从而出现异常显示的现象的问题。本公开实施例所述的移位寄存器单元，包括复位电路，所述复位电路与上拉节点连接，用于在复位阶段对上拉节点进行复位，所述移位寄存器单元还包括复位控制电路；
所述复位控制电路与所述复位电路连接，用于在输出阶段控制减小所述复位电路的漏电流，以维持所述上拉节点的电位为第一电压。输出阶段即为时钟信号端通过输出电路向栅极驱动信号输出端输出栅极驱动信号的阶段。
可选地，所述第一电压可以为高电压，但不以此为限，在输出阶段，所述复位控制电路通过控制减小复位电路的漏电流，以维持所述上拉节点PU的电位为第一电压，从而使得所述移位寄存器单元包括的与所述上拉节点PU连接的输出电路能够正常输出栅极驱动信号，相应行像素单元接收该栅极驱动信号，并相应行像素单元包括的开关晶体管导通，以将相应列数据线上的数据电压写入相应行相应列像素单元，以能进行正常显示。
可选的，所述复位电路可以包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体管的第二极与复位电压端连接；
所述复位控制电路与所述复位控制端和/或所述复位电压端连接，用于在所述输出阶段，通过控制所述复位控制端的电位和/或所述复位电压端的电位，以控制减小所述复位晶体管的漏电流。
本公开实施例所述的移位寄存器单元增设了复位控制电路，以在输出阶段(所述输出阶段即为所述移位寄存器单元输出相应的栅极驱动信号的阶段)通过控制所述复位控制端的电位和/或所述复位电压端的电位，从而在不改变现有时序的基础上，控制减小复位电路包括的复位晶体管的漏电流，实现对所述复位晶体管的漏电流的管控，规避了所述复位晶体管的漏电流对栅极驱动信号输出的影响，从而不会影响显示。
根据一种可选实施方式，所述复位控制电路可以在输出阶段，通过控制所述复位控制端的电位，或者通过控制所述复位控制端的电位和所述复位电压端的电位，以使得所述复位电路包括的复位晶体管的栅源电压处于预定电压范围内，从而使得所述复位晶体管处于反向锁定(即晶体管截止)状态，从而减小所述复位晶体管在所述输出阶段的漏电流；
所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
在实际操作时，当所述复位晶体管为n型晶体管时，所述复位晶体管的 栅源电压为正电压，即使该栅源电压小于复位晶体管的阈值电压，也会发生由于背光照射而产生的漏电流现象，使得栅极驱动电路输出不稳定，显示模组产生异常显示，因此本公开实施例需要在输出阶段保证复位晶体管处于反向锁定状态，也即，当所述复位晶体管为n型晶体管时，所述复位晶体管的栅源电压小于或等于0；当所述复位晶体管为p型晶体管时，所述复位晶体管的栅源电压大于或等于0，以使得复位晶体管的漏电流保持在最小状态，不影响显示模组正常显示。
根据另一种可选实施方式，所述复位控制电路可以在输出阶段，通过控制所述复位电压端的电位，以减小所述复位晶体管的漏电流。例如，可以将所述复位电压端的电位设置为第一电压，从而使得所述复位晶体管的源极的电位和所述复位晶体管的漏极电位相同，以减小复位晶体管的漏电流。
在实际操作时，所述复位控制电路可以用于在输出阶段，在反向锁定控制端的控制下，控制导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
所述复位控制电路还可以用于在所述复位阶段，在所述反向锁定控制端的控制下，控制断开所述复位控制端与所述复位电压端之间的连接，以使得复位电路包括的复位晶体管可以在复位控制端的控制下，对上拉节点进行复位，从而使得移位寄存器单元包括的复位电路能够下拉栅极驱动信号的电位；
所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
可选地，所述反向锁定控制端可以包括第一反向锁定控制端与第二反向锁定控制端，所述第一反向锁定控制端可以与所述上拉节点连接，所述第二反向锁定控制端可以与时钟信号端连接，但不以此为限。
可选的，所述复位控制电路可以包括第一锁定晶体管和第二锁定晶体管，其中，
所述第一锁定晶体管的栅极与所述上拉节点连接，所述第一锁定晶体管的第一极与所述复位电压端连接；
所述第二锁定晶体管的栅极与所述时钟信号端连接，所述第二锁定晶体管的第一极与所述第一锁定晶体管的第二极连接，所述第二锁定晶体管的第 二极与所述复位控制端连接。
可选地，所述移位寄存器单元还可以包括输出电路；
所述输出电路分别与所述上拉节点、所述时钟信号端和栅极驱动信号输出端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，控制将所述时钟信号端输出的时钟信号写入所述栅极驱动信号输出端；
所述复位电路还与所述栅极驱动信号输出端连接，用于在复位阶段，在所述复位控制端的控制下，控制所述栅极驱动信号输出端与所述复位电压端连接，以对所述栅极驱动信号输出端的电压进行复位。
可选地，所述移位寄存器单元还可以包括：
输入电路，分别与输入端和上拉节点连接，用于在输入阶段，在所述输入端的控制下，控制所述上拉节点的电位；以及，
存储电路，与所述上拉节点连接，用于在输入阶段维持所述上拉节点的电位，在输出阶段自举拉升所述上拉节点的电位。
可选的，所述输入电路可以包括输入晶体管，所述输入晶体管的栅极和所述输入晶体管的第一极都与所述输入端连接，所述输入晶体管的第二极与所述上拉节点连接；
所述存储电路包括存储电容，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与栅极驱动信号输出端连接。
与相关技术相比，本公开所述的移位寄存器单元、驱动方法、栅极驱动电路和显示装置增设了复位控制电路，所述复位控制电路通过控制减小复位电路的漏电流，以维持所述上拉节点的电位，从而使得所述移位寄存器单元包括的与所述上拉节点连接的输出电路能够正常输出栅极驱动信号，相应行像素单元接收该栅极驱动信号，并相应行像素单元包括的开关晶体管导通，以将相应列数据线上的数据电压写入相应行相应列像素单元，以能进行正常显示。
如图1所示，本公开实施例所述的移位寄存器单元包括输入电路11、复位电路12、输出电路13、存储电路14和复位控制电路15，其中，
所述输入电路11分别与输入端INPUT和上拉节点PU连接，用于在输入阶段在输入端INPUT的控制下，控制导通所述输入端INPUT与所述上拉节 点PU之间的连接，以使得在输入阶段所述上拉节点PU的电位为第一电压(在实际操作时，所述第一电压可以为高电压，但不以此为限)；
所述复位电路12分别与复位控制端RESET、复位电压端EN1、所述上拉节点PU和栅极驱动信号输出端OUTPUT连接，用于在复位阶段，在所述复位控制端RESET的控制下，控制将所述复位电压端EN1输出的复位电压写入所述上拉节点PU，以对上拉节点PU的电位进行复位，并用于在复位阶段，控制将所述复位电压端EN1输出的复位电压写入所述栅极驱动信号输出端OUTPUT，以对所述栅极驱动信号输出端OUTPUT输出的栅极驱动信号的电位进行复位；
所述输出电路13分别与所述上拉节点PU、时钟信号端CLK和栅极驱动信号输出端OUTPUT连接，用于在输入阶段在所述上拉节点PU的控制下，控制将所述时钟信号端CLK输出的时钟信号写入所述栅极驱动信号输出端OUTPUT，以使得所述栅极驱动信号输出端OUTPUT输出无效电平(所述无效电平指的是使得像素单元包括的栅极与该栅极驱动信号输出端连接的开关晶体管关断的电平)，所述输出电路13还用于在输出阶段在上拉节点PU的控制下，控制将所述时钟信号端CLK输出的时钟信号写入所述栅极驱动信号输出端OUTPUT，以使得所述栅极驱动信号输出端OUTPUT输出栅极驱动信号(所述栅极驱动信号是能够使得像素单元包括的栅极与该栅极驱动信号输出端OUTPUT连接的开关晶体管开启的信号)；
所述存储电路14的第一端与所述上拉节点PU连接，所述存储电路14的第二端与所述栅极驱动信号输出端OUTPUT连接；所述存储电路14用于在输入阶段维持所述上拉节点PU的电位，在输出阶段自举拉升所述上拉节点PU的电位；
所述复位电路12包括复位晶体管(图1中未示出)，所述复位晶体管的栅极与复位控制端RESET连接，所述复位晶体管的第一极与上拉节点PU连接，所述复位晶体管的第二极与复位电压端EN1连接；
所述复位控制电路15分别与复位控制端RESET、时钟信号端CLK、所述上拉节点PU和所述复位电压端EN1连接，用于在输出阶段，在所述时钟信号端CLK和所述上拉节点PU的控制下，控制所述复位控制端RESET与 所述复位电压端EN1连接，以使得所述复位晶体管(图1中未示出)的栅源电压处于预定电压范围内，以对所述复位晶体管施加反向电平，以对所述复位晶体管进行反向锁定，在输出阶段减小所述复位晶体管的漏电流；对所述复位晶体管施加反向电平，指的是：当所述复位晶体管为n型晶体管时，该复位晶体管的阈值电压为正电压，则控制所述复位晶体管的栅源电压小于或等于0V；当所述复位晶体管为p型晶体管，该复位晶体管的阈值电压为负电压，则控制所述复位晶体管的栅源电压大于或等于0V；
所述复位控制电路15还用于在复位阶段，在所述时钟信号端CLK的控制下，断开所述复位控制端RESET与所述复位电压端EN1之间的连接，以使得在所述复位阶段，所述复位晶体管能够开启，以能对所述上拉节点PU的电位进行复位。
本公开实施例所述的移位寄存器单元增设了复位控制电路15，以在输出阶段(所述输出阶段即为所述移位寄存器单元输出相应的栅极驱动信号的阶段)控制复位控制端RESET与复位电压端EN1之间导通，从而在不改变现有时序的基础上，实现对复位电路12包括的复位晶体管(图1中未示出，后续将结合实施例介绍)的漏电流的管控，规避了所述复位晶体管的漏电流对栅极驱动信号输出的影响，从而不会影响显示。
在输出阶段，所述复位控制电路15导通复位控制端RESET与复位电压端EN1之间的连接，此时由于EN1输入低电压，而所述复位电路包括的复位晶体管的栅极与RESET连接，从而使得复位晶体管的栅极也接入低电平，以使得所述复位晶体管处于反向锁定状态，从而避免当光照所述复位晶体管时其容易产生较大漏电流的现象发生；
在复位阶段，所述复位控制电路15断开复位控制端RESET与复位电压端EN1之间的连接，而在复位阶段RESET输出高电平，从而使得在复位阶段所述复位晶体管能够导通，以使得所述复位电路12包括的复位晶体管能够实现对上拉节点PU的放电，能够正确下拉栅极驱动信号的电位。
在实际操作时，每一显示周期可以依次包括输入阶段、输出阶段、复位阶段和输出截止保持阶段，本公开如图1所示的移位寄存器单元在工作时，
在所述输入阶段，所述时钟信号端CLK输出无效电平，在输入端INPUT 的控制下，输入电路11控制拉升所述上拉节点PU的电位，存储电路14控制维持所述上拉节点PU的电位；输出电路13在所述上拉节点PU的控制下导通栅极驱动信号输出端OUTPUT与所述时钟信号端CLK之间的连接，以使得所述栅极驱动信号输出端OUTPUT输出无效电平；
在所述输出阶段，所述时钟信号端CLK输出有效电平，存储电路14自举拉升所述上拉节点PU的电位，输出电路13在所述上拉节点PU的控制下导通栅极驱动信号输出端OUTPUT与所述时钟信号端CLK之间的连接，以使得所述栅极驱动信号输出端OUTPUT输出有效电平；复位控制电路15在上拉节点PU和时钟信号端CLK的控制下导通复位电压端EN1与复位控制端RESET之间的连接，从而将复位电路12包括的复位晶体管的栅极接入EN1输入的低电压，使得所述复位晶体管处于反向锁定状态，以改善所述复位电路12包括的复位晶体管的漏电现象；
在所述复位阶段，在所述复位控制端RESET的控制下，复位电路12导通所述上拉节点PU与所述复位电压端EN1之间的连接，以对所述上拉节点PU的电位进行复位；在所述上拉节点PU的控制下，输出电路13断开栅极驱动信号输出端OUTPUT与所述时钟信号端CLK之间的连接；在所述复位控制端RESET的控制下，所述复位电路12导通所述栅极驱动信号输出端OUTPUT与所述复位电压端EN1之间的连接，以使得所述栅极驱动信号输出端OUTPUT输出复位电压(所述复位电压为所述复位电压端输入的电压)；在所述时钟信号端CLK的控制下，复位控制电路15断开所述复位电压端EN1与所述复位控制端RESET之间的连接，以使得在复位阶段所述复位电路12包括的复位晶体管能够导通，以实现对上拉节点PU的放电，能够下拉栅极驱动信号的电位；
在所述输出截止保持阶段，在所述上拉节点PU的控制下，复位控制电路15断开所述复位控制端RESET与所述复位电压端EN1之间的连接，在所述上拉节点PU和所述复位控制端RESET的控制下，输出电路13控制维持栅极驱动信号的电位；所述栅极驱动信号为所述栅极驱动信号输出端OUTPUT输出的信号。
如图2所示，在图1所示的移位寄存器单元的实施例的基础上，所述复 位控制电路15包括第一锁定晶体管T6和第二锁定晶体管T5：
所述第一锁定晶体管T6的栅极与所述上拉节点PU连接，所述第一锁定晶体管T6的漏极与所述复位电压端EN1连接；以及，
所述第二锁定晶体管T5的栅极与所述时钟信号端CLK连接，所述第二锁定晶体管T5的漏极与所述第一锁定晶体管T6的源极连接，所述第二锁定晶体管T5的源极与所述复位控制端RESET连接；
如图2所示，复位电路12包括复位晶体管T3和输出复位晶体管T4；
所述复位晶体管T3的栅极与所述复位控制端RESET连接，所述复位晶体管T3的漏极与所述上拉节点PU连接，所述复位晶体管T3的源极与所述复位电压端EN1连接；
所述输出复位晶体管T4的栅极与所述复位控制端RESET连接，所述输出复位晶体管T4的漏极与所述栅极驱动信号输出端OUTPUT连接，所述输出复位晶体管T4的源极与所述复位电压端EN1连接。
在图2所示的实施例中，T6、T5、T3和T4都为n型晶体管，但不以此为限。
本公开图2所示的移位寄存器单元的实施例在工作时，在输出阶段，T6和T5都开启，以导通RESET与EN1之间的连接，EN1输入低电平，以使得T3的栅源电压为反向电压，对T3进行反向电压锁定，使得T3的漏电流保持在最小状态，不影响模组正常显示。
本公开如图2所示的实施例在工作时，通过T5和T6的搭配使用，能够实现T3进行反向电压锁定，同时T5受CLK控制，使得EN1对T3的控制仅在输出阶段，当需要对像素放电时(即在复位阶段)，CLK输出低电平，T5关闭，虽然T6由于PU的作用持续开启，但EN1将不能再对T3进行作用，能够实现对PU的电位进行放电。本公开实施例能够在不改变现有显示时序的基础上，实现了对T3的漏电流的管控，规避漏电流对正常显示的影响。
下面通过实施例来说明本公开所述的移位寄存器单元。
如图3所示，本公开所述的移位寄存器单元的一些实施例包括输入电路11、复位电路12、输出电路13、存储电路14和复位控制电路15，其中，
所述输入电路11包括输入晶体管T1，所述输入晶体管T1的栅极和所述 输入晶体管T1的漏极都与所述输入端INPUT连接，所述输入晶体管T1的源极与所述上拉节点PU连接；
所述复位电路12包括复位晶体管T3和输出复位晶体管T4；
所述复位晶体管T3的栅极与所述复位控制端RESET连接，所述复位晶体管T3的漏极与所述上拉节点PU连接，所述复位晶体管T3的源极与所述复位电压端EN1连接；
所述输出复位晶体管T4的栅极与所述复位控制端RESET连接，漏极与所述栅极驱动信号输出端OUTPUT连接，源极与所述复位电压端EN1连接；
所述输出电路13包括输出晶体管T2，所述输出晶体管T2的栅极与所述上拉节点PU连接，所述输出晶体管T2的漏极与所述时钟信号端CLK连接，所述输出晶体管T2的源极与所述栅极驱动信号输出端OUTPUT连接；
所述存储电路14包括：存储电容C1，第一端与所述上拉节点PU连接，第二端与栅极驱动信号输出端OUTPUT连接；
所述复位控制电路15包括第一锁定晶体管T6和第二锁定晶体管T5：
所述第一锁定晶体管T6的栅极与所述上拉节点PU连接，所述第一锁定晶体管T6的漏极与所述复位电压端EN1连接；以及，
所述第二锁定晶体管T5的栅极与所述时钟信号端CLK连接，所述第二锁定晶体管T5的漏极与所述第一锁定晶体管T6的源极连接，所述第二锁定晶体管T5的源极与所述复位控制端RESET连接。
在图3所示的移位寄存器单元的实施例中，所有的晶体管都为n型晶体管，但不以此为限。
T3的漏电流影响显示的原理为：在输入阶段，INPUT输入的输入信号对C1进行充电，充电完毕后所述输入信号恢复零电位，在输出阶段，C1自举拉升PU的电位，以保证栅极驱动信号的输出；在输出阶段，RESET无信号输入，RESET保持零电位状态，当光照T3时，如若T3未被反向电压锁死，T3将有概率出现漏电流较大的现象，由于此时EN1输入低电平，因此造成由PU通过T3流至EN1的漏电现象，致使PU的电位下降，从而使得T2不能保持有效开启状态，导致栅极驱动信号输出不稳定，OUTPUT不能对像素进行有效充电，导致模组显示异常。
本公开如图3所示的移位寄存器单元的实施例在工作时，在每一显示周期，
在输入阶段，INPUT输入高电平，RESET输入低电平，T1打开，INPUT通过T1向C1充电，以使得PU的电位为高电平，CLK输出低电平，T2导通，OUTPUT输出低电平；T5关断，从而RESET与EN1之间不连通；
在输出阶段，INPUT输入低电平，RESET输入低电平，C1自举拉升PU的电位，CLK输出高电平，OUTPU输出高电平；并T5和T6都开启，以导通RESET与EN1之间的连接，EN1输入的复位电压为低电平，从而对T3进行反向电压锁定，使得T3的漏电流保持最小，不影响模组正常显示；并且，由于T4的栅极也与RESET连接，则在输出阶段，同样也对T4进行反向电压锁定，减小T4的漏电流，以不影响OUTPUT输出的栅极驱动信号；
在复位阶段，INPUT输入低电平，RESET输入高电平，CLK输出低电平，T5关断，以断开RESET与EN1之间的连接，T3开启，以对PU的电位进行放电，使得PU的电位变为低电平，T4打开，以使得OUTPUT与EN1连接，OUTPUT输出低电平；
在输出截止保持阶段，INPUT和RESET都输入低电平，PU的电位保持为低电平，T6关断，以断开RESET与EN1之间的连接，OUTPUT持续输出低电平。
本公开实施例所述的移位寄存器单元的驱动方法，用于驱动上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：在每个显示周期的输出阶段，通过所述复位控制电路将所述上拉节点的电位保持在第一电压。
可选地所述第一电压可以为高电压，但不以此为限，在输出阶段，所述复位控制电路通过控制减小复位电路的漏电流，以维持所述上拉节点的电位为第一电压，从而使得所述移位寄存器单元包括的与所述上拉节点连接的输出电路能够正常输出栅极驱动信号，相应行像素单元接收该栅极驱动信号，并相应行像素单元包括的开关晶体管导通，以将相应列数据线上的数据电压写入相应行相应列像素单元，以能进行正常显示。
可选的，所述复位电路可以包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体 管的第二极与复位电压端连接；其中通过所述复位控制电路将所述上拉节点的电位保持在第一电压包括：
所述复位控制电路通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态。
本公开实施例所述的移位寄存器单元的驱动方法通过复位控制电路在输出阶段(所述输出阶段即为所述移位寄存器单元输出相应的栅极驱动信号的阶段)通过控制所述复位控制端的电位和/或所述复位电压端的电位，从而在不改变现有时序的基础上，控制减小复位电路包括的复位晶体管的漏电流，实现对所述复位晶体管的漏电流的管控，规避了所述复位晶体管的漏电流对栅极驱动信号输出的影响，从而不会影响显示。
根据一种可选实施方式，所述复位控制电路可以在输出阶段，通过控制所述复位控制端的电位，或者通过控制所述复位控制端的电位和所述复位电压端的电位，以使得所述复位电路包括的复位晶体管的栅源电压处于预定电压范围内，从而使得所述复位晶体管处于反向锁定状态，从而消除或减小所述复位晶体管在所述输出阶段可能出现的漏电流；
所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
在实际操作时，当所述复位晶体管为n型晶体管时，如果所述复位晶体管的栅源电压为正电压，即使该栅源电压小于复位晶体管的阈值电压，也会发生由于背光照射而产生的漏电流现象，使得栅极驱动电路输出不稳定，显示模组产生异常显示，因此本公开实施例需要在输出阶段保证复位晶体管处于反向锁定状态，也即，当所述复位晶体管为n型晶体管时，所述复位晶体管的栅源电压小于或等于0；当所述复位晶体管为p型晶体管时，所述复位晶体管的栅源电压大于或等于0，以使得复位晶体管的漏电流保持在最小状态，不影响显示模组正常显示。
根据另一种可选实施方式，所述复位控制电路可以在输出阶段，通过控制所述复位电压端的电位，以减小所述复位晶体管的漏电流。例如，可以将所述复位电压端的电位设置为第一电压，从而使得所述复位晶体管的源极的电位和所述复位晶体管的漏极电位相同，以减小复位晶体管的漏电流。
在实际操作时，所述显示周期还包括复位阶段；所述移位寄存器单元的驱动方法包括：
在所述输出阶段，所述复位控制电路在反向锁定控制端的控制下，控制导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
在所述复位阶段，所述复位控制电路在所述反向锁定控制端的控制下，控制断开通所述复位控制端与所述复位电压端之间的连接。
可选的，所述反向锁定控制端可以包括第一反向锁定控制端与第二反向锁定控制端；所述第一反向锁定控制端与所述上拉节点连接，所述第二反向锁定控制端与时钟信号端连接；所述移位寄存器单元的驱动方法包括：
在所述输出阶段，所述复位控制电路在所述上拉节点和所述时钟信号端的控制下导通所述复位电压端与所述复位控制端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
在所述复位阶段，所述反复位控制电路在所述时钟信号端的控制下，断开所述复位电压端与所述复位控制端之间的连接。
可选地，所述移位寄存器单元的驱动方法还可以包括：
在所述复位阶段，在所述复位控制端的控制下，复位电路控制所述上拉节点的电位为复位电压，所述复位电路控制栅极驱动信号输出端输出复位电压；
所述复位电压为所述复位电压端输入的电压。
可选的，所述显示周期还包括输入阶段和输出截止保持阶段，所述移位寄存器单元的驱动方法还包括：
在所述输入阶段，在所述时钟信号端的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内；
在所述输出截止保持阶段，在所述上拉节点的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内。
本公开实施例所述的栅极驱动电路，包括多级上述的移位寄存器单元； 所述移位寄存器单元还包括栅极驱动信号输出端和输入端；
除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位控制端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
图4示出了栅极驱动电路包括的第n级移位寄存器单元和第n+1级移位寄存器单元；n为正整数；
在图4中，标号为T1-n的为第n级移位寄存器单元包括的输入晶体管，标号为T2-n的为第n级移位寄存器单元包括的输出晶体管，T3-n为第n级移位寄存器单元包括的复位晶体管，标号为T4-n的为第n级移位寄存器单元包括的输出复位晶体管，标号为T5-n的为第n级移位寄存器单元包括的第二锁定晶体管，T6-n为第n级移位寄存器单元包括的第一锁定晶体管；标号为C1-n的为第n级移位寄存器单元包括的存储电容；
标号为T1-n+1的为第n+1级移位寄存器单元包括的输入晶体管，标号为T2-n+1的为第n+1级移位寄存器单元包括的输出晶体管，T3-n+1为第n+1级移位寄存器单元包括的复位晶体管，标号为T4-n+1的为第n+1级移位寄存器单元包括的输出复位晶体管，标号为T5-n+1的为第n+1级移位寄存器单元包括的第二锁定晶体管，T6-n+1为第n+1级移位寄存器单元包括的第一锁定晶体管；标号为C1-n的为第n级移位寄存器单元包括的存储电容；
在图4中，标号为INPUTn的为第n级输入端，标号为RESETn的为第n级复位端，标号为Pun的为第n级上拉节点，标号为EN1-n的为第n级复位电压端，CLKn为第n级时钟信号端；标号为OUTPUTn的为第n级栅极驱动信号输出端；标号为INPUTn+1的为第n+1级输入端，标号为RESETn+1的为第n+1级复位端，标号为Pun+1的为第n+1级上拉节点，标号为EN1-n+1的为第n+1级复位电压端，标号为CLKn+1的为第n+1级时钟信号端，标号为OUTPUTn+1的为第n+1级栅极驱动信号输出端；
在图4中，OUTPUTn与INPUTn+1连接，OUTPUTn+1与RESETn连接。
在图4中，所有的晶体管都为n型晶体管，但不以此为限；EN1-n和EN-n+1都输入低电平。
如图5所示，CLKn输入的第n级时钟信号与CLKn+1输入的第n+1级时钟信号相互反相。在图5中，STV为起始信号，STV为接入栅极驱动电路包括的第一级移位寄存器单元的输入端的起始信号，标号为SZ的为一帧显示时间。
如图5所示，本公开如图4所示的两级移位寄存器单元在工作时，
在第n输入阶段Sn1，INPUTn输入高电平，RESETn输入低电平，T1-n打开，以对Pun进行充电，C1-n维持Pun的电位，CLKn输入低电平，T2-n打开，OUTPUTn输出低电平；
在第n输出阶段Sn2，Inputn和RESETn都输入低电平，CLKn输入高电平，C1-n自举拉升PU-n的电位，T2-n开启，OUTPUTn输出高电平，此时第n行栅线保持开启，第n行像素开始接收数据信号，显示屏幕上的第n行像素可正常显示；T5-n和T6-n都开启，以使得T3-n处于反向电平锁定状态，将T3-n的漏电流维持在最小水平，以能保证PU-n的高电压保持，以避免由于T3-n的漏电流而导致的OUTPUTn不能正常输出高电平而导致的显示异常现象，保证第n行像素正常显示；
所述第n输出阶段Sn2也为第n+1输入阶段，在第n+1输入阶段，INPUTn+1输入高电平，RESETn+1输入低电平，T1-n+1打开，以对Pun+1进行充电，C1-n+1维持Pun+1的电位，CLKn+1输入低电平，T2-n+1打开，OUTPUTn+1输出低电平；
在第n复位阶段Sn3，RESETn输入高电平，INPUTn输入低电平，CLKn输入低电平，从而使得T5-n关断，以断开RESETn与EN1-n之间的连接，使得T3-n能够正确导通，从而对PUn的电位进行放电，并T4-n开启，以使得OUTPUTn与EN1-n连接，以使得OUTPUTn输出低电平；
所述第n复位阶段Sn3即为第n+1输出阶段，在该第n+1输出阶段，Inputn+1和RESETn+1都输入低电平，CLKn+1输入高电平，C1-n+1自举拉升PU-n+1的电位，T2-n+1开启，OUTPUTn+1输出高电平，此时第n+1行栅线保持开启，第n+1行像素开始接收数据信号，显示屏幕上的第n+1行像素可正常显示；T5-n+1和T6-n+1都开启，以使得T3-n+1处于反向电平锁定状态，将T3-n+1的漏电流维持在最小水平，以能保证PU-n+1的高电压保持， 以避免由于T3-n+1的漏电流而导致的OUTPUTn+1不能正常输出高电平而导致的显示异常现象，保证第n+1行像素正常显示。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
所述显示装置例如可以为：电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码向框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (18)

  1. 一种移位寄存器单元，包括复位电路和复位控制电路，其中，
    所述复位电路与上拉节点连接，用于在复位阶段对上拉节点的电位进行复位；
    所述复位控制电路与所述复位电路连接，用于在每个显示周期的输出阶段将所述上拉节点的电位保持在第一电压。
  2. 如权利要求1所述的移位寄存器单元，其中，所述复位电路包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体管的第二极与复位电压端连接，其中所述第一极和第二极中的一个为源极，所述第一极和第二极中的另一个为漏极；
    所述复位控制电路与所述复位控制端和所述复位电压端连接，通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态。
  3. 如权利要求2所述的移位寄存器单元，其中在输出阶段，所述复位控制电路在反向锁定控制端的控制下，导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
    其中所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
  4. 如权利要求2或3所述的移位寄存器单元，其中在复位阶段，所述复位控制电路在所述反向锁定控制端的控制下，断开所述复位控制端与所述复位电压端之间的连接。
  5. 如权利要求3所述的移位寄存器单元，其中，所述反向锁定控制端包括第一反向锁定控制端与第二反向锁定控制端；所述第一反向锁定控制端与所述上拉节点连接，所述第二反向锁定控制端与时钟信号端连接；
    所述复位控制电路包括第一锁定晶体管和第二锁定晶体管，其中，
    所述第一锁定晶体管的栅极与所述上拉节点连接，所述第一锁定晶体管的第一极与所述复位电压端连接；
    所述第二锁定晶体管的栅极与所述时钟信号端连接，所述第二锁定晶体 管的第一极与所述第一锁定晶体管的第二极连接，所述第二锁定晶体管的第二极与所述复位控制端连接。
  6. 如权利要求1至5中任一权利要求所述的移位寄存器单元，还包括输出电路；
    所述输出电路分别与所述上拉节点、时钟信号端和栅极驱动信号输出端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，控制将所述时钟信号端输出的时钟信号写入所述栅极驱动信号输出端；
    所述复位电路还与所述栅极驱动信号输出端连接，用于在复位阶段，在所述复位控制端的控制下，控制将所述复位电压端输出的复位电压写入所述栅极驱动信号输出端，以对所述栅极驱动信号输出端的电压进行复位。
  7. 如权利要求6所述的移位寄存器单元，其中，所述输出电路包括输出晶体管，所述复位电路还包括输出复位晶体管，其中，
    所述输出晶体管的栅极与所述上拉节点连接，所述输出晶体管的第一极与所述时钟信号端连接，所述输出晶体管的第二极与栅极驱动信号输出端连接；
    所述输出复位晶体管的栅极与所述复位控制端连接，所述输出复位晶体管的第一极与所述栅极驱动信号输出端连接，所述输出复位晶体管的第二极与所述复位电压端连接。
  8. 如权利要求1至5中任一权利要求所述的移位寄存器单元，还包括：
    输入电路，分别与输入端和上拉节点连接，用于在输入阶段，在所述输入端的控制下，控制所述上拉节点的电位；以及，
    存储电路，与所述上拉节点连接，用于在输入阶段维持所述上拉节点的电位，在输出阶段自举拉升所述上拉节点的电位。
  9. 如权利要求8所述的移位寄存器单元，其中，所述输入电路包括输入晶体管，所述输入晶体管的栅极和所述输入晶体管的第一极都与所述输入端连接，所述输入晶体管的第二极与所述上拉节点连接；
    所述存储电路包括存储电容，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与栅极驱动信号输出端连接。
  10. 一种移位寄存器单元的驱动方法，用于驱动如权利要求1至9中任 一权利要求所述的移位寄存器单元，所述驱动方法包括：
    在每个显示周期的输出阶段，通过所述复位控制电路将所述上拉节点的电位保持在第一电压。
  11. 如权利要求10所述的驱动方法，其中，所述复位电路包括复位晶体管，所述复位晶体管的栅极与复位控制端连接，所述复位晶体管的第一极与上拉节点连接，所述复位晶体管的第二极与复位电压端连接；所述通过所述复位控制电路将所述上拉节点的电位保持在第一电压包括：
    所述复位控制电路通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态。
  12. 如权利要求11所述的驱动方法，其中所述复位控制电路通过在所述输出阶段控制所述复位控制端的电位和/或所述复位电压端的电位以将所述复位晶体管置于反向锁定状态包括：
    在输出阶段，所述复位控制电路在反向锁定控制端的控制下，导通所述复位控制端与所述复位电压端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
    其中所述复位晶体管为n型晶体管，所述预定电压范围为小于或等于0V；或者，所述复位晶体管为p型晶体管，所述预定电压范围为大于或等于0V。
  13. 如权利要求12所述的驱动方法，其中，所述显示周期还包括复位阶段；所述驱动方法还包括：
    在所述复位阶段，所述复位控制电路在所述反向锁定控制端的控制下，控制断开通所述复位控制端与所述复位电压端之间的连接。
  14. 如权利要求13所述的驱动方法，其中，所述反向锁定控制端包括第一反向锁定控制端与第二反向锁定控制端；所述第一反向锁定控制端与所述上拉节点连接，所述第二反向锁定控制端与时钟信号端连接；所述驱动方法包括：
    在所述输出阶段，所述复位控制电路在所述上拉节点和所述时钟信号端的控制下导通所述复位电压端与所述复位控制端之间的连接，以控制所述复位晶体管的栅源电压处于预定电压范围内；
    在所述复位阶段，所述复位控制电路在所述时钟信号端的控制下，断开 所述复位电压端与所述复位控制端之间的连接。
  15. 如权利要求14所述的驱动方法，还包括：
    在所述复位阶段，在所述复位控制端的控制下，复位电路控制所述上拉节点的电位为复位电压，所述复位电路控制栅极驱动信号输出端输出复位电压；
    其中所述复位电压为所述复位电压端输入的电压。
  16. 如权利要求15所述的移位寄存器单元的驱动方法，其中，所述显示周期还包括输入阶段和输出截止保持阶段，所述移位寄存器单元的驱动方法还包括：
    在所述输入阶段，在所述时钟信号端的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内；
    在所述输出截止保持阶段，在所述上拉节点的控制下，复位控制电路断开所述复位控制端与所述复位电压端之间的连接，以使得所述复位晶体管的栅源电压处于所述预定电压范围内。
  17. 一种栅极驱动电路，包括多级如权利要求1至9中任一权利要求所述的移位寄存器单元；所述移位寄存器单元还包括栅极驱动信号输出端和输入端；
    除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
    除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位控制端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
  18. 一种显示装置，包括如权利要求17所述的栅极驱动电路。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN108717844B (zh) 2018-06-29 2020-08-04 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110610684B (zh) * 2019-10-29 2021-03-30 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130249884A1 (en) * 2012-03-22 2013-09-26 Cheol-min Kim Gate driving circuit and display apparatus using the same
CN106601176A (zh) * 2017-01-16 2017-04-26 京东方科技集团股份有限公司 移位寄存器单元电路、驱动方法、移位寄存器和显示装置
CN108717844A (zh) * 2018-06-29 2018-10-30 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010050262A1 (ja) * 2008-10-30 2010-05-06 シャープ株式会社 シフトレジスタ回路および表示装置ならびにシフトレジスタ回路の駆動方法
US8587508B2 (en) * 2008-12-10 2013-11-19 Sharp Kabushiki Kaisha Scanning signal line drive circuit, shift register, and drive method of driving shift register
CN101609718B (zh) * 2009-07-20 2012-06-27 友达光电股份有限公司 移位寄存器
CN102024500B (zh) * 2009-09-10 2013-03-27 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN103065578B (zh) * 2012-12-13 2015-05-13 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN203882580U (zh) * 2014-06-16 2014-10-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN104392704A (zh) * 2014-12-15 2015-03-04 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
KR102420236B1 (ko) * 2015-10-27 2022-07-14 엘지디스플레이 주식회사 표시장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130249884A1 (en) * 2012-03-22 2013-09-26 Cheol-min Kim Gate driving circuit and display apparatus using the same
CN106601176A (zh) * 2017-01-16 2017-04-26 京东方科技集团股份有限公司 移位寄存器单元电路、驱动方法、移位寄存器和显示装置
CN108717844A (zh) * 2018-06-29 2018-10-30 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

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