WO2021185328A1 - 移位寄存器及驱动方法、显示装置 - Google Patents

移位寄存器及驱动方法、显示装置 Download PDF

Info

Publication number
WO2021185328A1
WO2021185328A1 PCT/CN2021/081629 CN2021081629W WO2021185328A1 WO 2021185328 A1 WO2021185328 A1 WO 2021185328A1 CN 2021081629 W CN2021081629 W CN 2021081629W WO 2021185328 A1 WO2021185328 A1 WO 2021185328A1
Authority
WO
WIPO (PCT)
Prior art keywords
switching device
signal
voltage
terminal
coupled
Prior art date
Application number
PCT/CN2021/081629
Other languages
English (en)
French (fr)
Inventor
郑皓亮
玄明花
刘冬妮
张振宇
肖丽
陈亮
陈昊
赵蛟
袁丽君
欧阳义
齐琪
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/760,733 priority Critical patent/US11847966B2/en
Publication of WO2021185328A1 publication Critical patent/WO2021185328A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a driving method, and a display device.
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • a shift register in one aspect, includes a voltage control circuit and a bias compensation circuit.
  • the voltage control circuit is coupled to the first node and is configured to control the voltage of the first node to be the first voltage or the second voltage.
  • the bias compensation circuit is coupled to the first node, the first voltage terminal, the first signal terminal, the second signal terminal, the first signal output terminal, and the second signal output terminal, and is configured to respond to the first signal.
  • the voltage of a node is the first voltage, the first signal received by the first signal terminal is transmitted to the first signal output terminal, and the second signal received by the second signal terminal is transmitted to the first signal output terminal.
  • Two signal output terminals and, in response to the voltage of the first node being the second voltage, transmitting the signal received by the first voltage terminal to the first signal output terminal and the second signal output terminal .
  • the bias compensation circuit includes: a third switching device, a fourth switching device, a fifth switching device, and a sixth switching device.
  • the control pole and the first pole of the third switching device are both coupled to the first signal terminal, and the second pole of the third switching device is coupled to the first signal output terminal.
  • the control pole of the fourth switching device is coupled to the first node, the first pole of the fourth switching device is coupled to the first signal output terminal, and the second pole of the fourth switching device is coupled to The first voltage terminal is coupled.
  • the control pole and the first pole of the fifth switch device are both coupled to the second signal terminal, and the second pole of the fifth switch device is coupled to the second signal output terminal.
  • the control pole of the sixth switching device is coupled to the first node, the first pole of the sixth switching device is coupled to the second signal output terminal, and the second pole of the sixth switching device is coupled to the The first voltage terminal is coupled.
  • the voltage control circuit includes: an output sub-circuit and a denoising sub-circuit.
  • the output sub-circuit is coupled to a clock signal terminal, a second node, and the first node, and is configured to transmit the clock signal of the clock signal terminal to the first node in response to the voltage of the second node , So that the voltage of the first node is the first voltage or the second voltage.
  • the denoising sub-circuit is coupled to the first voltage terminal, the first node, and the third node, and is configured to control the voltage of the first node to be the first node in response to the voltage of the third node. Voltage.
  • the output sub-circuit includes an eleventh switching device, the control pole of the eleventh switching device is coupled to the second node, and the first pole of the eleventh switching device is connected to the second node.
  • the clock signal terminal is coupled, and the second pole of the eleventh switching device is coupled to the first node.
  • the output sub-circuit is further configured to increase or decrease the voltage of the second node in response to the voltage of the first node being the second voltage.
  • the output sub-circuit further includes an energy storage device, a first plate of the energy storage device is coupled to the first node, and a second plate of the energy storage device is connected to the first node. Two-node coupling.
  • the output sub-circuit is further connected to a third signal output terminal, a second voltage terminal, and the second node, and is further configured to respond to the voltage of the second node to connect the clock signal terminal The received clock signal is transmitted to the third signal output terminal.
  • the output sub-circuit further includes a tenth switching device, the control pole of the tenth switching device is coupled to the second node, and the first pole of the tenth switching device is connected to the clock The signal terminal is coupled, and the second pole of the tenth switch device is coupled to the third signal output terminal.
  • the denoising sub-circuit includes a seventeenth switching device, a control pole of the seventeenth switching device is coupled to the third node, and a first pole of the seventeenth switching device is coupled to the third node.
  • the first node is coupled, and the second pole of the seventeenth switching device is coupled to the first voltage terminal.
  • the denoising sub-circuit is further coupled to the third signal terminal, and is further configured to transmit the signal received by the third signal terminal to the third node.
  • the denoising sub-circuit further includes a fifteenth switching device, the control pole and the first pole of the fifteenth switching device are both coupled to the third signal terminal, and the fifteenth switching device The second pole of the switching device is coupled to the third node.
  • the denoising sub-circuit is further configured to transmit the signal received by the second voltage terminal to the third signal output terminal in response to the voltage of the third node.
  • the denoising sub-circuit further includes a sixteenth switching device, the control pole of the sixteenth switching device is coupled to the third node, and the first pole of the sixteenth switching device It is coupled to the third signal output terminal, and the second pole of the sixteenth switching device is coupled to the second voltage terminal.
  • the shift register further includes: an input circuit that is coupled to a signal input terminal, the second node, the third node, and the second voltage terminal, and is configured to In response to the input signal received by the signal input terminal, the voltage of the second node and the voltage of the third node are controlled.
  • the input circuit includes a seventh switching device and a ninth switching device.
  • the control pole and the first pole of the seventh switching device are both coupled to the signal input terminal, and the second pole of the seventh switching device is coupled to the second voltage terminal.
  • the control pole of the ninth switching device is coupled to the second node, the first pole of the ninth switching device is coupled to the third node, and the second pole of the ninth switching device is coupled to the The second voltage terminal is coupled.
  • the input circuit further includes an eighth switching device, the control pole of the eighth switching device is coupled to the signal input terminal, and the first pole of the eighth switching device is connected to the third Node coupling, and the second pole of the eighth switching device is coupled to the second voltage terminal.
  • the shift register further includes a reset circuit that is coupled to the first reset signal terminal, the second node, and the second voltage terminal, and is configured to respond to the first reset signal terminal, the second node, and the second voltage terminal.
  • the signal received by a reset signal terminal transmits the signal received by the second voltage terminal to the second node.
  • the reset circuit includes a thirteenth switching device, the control pole of the thirteenth switching device is coupled to the first reset signal terminal, and the first pole of the thirteenth switching device is coupled to the first reset signal terminal.
  • the second voltage terminal is coupled, and the second pole of the thirteenth switching device is coupled to the second node.
  • the reset circuit is further coupled to a second reset signal terminal, and the reset circuit is further configured to respond to the signal received by the second reset signal terminal to transfer the signal received by the second voltage terminal Transmitting a signal to the second node; and in response to the signal received by the second reset signal terminal, transmitting the signal received by the first voltage terminal to the first node, so that the voltage of the first node is The first voltage.
  • the reset circuit includes a twelfth switching device and a fourteenth switching device.
  • the control pole of the twelfth switching device is coupled to the second reset signal terminal, the first pole of the twelfth switching device is coupled to the second node, and the first pole of the twelfth switching device is coupled to the second node.
  • the two poles are coupled to the second voltage terminal.
  • a fourteenth switching device, the control pole of the fourteenth switching device is coupled to the second reset signal terminal, the first pole of the fourteenth switching device is coupled to the first node, and the The second pole of the fourteen switching device is coupled to the first voltage terminal.
  • a display device in another aspect, includes: the shift register and the pixel drive circuit described in any of the above embodiments.
  • the pixel driving circuit includes: a first switching device and a second switching device, a control pole of the first switching device is coupled to a first signal output terminal of the shift register, and a control pole of the second switching device Is coupled to the second signal output terminal of the shift register, the first pole of the first switching device is coupled to the first pole of the second switching device, and the second pole of the first switching device is coupled to The second pole of the second switching device is coupled.
  • a method for driving a shift register includes: a first node, a first signal terminal, a second signal terminal, a first signal output terminal, a second signal output terminal, and a first voltage terminal.
  • the driving method of the shift register includes:
  • the first signal received by the first signal terminal is transmitted to the first signal output terminal, and the second signal received by the second signal terminal is transmitted Transmitted to the second signal output terminal;
  • the signal received by the first voltage terminal is transmitted to the first signal output terminal and the second signal output terminal.
  • the first signal and the second signal are both rectangular wave signals, and the levels of the two are opposite.
  • the first signal and the second signal are both square wave signals.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is a structural diagram of sub-pixels of a display panel of a display device according to some embodiments
  • FIG. 3 is a structural diagram of a shift register of a display device according to some embodiments.
  • 4A is another structural diagram of the shift register of the display device according to some embodiments.
  • 4B is another structural diagram of the shift register of the display device according to some embodiments.
  • FIG. 5 is a structural diagram of a display panel of a display device according to some embodiments.
  • FIG. 6 is a signal flow diagram of the shift register of the display device in the initial stage according to some embodiments.
  • FIG. 7 is a signal flow diagram of the shift register of the display device according to some embodiments in the data writing stage
  • FIG. 8 is a signal flow diagram of the shift register of the display device in the denoising stage according to some embodiments.
  • FIG. 9 is a signal flow diagram of the shift register of the display device in the reset phase according to some embodiments.
  • FIG. 10 is a timing diagram of a driving method of a shift register of a display device according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device may be any device that displays whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or image. More specifically, the display device may be one of a variety of electronic devices, and the embodiment may be implemented in or associated with a variety of electronic devices, such as (but not limited to) Mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, Flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, camera view displays (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards Or signs, projectors, architectural structures, packaging and aesthetic structures (for example, a display for an image of a piece of jewelry), etc.
  • the embodiments of the present disclosure do not impose special
  • the display device 1 may include a display panel 10. As shown in FIG. 1, the display panel 10 has a display area (Active Area, AA) and a peripheral area S at least on one side of the AA area.
  • AA Active Area
  • a plurality of sub-pixels P are provided in the AA area of the display panel 10.
  • the multiple sub-pixels P are arranged in an orderly manner in the AA area, and the arrangement manner can be designed according to actual conditions.
  • a plurality of sub-pixels P are arranged in an array form, wherein the sub-pixels P arranged in a row along the X direction are called sub-pixels in the same row, and the sub-pixels P arranged in a row along the Y direction are called the same column. Pixels.
  • the peripheral area S of the display panel 10 is provided with a light emission control driving circuit 100.
  • the light emission control driving circuit 100 includes a plurality of shift registers SR(1) to SR(n). Each shift register SR(i) is coupled to a row of sub-pixels, and is used to output emission control signals EM1(i) and EM2(i) to the row of sub-pixels.
  • the display panel 10 further includes a plurality of light-emitting signal lines (for example, 2n light-emitting signal lines).
  • the plurality of light-emitting signal lines extend along the X direction in FIG.
  • the light emission control signal for example, a plurality of sub-pixels in the display panel 10 are divided into n rows of sub-pixels, wherein the i-th row of sub-pixels is coupled to the i-th stage shift register SR(i) through the light-emitting signal line, and n is a positive integer , 1 ⁇ i ⁇ n, i is an integer, so that the shift register SR(i) can transmit the emission control signals EM1(i) and EM2(i) to the i-th row of sub-pixels through the emission signal line.
  • At least one sub-pixel P (for example, each sub-pixel P) includes a pixel driving circuit 200 and a light emitting device L.
  • the pixel driving circuit 200 is coupled to the light emitting device L.
  • the pixel driving circuit 200 is configured to drive the light emitting device L to emit light.
  • the arrangement manner of the plurality of sub-pixels P may refer to the arrangement manner of the pixel driving circuits in the plurality of sub-pixels P, that is, the plurality of pixel driving circuits may be arranged in an array form.
  • the light-emitting device L may adopt Organic Light-Emitting Diode (OLED for short), Quantum Dot Light-Emitting Diodes (QLED for short), etc.
  • the light emitting device L includes a cathode and an anode, and a light emitting function layer located between the cathode and the anode.
  • the light-emitting functional layer may include, for example, a light-emitting layer, a hole transport layer (HTL) between the light-emitting layer and the anode, and an electron transport layer (Election Transporting Layer, ETL) between the light-emitting layer and the cathode.
  • a hole injection layer (Hole Injection Layer, HIL) can also be provided between the hole transport layer HTL and the anode, and an electron injection layer (HIL) can be provided between the electron transport layer ETL and the cathode.
  • HIL Hole Injection Layer
  • EIL election Injection Layer
  • the anode may be formed of a transparent conductive material with a high work function
  • the electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) oxide.
  • the cathode can be formed of materials with high conductivity and low work function, for example, and its electrode materials can include magnesium aluminum alloy (MgAl) and lithium Alloys such as aluminum alloy (LiAl) or simple metals such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag).
  • the material of the light-emitting layer can be selected according to the color of the emitted light.
  • the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • the light-emitting layer may adopt a doping system, that is, a dopant material is mixed into the host light-emitting material to obtain a usable light-emitting material.
  • the host luminescent material may use metal compound materials, anthracene derivatives, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, benzidine diamine derivatives, and triarylamine polymers.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel driving circuit, and can be designed according to actual conditions.
  • the pixel driving circuit is composed of electronic devices such as a switching device, a driving device, and a capacitor (Capacitance, C for short), where the switching device and the driving device may be a thin film transistor (TFT for short), for example, a switching device It may be a switching transistor, and the driving device may be a driving transistor.
  • TFT thin film transistor
  • the pixel driving circuit may include three thin film transistors (two switching transistors and one driving transistor) and a capacitor to form a 3T1C structure; of course, the pixel driving circuit may also include more than three thin film transistors (multiple switching transistors and one The driving transistor) and at least one capacitor form a 7T1C structure, an 8T1C structure, a 9T1C structure, and so on.
  • the control electrode (also referred to as the gate) of the thin film transistor in the pixel driving circuit can be used to receive different signals.
  • the control electrode of the driving transistor D-TFT in the pixel driving circuit 200 can be used to Receive the data signal V DATA , or receive the data signal V DATA +Vth compensated by the threshold voltage of the driving transistor D-TFT, where Vth is the threshold voltage of the driving transistor D-TFT, V DATA is the voltage signal, according to the received
  • the driving transistor D-TFT can control the intensity (for example, the magnitude of the current) of the electric signal flowing through the light-emitting device L, thereby controlling the light-emitting brightness of the light-emitting device L.
  • the switching devices in the pixel driving circuit may all be switching transistors.
  • the switching transistor can be turned on or off according to the signal received by its control pole.
  • the control electrode of the switch transistor of the pixel driving circuit can be used to receive the light emission control signal or the gate scan signal, and the switch transistor can be turned on or off according to the light emission control signal or the gate scan signal received.
  • the switching transistor can be an oxide thin-film transistor. Due to its own characteristics, the oxide thin-film transistor is more sensitive to positive and negative pressures. The threshold voltage of the transistor will occur if the transistor is exposed to the same pressure for a long time. Offset.
  • the prior art pixel driving circuit includes a switching transistor for receiving a light-emitting control signal. Because the switching transistor is under positive pressure for a long time, the threshold voltage is shifted, which causes the light-emitting device coupled to the pixel driving circuit to shift. The luminous brightness of the device decreases.
  • the pixel driving circuit 200 includes: a first switching device T1 and a second switching device T2.
  • the first switching device T1 and The second switching device T2 is configured to receive the light emission control signal.
  • the control pole of the first switching device T1 is coupled to the first signal output terminal EM1
  • the control pole of the second switching device is coupled to the second signal output terminal EM2
  • the first pole of the first switching device T1 is coupled to the second switching device T2
  • the first pole of the first switching device T1 is coupled to the second pole of the second switching device T2.
  • the first signal output terminal EM1 and the second signal output terminal EM2 may be located in a shift register, and the first signal output terminal EM1 may output the first light emission control signal to the first switching device T1.
  • the second signal output terminal EM2 can output a second light-emitting control signal to the second switching device T2, where the first light-emitting control signal and the second light-emitting control signal can be high and low alternating level signals.
  • the transistors in the pixel driving circuit 200 as an example of a high-on and low-off N-type transistor, for example, when the first light-emitting control signal is at a high level, the second light-emitting control signal is at a low level.
  • the first switch The device T1 is turned on, the second switching device T2 is turned off, and the light-emitting device L can emit light, or, when the first light-emitting control signal is at a low level, the second light-emitting control signal is at a high level, and at this time, the first switching device T1 is turned off Off, the second switching device T2 is turned on, and the light-emitting device L can also emit light, or, when the first light-emitting control signal is at a low level and the second light-emitting control signal is also at a low level, the first switching device T1 and the second switch The devices T2 are all turned off, and the light-emitting device L does not emit light.
  • the second light-emitting control signal When the first light-emitting control signal is at a high level, the second light-emitting control signal is at a low level. At this time, the first switch device T1 is turned on, the light-emitting device L can normally emit light, and the second switch device T2 is compensated. For example, if the output voltage of the first light-emitting control signal is 10V, the input voltage of the control electrode of the first switching device T1 is 10V, and the second electrode voltage of the first switching device T1 is the same as the control electrode voltage of the first switching device T1. For example, if the voltage drop of the first switching device T1 is 1V, then the voltage of the second pole of the first switching device T1 is 9V.
  • the control pole of the first switching device T1 and the second pole of the The voltage difference is 1V, so that the first switching device T1 is forward biased; since the second light-emitting control signal is a low-level signal, for example, its input voltage is -15V, and the second pole of the second switching device T2 is The second pole of a switching device T1 is coupled, so the voltage of the second pole of the second switching device T2 is equal to the voltage of the second pole of the first switching device T1, that is, 9V. Therefore, the control pole of the second switching device T2 The difference between the voltage of the second pole and the voltage of the second pole is (-19)V, so that the second switching device T2 is in a negative bias.
  • the first switching device T1 By controlling the first light-emitting control signal to a high and low level signal alternately, the first switching device T1 can be biased forward and negatively, respectively, and when the level signal is continuously switched, the first switching device T1 can also switch back and forth between positive bias and negative bias, so that the positive and negative pressure it receives can be offset, thereby avoiding or reducing the threshold voltage shift.
  • the second switching device T2 in the pixel driving circuit 200 can also achieve the purpose of avoiding or reducing the threshold voltage deviation by controlling the input of the second light-emitting control signal and the bias compensation of the second switching device T2. Similar, not repeat them.
  • the embodiment of the present disclosure provides a shift register SR for outputting a first light emission control signal and a second light emission control signal to the pixel driving circuit 200.
  • the shift register SR includes: a voltage control circuit 110 and a bias compensation circuit 120.
  • the voltage control circuit 110 is coupled to the first node Output
  • the bias compensation circuit 120 is connected to the first node Output, the first voltage terminal LVGL1, the first signal terminal VDD-A, the second signal terminal VDD-B, and the first signal
  • the output terminal EM1 is coupled to the second signal output terminal EM2.
  • the first voltage terminal LVGL1 is a DC low voltage terminal.
  • the voltage of the first voltage terminal LVGL1 is (-15)V, and the signal output by the first voltage terminal LVGL1 may be a low level signal.
  • the first signal terminal VDD-A and the second signal terminal VDD-B are signal receiving terminals, which can receive the first signal and the second signal, respectively.
  • the first signal output terminal EM1 and the second signal output terminal EM2 are the signal output terminals of the shift register SR, and are configured to transmit the output signal of the shift register SR to other circuits. For example, when the shift register and the pixel drive circuit When coupled, the shift register SR can transmit light emission control signals to the pixel driving circuit. For example, referring to FIGS.
  • the first signal output terminal EM1 and the second signal output terminal EM2 of the shift register SR are respectively connected to the pixel driving circuit.
  • the first switching device T1 and the second switching device T2 of the 200 are coupled to each other to transmit the first light-emitting control signal and the second light-emitting control signal to the first switching device T1 and the second switching device T2 to control the first switching device T1 ,
  • the second switching device T2 is turned on or off.
  • the voltage control circuit 110 is configured to control the voltage of the first node Output to be the first voltage or the second voltage.
  • the first voltage and the second voltage are two voltages with different levels.
  • the first voltage is a low voltage
  • the second voltage is a high voltage.
  • the first voltage is (-15)V and the second voltage is 10V.
  • the bias compensation circuit 120 is configured to transmit the first signal received by the first signal terminal VDD-A to the first signal output terminal EM1 in response to the voltage of the first node Output being the first voltage, and transfer the second signal terminal VDD-
  • the second signal received by B is transmitted to the second signal output terminal EM2; and, in response to the voltage of the first node Output being the second voltage, the signal received by the first voltage terminal LVGL1 is transmitted to the first signal output terminal EM1 and the second signal output terminal EM1 and the second signal output terminal EM1.
  • the first signal and the second signal may be respectively transmitted to the first signal output terminal EM1 and the second signal output terminal EM2.
  • the first signal and the second signal may both be high and low alternating level signals, and the output levels of the first signal and the second signal may be different at the same time.
  • the first signal output from the first signal terminal VDD-A and the second signal output from the second signal terminal VDD-B are mutually inverted signals.
  • the phase difference between the first signal and the second signal is 180°.
  • the first signal is a low-level signal
  • the second signal is a high-level signal; when the first signal is a high-level signal, the second signal is a low-level signal.
  • the first signal and the second signal will not be high-level signals at the same time.
  • the light emitting device L in the pixel driving circuit 200 can be made to emit light normally, and the first switching device T1 and the second switching device T2 can be compensated.
  • the first switching device T1 when the first signal is at a high level, the first switching device T1 is turned on to make the light emitting device L emit light.
  • the second signal since the second signal is a low level signal, Will not interfere with the light-emitting control signal of the light-emitting device L, and the second switching device T2 can still be negatively biased under the control of the low-level signal; similarly, when the second signal is high-level, the first signal It is low level, and its function is similar, so I won't repeat it.
  • the first signal terminal VDD-A and the second signal terminal VDD-B can be controlled to output different levels (high level or low level), and in the next light-emitting stage , The level of the two outputs is exchanged, that is, through special timing control, the first signal terminal VDD-A and the second signal terminal VDD-B output alternating high and low signals with opposite levels.
  • the first switching device T1 and the second switching device T2 perform time-sharing compensation, thereby avoiding or reducing the influence of threshold voltage offset.
  • the first signal terminal VDD-A outputs a high level
  • the second signal terminal VDD-B outputs a low level
  • the high level is used to switch the first switching device in the pixel driving circuit 200 T1 is turned on to make the light-emitting device L emit light normally, and the low level compensates for the second switching device T2
  • the first signal terminal VDD-A outputs a low level, so that the first switching device T1 is compensated.
  • the two signal terminals VDD-B output a high level, so that the second switch device T2 controls the light emitting device L to emit light normally, and so alternately.
  • the duty ratios of the first signal received at the first signal terminal VDD-A and the second signal received at the second signal terminal VDD-B are approximately the same, so that the first switching device T1 and the second signal
  • the positive and negative bias times of the two switching devices T2 are similar, so that the positive and negative pressures received by the first switching device T1 and the second switching device T2 are completely offset.
  • the signal received by the first voltage terminal LVGL1 can be transmitted to the first signal output terminal EM1 and the second signal output terminal EM2, for example, in the pixel driving circuit 200 to enter reset, compensation and data
  • the voltage of the first node Output is controlled to the second voltage, so that the first signal output terminal EM1 and the second signal output terminal EM2 receive the signal output by the first voltage terminal LVGL1, for example, the first voltage terminal LVGL1 receives
  • the signal of is a low-level signal, and the low-level signal is transmitted to the first signal output terminal EM1 and the second signal output terminal EM2 to turn off both the first switching device T1 and the second switching device T2 in the pixel driving circuit 200 Then, the light-emitting device L does not emit light.
  • the first signal terminal VDD-A when the voltage control circuit 110 outputs the first voltage to the first node Output, for example, the first signal terminal VDD-A can be connected to the first signal output terminal through the bias compensation circuit 120.
  • EM1 is coupled to couple the second signal terminal VDD-B to the second signal output terminal EM1, thereby transmitting the first signal received by the first signal terminal VDD-A to the first signal output terminal EM1, and the second signal terminal The second signal received by VDD-B is transmitted to the second signal output terminal EM2; when the voltage control circuit 110 outputs the second voltage to the first node Output, for example, the first voltage terminal LVGL1 can be transferred by the bias compensation circuit 120 It is coupled to the first signal output terminal EM1 and the second signal output terminal EM2 to transmit the signal received by the first voltage terminal LVGL1 to the first signal output terminal EM1 and the second signal output terminal EM2.
  • the bias compensation circuit 120 includes: a third switching device T3, a fourth switching device T4, a fifth switching device T5, and a sixth switching device T6.
  • the control pole and the first pole of the third switching device T3 are both coupled to the first signal terminal VDD-A, the second pole of the third switching device T3 is coupled to the first signal output terminal EM1; the fourth switching device T4
  • the control pole of the fourth switching device T4 is coupled to the first node Output, the first pole of the fourth switching device T4 is coupled to the first signal output terminal EM1, and the second pole of the fourth switching device T4 is coupled to the first voltage terminal LVGL1;
  • the control pole and the first pole of the switching device T5 are both coupled to the second signal terminal VDD-B, the second pole of the fifth switching device T5 is coupled to the second signal output terminal EM2; the control pole of the sixth switching device T6 is coupled to The first node Output is coupled, the first pole of the sixth switching device T6 is coupled to the second
  • the fourth switching device T4 and the sixth switching device T6 are turned off under the action of the first voltage, and the signal received by the first voltage terminal LVGL1 cannot be transmitted to the first node Output.
  • the third switching device T3 and the fifth switching device T5 are turned on under the action of the first signal and the second signal, and the first signal terminal VDD-A is coupled to the first signal output terminal EM1, and the second signal terminal VDD -B is coupled to the second signal output terminal EM2, so that the signals output by the first signal terminal VDD-A and the second signal terminal VDD-B are respectively transmitted to the first signal through the third switching device T3 and the fourth switching device T4
  • the output terminal EM1 and the second signal output terminal EM2 enable the first signal output terminal EM1 and the second signal output terminal EM2 to receive the first signal and the second signal, respectively.
  • the third switching device T3, the fourth switching device T4, the fifth switching device T5, and the sixth switching device T6 are all turned on, and because the fourth switching device
  • the sizes of T4 and the sixth switching device T6 are larger than the sizes of the third switching device T3 and the fifth switching device T5.
  • the aspect ratio of the fourth switching device T4 is 3 times that of the third switching device T3, and the sixth switching device T6
  • the aspect ratio of is 3 times that of the fifth switching device T5, so that the signals output by the first signal output terminal EM1 and the second signal output terminal EM2 are the signals received by the first voltage terminal LVGL1.
  • control pole of the third switching device T3 and the control pole of the fifth switching device T5 can also always be connected to a high-level terminal (such as VGH), so that the third switching device T3 and the fifth switching device T5 Always keep it open.
  • VGH high-level terminal
  • the voltage control circuit 110 When the voltage control circuit 110 outputs the first voltage to the first node Output, the signals of the first signal terminal VDD-A and the second signal terminal VDD-B can directly reach the first signal output terminal EM1 and the second signal output terminal EM2; When the voltage control circuit 110 outputs the second voltage to the first node Output, by setting the size of the fourth switching device T4 and the sixth switching device T6, the signal received by the first voltage terminal LVGL1 can also be transmitted to the first signal output terminal EM1 and the second signal output terminal EM2 are not affected.
  • the voltage control circuit 110 of the shift register SR includes an output sub-circuit 112 and a denoising sub-circuit 111.
  • the output sub-circuit 112 is coupled to the clock signal terminal GCLK, the second node PU, and the first node Output, and is configured to transmit the clock signal of the clock signal terminal GCLK to the first node Output in response to the voltage of the second node PU, so that The voltage of the first node Output is the first voltage or the second voltage.
  • the output sub-circuit 112 may couple the clock signal terminal GCLK to the first node Output to transmit the clock signal of the clock signal terminal GCLK to the first node Output.
  • the voltage of the first node Output is configured as the second voltage.
  • the signal transmitted by the clock signal to the first node Output is low, the signal of the first node Output is low.
  • the voltage is configured as the first voltage.
  • the output sub-circuit 112 includes an eleventh switching device T11, wherein the control pole of the eleventh switching device T11 is coupled to the second node PU, and the first pole of the eleventh switching device T11 is coupled to the second node PU.
  • the clock signal terminal GCLK is coupled, and the second pole of the eleventh switching device T11 is coupled to the first node Output.
  • the voltage of the second node PU is greater than a certain value (for example, 1V), for example, the voltage of the second node PU is 10V, and the voltage of the second node PU can turn on the eleventh switching device T11, and connect the clock signal terminal GCLK to the first A node Output is coupled, so that the clock signal of the clock signal terminal GCLK is transmitted to the first node Output through the eleventh switch device T11.
  • a certain value for example, 1V
  • the voltage of the second node PU is 10V
  • the voltage of the second node PU can turn on the eleventh switching device T11, and connect the clock signal terminal GCLK to the first A node Output is coupled, so that the clock signal of the clock signal terminal GCLK is transmitted to the first node Output through the eleventh switch device T11.
  • the output sub-circuit 112 is further configured to increase or decrease the voltage of the second node PU in response to the voltage of the first node Output being the second voltage.
  • the output sub-circuit 112 further includes an energy storage device C1, the first plate of the energy storage device C1 is coupled to the first node Output, and the second plate of the energy storage device C1 is coupled to the second node PU.
  • the energy storage device C1 can change the voltage of the node coupled to the energy storage device C1 through a “bootstrap” effect.
  • the voltage on the first electrode plate of the energy storage device C1 is the first voltage
  • the voltage on the second electrode plate is the second voltage.
  • the voltage on the coupled first plate is raised to the second voltage.
  • the voltage on the second plate can be raised to a higher value than the first With the higher voltage value of the second voltage, the voltage of the second node PU coupled to the second plate is also increased.
  • the output sub-circuit 112 is further connected to the third signal output terminal Out-C, the second voltage terminal LVGL2, and the second node PU, and is also configured to respond to the voltage of the second node PU to connect the clock signal terminal GCLK The received clock signal is transmitted to the third signal output terminal Out-C.
  • the output sub-circuit 112 may couple the clock signal terminal GCLK to the third signal output terminal Out-C to connect the clock received by the clock signal terminal GCLK The signal is transmitted to the third signal output terminal Out-C.
  • the output sub-circuit 112 further includes: a tenth switching device T10, the control pole of the tenth switching device T10 is coupled to the second node PU, and the first pole of the tenth switching device T10 is coupled to the clock signal terminal GCLK Then, the second pole of the tenth switching device T10 is coupled to the third signal output terminal Out-C.
  • the voltage of the second node PU is the second voltage
  • the tenth switching device T10 is turned on, and the clock signal terminal GCLK is coupled to the third signal output terminal Out-C, so that the clock signal of the clock signal terminal GCLK passes through the tenth switch
  • the device T10 is transmitted to the third signal output terminal Out-C.
  • the denoising sub-circuit 111 is coupled to the first voltage terminal LVGL1, the first node Output, and the third node PD, and is configured to control the voltage of the first node Output to the first voltage in response to the voltage of the third node PD.
  • the denoising sub-circuit 111 may couple the first voltage terminal LVGL1 to the first node Output, so that the signal received by the first voltage terminal LVGL1 is transmitted to the first voltage terminal LVGL1.
  • the node Output configures the voltage of the first node Output as the first voltage.
  • the denoising sub-circuit 111 includes a seventeenth switching device T17, the control pole of the seventeenth switching device T17 is coupled to the third node PD, and the first pole of the seventeenth switching device T17 is coupled to the first node. Output is coupled, and the second pole of the seventeenth switching device T17 is coupled to the first voltage terminal LVGL1.
  • the seventeenth switch device T17 When the voltage of the third node PD is the second voltage, the seventeenth switch device T17 is turned on to couple the first voltage terminal LVGL1 to the first node Output, so that the signal received by the first voltage terminal LVGL1 passes through the seventeenth switch The device T17 transmits to the first node Output, and configures the voltage of the first node Output as the first voltage.
  • the denoising sub-circuit 111 is also coupled to the third signal terminal VDD-C, and is further configured to transmit the signal received by the third signal terminal VDD-C to the third node PD.
  • the denoising sub-circuit 111 may couple the third signal terminal VDD-C to the third node PD, so as to transmit the signal received by the third signal terminal VDD-C to the third node PD.
  • the signal received by the third signal terminal VDD-C may also be a level signal.
  • the signal received by the third signal terminal VDD-C is a continuous high level signal.
  • the denoising sub-circuit further includes a fifteenth switching device T15, the control pole and the first pole of the fifteenth switching device T15 are both coupled to the third signal terminal VDD-C, and the fifteenth switching device T15 The second pole of is coupled to the third node PD.
  • the third signal terminal VDD-C receives a high-level signal
  • the high-level signal can turn on the fifteenth switching device T15 and couple the third signal terminal VDD-C to the third node PD, so that the third The high-level signal received by the signal terminal VDD-C is transmitted to the third node PD through the fifteenth switching device T15.
  • the denoising sub-circuit 111 is further configured to transmit the signal received by the second voltage terminal LVGL2 to the third signal output terminal Out-C in response to the voltage of the third node PD.
  • the second voltage terminal LVGL2 is a DC low voltage terminal.
  • the voltage of the second voltage terminal LVGL2 is equal to the voltage of the first voltage terminal LVGL1.
  • the second voltage terminal LVGL2 is coupled to the first voltage terminal LVGL1, and the second voltage terminal LVGL2 is coupled to the first voltage terminal LVGL1.
  • the signal output by the voltage terminal LVGL2 may be a low-level signal.
  • the denoising sub-circuit 111 may couple the second voltage terminal LVGL2 to the third signal output terminal Out-C to connect the signal received by the second voltage terminal LVGL2 The signal is transmitted to the third signal output terminal Out-C.
  • the denoising sub-circuit 111 further includes a sixteenth switching device T16, the control pole of the sixteenth switching device T16 is coupled to the third node PD, and the first pole of the sixteenth switching device is connected to the third signal output terminal Out- C) Coupling, the second pole of the sixteenth switching device T16 is coupled to the second voltage terminal LVGL2.
  • the sixteenth switching device T16 is turned on under the control of the second voltage, and the second voltage terminal LVGL2 is coupled to the third signal output terminal Out-C, so that the second The signal received by the voltage terminal LVGL2 is transmitted to the third signal output terminal Out-C.
  • the shift register further includes an input circuit 130, which is coupled to the signal input terminal STPV, the second node PU, the third node PD, and the second voltage terminal LVGL2, and is configured to respond to the signal input terminal
  • the input signal received by the STPV controls the voltage of the second node PU and the voltage of the third node PD.
  • the input circuit 130 may control the voltage of the second node PU and the voltage of the third node PD so that the level signals of the two are inverted signals.
  • the signal of the second node PU is a high-level signal.
  • the voltage of the third node PD is the first voltage, and the signal of the third node PD is Low-level signal.
  • the voltage of the third node PD is the second voltage, and the signal of the third node PD is It is a high level signal.
  • the signal input terminal STPV can be used as the start signal input terminal of a shift register SR.
  • the voltage of the second node PU may be set high.
  • the voltage of the second node PU may be the second voltage
  • the voltage of the third node PD may be Is set low, for example, the voltage of the third node PD is the first voltage.
  • the input circuit 130 includes a seventh switching device T7 and a ninth switching device T9.
  • the control pole and the first pole of the seventh switching device T7 are both coupled to the signal input terminal STPV.
  • the two poles are coupled to the second voltage terminal LVGL2; the control pole of the ninth switching device T9 is coupled to the second node PU, the first pole of the ninth switching device T9 is coupled to the third node PD, and the first pole of the ninth switching device T9 is coupled to the third node PD.
  • the two poles are coupled to the second voltage terminal LVGL2.
  • the seventh switch device T7 is turned on under the action of the high level, and the signal The input terminal STPV is coupled to the second node PU, so that the high-level signal input from the signal input terminal STPV is input to the second node PU, thereby setting the voltage of the second node PU high, for example, configuring the voltage of the second node PU Is the second voltage.
  • the ninth switching device T9 is turned on, and the second voltage terminal LVGL2 is coupled to the third node PD.
  • the signal received by the second voltage terminal LVGL2 can be transmitted to the third node PD, and the voltage of the third node PD is lowered.
  • the third node PD is Configured as the first voltage.
  • the input circuit 130 further includes an eighth switching device T8, the control pole of the eighth switching device T8 is coupled to the signal input terminal STPV, and the first pole of the eighth switching device T8 is coupled to the third node PD, The second pole of the eighth switching device T8 is coupled to the second voltage terminal LVGL2.
  • the eighth switch device T8 When the signal input terminal STPV inputs the first stage high level signal, the eighth switch device T8 is turned on under the action of the high level, and the second voltage terminal LVGL2 is coupled to the third node PD, so that the second voltage terminal LVGL2 is coupled to the third node PD.
  • the signal received by the voltage terminal LVGL2 is transmitted to the third node PD, and the third node PD is configured as the first voltage.
  • the gate of the eighth switching device T8 is directly coupled to the signal input terminal STPV, compared to the ninth switching device T9, the opening and closing of the ninth switching device T9 is directly controlled by the second node PU, so that the signal input terminal STPV The input signal first reaches the second node PU, and then reaches the gate of the ninth switching device T9 through the second node PU.
  • the eighth switching device T8 is more directly controlled by the input signal.
  • the shift register SR further includes a reset circuit 140, which is coupled to the first reset signal terminal RST1, the second node PU, and the second voltage terminal LVGL2, and is configured to respond to the first reset signal terminal
  • the signal received by RST1 transmits the signal received by the second voltage terminal LVGL2 to the second node PU.
  • the reset circuit 140 may couple the second voltage terminal LVGL2 to the second node PU, so that the signal received by the second voltage terminal LVGL2 is transmitted to For the second node PU, for example, the signal configures the voltage of the second node PU as the first voltage.
  • the reset circuit 140 includes a thirteenth switching device T13, the control pole of the thirteenth switching device T13 is coupled to the first reset signal terminal RST1, and the first pole of the thirteenth switching device T13 is coupled to the second voltage terminal LVGL2 , The second pole of the thirteenth switching device is coupled to the second node PU.
  • the signal input from the first reset signal terminal RST1 is a high-level signal
  • the high-level signal turns on the thirteenth switching device T13, coupling the second voltage terminal LVGL2 to the second node PU, so that the second voltage terminal
  • the signal received by LVGL2 is transmitted to the second node PU through the thirteenth switching device T13.
  • the reset circuit 140 is further coupled to the second reset signal terminal RST2, and the reset circuit 140 is further configured to transmit the signal received by the second voltage terminal LVGL2 to the signal received by the second reset signal terminal RST2.
  • the reset circuit 140 may couple the second voltage terminal LVGL2 to the second node PU to transmit the signal received by the second voltage terminal LVGL2 To the second node PU, and the reset circuit 140 can couple the first voltage terminal LVGL1 to the first node Output to transmit the signal received by the first voltage terminal LVGL1 to the first node Output.
  • the voltage of the first node Output is configured as the first voltage.
  • the reset circuit 140 includes a twelfth switching device T12 and a fourteenth switching device T14, the control pole of the twelfth switching device T12 is coupled to the second reset signal terminal RST2, and the first pole of the twelfth switching device T12 is coupled to the second reset signal terminal RST2.
  • the second node PU is coupled, the second pole of the twelfth switching device T12 is coupled to the second voltage terminal LVGL2; the control pole of the fourteenth switching device T14 is coupled to the second reset signal terminal RST2, the fourteenth switching device
  • the first pole of T14 is coupled to the first node Output, and the second pole of the fourteenth switching device T14 is coupled to the first voltage terminal LVGL1.
  • the high-level signal turns on the twelfth switching device T12 and the fourteenth switching device T14, coupling the second voltage terminal LVGL2 to the second node PU Then, the first voltage terminal LVGL1 is coupled to the first node Output, so that the signal received by the second voltage terminal LVGL2 is transmitted to the second node PU, and the signal received by the first voltage terminal LVGL1 is transmitted to the first node Output.
  • a plurality of shift registers SR(1) to SR(n) are usually cascaded in sequence.
  • each shift register The registers SR all have signal interaction with their adjacent shift registers.
  • FIG. 5 shows a cascade relationship diagram of the shift registers SR(1) to SR(n) provided by some embodiments of the present invention.
  • the first stage shift register SR(1) is In the row sub-pixels, the control electrodes of the first switching device T1 and the second switching device T2 coupled to the first-stage shift register SR(1) provide a first light-emitting control signal and a second light-emitting control signal;
  • the third signal output terminal Out-C of the second stage shift register SR(1) is coupled to the signal input terminal STPV of the second stage shift register SR(2), that is, the first stage shift register SR(1)
  • the signal output by the three-signal output terminal Out-C is used as the input signal of the second stage shift register SR(2).
  • the second-stage shift register SR(2) is adjacent to the first-stage shift register SR(1).
  • the second-stage shift register SR(2) provides the second row of sub-pixels to the control electrodes of the first switching device T1 and the second switching device T2 coupled to the second-stage shift register SR(2).
  • the third signal output terminal Out-C of the second-stage shift register SR(2) is coupled to the signal input terminal STPV of the third-stage shift register SR(3), namely ,
  • the signal output by the third signal output terminal Out-C of the second-stage shift register SR(2) is used as the input signal of the third-stage shift register SR(3).
  • the third-stage shift register SR(3) is adjacent to the second-stage shift register SR(2).
  • the cascading mode of the remaining shift registers is the same as described above.
  • the third signal output terminal Out-C of the above-mentioned second-stage shift register SR(2) outputs a signal while also providing the output signal to the first reset signal terminal RST1 of the first-stage shift register SR(1) , As the signal of the first reset signal terminal RST1 of the first stage shift register SR(1), so that the reset circuit 140 in the first stage shift register SR(1) is configured to respond to the first reset signal terminal RST1
  • the received signal transmits the signal received by the second voltage terminal LVGL2 to the second node PU.
  • the third signal output terminal Out-C of the aforementioned third-stage shift register SR(3) outputs a signal while also providing the output signal to the first reset signal terminal RST1 of the second-stage shift register SR(2) as The signal of the first reset signal terminal RST1 of the second stage shift register SR(2), so that the reset circuit 140 in the second stage shift register SR(2) is configured to respond to the signal received by the first reset signal terminal RST1 Signal to transmit the signal received by the second voltage terminal LVGL2 to the second node PU.
  • multiple cascaded shift registers SR(1) to SR(n-1) can be reset sequentially.
  • the second reset signal terminal RST2 of the shift register SR(n) can be directly coupled to the second reset signal Line, used to reset the sub-pixels in the nth row, and at the same time, the second reset signal terminal RST2 of the shift register SR(n) is also sequentially coupled to the shift registers SR(1) ⁇ SR(n-1)
  • the second reset signal terminal RST2 is used to provide an overall reset signal for this frame of picture.
  • circuits in the shift registers SR(1) to SR(n) such as the voltage control circuit 110, the bias compensation circuit 120, etc., have the same structure and function as the corresponding circuits in the above-mentioned shift register SR , Will not be described here.
  • FIG. 1 is only schematic, taking single-side driving (that is, setting the light-emitting control driving circuit on one side of the peripheral area of the display panel, and driving sequentially from the single side row by row) as an example for description. of.
  • dual-side simultaneous driving may be adopted (that is, a light-emission control driving circuit is respectively provided on two sides along the extension direction of the signal line for transmitting the light-emission control signal in the peripheral area of the display panel, and the two light-emitting Control the drive circuit to drive sequentially from both sides row by row at the same time).
  • the display panel can be driven by double-sided cross driving (that is, a light-emission control drive circuit is provided on two sides along the extension direction of the signal line for transmitting the light-emission control signal in the peripheral area of the display panel, and the light-emission control drive circuit is provided through the two sides.
  • a light-emitting control drive circuit alternately drives from both sides, row by row).
  • the first clock signal terminal and the second clock signal terminal of any two adjacent cascaded shift registers are respectively coupled to different first clock signal lines and second clock signal lines.
  • the clock signal terminal GCLK of the odd-numbered stage shift register is coupled to the first clock signal line GCLK1
  • the clock signal terminal GCLK of the even-numbered stage shift register is coupled to the second clock signal line CLK2.
  • the embodiment of the present disclosure also provides a method for driving a shift register SR, the shift register includes: a first node, a first signal terminal (VDD-A), a second signal terminal (VDD-B), a first The signal output terminal (EM1), the second signal output terminal (EM2) and the first voltage terminal (LVGL2).
  • the above-mentioned driving method of the shift register SR includes:
  • control the voltage of the first node Output to be the first voltage or the second voltage
  • the first signal received by the first signal terminal VDD-A is transmitted to the first signal output terminal EM1, and the first signal received by the second signal terminal VDD-B is transmitted The second signal is transmitted to the second signal output terminal EM2;
  • the signal received by the first voltage terminal LVGL2 is transmitted to the first signal output terminal EM1 and the second signal output terminal EM2;
  • the first signal and the second signal are both rectangular wave signals, and the levels of the two are opposite.
  • the first signal and the second signal are both square wave signals, where the square wave signal means that the duty cycle of the signal is close to 50%.
  • the above-mentioned driving process may include the following four stages: an initial stage, a data writing stage, a denoising stage, and a reset stage.
  • FIG. 10 shows a timing diagram of a method for driving a driving circuit (a circuit in a shift register).
  • the driving circuit of the embodiment of the present disclosure takes the shift register in the first row as an example, and STPV represents the electrical power at the signal input terminal.
  • GCLK1 and GCLK2 respectively represent the level timing of the clock signal terminal of the odd and even rows of sub-pixels
  • VDD-A represents the level timing of the first signal terminal
  • VDD-B represents the level timing of the second signal terminal
  • EM1 represents the level timing of the second signal terminal.
  • EM2 represents the level sequence received by the second signal output terminal, that is, the level sequence output by the first signal output terminal and the second signal output terminal
  • PU represents the second node Level timing.
  • the first signal terminal VDD-A outputs the second level (corresponding to the high level VGH), and the bias compensation circuit 120 sets the first signal terminal VDD-A is coupled to the first signal output terminal EM1, so that the second level is output to the first signal output terminal EM1 of the bias compensation circuit 120; the second signal terminal VDD-B outputs the first level (corresponding to the low level VGL), the bias compensation circuit 120 couples the second signal terminal VDD-B to the second signal output terminal EM2, and the second level is output to the second signal output terminal EM2 of the bias compensation circuit 120.
  • the signal input terminal STPV of the input circuit 130 in the shift register SR receives the second level, the seventh switching device T7 and the eighth switching device T8 are turned on, and the input circuit 130 transmits the second level to the shift register SR.
  • the second node PU configures the voltage of the second node PU as the second voltage.
  • the tenth switching device T10 and the eleventh switching device T11 are turned on to charge the energy storage device C1. Since the clock signal terminal GCLK1 inputs the first level in the initial stage, the first plate of the energy storage device CI can be charged At the first voltage, the second plate of the energy storage device CI is coupled to the second node PU, so the second plate can be charged to the second voltage.
  • the input circuit 130 is also provided with a ninth switching device T9, the control pole of the ninth switching device T9 is turned on under the action of the second voltage of the second node PU, and the first pole of the ninth switching device T9 is coupled to the third node PD, The second pole of the ninth switching device T9 is coupled to the second voltage terminal LVGL2, and can pull down the voltage of the third node PD.
  • the sixteenth switching device T16 and the seventeenth switching device T17 are in the off state.
  • the twelfth switching device T12, the thirteenth switching device T13, the fourteenth switching device T14, the sixteenth switching device T16, and the seventeenth switching device T17 are all in the off state, and the fourth switching device T4 and The sixth switching device T6 has not yet been turned on.
  • the control terminal of the fifteenth switching device T15 can always receive the second level of the third signal terminal VDD-C, and the fifteenth switching device T15 can always be in the on state, making the signal control more effective. It is simple.
  • the other switching devices of the denoising sub-circuit 111 are turned on and turned on correspondingly in each stage, which facilitates the subsequent third node PD to denoise the second node PU.
  • the signal input terminal STPV of the input circuit 130 receives the first level (low level VGL), and the seventh switch device T7 and the eighth switch device
  • the switching device T8 is turned off, and the twelfth switching device T12, the thirteenth switching device T13, the fourteenth switching device T14, the sixteenth switching device T16, and the seventeenth switching device T17 are all kept in the off state.
  • the fifth level terminal GCLK1 outputs the second level during the data writing stage.
  • the energy storage device C1 continues to raise the voltage of the second node PU through a "bootstrap" effect, for example, the voltage of the second node PU is greater than The second voltage (for example, the voltage of the second node PU is 20V), the voltage of the second node PU can further turn on the tenth switching device T10 and the eleventh switching device T11, so that the third signal output terminal Out-C outputs the second At this time, the second level output by the third signal output terminal Out-C is used as the signal of the first reset terminal RST1 of the reset circuit 140 of the previous shift register SR and the input circuit 130 of the next shift register SR The start level of the signal input terminal STPV. Referring to the timing diagram of the circuit driving method shown in FIG.
  • the clock signal terminal GCLK of each row sequentially inputs alternate bi-level signals.
  • GCLK1 in the first row is high
  • GCLK2 in the second row is low.
  • the eleventh switching device T11 is turned on
  • the second level of the clock signal terminal GCLK is output to the first node Output
  • the fourth switching device T4 and the sixth switching device T6 are turned on
  • the bias compensation circuit 120 The first voltage terminal LVGL1 is coupled to the first signal output terminal EM1 and the second signal output terminal EM2, so that the first signal output terminal EM1 and the second signal output terminal EM2 output the first level, which is convenient for the first switching device T1 and
  • the pixel driving circuit where the second switching device T2 is located performs reset, compensation, and data signal Data writing stages, and the entire reset, compensation, and data signal Data writing stages are completed in the data writing stage of the present disclosure.
  • the data writing stage After the data writing stage is completed, it enters the de-drying stage, as shown in FIG. 8, combined with the second frame shown in FIG. 9, in the de-noising stage, the first reset signal terminal RST1 receives the next stage shift register to the The signal input by the shift register, which is the signal output terminal Out-C of the next stage shift register outputs the second level, so that the thirteenth switching device T13 is turned on to connect the first voltage terminal LVGL1 to the second node
  • the PU is coupled to pull down the voltage of the second node PU to the first voltage.
  • the third signal terminal VDD-C outputs the second level to turn on the fifteenth switching device T15, and the denoising sub-circuit 111 transmits the second level output from the third signal terminal VDD-C to the third node PD.
  • the sixth switching device T16 and the seventeenth switching device T17 are turned on, so that the second voltage terminal LVGL2 is coupled to the third signal output terminal Out-C, and the first voltage terminal LVGL1 is coupled to the first node Output, thereby coupling the third voltage terminal LVGL2 to the first node Output.
  • the level of the signal output terminal Out-C is pulled down, and the voltage of the first node Output is configured as the first voltage to perform denoising.
  • the seventh switching device T7, the eighth switching device T8, the twelfth switching device T12, and the fourteenth switching device T14 remain closed, and the tenth switching device T10, the eleventh switching device T11, and the ninth switching device T9 are kept off. Turning off, the fourth switching device T4 and the sixth switching device T6 are also turned off.
  • the second reset signal terminal RST2 outputs the second level, and the twelfth switching device T12 and the fourteenth switching device T14 are turned on, so that the first The second voltage terminal LVGL2 is further coupled to the second node PU, and the first voltage terminal LVGL1 is further coupled to the first node Output to reset the second node PU and the first node Output.
  • the second reset signal terminal RST2 can input a signal after one frame is completed to discharge the second node PU again to avoid the occurrence of multiple outputs, and the entire frame of driving is completed.
  • the seventh switch device T7, the eighth switch device T8, the tenth switch device T10, the eleventh switch device T11, the ninth switch device T9, the fourth switch device T4, and the sixth switch device T6 remain closed.
  • the embodiment of the present disclosure may take one frame as the alternate switching of the levels of the first signal terminal VDD-A and the second signal terminal VDD-B as an example.
  • the second switching device T2 operates to compensate for the first frame.
  • the first switching device T1 works to compensate the threshold voltage of the second switching device T2, and then the process of the first and second frames is repeated, that is, the process of the first frame is repeated in the third frame ,
  • the first switching device T1 and the second switching device T2 are compensated in time sharing, and the first switching device T1 and the second switching device T2 are switched by positive pressure and negative pressure to ensure that the threshold voltage does not produce a large deviation.
  • the alternate switching time of the levels of the first signal terminal VDD-A and the second signal terminal VDD-B is not limited to one frame, but may also be several seconds, such as 1 second, 2 seconds, and 3 seconds.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位寄存器（SR）及显示方法、显示装置（1）。移位寄存器（SR）包括：电压控制电路（110）和偏压补偿电路（120）。电压控制电路（110）与第一节点（Output）耦接，被配置为控制第一节点（Output）的电压为第一电压或第二电压。偏压补偿电路（120）与第一节点（Output）、第一电压端（LVGL1）、第一信号端（VDD-A）、第二信号端（VDD-B）、第一信号输出端（EM1）和第二信号输出端（EM2）耦接，被配置为响应于第一节点（Output）的电压为第一电压，将第一信号端（VDD-A）接收的第一信号传输至第一信号输出端（EM1），将第二信号端（VDD-B）接收的第二信号传输至第二信号输出端（EM2）；以及，响应于第一节点（Output）的电压为第二电压，将第一电压端（LVGL1）接收的信号传输至第一信号输出端（EM1）和第二信号输出端（EM2）。

Description

移位寄存器及驱动方法、显示装置
本申请要求于2020年3月19日提交的、申请号为202010197530.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及驱动方法、显示装置。
背景技术
近年来，基于OLED(Organic Light Emitting Diode，有机发光二极管)的显示装置因具有自发光、视角广、发光效率高、色域广、工作电压低、面板薄等优点，成为国内外热门的显示产品。
发明内容
一方面，提供一种移位寄存器。所述移位寄存器包括电压控制电路和偏压补偿电路。所述电压控制电路与第一节点耦接，被配置为控制所述第一节点的电压为第一电压或第二电压。所述偏压补偿电路与所述第一节点、第一电压端、第一信号端、第二信号端、第一信号输出端和第二信号输出端耦接，被配置为响应于所述第一节点的电压为所述第一电压，将所述第一信号端接收的第一信号传输至所述第一信号输出端，将所述第二信号端接收的第二信号传输至所述第二信号输出端；以及，响应于所述第一节点的电压为所述第二电压，将所述第一电压端接收的信号传输至所述第一信号输出端和所述第二信号输出端。
在一些实施例中，所述偏压补偿电路包括：第三开关器件、第四开关器件、第五开关器件和第六开关器件。所述第三开关器件的控制极和第一极均与所述第一信号端耦接，所述第三开关器件的第二极与所述第一信号输出端耦接。所述第四开关器件的控制极与所述第一节点耦接，所述第四开关器件的第一极与所述第一信号输出端耦接，所述第四开关器件的第二极与所述第一电压端耦接。所述第五开关器件的控制极和第一极均与所述第二信号端耦接，所述第五开关器件的第二极与所述第二信号输出端耦接。所述第六开关器件的控制极与所述第一节点耦接，所述第六开关器件的第一极与所述第二信号输出端耦接，所述第六开关器件的第二极与所述第一电压端耦接。
在一些实施例中，所述电压控制电路包括：输出子电路和去噪子电路。所述输出子电路与时钟信号端、第二节点和所述第一节点耦接，被配置为响 应于所述第二节点的电压，将所述时钟信号端的时钟信号传输至所述第一节点，使得所述第一节点的电压为第一电压或第二电压。所述去噪子电路与第一电压端、所述第一节点、第三节点耦接，被配置为响应于所述第三节点的电压，控制所述第一节点的电压为所述第一电压。
在一些实施例中，所述输出子电路包括第十一开关器件，所述第十一开关器件的控制极与所述第二节点耦接，所述第十一开关器件的第一极与所述时钟信号端耦接，所述第十一开关器件的第二极与所述第一节点耦接。
在一些实施例中，所述输出子电路还被配置为响应于所述第一节点的电压为所述第二电压，提升或降低所述第二节点的电压。
在一些实施例中，所述输出子电路还包括储能器件，所述储能器件的第一极板与所述第一节点耦接，所述储能器件的第二极板与所述第二节点耦接。
在一些实施例中，所述输出子电路还与第三信号输出端、第二电压端和所述第二节点，还被配置为响应于所述第二节点的电压，将所述时钟信号端接收到的时钟信号传输至所述第三信号输出端。
在一些实施例中，所述输出子电路还包括第十开关器件，所述第十开关器件的控制极与所述第二节点耦接，所述第十开关器件的第一极与所述时钟信号端耦接，所述第十开关器件的第二极与所述第三信号输出端耦接。
在一些实施例中，所述去噪子电路包括第十七开关器件，所述第十七开关器件的控制极与所述第三节点耦接，所述第十七开关器件的第一极与所述第一节点耦接，所述第十七开关器件的第二极与所述第一电压端耦接。
在一些实施例中，所述去噪子电路还与所述第三信号端耦接，还被配置为，将所述第三信号端接收的信号传输至所述第三节点。
在一些实施例中，所述去噪子电路还包括第十五开关器件，所述第十五开关器件的控制极和第一极均与所述第三信号端耦接，所述第十五开关器件的第二极与所述第三节点耦接。
在一些实施例中，所述去噪子电路还被配置为响应于所述第三节点的电压，将所述第二电压端接收的信号传输至所述第三信号输出端。
在一些实施例中，所述去噪子电路还包括第十六开关器件，所述第十六开关器件的控制极与所述第三节点耦接，所述第十六开关器件的第一极与所述第三信号输出端耦接，所述第十六开关器件的第二极与所述第二电压端耦 接。
在一些实施例中，所述移位寄存器还包括：输入电路，所述输入电路与信号输入端、所述第二节点、所述第三节点以及所述第二电压端耦接，被配置为响应于所述信号输入端接收的输入信号，控制所述第二节点的电压和所述第三节点的电压。
在一些实施例中，所述输入电路包括第七开关器件和第九开关器件。所述第七开关器件的控制极和第一极均与所述信号输入端耦接，所述第七开关器件的第二极与所述第二电压端耦接。所述第九开关器件的控制极与所述第二节点耦接，所述第九开关器件的第一极与所述第三节点耦接，所述第九开关器件的第二极与所述第二电压端耦接。
在一些实施例中，所述输入电路还包括第八开关器件，所述第八开关器件的控制极与所述信号输入端耦接，所述第八开关器件的第一极与所述第三节点耦接，所述第八开关器件的第二极与所述第二电压端耦接。
在一些实施例中，所述移位寄存器还包括复位电路，所述复位电路与第一复位信号端、所述第二节点以及所述第二电压端耦接，被配置为响应于所述第一复位信号端接收的信号，将所述第二电压端接收的信号传输至所述第二节点。
在一些实施例中，所述复位电路包括第十三开关器件，所述第十三开关器件的控制极与所述第一复位信号端耦接，所述第十三开关器件的第一极与所述第二电压端耦接，所述第十三开关器件的第二极与所述第二节点耦接。
在一些实施例中，所述复位电路还与第二复位信号端耦接，所述复位电路还被配置为响应于所述第二复位信号端接收的信号，将所述第二电压端接收的信号传输至所述第二节点；以及响应于所述第二复位信号端接收的信号，将所述第一电压端接收的信号传输至所述第一节点，使得所述第一节点的电压为所述第一电压。
在一些实施例中，所述复位电路包括第十二开关器件和第十四开关器件。所述第十二开关器件的控制极与所述第二复位信号端耦接，所述第十二开关器件的第一极与所述第二节点耦接，所述第十二开关器件的第二极与所述第二电压端耦接。第十四开关器件，所述第十四开关器件的控制极与所述第二复位信号端耦接，所述第十四开关器件的第一极与所述第一节点耦接，所述第十四开关器件的第二极与所述第一电压端耦接。
另一方面，提供一种显示装置。所述显示装置包括：上述任一实施例所述的移位寄存器和像素驱动电路。所述像素驱动电路包括：第一开关器件和第二开关器件，所述第一开关器件的控制极与所述移位寄存器的第一信号输出端耦接，所述第二开关器件的控制极与所述移位寄存器的第二信号输出端耦接，所述第一开关器件的第一极与所述第二开关器件的第一极耦接，所述第一开关器件的第二极与所述第二开关器件的第二极耦接。
又一方面，提供一种移位寄存器的驱动方法。所述移位寄存器包括：第一节点、第一信号端、第二信号端、第一信号输出端、第二信号输出端和第一电压端。所述移位寄存器的驱动方法包括：
控制所述第一节点的电压为第一电压或第二电压；
响应于所述第一节点的电压为所述第一电压，将所述第一信号端接收的第一信号传输至所述第一信号输出端，将所述第二信号端接收的第二信号传输至所述第二信号输出端；
响应于所述第一节点的电压为所述第二电压，将所述第一电压端接收的信号传输至所述第一信号输出端和所述第二信号输出端。
其中，所述第一信号与所述第二信号均为矩形波信号，且二者的电平相反。
在一些实施例中，所述第一信号与所述第二信号均为方波信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示装置的显示面板的子像素的结构图；
图3为根据一些实施例的显示装置的移位寄存器的一种结构图；
图4A为根据一些实施例的显示装置的移位寄存器的另一种结构图；
图4B为根据一些实施例的显示装置的移位寄存器的又一种结构图；
图5为根据一些实施例的显示装置的显示面板的结构图；
图6为根据一些实施例的显示装置的移位寄存器在初始阶段的信号流向图；
图7为根据一些实施例的显示装置的移位寄存器在数据写入阶段的信号流向图；
图8为根据一些实施例的显示装置的移位寄存器在去噪阶段的信号流向图；
图9为根据一些实施例的显示装置的移位寄存器在复位阶段的信号流向图；
图10为根据一些实施例的显示装置的移位寄存器的驱动方法的时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通 信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供一种显示装置。示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，显示装置可以是多种电子装置中的一种，所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、 相机视图显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。本公开的实施例对上述显示装置的具体形式不做特殊限制。
本公开的一些实施例提供的显示装置1可以包括显示面板10。如图1所示，显示面板10具有显示区(Active Area，AA)和至少位于AA区一侧的周边区S。
显示面板10的AA区中设置有多个子像素P。多个子像素P在AA区中有序排列，其排列方式可以根据实际情况设计。例如，如图1所示，多个子像素P呈阵列形式排列，其中，沿X方向排列成一排的子像素P称为同一行子像素，沿Y方向排列成一排的子像素P称为同一列子像素。
显示面板10的周边区S设置有发光控制驱动电路100。发光控制驱动电路100包括多个移位寄存器SR(1)～SR(n)。每个移位寄存器SR(i)与一行子像素耦接，用于向该行子像素输出发光控制信号EM1(i)和EM2(i)。
示例性地，如图1所示，显示面板10还包括多条发光信号线(例如，2n条发光信号线)，例如，多条发光信号线沿图1中的X方向延伸，被配置为传输发光控制信号，例如，显示面板10中的多个子像素分为n行子像素，其中，第i行子像素通过发光信号线与第i级移位寄存器SR(i)耦接，n为正整数，1≤i≤n，i为整数，使得移位寄存器SR(i)可以通过发光信号线向第i行子像素传输发光控制信号EM1(i)和EM2(i)。
参见图2，至少一个子像素P(例如，每个子像素P)包括像素驱动电路200和发光器件L。其中，像素驱动电路200与发光器件L耦接。像素驱动电路200被配置为驱动发光器件L发光。多个子像素P的排列方式可以是指，多个子像素P中的像素驱动电路的排列方式，即多个像素驱动电路可以呈阵列形式排列。
发光器件L可以采用有机发光二极管(Organic Light-Emitting Diode，简称OLED)、量子点发光二极管(Quantum Dot Light-Emitting Diodes，简称QLED)等。发光器件L包括阴极和阳极，以及位于阴极和阳极之间的发光功能层。其中，发光功能层例如可以包括发光层、位于发光层和阳极之间的空穴传输层(Hole Transporting Layer，HTL)、位于发光层和阴极之间的电子传输层(Election Transporting Layer，ETL)。当然，根据需要在一些实施例中，还可 以在空穴传输层HTL和阳极之间设置空穴注入层(Hole Injection Layer，HIL)，可以在电子传输层ETL和阴极之间设置电子注入层(Election Injection Layer，EIL)。
示例性地，阳极例如可由具有高功函数的透明导电材料形成，其电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等；阴极例如可由高导电性和低功函数的材料形成，其电极材料可以包括镁铝合金(MgAl)和锂铝合金(LiAl)等合金或者镁(Mg)、铝(Al)、锂(Li)和银(Ag)等金属单质。发光层的材料可以根据其发射光颜色的不同进行选择。例如，发光层的材料包括荧光发光材料或磷光发光材料。例如，在本公开至少一个实施例中，发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物和三芳胺聚合物等。
本公开的实施例对像素驱动电路的具体结构不作限定，可以根据实际情况进行设计。示例性地，像素驱动电路由开关器件、驱动器件和电容(Capacitance，简称C)等电子器件组成，其中，开关器件和驱动器件可以是薄膜晶体管(Thin Film Transistor，简称TFT)，例如，开关器件可以是开关晶体管，驱动器件可以是驱动晶体管。例如，像素驱动电路可以包括三个薄膜晶体管(两个开关晶体管和一个驱动晶体管)和一个电容，构成3T1C结构；当然，像素驱动电路还可以包括三个以上的薄膜晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容，构成7T1C结构、8T1C结构、9T1C结构等。
像素驱动电路中的薄膜晶体管的控制极(也可称为栅极)可以用来接收不同的信号，示例性地，参见图2，像素驱动电路200中驱动晶体管D-TFT的控制极可以用来接收数据信号V DATA，或者，接收经驱动晶体管D-TFT的阈值电压补偿后的数据信号V DATA+Vth，其中，Vth为驱动晶体管D-TFT的阈值电压，V DATA为电压信号，根据所接收的数据信号，驱动晶体管D-TFT可以控制流经发光器件L的电信号强度(例如，电流大小)，从而控制发光器件L的发光亮度。
又示例性地，像素驱动电路中的开关器件可以均为开关晶体管。开关晶体管可以根据其控制极接收到的信号被打开或者关断。例如，像素驱动电路 的开关晶体管的控制极可以用来接收发光控制信号或栅极扫描信号，根据其所接收的发光控制信号或栅极扫描信号，开关晶体管可以被打开或者关断。示例性地，开关晶体管可以采用氧化物薄膜晶体管(Oxide thin-film transistor)，氧化物薄膜晶体管由于其本身的特性，对正负压力比较敏感，长时间处于同种压力会使晶体管的阈值电压发生偏移。例如，现有技术的像素驱动电路中包括一个用来接收发光控制信号的开关晶体管，由于该开关晶体管长期处于正压力，导致阈值电压发生偏移，会使与该像素驱动电路相耦接的发光器件的发光亮度下降。
为了避免这个问题，本公开的实施例提供一种像素驱动电路200，参见图2，像素驱动电路200包括：第一开关器件T1和第二开关器件T2，示例性地，第一开关器件T1和第二开关器件T2被配置为接收发光控制信号。第一开关器件T1的控制极与第一信号输出端EM1耦接，第二开关器件的控制极与第二信号输出端EM2耦接，第一开关器件T1的第一极与第二开关器件T2的第一极耦接，第一开关器件T1的第二极与第二开关器件T2的第二极耦接。
例如，参见图2，第一信号输出端EM1和第二信号输出端EM2可以位于一个移位寄存器中，并且，第一信号输出端EM1可以向第一开关器件T1输出第一发光控制信号，第二信号输出端EM2可以向第二开关器件T2输出第二发光控制信号，其中，第一发光控制信号和第二发光控制信号可以是高低交替的电平信号。以像素驱动电路200中的晶体管均为高开低断的N型晶体管为例，例如，当第一发光控制信号为高电平时，第二发光控制信号为低电平，此时，第一开关器件T1打开，第二开关器件T2关断，发光器件L可以发光，或者，当第一发光控制信号为低电平时，第二发光控制信号为高电平，此时，第一开关器件T1关断，第二开关器件T2打开，发光器件L也可以发光，再或者，当第一发光控制信号为低电平且第二发光控制信号也为低电平时，第一开关器件T1与第二开关器件T2均关断，发光器件L不发光。
当第一发光控制信号为高电平时，第二发光控制信号为低电平，此时，第一开关器件T1被打开，发光器件L可以正常发光，第二开关器件T2被补偿。例如，第一发光控制信号的输出电压为10V，则第一开关器件T1的控制极输入的电压为10V，而第一开关器件T1的第二极电压为其控制极电压与第一开关器件T1的压降之差，例如，第一开关器件T1的压降为1V，那么，第一开关器件T1的第二极电压为9V，此时，第一开关器件T1的控制极与第二极的电压差为1V，使得第一开关器件T1处于正向偏置；由于第二发光控制 信号为低电平信号，例如，其输入电压为-15V，且第二开关器件T2的第二极与第一开关器件T1的第二极耦接，因此第二开关器件T2的第二极的电压等于第一开关器件T1的第二极的电压，即为9V，因此，第二开关器件T2的控制极与第二极电压之差就为(-19)V，使第二开关器件T2处于负向偏置。
通过将第一发光控制信号控制为高、低交替的电平信号，可以使第一开关器件T1分别处于正向偏置和负向偏置，且当电平信号连续切换时，第一开关器件T1还可以在正向偏置与负向偏置之间来回切换，使得其受到的正、负压力可以抵消，从而避免或减小阈值电压偏移的现象。
类似地，像素驱动电路200中的第二开关器件T2也可以通过对第二发光控制信号的输入控制以及第二开关器件T2的偏置补偿来达到避免或减小阈值电压偏移的目的，原因类似，不再赘述。
本公开的实施例提供一种移位寄存器SR，用来向像素驱动电路200输出第一发光控制信号和第二发光控制信号。如图3所示，移位寄存器SR包括：电压控制电路110和偏压补偿电路120。
其中，电压控制电路110与第一节点Output耦接，偏压补偿电路120与第一节点Output、第一电压端LVGL1、第一信号端VDD-A、第二信号端VDD-B、第一信号输出端EM1和第二信号输出端EM2耦接。
第一电压端LVGL1为直流低电压端，示例性地，第一电压端LVGL1的电压为(-15)V，第一电压端LVGL1输出的信号可以是低电平信号。第一信号端VDD-A和第二信号端VDD-B为信号接收端，分别可以接收第一信号和第二信号。第一信号输出端EM1和第二信号输出端EM2是移位寄存器SR的信号输出端，被配置为向其他电路传输移位寄存器SR的输出信号，示例性地，当移位寄存器与像素驱动电路耦接时，移位寄存器SR可以向像素驱动电路传输发光控制信号，例如，参见图2和图3，移位寄存器SR的第一信号输出端EM1、第二信号输出端EM2分别与像素驱动电路200的第一开关器件T1、第二开关器件T2耦接，从而分别向第一开关器件T1、第二开关器件T2传输第一发光控制信号、第二发光控制信号，以控制第一开关器件T1、第二开关器件T2打开或关断。
电压控制电路110被配置为控制第一节点Output的电压为第一电压或第二电压。第一电压与第二电压为高低不同的两个电压，示例性地，第一电压为低电压，第二电压为高电压。例如，第一电压为(-15)V，第二电压为10V。
偏压补偿电路120被配置为响应于第一节点Output的电压为第一电压，将第一信号端VDD-A接收的第一信号传输至第一信号输出端EM1，将第二信号端VDD-B接收的第二信号传输至第二信号输出端EM2；以及，响应于第一节点Output的电压为第二电压，将第一电压端LVGL1接收的信号传输至第一信号输出端EM1和第二信号输出端EM2。
当第一节点Output输出第一电压时，第一信号和第二信号可以分别被传输至第一信号输出端EM1和第二信号输出端EM2。示例性地，第一信号和第二信号可以均为高、低交替的电平信号，且同一时刻第一信号和第二信号输出的电平可以不一样。例如，第一信号端VDD-A输出的第一信号与第二信号端VDD-B输出的第二信号互为反转信号。如，第一信号和第二信号的相位差为180°。在第一信号为低电平信号的情况下，第二信号为高电平信号；在第一信号为高电平信号的情况下，第二信号为低电平信号。例如，第一信号和第二信号不会同时为高电平信号。
示例性地，当第一信号和第二信号互为反转信号时，可以使像素驱动电路200中的发光器件L正常发光，且对第一开关器件T1、第二开关器件T2进行补偿。
例如，参见图2，在像素驱动电路200中，当第一信号为高电平时，第一开关器件T1被打开，使发光器件L发光，此时，由于第二信号为低电平信号，因此不会对发光器件L的发光控制信号产生干扰，且第二开关器件T2在低电平信号的控制下还能处于负向偏置；类似地，当第二信号为高电平时，第一信号为低电平，其作用类似，不再赘述。
示例性地，在发光器件L的一个发光阶段内，可以控制第一信号端VDD-A和第二信号端VDD-B输出不同的电平(高电平或低电平)，在下一个发光阶段，将二者输出的电平调换，即通过特殊的时序控制，使第一信号端VDD-A和第二信号端VDD-B输出高低交替且相反的电平信号。
这样，一方面，可以保证像素驱动电路200中一直有高电平的发光控制信号输入，使发光器件L的每个发光阶段均可以正常发光，另一方面，还可以对像素驱动电路200中的第一开关器件T1和第二开关器件T2进行分时补偿，从而避免或者减小阈值电压偏移产生的影响。例如，在一帧画面中，第一信号端VDD-A输出高电平，第二信号端VDD-B输出低电平，其中，高电平用来将像素驱动电路200中的第一开关器件T1打开，使发光器件L正常发 光，低电平对第二开关器件T2进行补偿；在下一帧画面中，第一信号端VDD-A输出低电平，使第一开关器件T1进行补偿，第二信号端VDD-B输出高电平，使第二开关器件T2控制发光器件L正常发光，如此交替。示例性地，在第一信号端VDD-A处接收的第一信号和在第二信号端VDD-B处接收的第二信号的占空比近似相同，这样可以使第一开关器件T1和第二开关器件T2的正、负偏置时间近似，从而使第一开关器件T1和第二开关器件T2受到的正、负压力完全抵消。
当第一节点Output输出第二电压时，第一电压端LVGL1接收的信号可以被传输至第一信号输出端EM1和第二信号输出端EM2，例如，在像素驱动电路200进入复位、补偿以及数据写入阶段时，将第一节点Output的电压控制为第二电压，使第一信号输出端EM1和第二信号输出端EM2接收第一电压端LVGL1输出的信号，例如，第一电压端LVGL1接收的信号为低电平信号，该低电平信号传输至第一信号输出端EM1和第二信号输出端EM2，将像素驱动电路200中的第一开关器件T1和第二开关器件T2均被关断，进而使发光器件L不发光。
在本发明的一些实施例中，当电压控制电路110向第一节点Output输出第一电压时，示例性地，可以通过偏压补偿电路120将第一信号端VDD-A与第一信号输出端EM1耦接，将第二信号端VDD-B与第二信号输出端EM1耦接，从而将第一信号端VDD-A接收的第一信号传输至第一信号输出端EM1，将第二信号端VDD-B接收的第二信号传输至第二信号输出端EM2；当电压控制电路110向第一节点Output输出第二电压时，示例性地，可以通过偏压补偿电路120将第一电压端LVGL1与第一信号输出端EM1和第二信号输出端EM2耦接，以将第一电压端LVGL1接收的信号传输至第一信号输出端EM1和第二信号输出端EM2。
例如，参见图4A，偏压补偿电路120包括：第三开关器件T3、第四开关器件T4、第五开关器件T5以及第六开关器件T6。其中，第三开关器件T3的控制极和第一极均与第一信号端VDD-A耦接，第三开关器件T3的第二极与第一信号输出端EM1耦接；第四开关器件T4的控制极与第一节点Output耦接，第四开关器件T4的第一极与第一信号输出端EM1耦接，第四开关器件T4的第二极与第一电压端LVGL1耦接；第五开关器件T5的控制极和第一极均与第二信号端VDD-B耦接，第五开关器件T5的第二极与第二信号输出端EM2耦接；第六开关器件T6的控制极与第一节点Output耦接，第六开关 器件T6的第一极与第二信号输出端EM2耦接，第六开关器件T6的第二极与第一电压端LVGL1耦接。
当电压控制电路110向第一节点Output输出第一电压时，第四开关器件T4和第六开关器件T6在第一电压的作用下被关断，第一电压端LVGL1接收的信号无法传输至第一信号输出端EM1和第二信号输出端EM2。而第三开关器件T3、第五开关器件T5在第一信号、第二信号的作用下被打开，将第一信号端VDD-A与第一信号输出端EM1耦接，将第二信号端VDD-B与第二信号输出端EM2耦接，使得第一信号端VDD-A和第二信号端VDD-B输出的信号分别经过第三开关器件T3和第四开关器件T4被传输至第一信号输出端EM1和第二信号输出端EM2，使第一信号输出端EM1和第二信号输出端EM2可以分别接收到第一信号和第二信号。
当电压控制电路110向第一节点Output输出第二电压时，第三开关器件T3、第四开关器件T4、第五开关器件T5以及第六开关器件T6均被打开，并且，由于第四开关器件T4和第六开关器件T6的尺寸大于第三开关器件T3和第五开关器件T5的尺寸，例如，第四开关器件T4的宽长比是第三开关器件T3的3倍，第六开关器件T6的宽长比是第五开关器件T5的3倍，使第一信号输出端EM1和第二信号输出端EM2输出的信号为第一电压端LVGL1接收的信号。
又如，参见图4B，第三开关器件T3的控制极和第五开关器件T5的控制极还可以始终接入一个高电平端(如VGH)，使第三开关器件T3和第五开关器件T5始终保持打开状态。当电压控制电路110向第一节点Output输出第一电压时，第一信号端VDD-A和第二信号端VDD-B的信号可以直接到达第一信号输出端EM1和第二信号输出端EM2；当电压控制电路110向第一节点Output输出第二电压时，通过对第四开关器件T4和第六开关器件T6的尺寸设置，第一电压端LVGL1接收的信号也可以传输至第一信号输出端EM1和第二信号输出端EM2，不受影响。
在一些实施例中，移位寄存器SR的电压控制电路110包括输出子电路112和去噪子电路111。
输出子电路112与时钟信号端GCLK、第二节点PU和第一节点Output耦接，被配置为响应于第二节点PU的电压，将时钟信号端GCLK的时钟信号传输至第一节点Output，使得第一节点Output的电压为第一电压或第二电 压。
示例性地，当第二节点PU的电压为一定值时，输出子电路112可以将时钟信号端GCLK与第一节点Output耦接，以将钟信号端GCLK的时钟信号传输至第一节点Output。当时钟信号传输给第一节点Output的信号为高电平时，第一节点Output的电压被配置为第二电压，当时钟信号传输给第一节点Output的信号为低电平时，第一节点Output的电压被配置为第一电压。
例如，参见图4A，输出子电路112包括第十一开关器件T11，其中，第十一开关器件T11的控制极与所述第二节点PU耦接，第十一开关器件T11的第一极与时钟信号端GCLK耦接，第十一开关器件T11的第二极与第一节点Output耦接。当第二节点PU的电压大于一定值(例如1V)时，例如，第二节点PU的电压为10V，第二节点PU的电压可以将第十一开关器件T11打开，将时钟信号端GCLK与第一节点Output耦接，使得钟信号端GCLK的时钟信号经过第十一开关器件T11传输至第一节点Output。
在一些实施例中，输出子电路112还被配置为响应于第一节点Output的电压为第二电压，提升或降低第二节点PU的电压。
示例性地，输出子电路112还包括储能器件C1，储能器件C1的第一极板与第一节点Output耦接，储能器件C1的第二极板与第二节点PU耦接。储能器件C1可以通过“自举”作用，改变与其向耦接的节点的电压。例如，参见图4A，在一个阶段中，储能器件C1的第一极板上的电压为第一电压，第二极板上的电压为第二电压，在下一个阶段中，与第一节点Output耦接的第一极板上的电压提升置第二电压，由于储能器件C1的两个极板之间的相对电压不会改变，那么第二极板上的电压就可以被提升至比第二电压更高的电压值上，使得与第二极板耦接的第二节点PU的电压也随之被提升。
在一些实施例中，输出子电路112还与第三信号输出端Out-C、第二电压端LVGL2和第二节点PU，还被配置为响应于第二节点PU的电压，将时钟信号端GCLK接收到的时钟信号传输至第三信号输出端Out-C。
示例性地，当第二节点PU的电压为第二电压时，输出子电路112可以将时钟信号端GCLK与第三信号输出端Out-C耦接，用以将钟信号端GCLK接收到的时钟信号传输至第三信号输出端Out-C。
例如，参见图4A，输出子电路112还包括：第十开关器件T10，第十开关器件T10的控制极与第二节点PU耦接，第十开关器件T10的第一极与时 钟信号端GCLK耦接，第十开关器件T10的第二极与第三信号输出端Out-C耦接。当第二节点PU的电压为第二电压时，第十开关器件T10被打开，将时钟信号端GCLK与第三信号输出端Out-C耦接，使得时钟信号端GCLK的时钟信号经过第十开关器件T10传输至第三信号输出端Out-C。
去噪子电路111与第一电压端LVGL1、第一节点Output、第三节点PD耦接，被配置为响应于第三节点PD的电压，控制第一节点Output的电压为第一电压。
示例性地，当第三节点PD的电压为第二电压时，去噪子电路111可以将第一电压端LVGL1与第一节点Output耦接，使得第一电压端LVGL1接收的信号传输至第一节点Output，将第一节点Output的电压配置为第一电压。
例如，参照图4A，去噪子电路111包括第十七开关器件T17，第十七开关器件T17的控制极与第三节点PD耦接，第十七开关器件T17的第一极与第一节点Output耦接，第十七开关器件T17的第二极与第一电压端LVGL1耦接。当第三节点PD的电压为第二电压时，第十七开关器件T17被打开，将第一电压端LVGL1与第一节点Output耦接，使得第一电压端LVGL1接收的信号经过第十七开关器件T17传输至第一节点Output，将第一节点Output的电压配置为第一电压。
在一些实施例中，去噪子电路111还与第三信号端VDD-C耦接，还被配置为，将第三信号端VDD-C接收的信号传输至第三节点PD。
示例性地，去噪子电路111可以将第三信号端VDD-C与第三节点PD耦接，以将第三信号端VDD-C接收的信号传输至第三节点PD。第三信号端VDD-C接收的信号也可以为电平信号，例如，第三信号端VDD-C接收的信号为持续的高电平信号。
例如，参见图4A，去噪子电路还包括第十五开关器件T15，第十五开关器件T15的控制极和第一极均与第三信号端VDD-C耦接，第十五开关器件T15的第二极与第三节点PD耦接。当第三信号端VDD-C接收到高电平信号时，该高电平信号可以将第十五开关器件T15打开，将第三信号端VDD-C与第三节点PD耦接，使得第三信号端VDD-C接收的高电平信号经过第十五开关器件T15传输至第三节点PD。
在一些实施例中，去噪子电路111还被配置为响应于第三节点PD的电压，将第二电压端LVGL2接收的信号传输至第三信号输出端Out-C。
第二电压端LVGL2为直流低电压端，示例性地，第二电压端LVGL2的电压与第一电压端LVGL1的电压相等，例如，第二电压端LVGL2与第一电压端LVGL1耦接，第二电压端LVGL2输出的信号可以是低电平信号。
示例性地，当第三节点PD的电压为第二电压时，去噪子电路111可以将第二电压端LVGL2与第三信号输出端Out-C耦接，以将第二电压端LVGL2接收的信号传输至第三信号输出端Out-C。
例如，去噪子电路111还包括第十六开关器件T16，第十六开关器件T16的控制极与第三节点PD耦接，第十六开关器件的第一极与第三信号输出端Out-C)耦接，第十六开关器件T16的第二极与第二电压端LVGL2耦接。当第三节点PD的电压为第二电压时，第十六开关器件T16在第二电压的控制下被打开，第二电压端LVGL2与第三信号输出端Out-C耦接，从而使第二电压端LVGL2接收的信号传输至第三信号输出端Out-C。
在一些实施例中，移位寄存器还包括输入电路130，输入电路130与信号输入端STPV、第二节点PU、第三节点PD以及第二电压端LVGL2耦接，被配置为响应于信号输入端STPV接收的输入信号，控制第二节点PU的电压和第三节点PD的电压。
输入电路130可以控制第二节点PU的电压和第三节点PD的电压，使得二者的电平信号互为反转信号。示例性地，当第二节点PU的电压为第二电压时，第二节点PU的信号为高电平信号，此时，第三节点PD的电压为第一电压，第三节点PD的信号为低电平信号。又示例性地，当第二节点PU的电压为第一电压时，第二节点PU的信号为低电平信号，此时，第三节点PD的电压为第二电压，第三节点PD的信号为高电平信号。
信号输入端STPV可以作为一个移位寄存器SR的起始信号输入端。示例性地，当信号输入端STPV输入第一阶段高电平信号时，第二节点PU的电压可以被置高，例如，第二节点PU的电压为第二电压，第三节点PD的电压可以被置低，例如，第三节点PD的电压为第一电压。
例如，参见图4A，输入电路130包括第七开关器件T7和第九开关器件T9，第七开关器件T7的控制极和第一极均与信号输入端STPV耦接，第七开关器件T7的第二极与第二电压端LVGL2耦接；第九开关器件T9的控制极与第二节点PU耦接，第九开关器件T9的第一极与第三节点PD耦接，第九开关器件的第二极与第二电压端LVGL2耦接。当信号输入端STPV输入第一阶 段高电平信号时，例如，该第一阶段高电平信号的输出电压为第二电压，第七开关器件T7在该高电平的作用下被打开，信号输入端STPV与第二节点PU耦接，使得信号输入端STPV输入的高电平信号输入至第二节点PU，从而将第二节点PU的电压置高，例如，将第二节点PU的电压配置为第二电压。当第二节点PU的电压为第二电压时，第九开关器件T9被打开，第二电压端LVGL2与第三节点PD耦接。由于第九开关器件T9的尺寸大于第十五开关器件T15，使得第二电压端LVGL2接收的信号可以传输至第三节点PD，将第三节点PD的电压置低，例如，第三节点PD被配置为第一电压。
在一些实施例中，输入电路130还包括第八开关器件T8，第八开关器件T8的控制极与信号输入端STPV耦接，第八开关器件T8的第一极与第三节点PD耦接，第八开关器件T8的第二极与第二电压端LVGL2耦接。当信号输入端STPV输入第一阶段高电平信号时，第八开关器件T8在该高电平的作用下被打开，将第二电压端LVGL2与耦接第三节点PD耦接，使得第二电压端LVGL2接收的信号传输至第三节点PD，将第三节点PD配置为第一电压。由于第八开关器件T8的栅极与信号输入端STPV直接耦接，相比于第九开关器件T9，第九开关器件T9的打开与关闭受第二节点PU的直接控制，使得信号输入端STPV的输入信号首先到达第二节点PU，再通过第二节点PU到达第九开关器件T9的栅极，第八开关器件T8受输入信号的控制更加直接，当第八开关器件T8和第九开关器件T9共同作用时，在提高效率的同时，可以使移位寄存器SR对第二节点PU、第三节点PD的电压控制的信赖性更高。
在一些实施例中，移位寄存器SR还包括复位电路140，复位电路140与第一复位信号端RST1、第二节点PU以及第二电压端LVGL2耦接，被配置为响应于第一复位信号端RST1接收的信号，将第二电压端LVGL2接收的信号传输至第二节点PU。
示例性地，当第一复位信号端RST1输入的信号为高电平信号时，复位电路140可以将第二电压端LVGL2与第二节点PU耦接，使得第二电压端LVGL2接收的信号传输至第二节点PU，例如，该信号将第二节点PU的电压配置为第一电压。
例如，复位电路140包括第十三开关器件T13，第十三开关器件T13的控制极与第一复位信号端RST1耦接，第十三开关器件T13的第一极与第二电压端LVGL2耦接，第十三开关器件的第二极与第二节点PU耦接。当当第一复位信号端RST1输入的信号为高电平信号时，该高电平信号使第十三开关 器件T13打开，将第二电压端LVGL2与第二节点PU耦接，使得第二电压端LVGL2接收的信号经过第十三开关器件T13传输至第二节点PU。
在一些实施例中，复位电路140还与第二复位信号端RST2耦接，复位电路140还被配置为响应于第二复位信号端RST2接收的信号，将第二电压端LVGL2接收的信号传输至第二节点PU；以及响应于第二复位信号端RST2接收的信号，将第一电压端LVGL1接收的信号传输至第一节点Output，使得第一节点Output的电压为第一电压。
示例性地，当第二复位信号端RST2输出的信号为高电平信号时，复位电路140可以将第二电压端LVGL2与第二节点PU耦接，以将第二电压端LVGL2接收的信号传输至第二节点PU，并且，复位电路140可以将第一电压端LVGL1与第一节点Output耦接，以将第一电压端LVGL1接收的信号传输至第一节点Output，在该信号的作用下，使得第一节点Output的电压被配置为第一电压。
例如，复位电路140包括第十二开关器件T12和第十四开关器件T14，第十二开关器件T12的控制极与第二复位信号端RST2耦接，第十二开关器件T12的第一极与第二节点PU耦接，第十二开关器件T12的第二极与第二电压端LVGL2耦接；第十四开关器件T14的控制极与第二复位信号端RST2耦接，第十四开关器件的第一极与第一节点Output耦接，第十四开关器件T14的第二极与第一电压端LVGL1耦接。当第二复位信号端RST2输出的信号为高电平信号时，该高电平信号使第十二开关器件T12和第十四开关器件T14打开，将第二电压端LVGL2与第二节点PU耦接，第一电压端LVGL1与第一节点Output耦接，使得第二电压端LVGL2接收的信号传输至第二节点PU，第一电压端LVGL1接收的信号传输至第一节点Output。
在发光控制驱动电路100中，多个移位寄存器SR(1)～SR(n)通常是依次级联的，示例性地，在多个移位寄存器依次级联的情况下，每个移位寄存器SR均与其相邻的移位寄存器存在信号交互。
示例性地，图5示出了本发明的一些实施例提供的移位寄存器SR(1)～SR(n)的级联关系图，例如，第一级移位寄存器SR(1)向第一行子像素中，与该第一级移位寄存器SR(1)的耦接的第一开关器件T1和第二开关器件T2的控制极提供第一发光控制信号和第二发光控制信号；第一级移位寄存器SR(1)的第三信号输出端Out-C与第二级移位寄存器SR(2)的信号输入端STPV耦接，即， 第一级移位寄存器SR(1)的第三信号输出端Out-C输出的信号作为第二级移位寄存器SR(2)的输入信号。第二级移位寄存器SR(2)与第一级移位寄存器SR(1)相邻。第二级移位寄存器SR(2)向第二行子像素中，与该第二级移位寄存器SR(2)的耦接的第一开关器件T1和第二开关器件T2的控制极提供第一发光控制信号和第二发光控制信号；第二级移位寄存器SR(2)的第三信号输出端Out-C与第三级移位寄存器SR(3)的信号输入端STPV耦接，即，第二级移位寄存器SR(2)的第三信号输出端Out-C输出的信号作为第三级移位寄存器SR(3)的输入信号。第三级移位寄存器SR(3)与第二级移位寄存器SR(2)相邻。此外，其余移位寄存器的级联方式同上所述。
此外，上述第二级移位寄存器SR(2)的第三信号输出端Out-C在输出信号的同时还向第一级移位寄存器SR(1)的第一复位信号端RST1提供该输出信号，作为第一级移位寄存器SR(1)的第一复位信号端RST1的信号，以使得第一级移位寄存器SR(1)中的复位电路140被配置为响应于第一复位信号端RST1接收的信号，将第二电压端LVGL2接收的信号传输至第二节点PU。上述第三级移位寄存器SR(3)的第三信号输出端Out-C在输出信号的同时还向第二级移位寄存器SR(2)的第一复位信号端RST1提供该输出信号，作为第二级移位寄存器SR(2)的第一复位信号端RST1的信号，以使得第二级移位寄存器SR(2)中的复位电路140被配置为响应于第一复位信号端RST1接收的信号，将第二电压端LVGL2接收的信号传输至第二节点PU。这样一来，多个级联的移位寄存器SR(1)～SR(n-1)可以被依次复位。
由于移位寄存器SR(n)不再有下一级的移位寄存器对其输入第一复位信号RST1，移位寄存器SR(n)的第二复位信号端RST2可以直接耦接至第二复位信号线上，用以将第n行的子像素复位，同时，移位寄存器SR(n)的第二复位信号端RST2还依次耦接至移位寄存器SR(1)～SR(n-1)的第二复位信号端RST2，用以为本帧画面的提供整体复位信号。
需要说明的是，移位寄存器SR(1)～SR(n)中的电路，例如电压控制电路110、偏压补偿电路120等均与上述的移位寄存器SR中对应的电路的结构和功能相同，在此不再描述。
对于发光控制驱动电路100而言，图1仅是示意的，以采用单侧驱动(即在显示面板的周边区的单侧设置发光控制驱动电路，从单侧逐行依次驱动)为例进行说明的。在另一些实施例中，可以采用双侧同时驱动(即在显示面板的周边区中沿传输发光控制信号的信号线的延伸方向上的两个侧边分别设 置发光控制驱动电路，通过两个发光控制驱动电路同时从两侧逐行依次驱动)。在另一些实施例中，显示面板可以采用双侧交叉驱动(即在显示面板的周边区中沿传输发光控制信号的信号线的延伸方向上的两个侧边分别设置发光控制驱动电路，通过两个发光控制驱动电路交替从两侧，逐行依次驱动)。本公开的实施例是以单侧驱动为例进行说明的。
示例性地，任意相邻的两个级联的移位寄存器中的第一时钟信号端和第二时钟信号端分别耦接不同的第一时钟信号线和第二时钟信号线。例如，如图5所示，奇数级移位寄存器的时钟信号端GCLK与第一时钟信号线GCLK1耦接，偶数级移位寄存器的时钟信号端GCLK与第二时钟信号线CLK2耦接。
本公开的实施例还提供一种移位寄存器SR的驱动方法，所述移位寄存器包括：第一节点、第一信号端(VDD-A)、第二信号端(VDD-B)、第一信号输出端(EM1)、第二信号输出端(EM2)和第一电压端(LVGL2)。
上述移位寄存器SR的驱动方法包括：
首先，控制所述第一节点Output的电压为第一电压或第二电压；
其次，响应于所述第一节点Output的电压为第一电压，将第一信号端VDD-A接收的第一信号传输至第一信号输出端EM1，将第二信号端VDD-B接收的第二信号传输至第二信号输出端EM2；
然后，响应于第一节点Output的电压为所述第二电压，将第一电压端LVGL2接收的信号传输至第一信号输出端EM1和第二信号输出端EM2；
其中，第一信号与第二信号均为矩形波信号，且二者的电平相反。
在一些实施例中，第一信号与所述第二信号均为方波信号，其中，方波信号是指，该信号的占空比接近50％。
接下来，详细描述应用本公开的一些实施例提供的移位寄存器SR的驱动方法对移位寄存器SR进行驱动的过程。上述驱动过程可以包括以下四个阶段：初始阶段，数据写入阶段、去噪阶段和复位阶段。
示例性地，以所有开关器件均为N型器件为例，以第一开关器件T1工作，第二开关器件T2进行阈值电压补偿进行说明，图6至图9分别示出了初始阶段、数据写入阶段、去噪阶段和复位阶段的信号流的示意图，黑色线条的箭头所示的方向为信号流的方向，图中“X”表示开关器件为关闭状态。图10示出了对驱动电路(一个移位寄存器中的电路)进行驱动的方法的时序图，本 公开的实施例的驱动电路以第一行的移位寄存器为例，STPV表示信号输入端的电平时序，GCLK1和GCLK2分别表示奇数行和偶数行子像素的时钟信号端的电平时序，VDD-A表示第一信号端的电平时序，VDD-B表示第二信号端的电平时序，EM1表示第一信号输出端所接收的电平时序，EM2表示第二信号输出端所接收的电平时序，也就是第一信号输出端和第二信号输出端输出的电平时序，PU表示第二节点的电平时序。
参见图4A所示，结合图10所示的第二帧，在初始阶段，第一信号端VDD-A输出第二电平(对应高电平VGH)，偏压补偿电路120将第一信号端VDD-A与第一信号输出端EM1耦接，使得第二电平输出到偏压补偿电路120的第一信号输出端EM1；第二信号端VDD-B输出第一电平(对应低电平VGL)，偏压补偿电路120将第二信号端VDD-B与第二信号输出端EM2耦接，第二电平输出到偏压补偿电路120的第二信号输出端EM2。
移位寄存器SR中的输入电路130的信号输入端STPV接收第二电平，第七开关器件T7和第八开关器件T8被打开，输入电路130将第二电平传输至移位寄存器SR中的第二节点PU并使将第二节点PU的电压配置为第二电压。此时，第十开关器件T10和第十一开关器件T11被打开，将储能器件C1充电，由于初始阶段时钟信号端GCLK1输入第一电平，储能器件CI的第一极板可以被充电至第一电压，储能器件CI的第二极板与第二节点PU耦接，因此第二极板可以被充电至第二电压。同时，由于第八开关器件T8也导通，为了防止第十六开关器件T16和第十七开关器件T17导通，影响数据写入阶段，需要将第三节点PD的电压降低，因此，输入电路130还设置有第九开关器件T9，第九开关器件T9的控制极在第二节点PU的第二电压的作用下导通，第九开关器件T9的第一极与第三节点PD耦接，第九开关器件T9的第二极与第二电压端LVGL2耦接，可以将第三节点PD的电压下拉。第十六开关器件T16、第十七开关器件T17处于关闭状态。在此阶段，第十二开关器件T12、第十三开关器件T13、第十四开关器件T14、第十六开关器件T16的、第十七开关器件T17均处于关闭状态，第四开关器件T4和第六开关器件T6也还未导通。同时，整个偏压补偿阶段，第十五开关器件T15的控制端可以一直接收第三信号端VDD-C的第二电平，第十五开关器件T15可以一直处于导通状态，使得信号控制更简单，去噪子电路111的其他开关器件的在各个阶段对应打开和导通，便于后续第三节点PD对第二节点PU去噪。
参见图7所示，结合图10所示的第二帧，在数据写入阶段，输入电路130 的信号输入端STPV接收第一电平(低电平VGL)，第七开关器件T7和第八开关器件T8关闭，第十二开关器件T12、第十三开关器件T13、第十四开关器件T14、第十六开关器件T16、第十七开关器件T17均保持关闭状态。第五电平端GCLK1在数据写入阶段输出第二电平，此时，储能器件C1通过“自举”作用，使第二节点PU的电压继续抬高，例如，第二节点PU的电压大于第二电压(如第二节点PU的电压为20V)，第二节点PU的电压进一步可以将第十开关器件T10和第十一开关器件T11打开，使第三信号输出端Out-C输出第二电平，此时第三信号输出端Out-C输出的第二电平作为上一个移位寄存器SR的复位电路140的第一复位端RST1的信号和下一个移位寄存器SR的输入电路130的信号输入端STPV的起始电平。参见图10所示的电路驱动方法的时序图，每行的时钟信号端GCLK依次输入交替的双电平信号，当第一行的GCLK1为高电平时，第二行的GCLK2为低电平。在数据写入阶段，第十一开关器件T11导通，将时钟信号端GCLK的第二电平输出第一节点Output，第四开关器件T4和第六开关器件T6导通，偏压补偿电路120使第一电压端LVGL1与第一信号输出端EM1、第二信号输出端EM2耦接，使得第一信号输出端EM1、第二信号输出端EM2输出第一电平，便于第一开关器件T1和第二开关器件T2所在的像素驱动电路进行复位、补偿、数据信号Data写入阶段，整个复位、补偿、数据信号的Data写入阶段均在本公开的数据写入阶段完成。
数据写入阶段完成之后，进入去燥阶段，参见图8所示，结合图9所示的第二帧，在去噪阶段，第一复位信号端RST1接收到下一级移位寄存器向本级移位寄存器输入的信号，该信号为下一级移位寄存器的信号输出端Out-C输出第二电平，使得第十三开关器件T13被打开，以将第一电压端LVGL1与第二节点PU耦接，将第二节点PU的电压拉低至第一电压。此外，第三信号端VDD-C输出第二电平打开第十五开关器件T15，去噪子电路111将第三信号端VDD-C输出的第二电平传输到第三节点PD，第十六开关器件T16和第十七开关器件T17导通，以使第二电压端LVGL2与第三信号输出端Out-C耦接，第一电压端LVGL1与第一节点Output耦接，从而将第三信号输出端Out-C的电平拉低，将第一节点Output的电压配置为第一电压，进行去噪。在此阶段，第七开关器件T7、第八开关器件T8、第十二开关器件T12、第十四开关器件T14保持关闭，第十开关器件T10、第十一开关器件T11、第九开关器件T9关闭，第四开关器件T4和第六开关器件T6也关闭。
参见图9所示，结合图10所示的第二帧，在复位阶段，第二复位信号端RST2输出第二电平，第十二开关器件T12和第十四开关器件T14导通，使得第二电压端LVGL2与第二节点PU进一步耦接，第一电压端LVGL1与第一节点Output进一步耦接，对第二节点PU和第一节点Output进行复位。第二复位信号端RST2可以在一帧完成后输入信号，对第二节点PU再次放电，避免出现多输出的发生，整帧驱动完成。在此阶段，第七开关器件T7、第八开关器件T8、第十开关器件T10、第十一开关器件T11、第九开关器件T9、第四开关器件T4、第六开关器件T6保持关闭。
参见图10，本公开的实施例可以以1帧为第一信号端VDD-A和第二信号端VDD-B的电平交替切换为例，第一帧时第二开关器件T2工作，补偿第一开关器件T1的阈值电压，第二帧时第一开关器件T1工作，补偿第二开关器件T2的阈值电压，后续重复第一、二两帧过程，也就是第三帧重复第一帧的过程，分时对第一开关器件T1和第二开关器件T2进行补偿，第一开关器件T1和第二开关器件T2受到正压力负压力切换来保证阈值电压不会产生较大偏移。在实际应用中，第一信号端VDD-A和第二信号端VDD-B的电平交替切换时间不局限在一帧，也可能是几秒，如1秒、2秒和3秒等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种移位寄存器，包括：
    电压控制电路，与第一节点耦接，被配置为控制所述第一节点的电压为第一电压或第二电压；
    偏压补偿电路，与所述第一节点、第一电压端、第一信号端、第二信号端、第一信号输出端和第二信号输出端耦接，被配置为响应于所述第一节点的电压为所述第一电压，将所述第一信号端接收的第一信号传输至所述第一信号输出端，将所述第二信号端接收的第二信号传输至所述第二信号输出端；以及，响应于所述第一节点的电压为所述第二电压，将所述第一电压端接收的信号传输至所述第一信号输出端和所述第二信号输出端。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述偏压补偿电路包括：
    第三开关器件，所述第三开关器件的控制极和第一极均与所述第一信号端耦接，所述第三开关器件的第二极与所述第一信号输出端耦接；
    第四开关器件，所述第四开关器件的控制极与所述第一节点耦接，所述第四开关器件的第一极与所述第一信号输出端耦接，所述第四开关器件的第二极与所述第一电压端耦接；
    第五开关器件，所述第五开关器件的控制极和第一极均与所述第二信号端耦接，所述第五开关器件的第二极与所述第二信号输出端耦接；
    第六开关器件，所述第六开关器件的控制极与所述第一节点耦接，所述第六开关器件的第一极与所述第二信号输出端耦接，所述第六开关器件的第二极与所述第一电压端耦接。
  3. 根据权利要求1所述的移位寄存器，其中，
    所述电压控制电路包括：
    输出子电路，与时钟信号端、第二节点和所述第一节点耦接，被配置为响应于所述第二节点的电压，将所述时钟信号端的时钟信号传输至所述第一节点，使得所述第一节点的电压为第一电压或第二电压；
    去噪子电路，与第一电压端、所述第一节点、第三节点耦接，被配置为响应于所述第三节点的电压，控制所述第一节点的电压为所述第一电压。
  4. 根据权利要求3所述的移位寄存器，其中，
    所述输出子电路包括：
    第十一开关器件，所述第十一开关器件的控制极与所述第二节点耦接，所述第十一开关器件的第一极与所述时钟信号端耦接，所述第十一开关器件的第二极与所述第一节点耦接。
  5. 根据权利要求3或4所述的移位寄存器，其中，
    所述输出子电路还被配置为响应于所述第一节点的电压为所述第二电压，提升或降低所述第二节点的电压。
  6. 根据权利要求5所述的移位寄存器，其中，
    所述输出子电路还包括：
    储能器件，所述储能器件的第一极板与所述第一节点耦接，所述储能器件的第二极板与所述第二节点耦接。
  7. 根据权利要求3至6中的任一项所述的移位寄存器，其中，
    所述输出子电路还与第三信号输出端、第二电压端和所述第二节点，还被配置为响应于所述第二节点的电压，将所述时钟信号端接收到的时钟信号传输至所述第三信号输出端。
  8. 根据权利要求7所述的移位寄存器，其中，
    所述输出子电路还包括：
    第十开关器件，所述第十开关器件的控制极与所述第二节点耦接，所述第十开关器件的第一极与所述时钟信号端耦接，所述第十开关器件的第二极与所述第三信号输出端耦接。
  9. 根据权利要求3至8中的任一项所述的移位寄存器，其中，
    所述去噪子电路包括：
    第十七开关器件，所述第十七开关器件的控制极与所述第三节点耦接，所述第十七开关器件的第一极与所述第一节点耦接，所述第十七开关器件的第二极与所述第一电压端耦接。
  10. 根据权利要求3至9中的任一项所述的移位寄存器，其中，
    所述去噪子电路还与第三信号端耦接，还被配置为，将所述第三信号端接收的信号传输至所述第三节点。
  11. 根据权利要求10所述的移位寄存器，其中，
    所述去噪子电路还包括：
    第十五开关器件，所述第十五开关器件的控制极和第一极均与所述第三信号端耦接，所述第十五开关器件的第二极与所述第三节点耦接。
  12. 根据权利要求3至11中的任一项所述的移位寄存器，其中，
    所述去噪子电路还被配置为响应于所述第三节点的电压，将所述第二电压端接收的信号传输至第三信号输出端。
  13. 根据权利要求12所述的移位寄存器，其中，
    所述去噪子电路还包括：
    第十六开关器件，所述第十六开关器件的控制极与所述第三节点耦接，所述第十六开关器件的第一极与所述第三信号输出端耦接，所述第十六开关器件的第二极与所述第二电压端耦接。
  14. 根据权利要求1至13中的任一项所述的移位寄存器，其中，
    所述移位寄存器还包括：
    输入电路，与信号输入端、第二节点、第三节点以及所述第二电压端耦接，被配置为响应于所述信号输入端接收的输入信号，控制所述第二节点的电压和所述第三节点的电压。
  15. 根据权利要求14所述的移位寄存器，其中，
    所述输入电路包括：
    第七开关器件，所述第七开关器件的控制极和第一极均与所述信号输入端耦接，所述第七开关器件的第二极与所述第二电压端耦接；
    第九开关器件，所述第九开关器件的控制极与所述第二节点耦接，所述第九开关器件的第一极与所述第三节点耦接，所述第九开关器件的第二极与所述第二电压端耦接。
  16. 根据权利要求15所述的移位寄存器，其中，
    所述输入电路还包括：
    第八开关器件，所述第八开关器件的控制极与所述信号输入端耦接，所述第八开关器件的第一极与所述第三节点耦接，所述第八开关器件的第二极 与所述第二电压端耦接。
  17. 根据权利要求1至16中的任一项所述的移位寄存器，其中，
    所述移位寄存器还包括：
    复位电路，所述复位电路与第一复位信号端、第二节点以及所述第二电压端耦接，被配置为响应于所述第一复位信号端接收的信号，将所述第二电压端接收的信号传输至所述第二节点。
  18. 根据权利要求17所述的移位寄存器，其中，
    所述复位电路包括：
    第十三开关器件，所述第十三开关器件的控制极与所述第一复位信号端耦接，所述第十三开关器件的第一极与所述第二电压端耦接，所述第十三开关器件的第二极与所述第二节点耦接。
  19. 根据权利要求17或18所述移位寄存器，其中，
    所述复位电路还与第二复位信号端耦接，所述复位电路还被配置为响应于所述第二复位信号端接收的信号，将所述第二电压端接收的信号传输至所述第二节点；以及响应于所述第二复位信号端接收的信号，将所述第一电压端接收的信号传输至所述第一节点，使得所述第一节点的电压为所述第一电压。
  20. 根据权利要求19所述的移位寄存器，其中，
    所述复位电路包括：
    第十二开关器件，所述第十二开关器件的控制极与所述第二复位信号端耦接，所述第十二开关器件的第一极与所述第二节点耦接，所述第十二开关器件的第二极与所述第二电压端耦接；
    第十四开关器件，所述第十四开关器件的控制极与所述第二复位信号端耦接，所述第十四开关器件的第一极与所述第一节点耦接，所述第十四开关器件的第二极与所述第一电压端耦接。
  21. 一种显示装置，所述显示装置包括：
    权利要求1至20中的任一项所述的移位寄存器；
    像素驱动电路，所述像素驱动电路包括：第一开关器件和第二开关器件，所述第一开关器件的控制极与所述移位寄存器的第一信号输出端耦接，所述 第二开关器件的控制极与所述移位寄存器的第二信号输出端耦接，所述第一开关器件的第一极与所述第二开关器件的第一极耦接，所述第一开关器件的第二极与所述第二开关器件的第二极耦接。
  22. 一种移位寄存器的驱动方法，所述移位寄存器包括：第一节点、第一信号端、第二信号端、第一信号输出端、第二信号输出端和第一电压端；所述移位寄存器的驱动方法包括：
    控制所述第一节点的电压为第一电压或第二电压；
    响应于所述第一节点的电压为所述第一电压，将所述第一信号端接收的第一信号传输至所述第一信号输出端，将所述第二信号端接收的第二信号传输至所述第二信号输出端；
    响应于所述第一节点的电压为所述第二电压，将所述第一电压端接收的信号传输至所述第一信号输出端和所述第二信号输出端；
    其中，所述第一信号与所述第二信号均为矩形波信号，且二者的电平相反。
  23. 根据权利要求22所述的移位寄存器的驱动方法，其中，
    所述第一信号与所述第二信号均为方波信号。
PCT/CN2021/081629 2020-03-19 2021-03-18 移位寄存器及驱动方法、显示装置 WO2021185328A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/760,733 US11847966B2 (en) 2020-03-19 2021-03-18 Shift register and driving method therefor, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010197530.5 2020-03-19
CN202010197530.5A CN111243516B (zh) 2020-03-19 2020-03-19 驱动电路、显示面板、显示装置及电路驱动方法

Publications (1)

Publication Number Publication Date
WO2021185328A1 true WO2021185328A1 (zh) 2021-09-23

Family

ID=70880531

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/081629 WO2021185328A1 (zh) 2020-03-19 2021-03-18 移位寄存器及驱动方法、显示装置

Country Status (3)

Country Link
US (1) US11847966B2 (zh)
CN (1) CN111243516B (zh)
WO (1) WO2021185328A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111243516B (zh) 2020-03-19 2021-11-05 京东方科技集团股份有限公司 驱动电路、显示面板、显示装置及电路驱动方法
CN113689821A (zh) * 2021-09-03 2021-11-23 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板
CN114023281B (zh) * 2021-11-30 2023-03-31 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110057864A1 (en) * 2009-09-08 2011-03-10 Chung Kyung-Hoon Emission control driver and organic light emitting display using the same
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN105719599A (zh) * 2016-04-18 2016-06-29 京东方科技集团股份有限公司 移位寄存器电路单元、栅极驱动电路和显示装置
CN106782337A (zh) * 2017-02-14 2017-05-31 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及有机电致发光显示面板
CN109003574A (zh) * 2018-08-15 2018-12-14 京东方科技集团股份有限公司 像素单元、驱动方法、像素模组及其驱动方法和显示装置
CN111243516A (zh) * 2020-03-19 2020-06-05 京东方科技集团股份有限公司 驱动电路、显示面板、显示装置及电路驱动方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3838180B2 (ja) * 2002-09-12 2006-10-25 富士通株式会社 クロック生成回路及びクロック生成方法
KR100686334B1 (ko) * 2003-11-14 2007-02-22 삼성에스디아이 주식회사 표시장치 및 그의 구동방법
KR100582402B1 (ko) 2004-09-10 2006-05-22 매그나칩 반도체 유한회사 패널에서 플리커 프리 디스플레이를 지원하는 메모리읽기/쓰기 타이밍 제어방법 및 그 방법을 이용한 ｔｄｃ패널 구동장치
KR100782455B1 (ko) * 2005-04-29 2007-12-05 삼성에스디아이 주식회사 발광제어 구동장치 및 이를 구비하는 유기전계발광표시장치
KR101943293B1 (ko) * 2009-10-16 2019-01-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 표시 장치 및 전자 장치
KR101895530B1 (ko) * 2012-02-10 2018-09-06 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN102708799B (zh) 2012-05-31 2014-11-19 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
US9754535B2 (en) 2013-04-02 2017-09-05 Sharp Kabushiki Kaisha Display device and method for driving display device
KR102072201B1 (ko) * 2013-06-28 2020-02-03 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 구동 방법
US10033361B2 (en) * 2015-12-28 2018-07-24 Semiconductor Energy Laboratory Co., Ltd. Level-shift circuit, driver IC, and electronic device
US9634678B1 (en) * 2016-02-25 2017-04-25 Silicon Laboratories Inc. Feedback control system with rising and falling edge detection and correction
CN106356015B (zh) 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置
CN107170408B (zh) * 2017-06-27 2019-05-24 上海天马微电子有限公司 像素电路、驱动方法、有机电致发光显示面板及显示装置
KR102349850B1 (ko) * 2017-12-28 2022-01-11 엘지디스플레이 주식회사 발광 제어 구동부
CN110391267B (zh) * 2018-04-19 2022-01-18 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN108877716B (zh) * 2018-07-20 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN108877636B (zh) * 2018-08-29 2021-05-14 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110226195A (zh) * 2018-11-22 2019-09-10 京东方科技集团股份有限公司 用于单列中的多行像素的显示驱动电路、显示装置和显示方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110057864A1 (en) * 2009-09-08 2011-03-10 Chung Kyung-Hoon Emission control driver and organic light emitting display using the same
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN105719599A (zh) * 2016-04-18 2016-06-29 京东方科技集团股份有限公司 移位寄存器电路单元、栅极驱动电路和显示装置
CN106782337A (zh) * 2017-02-14 2017-05-31 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及有机电致发光显示面板
CN109003574A (zh) * 2018-08-15 2018-12-14 京东方科技集团股份有限公司 像素单元、驱动方法、像素模组及其驱动方法和显示装置
CN111243516A (zh) * 2020-03-19 2020-06-05 京东方科技集团股份有限公司 驱动电路、显示面板、显示装置及电路驱动方法

Also Published As

Publication number Publication date
CN111243516B (zh) 2021-11-05
US11847966B2 (en) 2023-12-19
US20220335889A1 (en) 2022-10-20
CN111243516A (zh) 2020-06-05

Similar Documents

Publication Publication Date Title
WO2021185328A1 (zh) 移位寄存器及驱动方法、显示装置
US11462592B2 (en) Array substrate with pixel circuits sharing voltage control circuit, driving method, organic light emitting display panel and display device
WO2020186933A1 (zh) 像素电路、其驱动方法、电致发光显示面板及显示装置
CN107146575B (zh) 有机发光二极管显示器
WO2021223579A1 (zh) 像素驱动电路及驱动方法、移位寄存器电路、显示装置
CN113192463B (zh) 发光控制移位寄存器、栅极驱动电路、显示装置及方法
WO2021136496A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US20210193036A1 (en) Pixel unit, array substrate and display terminal
US20230136129A1 (en) Pixel circuit and driving method thereof, display panel, and display device
WO2023236502A1 (zh) 像素驱动电路、像素驱动方法及显示面板
US11862216B2 (en) Shift register and driving method therefor, gate driver circuit, and display apparatus
WO2022222408A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US11244602B2 (en) Shift register and method for driving the same, light-emitting control circuit and display apparatus
US20210110759A1 (en) Driving circuit, driving method thereof, display panel and display device
WO2021139708A1 (zh) 移位寄存器及其控制方法、栅极驱动电路和显示面板
WO2024041314A1 (zh) 像素电路、驱动方法及显示装置
WO2023231742A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2022061898A1 (zh) 移位寄存器及驱动方法、发光控制驱动电路、显示装置
CN218849052U (zh) 像素电路及显示装置
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
WO2021063322A1 (zh) 显示装置、栅极驱动电路、移位寄存电路及其驱动方法
US20220101782A1 (en) Shift register and driving method thereof, gate driving circuit and display apparatus
WO2021018206A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US11842684B2 (en) Display panel and method for driving the same, and display apparatus
WO2022246611A1 (zh) 移位寄存器及其驱动方法、扫描驱动电路、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21772105

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21772105

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 16/05/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21772105

Country of ref document: EP

Kind code of ref document: A1