WO2022246611A1 - 移位寄存器及其驱动方法、扫描驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、扫描驱动电路、显示装置 Download PDF

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Publication number
WO2022246611A1
WO2022246611A1 PCT/CN2021/095584 CN2021095584W WO2022246611A1 WO 2022246611 A1 WO2022246611 A1 WO 2022246611A1 CN 2021095584 W CN2021095584 W CN 2021095584W WO 2022246611 A1 WO2022246611 A1 WO 2022246611A1
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WIPO (PCT)
Prior art keywords
node
voltage
control
electrically connected
clock signal
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Application number
PCT/CN2021/095584
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English (en)
French (fr)
Inventor
青海刚
肖云升
谷泉泳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21942200.3A priority Critical patent/EP4207150A4/en
Priority to US17/789,268 priority patent/US11948513B2/en
Priority to PCT/CN2021/095584 priority patent/WO2022246611A1/zh
Priority to KR1020237013597A priority patent/KR20240011119A/ko
Priority to JP2023546152A priority patent/JP2024520247A/ja
Priority to CN202180001244.XA priority patent/CN115812231A/zh
Publication of WO2022246611A1 publication Critical patent/WO2022246611A1/zh
Priority to US18/589,959 priority patent/US20240203360A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register and its driving method, a scan driving circuit, and a display device.
  • the scan driving circuit is an important part of the display device.
  • the scan driving circuit may include multi-stage cascaded shift registers, and the multi-stage shift registers may be respectively electrically connected to multiple wires in the display device.
  • the scan driving circuit can input scan signals row by row to a plurality of wires (such as gate wires or enable signal wires) in the display device, so that the display device can display images.
  • the scanning driving circuit is provided in the display device, which can effectively reduce the cost and improve the yield rate.
  • a shift register in one aspect, includes: an input circuit, an output circuit, a first control circuit and a holding circuit.
  • the input circuit is electrically connected to the first clock signal terminal, the input signal terminal and the first node.
  • the input circuit is configured to transmit an input signal received at the input signal terminal to the first node under the control of a first clock signal transmitted by the first clock signal terminal.
  • the output circuit is electrically connected to the first node, the second clock signal terminal and the output signal terminal.
  • the output circuit is configured to transmit a second clock signal received at the second clock signal terminal to the output signal terminal under the control of the voltage of the first node.
  • the first control circuit is electrically connected to the first node, the first voltage signal terminal, the second clock signal terminal and the second node.
  • the first control circuit is configured to control the voltage of the second node under the control of the voltage of the first node and the second clock signal.
  • the holding circuit is electrically connected to the second node, the first voltage signal terminal and the output signal terminal.
  • the holding circuit is configured to transmit the first voltage signal to the output signal terminal under the control of the voltage of the second node.
  • the first control circuit includes a first sub-control circuit and a second sub-control circuit.
  • the first sub-control circuit is electrically connected to the first node, the first voltage signal terminal, the second clock signal terminal and the third node; the first sub-control circuit is configured to, in the Under the control of the voltage of the first node and the second clock signal, the voltage of the third node is controlled.
  • the second sub-control circuit is electrically connected to the first node, the third node, the first voltage signal terminal, the second clock signal terminal and the second node; the second sub-control circuit The circuit is configured to control the voltage of the second node under the control of the voltage of the first node and the voltage of the third node.
  • the first sub-control circuit includes: a third transistor and a second capacitor.
  • the control electrode of the third transistor is electrically connected to the first node
  • the first electrode of the third transistor is electrically connected to the first voltage signal terminal
  • the second electrode of the third transistor is electrically connected to the first node.
  • a first end of the second capacitor is electrically connected to the second clock signal end, and a second end of the second capacitor is electrically connected to the third node.
  • the second sub-control circuit includes: a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.
  • the two nodes are electrically connected.
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first clock signal terminal. The two nodes are electrically connected.
  • the shift register further includes: a potential stabilization circuit.
  • the potential stabilization circuit is electrically connected to the first node, the second voltage signal terminal and the fourth node; the potential stabilization circuit is configured to control the second voltage signal transmitted at the second voltage signal terminal Next, the input signal from the first node is transmitted to the fourth node, and the voltage of the fourth node is stabilized.
  • the output circuit is electrically connected to the fourth node, and is electrically connected to the first node through the potential stabilization circuit; the output circuit is configured to, under the control of the voltage of the fourth node , transmitting the second clock signal received at the second clock signal terminal to the output signal terminal.
  • the potential stabilization circuit includes: a seventh transistor.
  • the control electrode of the seventh transistor is electrically connected to the second voltage signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the first node. Four-node electrical connection.
  • the shift register further includes: a second control circuit.
  • the second control circuit is electrically connected to the second node, the first voltage signal terminal and the first node; the second control circuit is configured to, under the control of the voltage of the second node , transmitting the first voltage signal to the first node.
  • the second control circuit includes: an eighth transistor.
  • the control electrode of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the eighth transistor is electrically connected to the first voltage signal terminal.
  • the shift register further includes: a third control circuit.
  • the third control circuit is electrically connected to the second clock signal terminal, the fifth node, and the first node; the second control circuit is electrically connected to the fifth node, and through the third control circuit electrically connected to the first node.
  • the second control circuit is configured to transmit the first voltage signal to the fifth node under the control of the voltage of the second node.
  • the third control circuit is configured to transmit the first voltage signal from the fifth node to the first node under the control of the second clock signal.
  • the third control circuit includes: a ninth transistor.
  • the control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the fifth node, and the second electrode of the ninth transistor is electrically connected to the first One node electrical connection.
  • the second control circuit includes an eighth transistor, the second pole of the eighth transistor is electrically connected to the fifth node, and is electrically connected to the first node through the ninth transistor.
  • the input circuit includes: a first transistor.
  • the control pole of the first transistor is electrically connected to the first clock signal terminal, the first pole of the first transistor is electrically connected to the input signal terminal, and the second pole of the first transistor is electrically connected to the first clock signal terminal.
  • the output circuit includes: a second transistor and a first capacitor.
  • the control electrode of the second transistor is electrically connected to the first node
  • the first electrode of the second transistor is electrically connected to the second clock signal terminal
  • the second electrode of the second transistor is electrically connected to the output
  • the signal terminal is electrically connected.
  • a first end of the first capacitor is electrically connected to the first node
  • a second end of the first capacitor is electrically connected to the output signal end.
  • the potential stabilizing circuit includes a seventh transistor
  • the control electrode of the second transistor is electrically connected to the fourth node, and is electrically connected to the first node through the seventh transistor.
  • the holding circuit includes: a sixth transistor and a third capacitor.
  • the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the output The signal terminal is electrically connected.
  • a first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the first voltage signal end.
  • the conduction types of the plurality of transistors included in the shift register are the same.
  • the first clock signal and the second clock signal are mutually inverse signals.
  • a method for driving a shift register as described in any one of the above includes: comprising: a first stage and a second stage.
  • the input circuit in response to a first clock signal received at a first clock signal terminal, the input circuit is turned on, and an input signal received at an input signal terminal is transmitted to a first node; at said first node Under the control of the voltage of the output circuit, the output circuit is turned on, and the second clock signal received at the second clock signal terminal is transmitted to the output signal terminal; under the control of the voltage of the first node and the second clock signal,
  • the first control circuit transmits the first voltage signal transmitted by the first voltage signal terminal to the second node, and controls the voltage of the second node; under the control of the voltage of the second node, keeps the circuit off;
  • the input circuit in response to the first clock signal received at the first clock signal terminal, the input circuit is turned on, and the input signal received at the input signal terminal is transmitted to the first node ; under the control of the voltage of the first clock signal terminal.
  • the first phase includes an input phase and a scanning phase.
  • the input circuit in response to the first clock signal, the input circuit is turned on to transmit the input signal to the first node; under the control of the voltage of the first node, the output circuit conducts On, the second clock signal will be transmitted to the output signal terminal; under the control of the voltage of the first node and the second clock signal, the first control circuit will transmit the first voltage signal transmit to the second node, and control the voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned off.
  • the input circuit in response to the first clock signal, the input circuit is turned off; the voltage of the first node remains substantially unchanged, and the output circuit is controlled by the voltage of the first node keep the on state, and transmit the second clock signal to the output signal terminal; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first The voltage signal is transmitted to the second node to control the voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned off.
  • the second phase includes: a first maintenance phase and a second maintenance phase.
  • the input circuit in response to the first clock signal, the input circuit is turned on to transmit the input signal to the first node; under the control of the voltage of the first node, the The output circuit is turned off; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the first The voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned off.
  • the input circuit in response to the first clock signal, the input circuit is turned off; the voltage of the first node remains substantially unchanged, and the output circuit is at the voltage of the first node under the control to maintain the off state; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the the voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned on, and transmits the first voltage signal to the output signal terminal.
  • a scan driving circuit includes: a plurality of cascaded shift registers as described in any one of the above embodiments. Except for the last i shift register, the output signal end of the Nth shift register is electrically connected to the input signal end of the N+ith shift register; wherein, N and i are both positive integers, and i ⁇ N.
  • the scan driving circuit further includes: at least one first clock signal line and at least one second clock signal line.
  • a first clock signal line is electrically connected to the first clock signal end of the 2N-1 shift register and the second clock signal end of the 2N shift register;
  • a second clock signal The wire is electrically connected to the second clock signal end of the 2N-1th shift register and the first clock signal end of the 2Nth shift register.
  • a display device includes: the scanning driving circuit as described in any one of the above-mentioned embodiments.
  • FIG. 1 is a structural diagram of a shift register according to an implementation
  • FIG. 2 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Fig. 3 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure.
  • Fig. 5 is a structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 11 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 12 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 13 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 14 is a timing control diagram corresponding to the shift register shown in FIG. 13 according to some embodiments of the present disclosure.
  • FIG. 15 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used. For example, the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the control pole of each transistor used in the shift register is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor.
  • the source and the drain of the transistor may be symmetrical in structure, there may be no structural difference between the source and the drain, that is to say, the first and second electrodes of the transistor in the embodiments of the present disclosure
  • the two poles may be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first pole of the transistor is the source
  • the second pole is the drain
  • the second pole is the source.
  • nodes do not represent actual components, but represent the confluence points of relevant electrical connections in the circuit diagram, that is, these nodes are confluence points of relevant electrical connections in the circuit diagram, etc. Nodes that are made effective.
  • all transistors are P-type transistors as an example for description. It should be noted that the transistors in the circuits mentioned below adopt the same conduction type, which can simplify the process flow, reduce process difficulty, and improve the yield of products (such as the scan driving circuit 1000 and the display device 2000 ).
  • Some embodiments of the present disclosure provide a shift register 100 and its driving method, a scan driving circuit 1000, and a display device 2000.
  • the display device 2000 may be any device that displays images, whether moving (for example, video) or stationary (for example, still images), and regardless of text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Cameras GPS Receivers/Navigators
  • Cameras
  • the display device 2000 includes a frame, a display panel PNL disposed in the frame, a circuit board, a data driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display panel PNL disposed in the frame
  • a circuit board a circuit board
  • a data driver IC Integrated Circuit, integrated circuit
  • the above-mentioned display panel PNL can be, for example, an organic light emitting diode (Organic Light Emitting Diode, referred to as OLED) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) display panel, a micro light emitting diode (Micro Light Emitting Diodes, referred to as Micro LED) display panel or Mini Light Emitting Diodes (Mini Light Emitting Diodes, Mini LED for short), etc., which are not specifically limited in this disclosure.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • Mini Light Emitting Diodes Mini Light Emitting Diodes, Mini LED for short
  • Some embodiments of the present disclosure will be schematically described below by taking the aforementioned display panel PNL as an OLED display panel as an example.
  • the display panel PNL has a display area A and a frame area B disposed beside the display area A.
  • side refers to one side, two sides, three sides or surrounding sides of the display area A, that is, the border area B can be located on one side, two sides or three sides of the display area A, or the border Area B may be arranged around display area A.
  • the display panel PNL may include: a substrate 200, and a plurality of sub-pixels P disposed on one side of the substrate 200, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of An enable signal line EL.
  • the substrate 200 may be a rigid substrate.
  • the rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the substrate 200 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or a PI (Polyimide , polyimide) substrates, etc.
  • the display panel PNL may be a flexible display panel.
  • the plurality of sub-pixels P, the plurality of gate lines GL, the plurality of data lines DL and the plurality of enable signal lines EL may be located in the display area A, and the plurality of gate lines GL may be Extending along the first direction X, the plurality of data lines DL may extend along the second direction Y, and the plurality of enable signal lines EL may extend along the first direction X.
  • the plurality of enable signal lines EL may be arranged on the same layer as the aforementioned plurality of gate lines GL, for example.
  • first direction X and the second direction Y cross each other.
  • the included angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the included angle between the first direction X and the second direction Y may be 85°, 88°, 90°, 92° or 95° and so on.
  • the plurality of sub-pixels P may be arranged in an array, that is, the plurality of sub-pixels P may be arranged in multiple rows along the first direction X, and arranged in multiple rows along the second direction Y.
  • the sub-pixels P arranged in a row along the first direction X may be referred to as sub-pixels P of the same row
  • the sub-pixels P arranged in a row along the second direction Y may be referred to as sub-pixels P of the same column.
  • the sub-pixels P in the same row may be electrically connected to at least one gate line GL and at least one enable signal line EL
  • the sub-pixels P in the same column may be electrically connected to one data line DL.
  • the number of gate lines GL and enable signal lines EL electrically connected to the sub-pixels P in the same row can be set according to the structure of the sub-pixels P.
  • the sub-pixels P in the same row are electrically connected to a gate line GL and an enable signal line EL as an example for illustration.
  • each sub-pixel P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit.
  • the display panel PNL is an OLED display panel
  • the light emitting device is an OLED.
  • the structure of the pixel driving circuit may include structures such as "4T1C”, “6T1C”, “7T1C”, “6T2C”, “7T2C” or “8T2C”.
  • T represents a transistor
  • the number before “T” represents the number of transistors
  • C represents a storage capacitor
  • the number before “C” represents the number of storage capacitors.
  • the light-emitting device may include an anode, a light-emitting layer, and a cathode that are sequentially stacked.
  • the light-emitting device can also include, for example, a hole injection layer and/or a hole transport layer disposed between the anode and the light-emitting layer, and can also include, for example, an electron transport layer and/or an electron injection layer disposed between the light-emitting layer and the cathode.
  • the pixel driving circuit is electrically connected to the anode of the light emitting device, for example.
  • the pixel drive circuit includes: a first reset transistor M1, a compensation transistor M2, a drive transistor M3, a switch transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset Transistor M7 and storage capacitor Cst.
  • the control electrode of the first reset transistor M1 is electrically connected to the reset signal terminal RESET, the first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal INIT, and the first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal INIT.
  • the diode is electrically connected to the first pixel node Q1.
  • the first reset transistor M1 is configured to transmit the initial signal received from the initial signal terminal INIT to the first pixel node Q1 under the control of the reset signal transmitted by the reset signal terminal RESET, and the first pixel node Q1 Do a reset.
  • the control electrode of the compensation transistor M2 is electrically connected to the scanning signal terminal Gate
  • the first electrode of the compensation transistor M2 is electrically connected to the second pixel node Q2
  • the second electrode of the compensation transistor M2 is electrically connected to the first pixel node Q2.
  • the pixel node Q1 is electrically connected.
  • the compensation transistor M2 is configured to transmit the signal (such as a data signal) from the second pixel node Q2 to the first pixel node Q1 under the control of the scanning signal transmitted by the scanning signal terminal Gate, and to drive the transistor T3 Perform threshold voltage compensation.
  • the control electrode of the driving transistor M3 is electrically connected to the first pixel node Q1, the first electrode of the driving transistor M3 is electrically connected to the third pixel node Q3, and the second electrode of the driving transistor M3 is electrically connected to the first pixel node Q3.
  • the two pixel nodes Q2 are electrically connected.
  • the driving transistor M3 is configured to transmit a signal (such as a data signal) from the third pixel node Q3 to the second pixel node Q2 under the control of the voltage of the first pixel node Q1 .
  • the control electrode of the switching transistor M4 is electrically connected to the scanning signal terminal Gate
  • the first electrode of the switching transistor M4 is electrically connected to the data signal terminal Data
  • the second electrode of the switching transistor M4 is electrically connected to the third pixel terminal.
  • Node Q3 is electrically connected.
  • the switch transistor M4 is configured to transmit the data signal transmitted by the data signal terminal Data to the third pixel node Q3 under the control of the scan signal transmitted by the scan signal terminal Gate.
  • the control electrode of the first light emission control transistor M5 is electrically connected to the light emission control signal terminal EM
  • the first electrode of the first light emission control transistor M5 is electrically connected to the first power signal terminal VDD
  • the first light emission control transistor M5 is electrically connected to the first power signal terminal VDD.
  • the second electrode of the light emission control transistor M5 is electrically connected to the third pixel node Q3.
  • the first light emission control transistor M5 is configured to transmit the first power signal transmitted by the first power signal terminal VDD to the third pixel node Q3 under the control of the light emission control signal transmitted by the light emission control signal terminal EM.
  • the control electrode of the second light emission control transistor M6 is electrically connected to the light emission control signal terminal EM
  • the first electrode of the second light emission control transistor M6 is electrically connected to the second pixel node Q2
  • the second light emission control transistor M6 is electrically connected to the second pixel node Q2.
  • the second pole of the control transistor M6 is electrically connected to the anode of the light emitting device.
  • the second light emission control transistor M6 is configured to transmit the signal (such as the first power signal) from the second pixel node Q2 to the light emitting device under the control of the light emission control signal transmitted by the light emission control signal terminal EM. anode.
  • the control electrode of the second reset transistor M7 is electrically connected to the scan signal terminal Gate
  • the first electrode of the second reset transistor M7 is electrically connected to the initial signal terminal INIT
  • the second electrode of the second reset transistor M7 is electrically connected to the initial signal terminal INIT.
  • the diode is electrically connected to the anode of the light emitting device.
  • the second reset transistor M7 is configured to, under the control of the scanning signal transmitted by the scanning signal terminal Gate, transmit the initial signal received from the initial signal terminal INIT to the anode of the light emitting device, and reset the anode of the light emitting device .
  • the cathode of the light emitting device is electrically connected to the second power signal terminal VSS.
  • the light emitting device is configured to emit light under the control of the first power signal and the second power signal transmitted by the second power signal terminal VSS.
  • the first terminal of the storage capacitor Cst is electrically connected to the first power signal terminal VDD, and the second terminal of the storage capacitor Cst is electrically connected to the first pixel node Q1 .
  • the storage capacitor Cst is configured to store the signal transmitted to the first pixel node Q1 and maintain the voltage of the first pixel node Q1.
  • the above-mentioned pixel driving circuit can be electrically connected to the corresponding gate line GL through the scanning signal terminal Gate, electrically connected to the corresponding data line DL through the data signal terminal Data, and connected to the corresponding enable signal line through the light emission control signal terminal EM. EL electrical connection.
  • the pixel drive circuit can receive the scan signal from the corresponding gate line GL, the data signal from the corresponding data line DL and the enable signal from the corresponding enable signal line EL to form a drive current.
  • the driving current can be transmitted to the light emitting device through the first light emitting control transistor M5 , the driving transistor M3 and the second light emitting control transistor M6 to drive the light emitting device to emit light.
  • the cooperation of the light-emitting devices of the multiple sub-pixels P enables the display panel PNL to display images.
  • each transistor in the pixel driving circuit may include, for example, at least one of a Low Temperature Poly-Silicon Thin Film Transistor (LTPS TFT for short) and an oxide thin film transistor.
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • LTPS TFT and oxide thin film transistor can be integrated in the same display panel to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display panel, so that the advantages of both can be used to achieve high Resolution (Pixel Per Inch, PPI for short), low frequency drive, help reduce power consumption and improve display quality.
  • the above-mentioned data driver IC may be the frame area B, and is electrically connected to a plurality of data lines DL located in the display area A, and through the plurality of data lines DL to the corresponding pixel driver circuit Provides a data signal.
  • the display panel PNL may include: the scan driving circuit 1000 described above.
  • the scan driving circuit 1000 may be located on the same side of the substrate 200 as the plurality of sub-pixels P, the gate lines GL, the data lines DL, and the like.
  • the scan driving circuit 1000 may be a gate driving circuit GD.
  • the gate driving circuit GD may be electrically connected to the plurality of gate lines GL, so as to provide scanning signals to corresponding pixel driving circuits through the plurality of gate lines GL.
  • the scan driving circuit 1000 may also be an emission control circuit ED.
  • the light emission control circuit ED may be electrically connected to the plurality of enable signal lines EL, so as to provide enable signals to corresponding pixel driving circuits through the plurality of enable signal lines EL.
  • the scan driving circuit 1000 may be disposed in the frame area B and located on at least one side of the extending direction of the plurality of gate lines GL.
  • At least a part of the above scan driving circuit 1000 may be disposed in the display area A. As shown in FIG. This helps to reduce the occupied area of the scan driving circuit 1000 in the frame area B, and further helps to reduce the size of the frame area B, so that the display panel PNL and the display device 2000 can realize a narrow frame design.
  • the following schematic description will be given by taking the scanning driving circuit 1000 as the gate driving circuit GD and the scanning driving circuit 1000 being arranged in the frame area B as an example.
  • the scan driving circuit 1000 includes a plurality of shift registers 100 , and the plurality of shift registers 100 can be cascaded.
  • the number of shift registers 100 included in the scan driving circuit 1000 and the number of rows of sub-pixels P may be equal or different.
  • the number of shift registers 100 may be equal to the number of rows of sub-pixels P.
  • one shift register 100 can be electrically connected to the pixel driving circuit in the same row of sub-pixels P through one gate line GL.
  • the number of shift registers 100 may be greater than the number of rows of sub-pixels P.
  • one shift register 100 can be electrically connected to the pixel driving circuit in the same row of sub-pixels P through a gate line GL, and the output signal terminals Gout of the remaining shift registers 100 that are not electrically connected to the gate line GL can be in a floating state .
  • the output signal terminal Gout reference may be made to the description below, and details will not be repeated here.
  • the number of shift registers 100 may be smaller than the number of rows of sub-pixels P.
  • one shift register 100 may be electrically connected to the pixel driving circuits in corresponding rows of sub-pixels P through multiple gate lines GL.
  • the structure of the above-mentioned shift register 100 includes various types, which can be selected and set according to actual needs.
  • the structure of the shift register 100 is schematically described below, but the structure of the shift register 100 in the present disclosure is not limited to the illustrated structure.
  • the above-mentioned shift register 100 includes a plurality of transistors, and the conduction types of the plurality of transistors are the same.
  • the plurality of transistors may all be N-type transistors, or, the plurality of transistors may all be P-type transistors.
  • the types of transistors are different, the corresponding timing diagrams may also be different, so the timing diagrams in this application are not limited accordingly.
  • the structure types of the above-mentioned multiple transistors may be the same or different.
  • the multiple transistors may include low temperature polysilicon thin film transistors, amorphous silicon thin film transistors or metal oxide thin film transistors.
  • the shift register 100 may include: an input circuit 1 , an output circuit 2 , a first control circuit 3 and a holding circuit 4 .
  • the input circuit 1 is electrically connected to the first clock signal terminal CK, the input signal terminal STV and the first node N1. Wherein, the input circuit 1 is configured to transmit the input signal received at the input signal terminal STV to the first node N1 under the control of the first clock signal transmitted by the first clock signal terminal CK.
  • the input circuit 1 when the level of the first clock signal is low, the input circuit 1 can be turned on under the control of the first clock signal, and transmit the input signal received at the input signal terminal STV to The first node N1 charges the first node N1.
  • the voltage of the first node N1 when the level of the input signal is low level, the voltage of the first node N1 is low level; when the level of the input signal is high level, the voltage of the first node N1 is high level.
  • the output circuit 2 is electrically connected to the first node N1 , the second clock signal terminal CB, and the output signal terminal Gout. Wherein, the output circuit 2 is configured to transmit the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout under the control of the voltage of the first node N1.
  • the output circuit 2 may be turned on under the control of the voltage of the first node N1, and receive and transmit the second clock signal to the output signal terminal Gout.
  • the output signal terminal Gout can output the second clock signal as the output signal.
  • the output signal is a scanning signal received by the pixel driving circuit.
  • the first control circuit 3 is electrically connected to the first node N1 , the first voltage signal terminal VGH, the second clock signal terminal CB, and the second node N2 . Wherein, the first control circuit 3 is configured to control the voltage of the second node N2 under the control of the voltage of the first node N1 and the second clock signal.
  • the first voltage signal terminal VGH is configured to transmit a DC high-level signal (for example, higher than or equal to the high-level part of the clock signal); the DC high-level signal is referred to as a first voltage signal here.
  • the first control circuit 3 may receive and transmit the first voltage signal terminal VGH to the second node N2 under the control of the voltage of the first node N1 , to charge the second node N2, so that the voltage of the second node N2 is at a high level.
  • the first control circuit 3 may receive and transmit the second clock signal under the control of the second clock signal To the second node N2, the second node N2 is charged, so that the voltage of the second node N2 is at a low level.
  • the voltage of the second node N2 may remain unchanged. That is, the voltage of the second node N2, for example, can be maintained as the voltage when the voltage of the first node N1 is at a high level and the level of the second clock signal is at a low level; or, the voltage of the second node N2, For example, the voltage at the first node N1 may be held at a low level and the second clock signal is at a high level.
  • the first control circuit 3 may include a first sub-control circuit 31 and a second sub-control circuit 32 .
  • the first sub-control circuit 31 is electrically connected to the first node N1 , the first voltage signal terminal VGH, the second clock signal terminal CB and the third node N3 .
  • the first sub-control circuit 31 is configured to control the voltage of the third node N3 under the control of the voltage of the first node N1 and the second clock signal.
  • the third node N3 when the voltage of the first node N1 is at a high level, the third node N3 is in a floating state.
  • the first sub-control circuit 31 may couple the second clock signal to the third node N3, and the voltage of the third node N3 may be the same as the level of the second clock signal.
  • the level of the second clock signal when the level of the second clock signal is low level, the voltage of the third node N3 is low level; when the level of the second clock signal is high level, the third node N3 The voltage is high level.
  • the first sub-control circuit 31 can receive and transmit the first voltage signal terminal VGH to the third node N3 to charge the third node N3, so that the third node N3 The voltage is high level.
  • the second clock signal is coupled to the third node N3, but no matter whether the level of the second clock signal is high level or low level, the voltage of the third node N3 is determined by the first The voltage signal is determined.
  • the second sub-control circuit 32 is electrically connected to the first node N1 , the third node N3 , the first voltage signal terminal, the second clock signal terminal CB and the second node N2 .
  • the second sub-control circuit 32 is configured to control the voltage of the second node N2 under the control of the voltage of the first node N1 and the voltage of the third node N3.
  • the second sub-control circuit 32 may receive and transmit the first voltage signal terminal VGH to the second node N2, The second node N2 is charged, so that the voltage of the second node N2 is at a high level.
  • the second sub-control circuit 32 can receive and transmit the second The second clock signal is sent to the second node N2 to charge the second node N2 so that the voltage of the second node N2 is at a low level.
  • the voltage of the second node N2 may remain unchanged. That is, the voltage of the second node N2, for example, may be maintained at a low level when the voltage of the first node N1 is at a high level and the level of the second clock signal is at a low level; or, the voltage of the second node N2 The voltage can be maintained at a high level when, for example, the voltage of the first node N1 is at a low level and the level of the second clock signal is at a high level.
  • the holding circuit 4 is electrically connected to the second node N2 , the first voltage signal terminal VGH and the output signal terminal Gout. Wherein, the holding circuit 4 is configured to transmit the first voltage signal to the output signal terminal Gout under the control of the voltage of the second node N2.
  • the holding circuit 4 may be turned on under the control of the voltage of the second node N2, and receive and transmit the first voltage signal to the output signal terminal Gout.
  • the output signal terminal Gout can output the first voltage signal as the output signal.
  • the holding circuit 4 is kept in an off state to avoid transmitting the first voltage signal to the output signal terminal Gout, and then Can avoid affecting the accuracy of the output signal.
  • the output circuit 2 is maintained in an off state, avoiding transmitting the second clock signal to the output signal terminal Gout, thereby avoiding affecting the output signal accuracy.
  • the working process of the shift register 100 includes: a first stage S1 and a second stage S2.
  • the level of the first clock signal is low level, and the level of the input signal is low level.
  • the input circuit 1 In response to the first clock signal received at the first clock signal terminal CK, the input circuit 1 is turned on, and transmits the input signal received at the input signal terminal STV to the first node N1, so that the voltage of the first node N1 is low. flat.
  • the output circuit 2 Under the control of the voltage of the first node N1, the output circuit 2 is turned on, and transmits the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout.
  • the output circuit 2 has a voltage storage function, that is, the output circuit 2 can store low-level input signals. Even if the input circuit 1 is turned off in the first stage S1, the function of the output circuit 2 can also keep the voltage of the first node N1 at a low level in the first stage S1, and then make the output circuit 2 maintain a low level in the first stage S1. conduction state.
  • the first control circuit 3 Under the control of the voltage of the first node N1 and the second clock signal, the first control circuit 3 transmits the first voltage signal transmitted by the first voltage signal terminal VGH to the second node N2 to control the voltage of the second node N2.
  • the holding circuit 4 Under the control of the voltage of the above-mentioned second node N2, the holding circuit 4 is turned off. Since in the first phase S1, the voltage of the first node N1 is maintained at a low level, therefore, the first control circuit 3 can continuously transmit the first voltage signal to the second node N2 without being affected by the second clock signal , so that the voltage of the second node N2 is kept at a high level, thereby keeping the holding circuit 4 in an off state.
  • the waveform of the output signal output by the output signal terminal Gout is the same as the waveform of the second clock signal. Since the second clock signal is maintained at a high level and then transitions to a low level, the output signal is maintained at a high level and then transitioned to a low level.
  • the waveform of the output signal can be shown in FIG. 14 .
  • the level of the first clock signal is low level, and the level of the input signal is high level.
  • the input circuit 1 In response to the first clock signal received at the first clock signal terminal CK, the input circuit 1 is turned on, and transmits the input signal received at the input signal terminal STV to the first node N1, so that the voltage of the first node N1 is high. flat.
  • the output circuit 2 Under the control of the voltage of the above-mentioned first node N1, the output circuit 2 is turned off. Since the output circuit 2 has a voltage storage function, that is, the output circuit 2 will store high-level input signals. Even if the input circuit 1 is turned off in the second stage S1, this function of the output circuit 2 can also keep the voltage of the first node N1 at a high level in the second stage S1, and then make the output circuit 2 maintain a high level in the second stage S1. off state.
  • the first control circuit 3 Under the control of the voltage of the first node N1 and the second clock signal, the first control circuit 3 transmits the second clock signal to the second node N2 to control the voltage of the second node N2.
  • the holding circuit 4 Under the control of the voltage of the second node N2, the holding circuit 4 is turned on, and transmits the first voltage signal to the output signal terminal Gout. Since in the second stage S2, the voltage of the first node N1 is maintained at a high level, the voltage of the second node N2 is affected by the second clock signal and changes. For example, when the level of the second clock signal transitions to a low level, the voltage of the second node N2 may change to a low level under the action of the second clock signal.
  • the waveform of the output signal output by the output signal terminal Gout is the same as the waveform of the first voltage signal. That is, the level of the output signal remains at a high level, and the waveform of the output signal may be as shown in FIG. 14 .
  • the low-level part of the output signal can be called the working level, which is used to turn on some transistors in the corresponding pixel driving circuit;
  • the high-level part of the output signal can be called the non-working level, which is used to turn off Part of the transistors in the corresponding pixel driver circuit.
  • the shift register 100 provided by some embodiments of the present disclosure, by setting the input circuit 1, the output circuit 2, the first control circuit 3 and the holding circuit 4, and setting the input circuit 1, the output circuit 2, the first control circuit
  • the circuit 3 and the holding circuit 4 are respectively electrically connected to the corresponding signal terminals, and the mutual cooperation between the signal terminals can be used to make the output circuit 2 and the holding circuit 4 conduct at different time intervals, and make the first signal output by the output circuit 2
  • the two clock signals and the first voltage signal output by the holding circuit 4 together constitute an output signal.
  • the output signal can be used to drive the corresponding sub-pixel P for display.
  • the structure of the shift register 100 provided by some embodiments of the present disclosure is relatively simple, which is beneficial to improving the manufacturing yield of the shift register 100 and reducing the occupied area of the shift register 100 in the display panel PNL.
  • the shift register 100 is arranged in the frame area B, it is beneficial to reduce the size of the frame area B, and further facilitates the realization of a narrow frame design.
  • the above-mentioned first clock signal and the second clock signal are mutually inverse signals.
  • the "inversion signal” here means that within a certain period of time, the level of the first clock signal and the level of the second voltage signal remain unchanged, and the level of the first clock signal In the case of high level, the level of the second clock signal is low level, and in the case of low level of the first clock signal, the level of the second clock signal is high level.
  • the foregoing anti-phase signal can be set in various ways, and the setting can be selected according to actual needs, which is not limited in the present disclosure.
  • the level of the second clock signal transitions from low level to high level.
  • the level of the second clock signal changes from high level to low level.
  • the level of the first clock signal and the level of the second clock signal do not change at the same time.
  • the second clock signal has already transitioned from low level to high level.
  • the waveform of the first clock signal and the waveform of the second clock signal can be Set to the waveform shown in Figure 14.
  • the present disclosure is schematically described by taking the waveforms of the first clock signal and the second clock signal as shown in FIG. 14 as an example.
  • the structure of the shift register 100 simplifies the structure of the scanning driving circuit 1000 applied to the shift register 100, which is beneficial to the realization of a narrow frame design.
  • the structures of the input circuit 1 , the output circuit 2 , the first control circuit 3 and the holding circuit 4 are schematically described below in conjunction with FIG. 7 .
  • the input circuit 1 includes: a first transistor T1.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK
  • the first electrode of the first transistor T1 is electrically connected to the input signal terminal STV
  • the first electrode of the first transistor T1 is electrically connected to the input signal terminal STV.
  • the diode is electrically connected to the first node N1.
  • the first transistor T1 when the level of the first clock signal is low, the first transistor T1 can be turned on under the control of the first clock signal, receive and transmit the input signal to the first node N1, and the first node N1 is charged.
  • the voltage of the first node N1 when the level of the input signal is low level, the voltage of the first node N1 is low level; when the level of the input signal is high level, the voltage of the first node N1 is high level.
  • the output circuit 2 includes: a second transistor T2 and a first capacitor C1.
  • control electrode of the second transistor T2 is electrically connected to the first node N1
  • first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB
  • second electrode of the second transistor T2 The pole is electrically connected to the output signal terminal Gout.
  • the second transistor T2 may be turned on under the control of the voltage of the first node N1 to receive and transmit the second clock signal to the output signal terminal Gout.
  • the first terminal of the first capacitor C1 is electrically connected to the first node N1
  • the second terminal of the first capacitor C1 is electrically connected to the output signal terminal Gout.
  • the first capacitor C1 can also be charged.
  • the first capacitor C1 can be discharged to maintain the voltage of the first node N1.
  • the first capacitor C1 may be discharged, so that the voltage of the first node N1 is maintained at a low level, and then the second transistor T2 is kept in a conductive state, and continuously receives and transmits the first The second clock signal is sent to the output signal terminal Gout.
  • the first sub-control circuit 31 includes: a third transistor T3 and a second capacitor C2.
  • the control electrode of the third transistor T3 is electrically connected to the first node N1
  • the first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal VGH
  • the second electrode of the third transistor T3 pole is electrically connected to the third node N3.
  • a first terminal of the second capacitor C2 is electrically connected to the second clock signal terminal CB, and a second terminal of the second capacitor C2 is electrically connected to the third node N3.
  • the third transistor T3 may be turned off under the control of the voltage of the first node N1. At this time, the third node N3 is in a floating state.
  • the second capacitor C2 may couple the second clock signal to the third node N3. When the level of the second clock signal is high level, the voltage of the third node N3 is high level, and when the level of the second clock signal is low level, the voltage of the third node N3 is low.
  • the third transistor T3 When the voltage of the first node N1 is at a low level, the third transistor T3 may be turned on under the control of the voltage of the first node N1, and receive and transmit the first voltage signal to the third node N3, for the third The node N3 is charged, so that the voltage of the third node N3 increases. In this case, the second clock signal will still be coupled to the third node N3 through the second capacitor C2, but no matter whether the level of the second clock signal is high level or low level, the voltage of the third node N3 is determined by the first controlled by a voltage signal.
  • the second sub-control circuit 32 includes: a fourth transistor T4 and a fifth transistor T5 .
  • control electrode of the fourth transistor T4 is electrically connected to the first node N1
  • first electrode of the fourth transistor T4 is electrically connected to the first voltage signal terminal VGH
  • second electrode of the fourth transistor T4 The pole is electrically connected to the second node N2.
  • the fourth transistor T4 may be turned on under the control of the voltage of the first node N1, and receive and transmit the first voltage signal to the second node N2.
  • the second node N2 is charged, so that the voltage of the second node N2 increases.
  • control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the second electrode of the fifth transistor T5 The pole is electrically connected to the second node N2.
  • the fifth transistor T5 may be turned on under the control of the voltage of the third node N3, and receive and transmit the second clock signal to the second node N2.
  • the second node N2 is charged.
  • the third transistor T3 and the fourth transistor T4 can be turned on under the control of the voltage of the first node N1, and the third transistor T3 can receive and The first voltage signal is transmitted to the third node N3 so that the fifth transistor T5 is turned off, and the fourth transistor T4 can receive and transmit the first voltage signal to the second node N2 so that the voltage of the second node N2 is at a high level.
  • the third transistor T3 and the fourth transistor T4 may be turned off under the control of the voltage of the first node N1.
  • the second capacitor C2 may couple the second clock signal to the third node N3, so that the fifth transistor T5 is turned on.
  • the fifth transistor T5 can receive and transmit the second clock signal to the second node N2, so that the voltage of the second node N2 is at a low level.
  • the holding circuit 4 includes: a sixth transistor T6 and a third capacitor C3.
  • control electrode of the sixth transistor T6 is electrically connected to the second node N2
  • first electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH
  • second electrode of the sixth transistor T6 The pole is electrically connected to the output signal terminal Gout.
  • the sixth transistor T6 may be turned on under the control of the voltage of the second node N2 to receive and transmit the first voltage signal to the output signal terminal Gout.
  • the first terminal of the third capacitor C3 is electrically connected to the second node N2
  • the second terminal of the third capacitor C3 is electrically connected to the first voltage signal terminal VGH.
  • the third capacitor C3 can also be charged.
  • the third capacitor C3 can be discharged to maintain the voltage of the second node N2.
  • the third capacitor C3 may be discharged, so that the voltage of the second node N2 is maintained at a low level, and then the sixth transistor T6 is kept in a conductive state, and continues to receive and transmit the second A voltage signal is sent to the output signal terminal Gout.
  • the shift register includes two D flip-flops.
  • the first D flip-flop includes a first transmission gate TG1, a first NAND gate Nand1, a first inverter INV1 and a second transmission gate TG2.
  • the second D flip-flop includes a third transmission gate TG3, a second NAND gate Nand2, a second inverter INV2 and a fourth transmission gate TG4.
  • the driving method is: when the level of the clock signal clk is low and the level of the inverted clock signal clkb is high, the first D flip-flop is turned on, and the signals output by the previous shift registers Transmitted to the first D flip-flop, since the third transmission gate TG3 of the second D flip-flop is in the off state, the signal cannot enter the second D flip-flop; when the level of the clock signal clk is high When the levels of the flat and inverted clock signals clkb are low, the first D flip-flop is turned off and latches the signal, and at this time, the second D flip-flop is turned on and outputs the signal. Thus, shifting from the previous shift register to the next shift register is realized.
  • each D flip-flop of the shift register in the related art needs two transmission gates, an inverter and a NAND gate, and each shift register needs two D flip-flops, this will make the circuit configuration more complex. It is complex and needs to occupy a large typesetting space, making it difficult to achieve a narrow border design.
  • the shift register 100 provided by some embodiments of the present disclosure includes six transistors and three capacitors, and has a simple structure. This is beneficial to improving the manufacturing yield of the shift register 100 and reducing the occupied area of the shift register 100 in the display panel PNL. Under the condition that the shift register 100 is arranged in the frame area B, it is beneficial to reduce the size of the frame area B, and further facilitates the realization of a narrow frame design.
  • electrical connection mentioned in the present disclosure may refer to direct electrical connection or indirect electrical connection, which may be determined according to actual needs.
  • the shift register 100 may further include: a potential stabilization circuit 5 .
  • the potential stabilization circuit 5 is electrically connected to the first node N1 , the second voltage signal terminal VGL and the fourth node N4 .
  • the potential stabilizing circuit 5 is configured to, under the control of the second voltage signal transmitted by the second voltage signal terminal VGL, transmit the input signal from the first node N1 to the fourth node N4, and stabilize the fourth node The voltage of N4.
  • the above-mentioned output circuit 2 is electrically connected to the fourth node N4, and is electrically connected to the first node N1 through the potential stabilization circuit 5. That is, the electrical connection between the output circuit 2 and the input circuit 1 is an indirect electrical connection, and the electrical connection between the two is realized through the potential stabilization circuit 5 .
  • the output circuit 2 is configured to transmit the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout under the control of the voltage of the fourth node N4.
  • the second voltage signal terminal VGL is configured to transmit a DC low-level signal (for example, lower than or equal to the low-level part of the clock signal); the DC low-level signal is referred to as a second voltage signal here.
  • a DC low-level signal for example, lower than or equal to the low-level part of the clock signal
  • the DC low-level signal is referred to as a second voltage signal here.
  • the "high level” and “low level” mentioned herein are relative terms, and the voltage value of "high level” and “low level” are not limited.
  • the level of the second voltage signal is low level, and the potential stabilizing circuit 5 remains on.
  • the input circuit 1 is turned on and transmits the input signal to the first node N1
  • the potential stabilization circuit 5 can transmit the input signal to the fourth node N4.
  • the output circuit 2 can be turned on under the control of the voltage of the fourth node N4, and receive and transmit the second clock signal to the output signal terminal Gout .
  • the input circuit 1 When the input circuit 1 is turned off, the input circuit 1 has no signal output. At this time, the first node N1 is in a floating state.
  • the voltage of the fourth node N4 is likely to further decrease due to the bootstrap effect of the first capacitor C1.
  • the potential stabilizing circuit 5 can be turned off to prevent the fourth node N4 from leaking through the input circuit 1, thereby stabilizing the voltage of the fourth node N4 and ensuring the stable conduction state of the output circuit 2, In turn, the accuracy of the output signal can be ensured.
  • the voltage of the first node N1 can be prevented from greatly decreasing due to the influence of the voltage change of the fourth node N4, thereby preventing the voltage of the first node N1 from being greatly reduced by the two pairs of input circuits. 1 (that is, the first transistor T1 ) and the third control circuit 7 (that is, the ninth transistor T9 ) are adversely affected.
  • the third control circuit 7 that is, the ninth transistor T9
  • the structure of the potential stabilizing circuit 5 will be schematically described below with reference to FIG. 9 .
  • the potential stabilization circuit 5 includes: a seventh transistor T7.
  • control electrode of the seventh transistor T7 is electrically connected to the second voltage signal terminal VGL
  • first electrode of the seventh transistor T7 is electrically connected to the first node N1
  • second electrode of the seventh transistor T7 pole is electrically connected to the fourth node N4.
  • the seventh transistor T7 since the control electrode of the seventh transistor T7 is electrically connected to the second voltage signal terminal VGL, and the second voltage signal is a DC low-level signal, the seventh transistor T7 is in a normally-on state, and will receive voltage from the first node N1. The input signal of is transmitted to the fourth node N4.
  • the control electrode of the second transistor T2 is electrically connected to the fourth node N4, and is electrically connected to the first node N1 through the seventh transistor T7. connect. That is, the electrical connection relationship between the control electrode of the second transistor T2 and the first node N1 is an indirect electrical connection.
  • the seventh transistor T7 By setting the seventh transistor T7, it is possible to prevent the fourth node N4 from leaking through the first transistor T1, thereby making the voltage of the fourth node N4 relatively stable, so that the second transistor T2 has a relatively stable conduction state. Moreover, the voltage of the first node N1 can be controlled and stabilized, so as to avoid affecting the performance of the first transistor T1 and the ninth transistor T9 due to a large change in the voltage of the first node N1 .
  • the shift register 100 may further include: a second control circuit 6 .
  • the above-mentioned second control circuit 6 is electrically connected to the second node N2 , the first voltage signal terminal VGH and the first node N1 .
  • the second control circuit 6 is configured to transmit the first voltage signal to the first node N1 under the control of the voltage of the second node N2.
  • the second control circuit 6 may be turned on under the control of the voltage of the second node N2, and receive and transmit the first voltage signal to the first node N1 , to charge the first node N1, so that the voltage of the first node N1 is at a high level.
  • the voltage of the first node N1 can be made to be at a high level, thereby making the third node N3 in a floating state, so that the third node The voltage of N3 is controlled by the low-level second clock signal. This can prevent the first sub-control circuit 31 from mistakenly transmitting the high-level first voltage signal to the third node N3, and prevent the second sub-control circuit 32 from mistakenly transmitting the high-level first voltage signal to the third node N3.
  • the voltage of the second node N2 remains in a low-level state, which in turn helps to ensure that the holding circuit 4 is in a relatively stable conduction state, and ensures that the holding circuit 4 can maintain the first high-level voltage.
  • the stable transmission of the voltage signal ensures the stable output of the high-level output signal at the output signal terminal Gout.
  • the structure of the second control circuit 6 will be schematically described below with reference to FIG. 11 .
  • the second control circuit 6 includes: an eighth transistor T8.
  • control electrode of the eighth transistor T8 is electrically connected to the second node N2
  • first electrode of the eighth transistor T8 is electrically connected to the first voltage signal terminal VGH
  • second electrode of the eighth transistor T8 The pole is electrically connected to the first node N1.
  • the eighth transistor T8 may be turned on under the control of the voltage of the second node N2, receive and transmit the first voltage signal to the first node N1, and A node N1 is charged, so that the voltage of the first node N1 is at a high level.
  • the eighth transistor T8 when the voltage of the second node N2 is at a low level, the voltage of the first node N1 can be at a high level, thereby keeping the third transistor T3 and the fourth transistor T4 in an off state . In this way, it can avoid the situation that the fifth transistor T5 is turned off due to the wrong conduction of the third transistor T3, and it is difficult to transmit the low-level second clock signal to the second node N2, and the situation that the fourth transistor T4 is wrongly turned on can be avoided.
  • the sixth transistor T6 can maintain the stable transmission of the high-level first voltage signal, and ensure the stable output of the high-level output signal at the output signal terminal Gout.
  • the shift register 100 may further include: a third control circuit 7 .
  • the third control circuit 7 is electrically connected to the second clock signal terminal CB, the fifth node N5 and the first node N1 .
  • the second control circuit 6 is electrically connected to the fifth node N5, and is electrically connected to the first node N1 through the third control circuit 7 . That is, the electrical connection relationship between the second control circuit 6 and the first node N1 is an indirect electrical connection, and the two are electrically connected through the third control circuit 7 .
  • the second control circuit 6 is configured to transmit the first voltage signal to the fifth node N5 under the control of the voltage of the second node N2.
  • the third control circuit 7 is configured to transmit the first voltage signal from the fifth node N5 to the first node N1 under the control of the second clock signal.
  • the second control circuit 6 may be turned on under the control of the voltage of the second node N2, and receive and transmit the first voltage signal to the fifth node N5 .
  • the third control circuit 7 can be turned on under the control of the second clock signal, and transmit the first voltage signal from the fifth node N5 to the first node N1, charging the first node N1, so that the voltage of the first node N1 is at a high level.
  • the first voltage signal can pass through the second control circuit 6 and the third control circuit in sequence 7 is transmitted to the first node N1, and the voltage of the first node N1 is controlled to avoid affecting the voltage of the second node N2.
  • the voltage of the second node N2 jumps from a low level to a high level, and the level of the first clock signal and the level of the input signal both jump to a low level,
  • the input circuit 1 transmits the input signal to the first node N1, so that the voltage of the first node N1 jumps from a high level to a low level.
  • the voltage of the first node N1 may be unstable.
  • the third control circuit 7 By setting the third control circuit 7 between the second control circuit 6 and the first node N1, it is possible to ensure that the third control circuit 7 is in the off state when the first stage S1 is just started, and then the input circuit 1 In the process of transmitting the input signal to the first node N1, avoid the voltage of the first node N1 from being affected by the first voltage signal, and ensure that the voltage of the first node N1 is controlled by the input signal, which is beneficial to improve the shift register 100. overall reliability.
  • the structure of the third control circuit 7 will be schematically described below with reference to FIG. 13 .
  • the third control circuit 7 includes: a ninth transistor T9.
  • the control electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal CB
  • the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5
  • the second electrode of the ninth transistor T9 The pole is electrically connected to the first node N1.
  • the second control circuit 6 includes the eighth transistor T8
  • the second pole of the eighth transistor T8 is electrically connected to the fifth node N5, and is electrically connected to the first node N1 through the ninth transistor T9. That is, the electrical connection relationship between the second pole of the eighth transistor T8 and the first node N1 is an indirect electrical connection.
  • the eighth transistor T8 may be turned on under the control of the voltage of the second node N2 to receive and transmit the first voltage signal to the fifth node N5.
  • the ninth transistor T9 may be turned on under the control of the second clock signal, and transmit the first voltage signal from the fifth node N5 to the first node N1 , to charge the first node N1, so that the voltage of the first node N1 is at a high level.
  • the ninth transistor T9 can be turned off under the control of the second clock signal to avoid The first voltage signal of N5 is transmitted to the first node N1.
  • the first transistor T1 is turned on under the control of the first low-level clock signal, and transmits the low-level input signal to the first node N1. At this time, it is difficult to determine the voltage of the first node N1, and it is also difficult to determine the conduction states of the third transistor T3 and the fourth transistor T4.
  • the ninth transistor T9 By disposing the ninth transistor T9 between the eighth transistor T8 and the first node N1, when the first transistor T1 is turned on, the ninth transistor T9 can be ensured to be in an off state, so as to avoid transmitting the first voltage signal to the first node N1 can further ensure that the voltage of the first node N1 is also controlled by a low-level input signal at the beginning of the first stage S1, ensuring that the third transistor T3 and the fourth transistor T4 are in an on state. This is beneficial to improve the overall reliability of the shift register 100 .
  • the shift register 100 provided by some embodiments of the present disclosure only includes nine transistors and three capacitors, which can realize the output of the output signal, and in the first stage S1, the output signal terminal Gout outputs a low level
  • the first control circuit 3, the second control circuit 6 and the third control circuit 7 can be used to reset the first node N1 and the fourth node N4, and in the second stage S2, a capacitor can be used to couple the transistor gate In this way, the potential of the second node N2 is controlled, so that the holding circuit 4 can output the high-level first voltage signal more stably, which is beneficial to improve the accuracy of the output signal.
  • the shift register 100 has a simple structure, which is beneficial to improving the manufacturing yield of the shift register 100 and reducing the occupied area of the shift register 100 in the display panel PNL.
  • the shift register 100 is arranged in the frame area B, it is beneficial to reduce the size of the frame area B, and further facilitates the realization of a narrow frame design.
  • the cascading relationship of the multiple shift registers 100 may include various types, which may be selected and set according to actual needs.
  • the output signal terminal Gout of the Nth shift register 100 is the same as the input signal of the N+i shift register 100 Terminal STV is electrically connected.
  • N and i are positive integers, and i ⁇ N.
  • the output signal output by the Nth shift register 100 can be used as the input signal of the N+ith shift register 100 .
  • i 1, as shown in FIG. 15 .
  • the output signal terminal Gout of each shift register 100 can be electrically connected to the input signal terminal STV of the next shift register 100 . That is, except the last shift register 100 , the output signal of each shift register 100 can be used as the input signal of the next shift register 100 .
  • the output signal terminal Gout of the Nth shift register 100 is electrically connected to the input signal terminal STV of the N+2th shift register 100 . That is, the above-mentioned plurality of shift registers 100 can be divided into two groups of shift registers.
  • One group of shift registers includes an odd number of shift registers, and each odd number of shift register output signal terminals Gout can be electrically connected to the input signal end STV of the next odd number of shift registers 100; another group of shift registers includes even number of shift registers.
  • the output signal terminal Gout of each even number of shift registers can be electrically connected to the input signal terminal STV of the next even number of shift registers 100 .
  • the scan driving circuit 1000 may further include: at least one first clock signal line 201 and at least one second clock signal line 202 .
  • the scan driving circuit 1000 may include: a first clock signal line 201 and a second clock signal line 202 .
  • the scan driving circuit 1000 may include: multiple first clock signal lines 201 and multiple second clock signal lines 202 .
  • the number of the first clock signal lines 201 and the number of the second clock signal lines 202 included in the scan driving circuit 1000 may be determined according to the cascade relationship of the above-mentioned plurality of shift registers 100 .
  • the scan driving circuit 1000 may include a first clock signal line 201 and a second clock signal line 202 .
  • the first clock signal line 201 can be electrically connected to the first clock signal terminal CK of the 2N-1th shift register 100 and the second clock signal terminal CB of the 2Nth shift register 100 connect.
  • the second clock signal line 202 can be electrically connected to the second clock signal terminal CB of the 2N ⁇ 1th shift register 100 and the first clock signal terminal CK of the 2Nth shift register 100 .
  • the 2N ⁇ 1th shift register 100 may use the clock signal transmitted by the first clock signal line 201 as the first clock signal, and may use the clock signal transmitted by the second clock signal line 202 as the second clock signal.
  • the 2Nth shift register 100 may use the clock signal transmitted by the second clock signal line 202 as the first clock signal, and may use the clock signal transmitted by the first clock signal line 201 as the second clock signal.
  • the scan driving circuit 1000 may further include: a start signal line 203 .
  • the input signal end of the first shift register 100 in the scan driving circuit 1000 can be electrically connected to the start signal line 203, so that the start signal transmitted by the start signal line 203 can be used as input signal.
  • the scan driving circuit 1000 may further include: a first voltage signal line 204 and a second voltage signal line 205 .
  • first voltage signal terminal VGH of each shift register 100 can be electrically connected to the first voltage signal line 204 to receive the first voltage signal.
  • the second voltage signal terminal VGL of each shift register 100 can be electrically connected to the second voltage signal line 205 to receive the second voltage signal.
  • the driving method of the shift register 100 shown in FIG. 13 will be schematically described below with reference to FIG. 14 and FIG. 15 .
  • A1, A2, A3, A4... AN-1, AN shown in Fig. 15 represent the 1st shift register 100, the 2nd shift register 100, the 3rd shift register 100, the 4th shift register respectively.
  • FIG. 14 shows a timing diagram of the operation of the shift register 100 shown in FIG. 13 .
  • N1 ⁇ 1>, N2 ⁇ 1>, N3 ⁇ 1> and N4 ⁇ 1> represent the first node N1, the second node N2, the third node N3 and the first shift register 100 respectively.
  • Gout ⁇ 1> represents the output signal terminal Gout of the first shift register 100 .
  • the driving method for the first shift register 100 (ie corresponding to the first row of sub-pixels P of the display panel PNL) is described as follows.
  • the driving method includes a first stage S1 and a second stage S2.
  • the first stage S2 includes an input stage S11 and a scanning stage S12
  • the second stage S2 includes a first holding stage S21 and a second holding stage S22.
  • the level of the input signal is low level
  • the level of the first clock signal is low level
  • the level of the second clock signal is high level
  • the first transistor T1 in the input circuit 1 is turned on, transmits the input signal to the first node N1 ⁇ 1>, and charges the first node N1 ⁇ 1>, so that the first node N1 ⁇ 1> voltage is low.
  • the first control circuit 3 transmits the first voltage signal to the second node N2 ⁇ 1> to control the voltage of the second node N2 ⁇ 1>.
  • the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are turned on under the control of the voltage of the first node N1 ⁇ 1>.
  • the third transistor T3 transmits the first voltage signal to the third node N3 ⁇ 1>, and charges the third node N3 ⁇ 1>, so that the voltage of the third node N3 ⁇ 1> is at a high level, thereby making the fifth transistor T5 is turned off.
  • the fourth transistor T4 transmits the first voltage signal to the second node N2 ⁇ 1>, and charges the second node N2 ⁇ 1>, so that the voltage of the second node N2 ⁇ 1> is at a high level.
  • the sixth transistor T6 in the holding circuit 4 is turned off. At this time, the first voltage signal simultaneously charges the third capacitor C3.
  • the eighth transistor T8 in the second control circuit 6 is turned off under the control of the voltage of the second node N2 ⁇ 1>.
  • the ninth transistor T9 in the third control circuit 7 is turned off under the control of the second clock signal.
  • the seventh transistor T7 in the potential stabilizing circuit 5 is kept in a conducting state, so as to transmit the input signal at the first node N1 ⁇ 1> to the fourth node N4 ⁇ 1>, so that the fourth The voltage of the node N4 ⁇ 1> is low level.
  • the first capacitor C1 is charged at the same time.
  • the second transistor T2 in the output circuit 2 Under the control of the voltage of the first node N1 ⁇ 1> (that is, the fourth node N4 ⁇ 1>), the second transistor T2 in the output circuit 2 is turned on, and transmits the second clock signal to the output signal terminal Gout ⁇ 1> , as an output signal from the output signal terminal Gout ⁇ 1>. In this stage, the level of the second clock signal is high level, therefore, the level of the output signal is high level.
  • the level of the input signal is high level
  • the level of the first clock signal is high level
  • the level of the second clock signal is low level.
  • the first transistor T1 in the input circuit 1 is turned off.
  • the first node N1 ⁇ 1> has no discharge path, therefore, the voltage of the first node N1 ⁇ 1> remains basically unchanged, that is, the voltage of the first node N1 ⁇ 1> remains at a low level.
  • the first control circuit 3 transmits the first voltage signal to the second node N2 ⁇ 1> to control the voltage of the second node N2 ⁇ 1>.
  • the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are kept in a conductive state under the control of the voltage of the first node N1 ⁇ 1>.
  • the voltage of the third node N3 ⁇ 1> is still at a high level, and the fifth transistor T5 remains in an off state.
  • the voltage of the second node N2 ⁇ 1> is still at a high level, and under the control of the voltage of the second node N2 ⁇ 1>, the sixth transistor T6 in the holding circuit 4 is kept in an off state.
  • the third capacitor C3 is continuously charged.
  • the eighth transistor T8 in the second control circuit 6 is kept in an off state under the control of the voltage of the second node N2 ⁇ 1>.
  • the ninth transistor T9 in the third control circuit 7 is turned on under the control of the second clock signal.
  • the first capacitor C1 is discharged so that the voltage of the fourth node N4 ⁇ 1> remains at a low level.
  • the second transistor T2 in the output circuit 2 remains on under the control of the voltage of the first node N1 ⁇ 1> (that is, the fourth node N4 ⁇ 1>), and continuously transmits the second clock signal to the output signal terminal Gout ⁇ 1>. In this stage, the level of the second clock signal is low level, therefore, the level of the output signal is low level.
  • the level of the input signal is high level
  • the level of the first clock signal is kept at high level first, then jumps to low level
  • the level of the second clock signal is high level. flat.
  • the voltage of the first node N1 ⁇ 1 > and the voltage of the fourth node N4 ⁇ 1 > remain at a low level. Based on this, the voltage of the second node N2 ⁇ 1> and the voltage of the third node N3 ⁇ 1> are still kept at a high level.
  • the second transistor T2 in the output circuit 2 is kept in a conducting state, and continuously transmits the second clock signal to the output signal terminal Gout ⁇ 1>. Since the level of the second clock signal is high level, the level of the output signal is high level.
  • the first transistor T1 in the input circuit 1 After the level of the first clock signal transitions to a low level, in response to the first clock signal, the first transistor T1 in the input circuit 1 is turned on, and transmits the input signal to the first node N1 ⁇ 1>, for the first A node N1 ⁇ 1> is charged, so that the voltage of the first node N1 ⁇ 1> is at a high level.
  • the seventh transistor T7 in the potential stabilizing circuit 5 is kept in a conducting state, so as to transmit the input signal at the first node N1 ⁇ 1> to the fourth node N4 ⁇ 1>, so that the fourth The voltage of the node N4 ⁇ 1> is high level. In this way, the resetting of the first node N1 ⁇ 1> and the fourth node N4 ⁇ 1> is completed. At this time, the first capacitor C1 is charged at the same time.
  • the second transistor T2 in the output circuit 2 is turned off.
  • the first control circuit 3 transmits the second clock signal to the second node N2 ⁇ 1> to control the voltage of the second node N2 ⁇ 1>.
  • the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are turned off under the control of the voltage of the first node N1 ⁇ 1>.
  • the third node N3 ⁇ 1> is in a suspended state. Since the level of the second clock signal is high level, the voltage of the third node N3 ⁇ 1> may become high level under the coupling effect of the second capacitor C2, thereby keeping the fifth transistor T5 in an off state.
  • the third capacitor C3 is discharged so that the voltage of the second node N2 ⁇ 1> remains at a high level.
  • the sixth transistor T6 in the holding circuit 4 is kept in an off state.
  • the eighth transistor T8 in the second control circuit 6 is kept in an off state under the control of the voltage of the second node N2 ⁇ 1>.
  • the level of the output signal output by the output signal terminal Gout ⁇ 1> is consistent with the first clock signal
  • the stage before the level jump of the Gout is the same, that is, the level of the output signal output by the output signal terminal Gout ⁇ 1> is still at a high level.
  • the level of the input signal is high level
  • the level of the first clock signal is high level
  • the level of the second clock signal is low level.
  • the first transistor T1 in the input circuit 1 is turned off.
  • the voltage of the first node N1 ⁇ 1> and the voltage of the fourth node N4 ⁇ 1> remain basically unchanged, that is, the voltage of the first node N1 ⁇ 1> and the voltage of the fourth node N4 ⁇ 1> remain high flat.
  • the second transistor T2 in the output circuit 2 is kept in an off state under the control of the voltage of the first node N1 ⁇ 1> (ie, the fourth node N4 ⁇ 1>).
  • the first control circuit 3 transmits the second clock signal to the second node N2 ⁇ 1> to control the voltage of the second node N2 ⁇ 1>.
  • the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are kept in an off state under the control of the voltage of the first node N1 ⁇ 1>, so that the third node N3 ⁇ 1> remains in a floating state. Since the level of the second clock signal is low level, the voltage of the third node N3 ⁇ 1> may become low level under the coupling effect of the second capacitor C2, thereby turning on the fifth transistor T5.
  • the fifth transistor T5 transmits the second clock signal to the second node N2 ⁇ 1> to charge the second node N2 ⁇ 1>, so that the voltage of the second node N2 ⁇ 1> is at a low level.
  • the eighth transistor T8 in the second control circuit 6 is turned on under the control of the voltage of the second node N2 ⁇ 1>, and transmits the first voltage signal to the fifth node N5.
  • the ninth transistor T9 in the third control circuit 7 is turned on under the control of the second clock signal, and transmits the first voltage signal from the fifth node N5 to the first node N1 ⁇ 1>, and the first node N1 ⁇ 1> Charging is performed so that the voltage of the first node N1 ⁇ 1> is at a high level.
  • the sixth transistor T6 in the holding circuit 4 is turned on to transmit the first voltage signal to the output signal terminal Gout ⁇ 1>.
  • the level of the output signal output by the output signal terminal Gout ⁇ 1> is high level.
  • the driving method of the shift register 100 may include a plurality of stages S21 and S22 that are cyclically performed in sequence.
  • the eighth transistor T8 in the second control circuit 6 and the ninth transistor T9 in the third control circuit 7 are kept on, and the sixth transistor T6 in the holding circuit 4 is kept on, and continuously
  • the first voltage signal is transmitted to the output signal terminal Gout ⁇ 1>, so that the output signal terminal Gout ⁇ 1> continuously outputs a high-level output signal.
  • the level of the control electrode of the fifth transistor T5 will be coupled and pulled down once, and the fifth transistor T5 will therefore be turned on, and the second clock signal will be turned on.
  • the second clock signal is transmitted to the second node N2 ⁇ 1>, and at the same time, the third capacitor C3 is charged, so that the voltage of the second node N2 ⁇ 1> can be kept at a low level. This process ends when the level of the input signal transitions to a low level.

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Abstract

一种移位寄存器（100），包括：输入电路（1）、输出电路（2）、第一控制电路（3）及保持电路（4）。输入电路（1）与第一时钟信号端（CK）、输入信号端（STV）及第一节点（N1）电连接。输入电路（1）被配置为，将在输入信号端（STV）处接收的输入信号传输至第一节点（N1）。输出电路（2）与第一节点（N1）、第二时钟信号端（CB）及输出信号端（Gout）电连接。输出电路（2）被配置为，将在第二时钟信号端（CB）处接收的第二时钟信号传输至输出信号端（Gout）。第一控制电路（3）与第一节点（N1）、第一电压信号端（VGH）、第二时钟信号端（CB）及第二节点（N2）电连接。第一控制电路（3）被配置为，在第一节点（N1）的电压及第二时钟信号的控制下，控制第二节点（N2）的电压。保持电路（4）与第二节点（N2）、第一电压信号端（VGH）及输出信号端（Gout）电连接。保持电路（4）被配置为，将第一电压信号传输至输出信号端（Gout）。

Description

移位寄存器及其驱动方法、扫描驱动电路、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、扫描驱动电路、显示装置。
背景技术
扫描驱动电路为显示装置中的重要组成部分。扫描驱动电路可以包括多级级联的移位寄存器，多级移位寄存器可以分别与显示装置中的多条走线电连接电连接。扫描驱动电路可以向显示装置中的多条走线(例如栅线或使能信号线等)中逐行输入扫描信号，以使得显示装置能够进行画面显示。
在显示装置中设置扫描驱动电路，能够有效降低成本、提高良率。
发明内容
一方面，提供一种移位寄存器。所述移位寄存器包括：输入电路、输出电路、第一控制电路以及保持电路。所述输入电路与第一时钟信号端、输入信号端及第一节点电连接。所述输入电路被配置为，在所述第一时钟信号端所传输的第一时钟信号的控制下，将在所述输入信号端处接收的输入信号传输至所述第一节点。所述输出电路与所述第一节点、第二时钟信号端及输出信号端电连接。所述输出电路被配置为，在所述第一节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述输出信号端。所述第一控制电路，与所述第一节点、第一电压信号端、所述第二时钟信号端及第二节点电连接。所述第一控制电路被配置为，在所述第一节点的电压及所述第二时钟信号的控制下，控制所述第二节点的电压。所述保持电路，与所述第二节点、所述第一电压信号端及所述输出信号端电连接。所述保持电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述输出信号端。
在一些实施例中，所述第一控制电路包括第一子控制电路和第二子控制电路。所述第一子控制电路与所述第一节点、所述第一电压信号端、所述第二时钟信号端及第三节点电连接；所述第一子控制电路被配置为，在所述第一节点的电压及所述第二时钟信号的控制下，控制所述第三节点的电压。所述第二子控制电路与所述第一节点、所述第三节点、所述第一电压信号端、所述第二时钟信号端及所述第二节点电连接；所述第二子控制电路被配置为，在所述第一节点的电压及所述第三节点的电压的控制下，控制所述第二节点的电压。
在一些实施例中，所述第一子控制电路包括：第三晶体管和第二电容器。所述第三晶体管的控制极与所述第一节点电连接，所述第三晶体管的第一极与所述第一电压信号端电连接，所述第三晶体管的第二极与所述第三节点电连接。所述第二电容器的第一端与所述第二时钟信号端电连接，所述第二电容器的第二端与所述第三节点电连接。
在一些实施例中，所述第二子控制电路包括：第四晶体管和第五晶体管。所述第四晶体管的控制极与所述第一节点电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第二节点电连接。所述第五晶体管的控制极与所述第三节点电连接，所述第五晶体管的第一极与所述第二时钟信号端电连接，所述第五晶体管的第二极与所述第二节点电连接。
在一些实施例中，所述移位寄存器，还包括：电位稳定电路。所述电位稳定电路与所 述第一节点、第二电压信号端及第四节点电连接；所述电位稳定电路被配置为，在所述第二电压信号端所传输的第二电压信号的控制下，将来自所述第一节点的输入信号传输至所述第四节点，并稳定所述第四节点的电压。其中，所述输出电路与所述第四节点电连接，并通过所述电位稳定电路与所述第一节点电连接；所述输出电路被配置为，在所述第四节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述输出信号端。
在一些实施例中，所述电位稳定电路包括：第七晶体管。所述第七晶体管的控制极与所述第二电压信号端电连接，所述第七晶体管的第一极与所述第一节点电连接，所述第七晶体管的第二极与所述第四节点电连接。
在一些实施例中，所述移位寄存器，还包括：第二控制电路。所述第二控制电路与所述第二节点、所述第一电压信号端及所述第一节点电连接；所述第二控制电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第一节点。
在一些实施例中，所述第二控制电路包括：第八晶体管。所述第八晶体管的控制极与所述第二节点电连接，所述第八晶体管的第一极与所述第一电压信号端电连接，所述第八晶体管的第二极与所述第一节点电连接。
在一些实施例中，所述移位寄存器，还包括：第三控制电路。所述第三控制电路与所述第二时钟信号端、第五节点及所述第一节点电连接；所述第二控制电路与所述第五节点电连接，并通过所述第三控制电路与所述第一节点电连接。所述第二控制电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第五节点。所述第三控制电路被配置为，在所述第二时钟信号的控制下，将来自所述第五节点的第一电压信号传输至所述第一节点。
在一些实施例中，所述第三控制电路包括：第九晶体管。所述第九晶体管的控制极与所述第二时钟信号端电连接，所述第九晶体管的第一极与所述第五节点电连接，所述第九晶体管的第二极与所述第一节点电连接。在所述第二控制电路包括第八晶体管的情况下，所述第八晶体管的第二极与所述第五节点电连接，并通过所述第九晶体管与所述第一节点电连接。
在一些实施例中，所述输入电路包括：第一晶体管。所述第一晶体管的控制极与所述第一时钟信号端电连接，所述第一晶体管的第一极与所述输入信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
在一些实施例中，所述输出电路包括：第二晶体管和第一电容器。所述第二晶体管的控制极与所述第一节点电连接，所述第二晶体管的第一极与所述第二时钟信号端电连接，所述第二晶体管的第二极与所述输出信号端电连接。所述第一电容器的第一端与所述第一节点电连接，所述第一电容器的第二端与所述输出信号端电连接。在所述电位稳定电路包括第七晶体管的情况下，所述第二晶体管的控制极与所述第四节点电连接，并通过所述第七晶体管与所述第一节点电连接。
在一些实施例中，所述保持电路包括：第六晶体管和第三电容器。所述第六晶体管的控制极与所述第二节点电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述输出信号端电连接。所述第三电容器的第一端与所述第二节点电连接，所述第三电容器的第二端与所述第一电压信号端电连接。
在一些实施例中，所述移位寄存器所包括的多个晶体管的导通类型相同。
在一些实施例中，所述第一时钟信号和所述第二时钟信号互为反相信号。
另一方面，提供一种如上述任一项所述的移位寄存器的驱动方法。所述驱动方法包括：包括：第一阶段和第二阶段。在所述第一阶段中，响应于在第一时钟信号端处接收的第一时钟信号，输入电路开启，将在输入信号端处接收的输入信号传输至第一节点；在所述第一节点的电压的控制下，输出电路导通，将在第二时钟信号端处接收的第二时钟信号传输至输出信号端；在所述第一节点的电压及所述第二时钟信号的控制下，第一控制电路将第一电压信号端所传输的第一电压信号传输至第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，保持电路关断；在所述第二阶段中，响应于在所述第一时钟信号端处接收的第一时钟信号，所述输入电路开启，将在所述输入信号端处接收的输入信号传输至所述第一节点；在所述第一节点的电压的控制下，所述输出电路关断；在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二时钟信号传输至所述第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，所述保持电路开启，将所述第一电压信号传输至所述输出信号端。
在一些实施例中，所述第一阶段包括输入阶段和扫描阶段。在所述输入阶段中，响应于所述第一时钟信号，所述输入电路开启，将所述输入信号传输至所述第一节点；在所述第一节点的电压的控制下，输出电路导通，将在所述第二时钟信号传输至所述输出信号端；在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第一电压信号传输至所述第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，所述保持电路关断。在所述扫描阶段中，响应于所述第一时钟信号，所述输入电路关断；所述第一节点的电压基本保持不变，所述输出电路在所述第一节点的电压的控制下保持导通状态，将所述第二时钟信号传输至所述输出信号端；在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第一电压信号传输至所述第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，所述保持电路关断。所述第二阶段包括：第一保持阶段和第二保持阶段。在所述第一保持阶段中，响应于所述第一时钟信号，所述输入电路开启，将所述输入信号传输至所述第一节点；在所述第一节点的电压的控制下，所述输出电路关断；在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二时钟信号传输至所述第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，所述保持电路关断。在所述第二保持阶段中，响应于所述第一时钟信号，所述输入电路关断；所述第一节点的电压基本保持不变，所述输出电路在所述第一节点的电压的控制下保持关断状态；在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二时钟信号传输至所述第二节点，控制所述第二节点的电压；在所述第二节点的电压的控制下，所述保持电路开启，将所述第一电压信号传输至所述输出信号端。
又一方面，提供一种扫描驱动电路。所述扫描驱动电路包括：多个级联的如上述任一实施例所述的移位寄存器。除最后i个移位寄存器外，第N个移位寄存器的输出信号端与第N+i个移位寄存器的输入信号端电连接；其中，N和i均为正整数，且i＜N。
在一些实施例中，所述扫描驱动电路，还包括：至少一条第一时钟信号线和至少一条第二时钟信号线。在i＝1的情况下，一条第一时钟信号线与第2N-1个移位寄存器的第一时钟信号端及第2N个移位寄存器的第二时钟信号端电连接；一条第二时钟信号线与第2N-1个移位寄存器的第二时钟信号端及第2N个移位寄存器的第一时钟信号端电连接。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的扫描驱动电路。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一种实现方式中的一种移位寄存器的结构图；
图2根据本公开一些实施例中的一种显示装置的结构图；
图3为根据本公开一些实施例中的一种显示面板的结构图；
图4为根据本公开一些实施例中的一种子像素的电路图；
图5为根据本公开一些实施例中的一种移位寄存器的结构图；
图6为根据本公开一些实施例中的另一种移位寄存器的结构图；
图7为根据本公开一些实施例中的一种移位寄存器的电路图；
图8为根据本公开一些实施例中的又一种移位寄存器的结构图；
图9为根据本公开一些实施例中的另一种移位寄存器的电路图；
图10为根据本公开一些实施例中的又一种移位寄存器的结构图；
图11为根据本公开一些实施例中的又一种移位寄存器的电路图；
图12为根据本公开一些实施例中的又一种移位寄存器的结构图；
图13为根据本公开一些实施例中的又一种移位寄存器的电路图；
图14为根据本公开一些实施例中的一种对应于图13所示的移位寄存器的时序控制图；
图15为根据本公开一些实施例中的一种扫描驱动电路的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明， “多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，移位寄存器所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，“节点”并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
下面，在本公开的实施例提供的电路中，以晶体管均以P型晶体管为例进行说明。需要说明的是，下面提及的各电路中的晶体管采用相同的导通类型，可以简化工艺流程，减少工艺难度，提高产品(例如扫描驱动电路1000及显示装置2000)的良率。
本公开的一些实施例提供了一种移位寄存器100及其驱动方法、扫描驱动电路1000、显示装置2000，以下对移位寄存器100、移位寄存器100的驱动方法、扫描驱动电路1000及显示装置2000分别进行介绍。
本公开的一些实施例提供一种显示装置2000，如图2所示。该显示装置2000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，上述显示装置2000包括框架、设置于框架内的显示面板PNL、电路板、数据驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
上述显示面板PNL例如可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示面板或迷你发光二极管(Mini Light Emitting Diodes，简称Mini LED)等，本公开对此不做具体限定。
下面以上述显示面板PNL为OLED显示面板为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图3所示，上述显示面板PNL具有显示区A，以及设置在显示区A旁侧的边框区B。其中，“旁侧”指的是显示区A的一侧、两侧、三侧或者周侧等，也即，边框区B可以位于显示区A的一侧、两侧或三侧，或者，边框区B可以围绕显示区A设置。
在一些示例中，如图3所示，显示面板PNL可以包括：衬底200，以及设置在该衬底200的一侧的多个子像素P、多条栅线GL、多条数据线DL及多条使能信号线EL。
上述衬底200的类型包括多种，可以根据实际需要选择设置。
示例性的，衬底200可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性的，衬底200可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底等。此时，显示面板PNL可以为柔性显示面板。
可选的，如图3所示，上述多个子像素P、多条栅线GL、多条数据线DL及多条使能信号线EL可以位于显示区A内，且该多条栅线GL可以沿第一方向X延伸，该多条数据线DL可以沿第二方向Y延伸，该多条使能信号线EL可以沿第一方向X延伸。该多条使能信号线EL例如可以和上述多条栅线GL同层设置。
此处，第一方向X和第二方向Y相互交叉。第一方向X和第二方向Y之间的夹角可以根据实际需要选择设置。示例性的，第一方向X和第二方向Y之间的夹角可以为85°、 88°、90°、92°或95°等。
例性的，上述多个子像素P可以呈阵列状排布，也即，该多个子像素P例如可以沿第一方向X排列为多排，并沿第二方向Y排列为多排。其中，可以将沿第一方向X排列成一排的子像素P称为同一行子像素P，将沿第二方向Y排列成一排的子像素P称为同一列子像素P。同一行子像素P可以与至少一条栅线GL及至少一条使能信号线EL电连接，同一列子像素P可以与一条数据线DL电连接。其中，与同一行子像素P电连接的栅线GL及使能信号线EL的数量，可以根据子像素P的结构设置。本公开以同一行子像素P与一条栅线GL及一条使能信号线EL电连接为例进行说明。
在一些示例中，如图3所示，上述多个子像素P中，每个子像素P可以包括像素驱动电路及与该像素驱动电路电连接的发光器件。在显示面板PNL为OLED显示面板的情况下，该发光器件则为OLED。
上述像素驱动电路的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路的结构可以包括“4T1C”、“6T1C”、“7T1C”、“6T2C”、“7T2C”或“8T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
示例性的，发光器件可以包括依次层叠设置的阳极、发光层和阴极。此外，发光器件例如还可以包括设置在阳极和发光层之间的空穴注入层和/或空穴传输层，例如还可以包括设置在发光层和阴极之间的电子传输层和/或电子注入层。其中，像素驱动电路例如与发光器件的阳极电连接。
下面以像素驱动电路的结构为“7T1C”的结构为例，对子像素P的结构及其与栅线GL、数据线DL、使能信号线EL之间的连接关系进行示意性说明。
示例性的，如图4所示，像素驱动电路包括：第一复位晶体管M1、补偿晶体管M2、驱动晶体管M3、开关晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6、第二复位晶体管M7和存储电容器Cst。
示例性的，如图4所示，第一复位晶体管M1的控制极与复位信号端RESET电连接，第一复位晶体管M1的第一极与初始信号端INIT电连接，第一复位晶体管M1的第二极与第一像素节点Q1电连接。其中，第一复位晶体管M1被配置为，在复位信号端RESET所传输的复位信号的控制下，将从初始信号端INIT处接收的初始信号传输至第一像素节点Q1，对第一像素节点Q1进行复位。
示例性的，如图4所示，补偿晶体管M2的控制极与扫描信号端Gate电连接，补偿晶体管M2的第一极与第二像素节点Q2电连接，补偿晶体管M2的第二极与第一像素节点Q1电连接。其中，补偿晶体管M2被配置为，在扫描信号端Gate所传输的扫描信号的控制下，将来自第二像素节点Q2的信号(例如为数据信号)传输至第一像素节点Q1，对驱动晶体管T3进行阈值电压补偿。
示例性的，如图4所示，驱动晶体管M3的控制极与第一像素节点Q1电连接，驱动晶体管M3的第一极与第三像素节点Q3电连接，驱动晶体管M3的第二极与第二像素节点Q2电连接。其中，驱动晶体管M3被配置为，在第一像素节点Q1的电压的控制下，将来自第三像素节点Q3的信号(例如为数据信号)传输至第二像素节点Q2。
示例性的，如图4所示，开关晶体管M4的控制极与扫描信号端Gate电连接，开关晶体管M4的第一极与数据信号端Data电连接，开关晶体管M4的第二极与第三像素节点 Q3电连接。其中，开关晶体管M4被配置为，在扫描信号端Gate所传输的扫描信号的控制下，将数据信号端Data所传输的数据信号传输至第三像素节点Q3。
示例性的，如图4所示，第一发光控制晶体管M5的控制极与发光控制信号端EM电连接，第一发光控制晶体管M5的第一极与第一电源信号端VDD电连接，第一发光控制晶体管M5的第二极与第三像素节点Q3电连接。其中，第一发光控制晶体管M5被配置为，在发光控制信号端EM所传输的发光控制信号的控制下，将第一电源信号端VDD所传输的第一电源信号传输至第三像素节点Q3。
示例性的，如图4所示，第二发光控制晶体管M6的控制极与发光控制信号端EM电连接，第二发光控制晶体管M6的第一极与第二像素节点Q2电连接，第二发光控制晶体管M6的第二极与发光器件的阳极电连接。其中，第二发光控制晶体管M6被配置为，在发光控制信号端EM所传输的发光控制信号的控制下，将来自第二像素节点Q2的信号(例如为第一电源信号)传输至发光器件的阳极。
示例性的，如图4所示，第二复位晶体管M7的控制极与扫描信号端Gate电连接，第二复位晶体管M7的第一极与初始信号端INIT电连接，第二复位晶体管M7的第二极与发光器件的阳极电连接。其中，第二复位晶体管M7被配置为，在扫描信号端Gate所传输的扫描信号的控制下，将从初始信号端INIT处接收的初始信号传输至发光器件的阳极，对发光器件的阳极进行复位。
示例性的，如图4所示，发光器件的阴极与第二电源信号端VSS电连接。其中，发光器件被配置为，在第一电源信号和第二电源信号端VSS所传输的第二电源信号的控制之下，进行发光。
示例性的，如图4所示，存储电容器Cst的第一端与第一电源信号端VDD电连接，存储电容器Cst的第二端与第一像素节点Q1电连接。其中，存储电容器Cst被配置为，对传输至第一像素节点Q1的信号进行存储，并维持第一像素节点Q1的电压。
示例性的，上述像素驱动电路可以通过扫描信号端Gate与相应的栅线GL电连接，通过数据信号端Data与相应的数据线DL电连接，通过发光控制信号端EM与相应的使能信号线EL电连接。
在显示面板PNL进行显示的过程中，像素驱动电路可以接收来自相应栅线GL的扫描信号、来自相应数据线DL的数据信号及来自相应使能信号线EL的使能信号，形成驱动电流，该驱动电流可以经第一发光控制晶体管M5、驱动晶体管M3和第二发光控制晶体管M6传输至发光器件，驱动发光器件发光。多个子像素P的发光器件相配合，便可以使得显示面板PNL进行图像显示。
此处，像素驱动电路中的各晶体管例如可以包括低温多晶硅薄膜晶体管(Low Temperature Poly-Silicon Thin Film Transistor，简称LTPS TFT)和氧化物薄膜晶体管中的至少一者。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在本示例中，可以将LTPS TFT和氧化物薄膜晶体管集成在同一个显示面板中，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示面板，这样可以利用两者的优势，实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，有利于降低功耗，提高显示品质。
在一些示例中，如图3所示，上述数据驱动IC可以为边框区B，并与位于显示区A的多条数据线DL电连接，一通过该多条数据线DL向相应的像素驱动电路提供数据信号。
在一些示例中，如图3所示，显示面板PNL可以包括：上述扫描驱动电路1000。该扫描驱动电路1000与上述多个子像素P、栅线GL及数据线DL等可以位于衬底200的同一侧。
上述扫描驱动电路1000的结构包括多种，可以根据实际需要选择设置。
示例性的，扫描驱动电路1000可以为栅极驱动电路GD。该栅极驱动电路GD可以与上述多条栅线GL电连接，以通过该多条栅线GL向相应的像素驱动电路提供扫描信号。
示例性的，扫描驱动电路1000还可以为发光控制电路ED。该发光控制电路ED可以与上述多条使能信号线EL电连接，以通过该多条使能信号线EL向相应的像素驱动电路提供使能信号。
上述扫描驱动电路1000的设置位置包括多种，可以根据实际需要选择设置。
示例性的，如图3所示，上述扫描驱动电路1000可以设置在边框区B内，并位于上述多条栅线GL的延伸方向的至少一侧。
示例性的，上述扫描驱动电路1000的至少一部分可以设置在显示区A内。这样有利于减少扫描驱动电路1000在边框区B内的占用面积，进而有利于减小边框区B的尺寸，使得显示面板PNL及显示装置2000能够实现窄边框设计。
下面以扫描驱动电路1000为栅极驱动电路GD、且扫描驱动电路1000设置在边框区B内为例为例进行示意性说明。
在一些实施例中，如图15所示，扫描驱动电路1000包括多个移位寄存器100，该多个移位寄存器100可以级联设置。
在一些示例中，上述扫描驱动电路1000所包括的移位寄存器100的数量，和子像素P的行数，可以相等或者不等。
例如，移位寄存器100的数量可以与子像素P的行数相等。基于此，一个移位寄存器100可以通过一条栅线GL与同一行子像素P中的像素驱动电路电连接。
又如，移位寄存器100的数量可以大于子像素P的行数。基于此，一个移位寄存器100可以通过一条栅线GL与同一行子像素P中的像素驱动电路电连接，未与栅线GL电连接的其余移位寄存器100的输出信号端Gout可以处于悬浮状态。关于输出信号端Gout的说明可以参见下文中的描述，此处不再赘述。
又如，移位寄存器100的数量可以小于子像素P的行数。基于此，一个移位寄存器100可以通过多条栅线GL与相应的多行子像素P中的像素驱动电路电连接。
上述移位寄存器100的结构包括多种，可以根据实际需要选择设置。下面对移位寄存器100的结构进行示意性说明，但本公开中的移位寄存器100的结构并不局限于所举例的结构。
需要说明的是，上述移位寄存器100包括多个晶体管，该多个晶体管的导通类型相同。示例性的，该多个晶体管可以均为N型晶体管，或者，该多个晶体管可以均为P型晶体管。本领域技术人员可以理解到，当各晶体管的类型不同时，对应的时序图也可能不同，所以本申请中的时序图并不因此而限定。
此外，上述多个晶体管的结构类型可以相同，也可以不同。示例性的，该多个晶体管可以包括低温多晶硅薄膜晶体管、非晶硅薄膜晶体管或金属氧化物薄膜晶体管。
下面，在本公开的实施例提供的移位寄存器100中，以晶体管均为LTPS TFT为例进行说明。
在一些实施例中，如图5～图7所示，上述移位寄存器100可以包括：输入电路1、输出电路2、第一控制电路3和保持电路4。
在一些示例中，如图5～图7所示，输入电路1与第一时钟信号端CK、输入信号端STV及第一节点N1电连接。其中，该输入电路1被配置为，在第一时钟信号端CK所传输的第一时钟信号的控制下，将在输入信号端STV处接收的输入信号传输至第一节点N1。
示例性的，在第一时钟信号的电平为低电平的情况下，输入电路1可以在该第一时钟信号的控制下导通，并将在输入信号端STV处接收的输入信号传输至第一节点N1，对第一节点N1进行充电。其中，在输入信号的电平为低电平的情况下，第一节点N1的电压则为低电平；在输入信号的电平为高电平的情况下，第一节点N1的电压则为高电平。
在一些示例中，如图5～图7所示，输出电路2与第一节点N1、第二时钟信号端CB及输出信号端Gout电连接。其中，该输出电路2被配置为，在第一节点N1的电压的控制下，将在第二时钟信号端CB处接收的第二时钟信号传输至输出信号端Gout。
示例性的，在第一节点N1的电压为低电平的情况下，输出电路2可以在该第一节点N1的电压的控制下导通，接收并传输第二时钟信号至输出信号端Gout。
此处，在输出电路2导通的时段，输出信号端Gout可以将第二时钟信号作为输出信号输出。该输出信号则为像素驱动电路所接收的扫描信号。
在一些示例中，如图5～图7所示，第一控制电路3与第一节点N1、第一电压信号端VGH、第二时钟信号端CB及第二节点N2电连接。其中，该第一控制电路3被配置为，在第一节点N1的电压及第二时钟信号的控制下，控制第二节点N2的电压。
此处，第一电压信号端VGH被配置为传输直流高电平信号(例如高于或等于时钟信号的高电平部分)；这里将该直流高电平信号称为第一电压信号。
示例性的，在第一节点N1的电压为低电平的情况下，第一控制电路3可以在第一节点N1的电压的控制下，接收并传输第一电压信号端VGH至第二节点N2，对第二节点N2进行充电，使得第二节点N2的电压为高电平。在第一节点N1的电压为高电平、且第二时钟信号的电平为低电平的情况下，第一控制电路3可以在第二时钟信号的控制下，接收并传输第二时钟信号至第二节点N2，对第二节点N2进行充电，使得第二节点N2的电压为低电平。
此外，在第一节点N1的电压为高电平、且第二时钟信号的电平为高电平的情况下，第二节点N2的电压可以保持不变。也即，第二节点N2的电压，例如可以保持为第一节点N1的电压为高电平且第二时钟信号的电平为低电平情况下的电压；或者，第二节点N2的电压，例如可以保持为第一节点N1的电压为低电平、且第二时钟信号的电平为高电平的情况下的电压。
可选的，如图6～图7所示，第一控制电路3可以包括第一子控制电路31和第二子控制电路32。
示例性的，如图6～图7所示，第一子控制电路31与第一节点N1、第一电压信号端VGH、第二时钟信号端CB及第三节点N3电连接。其中，该第一子控制电路31被配置为，在第一节点N1的电压及第二时钟信号的控制下，控制第三节点N3的电压。
例如，在第一节点N1的电压为高电平的情况下，第三节点N3处于悬浮状态。此时，第一子控制电路31可以将第二时钟信号耦合至第三节点N3，第三节点N3的电压则可以与第二时钟信号的电平相同。例如，在第二时钟信号的电平为低电平的情况下，第三节点 N3的电压则为低电平；在第二时钟信号的电平为高电平的情况下，第三节点N3的电压则为高电平。
在第一节点N1的电压为低电平的情况下，第一子控制电路31可以接收并传输第一电压信号端VGH至第三节点N3，对第三节点N3进行充电，使得第三节点N3的电压为高电平。需要说明的是，在此情况下，第二时钟信号会耦合至第三节点N3，但无论第二时钟信号的电平是高电平还是低电平，第三节点N3的电压是由第一电压信号确定的。
示例性的，如图6～图7所示，第二子控制电路32与第一节点N1、第三节点N3、第一电压信号端、第二时钟信号端CB及第二节点N2电连接。其中，该第二子控制电路32被配置为，在第一节点N1的电压及第三节点N3的电压的控制下，控制第二节点N2的电压。
例如，在第一节点N1的电压为低电平的情况下，第三节点N3的电压为高电平，第二子控制电路32可以接收并传输第一电压信号端VGH至第二节点N2，对第二节点N2进行充电，使得第二节点N2的电压为高电平。
在第一节点N1的电压为高电平、且第二时钟信号的电平为低电平的情况下，第三节点N3的电压为低电平，第二子控制电路32可以接收并传输第二时钟信号至第二节点N2，对第二节点N2进行充电，使得第二节点N2的电压为低电平。
此外，在第一节点N1的电压为高电平、且第二时钟信号的电平为高电平的情况下，第二节点N2的电压可以保持不变。也即，第二节点N2的电压，例如可以保持为第一节点N1的电压为高电平且第二时钟信号的电平为低电平情况下的低电平；或者，第二节点N2的电压，例如可以保持为第一节点N1的电压为低电平、且第二时钟信号的电平为高电平的情况下的高电平。
在一些示例中，如图5～图7所示，保持电路4与第二节点N2、第一电压信号端VGH及输出信号端Gout电连接。其中，该保持电路4被配置为，在第二节点N2的电压的控制下，将第一电压信号传输至输出信号端Gout。
示例性的，在第二节点N2的电压为低电平的情况下，保持电路4可以在第二节点N2的电压的控制下导通，接收并传输第一电压信号至输出信号端Gout。
此处，在保持电路4导通的时段，输出信号端Gout可以将第一电压信号作为输出信号输出。
由上可知，在第一节点N1的电压为低电平的情况下，第二节点N2的电压为高电平；在第二节点N2的电压为低电平的情况下，第一节点N1的电压为高电平。也就是说，在输出电路2导通、并将第二时钟信号传输至输出信号端Gout的过程中，保持电路4维持为关断状态，避免将第一电压信号传输至输出信号端Gout，进而可以避免影响输出信号的准确性。在保持电路4导通、并将第一电压信号传输至输出信号端Gout的过程中，输出电路2维持为关断状态，避免将第二时钟信号传输至输出信号端Gout，进而可以避免影响输出信号的准确性。
下面以如图14所示的时序图为例，结合图5～图7所示的结构，对移位寄存器100所包括的输入电路1、输出电路2、第一控制电路3和保持电路4的驱动方法进行示意性说明。
如图14所示，移位寄存器100的工作过程包括：第一阶段S1和第二阶段S2。
在第一阶段S1中，首先第一时钟信号的电平为低电平，输入信号的电平为低电平。
响应于在第一时钟信号端CK处接收的第一时钟信号，输入电路1开启，将在输入信号端STV处接收的输入信号传输至第一节点N1，使得第一节点N1的电压为低电平。
在上述第一节点N1的电压的控制下，输出电路2导通，将在第二时钟信号端CB处接收的第二时钟信号传输至输出信号端Gout。此处，输出电路2具有电压存储功能，也即，输出电路2会对低电平的输入信号进行存储。即使输入电路1在第一阶段S1中关断，输出电路2的该功能也可以在第一阶段S1使得第一节点N1的电压保持为低电平，进而使得输出电路2在第一阶段S1保持导通状态。
在第一节点N1的电压及第二时钟信号的控制下，第一控制电路3将第一电压信号端VGH所传输的第一电压信号传输至第二节点N2，控制第二节点N2的电压。
在上述第二节点N2的电压的控制下，保持电路4关断。由于在第一阶段S1中，第一节点N1的电压保持为低电平，因此，第一控制电路3可以不受第二时钟信号的影响、持续地将第一电压信号传输至第二节点N2，使得第二节点N2的电压保持为高电平，进而使得保持电路4保持关断状态。
在此阶段中，输出信号端Gout所输出的输出信号的波形与第二时钟信号的波形相同。由于第二时钟信号先保持为高电平后跳变为低电平，因此输出信号则先保持为高电平后跳变为低电平，输出信号的波形可以如图14所示。
在第二阶段S2中，首先第一时钟信号的电平为低电平，输入信号的电平为高电平。
响应于在第一时钟信号端CK处接收的第一时钟信号，输入电路1开启，将在输入信号端STV处接收的输入信号传输至第一节点N1，使得第一节点N1的电压为高电平。
在上述第一节点N1的电压的控制下，输出电路2关断。由于输出电路2具有电压存储功能，也即，输出电路2会对高电平的输入信号进行存储。即使输入电路1在第二阶段S1中关断，输出电路2的该功能也可以在第二阶段S1使得第一节点N1的电压保持为高电平，进而使得输出电路2在第二阶段S1保持关断状态。
在第一节点N1的电压及第二时钟信号的控制下，第一控制电路3将第二时钟信号传输至第二节点N2，控制第二节点N2的电压。
在上述第二节点N2的电压的控制下，保持电路4开启，将第一电压信号传输至输出信号端Gout。由于在第二阶段S2中，第一节点N1的电压保持为高电平，因此，第二节点N2的电压则会受到第二时钟信号的影响而发生变化。例如，在第二时钟信号的电平跳变为低电平的情况下，第二节点N2的电压则可以在第二时钟信号的作用下变为低电平。
在此阶段中，输出信号端Gout所输出的输出信号的波形与第一电压信号的波形相同。也即，输出信号的电平保持为高电平，输出信号的波形可以如图14所示。
需要说明的是，输出信号的低电平部分可以称为工作电平，用于开启相应像素驱动电路中的部分晶体管；输出信号的高电平部分可以称为非工作电平，用于关断相应像素驱动电路中的部分晶体管。通过将移位寄存器100与相应子像素P中的像素驱动电路电连接，便可以利用移位寄存器100向该相应子像素P中的像素驱动电路提供所需的工作时序，驱动该相应子像素P进行显示。
由此，本公开的一些实施例所提供的移位寄存器100，通过设置输入电路1、输出电路2、第一控制电路3和保持电路4，并将输入电路1、输出电路2、第一控制电路3和保持电路4分别与相应的信号端电连接，可以利用各信号端之间的相互配合，使得输出电路2和保持电路4在不同的时段导通，并使得输出电路2所输出的第二时钟信号和保持电路 4所输出的第一电压信号共同构成输出信号。该输出信号能够用于驱动相应子像素P进行显示。
本公开的一些实施例所提供的移位寄存器100结构较为简单，这样有利于提高移位寄存器100的制备良率，减少移位寄存器100在显示面板PNL中的占用面积。在将该移位寄存器100设置在边框区B内的情况下，有利于减小边框区B的尺寸，进而有利于实现窄边框设计。
在一些实施例中，上述第一时钟信号和第二时钟信号互为反相信号。
示例性的，此处的“反相信号”指的是，在某一时间段内，第一时钟信号的电平和第二电压信号的电平保持不变，且在第一时钟信号的电平为高电平的情况下，第二时钟信号的电平为低电平，在第一时钟信号的电平为低电平的情况下，第二时钟信号的电平为高电平。
上述反相信号可以有多种设置方式，具体可以根据实际需要选择设置，本公开对此不作限定。
示例性的，在某一时间段内，在第一时钟信号的电平由高电平跳变为低电平的同时，第二时钟信号的电平由低电平跳变为高电平。在第一时钟信号的电平由低电平跳变为高电平的同时，第二时钟信号的电平由高电平跳变为低电平。
示例性的，如图14所示，第一时钟信号的电平和第二时钟信号的电平未同时发生变化。
例如，在第一时钟信号的电平由高电平跳变为低电平之前，第二时钟信号已经由低电平跳变为高点平。
需要说明的是，在移位寄存器100进行驱动的过程中，考虑到较多不可控的因素(例如晶体管的老化或负载不同等)，第一时钟信号的波形和第二时钟信号的波形，可以设置为如图14所示的波形。
本公开以第一时钟信号的波形和第二时钟信号的波形为图14所示的波形为例进行示意性说明。
通过将第一时钟信号和第二时钟信号设置为反相信号，不仅便于对时钟信号进行控制，还有利于减少第一时钟信号端CK和第二时钟信号端CB的设置数量，简化移位寄存器100的结构，简化该移位寄存器100所应用的扫描驱动电路1000的结构，进而有利于实现窄边框设计。
下面结合图7，对输入电路1、输出电路2、第一控制电路3和保持电路4的结构进行示意性说明。
在一些示例中，如图7所示，输入电路1包括：第一晶体管T1。
示例性的，如图7所示，上述第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与输入信号端STV电连接，第一晶体管T1的第二极与第一节点N1电连接。
例如，在第一时钟信号的电平为低电平的情况下，第一晶体管T1可以在该第一时钟信号的控制下导通，接收并传输输入信号至第一节点N1，对第一节点N1进行充电。其中，在输入信号的电平为低电平的情况下，第一节点N1的电压则为低电平；在输入信号的电平为高电平的情况下，第一节点N1的电压则为高电平。
在一些示例中，如图7所示，输出电路2包括：第二晶体管T2和第一电容器C1。
示例性的，如图7所示，第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第二时钟信号端CB电连接，第二晶体管T2的第二极与输出信号端Gout电连接。
例如，在第一节点N1的电压为低电平的情况下，第二晶体管T2可以在该第一节点N1的电压的控制下导通，接收并传输第二时钟信号至输出信号端Gout。
示例性的，如图7所示，第一电容器C1的第一端与第一节点N1电连接，第一电容器C1的第二端与输出信号端Gout电连接。
例如，在第一晶体管T1导通、并将输入信号传输至第一节点N1的过程中，还可以对第一电容器C1进行充电。在第一晶体管T1关断的情况下，第一电容器C1可以进行放电，维持第一节点N1的电压。
可选的，在第一晶体管T1关断后，第一电容器C1可以进行放电，使得第一节点N1的电压维持为低电平，进而使得第二晶体管T2保持导通状态，持续接收并传输第二时钟信号至输出信号端Gout。
在一些示例中，如图7所示，第一子控制电路31包括：第三晶体管T3和第二电容器C2。
示例性的，如图7所示，第三晶体管T3的控制极与第一节点N1电连接，第三晶体管T3的第一极与第一电压信号端VGH电连接，第三晶体管T3的第二极与第三节点N3电连接。第二电容器C2的第一端与第二时钟信号端CB电连接，第二电容器C2的第二端与第三节点N3电连接。
例如，在第一节点N1的电压为高电平的情况下，第三晶体管T3可以在该第一节点N1的电压的控制下关断。此时，第三节点N3处于悬浮状态。第二电容器C2可以将第二时钟信号耦合至第三节点N3。在第二时钟信号的电平为高电平的情况下，第三节点N3的电压则为高电平，在第二时钟信号的电平为低电平的情况下，第三节点N3的电压则为低电平。
在第一节点N1的电压为低电平的情况下，第三晶体管T3可以在该第一节点N1的电压的控制下导通，接收并传输第一电压信号至第三节点N3，对第三节点N3进行充电，使得第三节点N3的电压升高。在此情况下，第二时钟信号仍会通过第二电容器C2耦合至第三节点N3，但无论第二时钟信号的电平是高电平还是低电平，第三节点N3的电压是由第一电压信号控制的。
在一些示例中，如图7所示，第二子控制电路32包括：第四晶体管T4和第五晶体管T5。
示例性的，如图7所示，第四晶体管T4的控制极与第一节点N1电连接，第四晶体管T4的第一极与第一电压信号端VGH电连接，第四晶体管T4的第二极与第二节点N2电连接。
例如，在第一节点N1的电压为低电平的情况下，第四晶体管T4可以在该第一节点N1的电压的控制下导通，接收并传输第一电压信号至第二节点N2，对第二节点N2进行充电，使得第二节点N2的电压升高。
示例性的，如图7所示，第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CB电连接，第五晶体管T5的第二极与第二节点N2电连接。
例如，在第三节点N3的电压为低电平的情况下，第五晶体管T5可以在该第三节点N3的电压的控制下导通，接收并传输第二时钟信号至第二节点N2，对第二节点N2进行充电。
这也就是说，在第一节点N1的电压为低电平的情况下，第三晶体管T3和第四晶体管T4可以在第一节点N1的电压的控制下导通，第三晶体管T3可以接收并传输第一电压信号至第三节点N3，使得第五晶体管T5关断，第四晶体管T4可以接收并传输第一电压信号至第二节点N2，使得第二节点N2的电压为高电平。
在第一节点N1的电压为高电平的情况下，第三晶体管T3和第四晶体管T4可以在第一节点N1的电压的控制下关断。在第二时钟信号的电平为低电平的情况下，第二电容器C2可以将第二时钟信号耦合至第三节点N3，使得第五晶体管T5导通。第五晶体管T5可以接收并传输第二时钟信号至第二节点N2，使得第二节点N2的电压为低电平。
在一些示例中，如图7所示，保持电路4包括：第六晶体管T6和第三电容器C3。
示例性的，如图7所示，第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电压信号端VGH电连接，第六晶体管T6的第二极与输出信号端Gout电连接。
例如，在第二节点N2的电压为低电平的情况下，第六晶体管T6可以在该第二节点N2的电压的控制下导通，接收并传输第一电压信号至输出信号端Gout。
示例性的，如图7所示，第三电容器C3的第一端与第二节点N2电连接，第三电容器C3的第二端与第一电压信号端VGH电连接。
例如，在第五晶体管T5导通、并将第二时钟信号传输至第二节点N2的过程中，还可以对第三电容器C3进行充电。在第五晶体管T5关断的情况下，第三电容器C3可以进行放电，维持第二节点N2的电压。
可选的，在第五晶体管T5关断后，第三电容器C3可以进行放电，使得第二节点N2的电压维持为低电平，进而使得第六晶体管T6保持导通状态，持续接收并传输第一电压信号至输出信号端Gout。
在相关技术中，如图1所示，移位寄存器包括两个D触发器。第一个D触发器包括第一传输门TG1、第一与非门Nand1、第一反相器INV1和第二传输门TG2。第二个D触发器包括第三传输门TG3、第二与非门Nand2、第二反相器INV2和第四传输门TG4。其驱动方法为：在时钟信号clk的电平为低电平、反相时钟信号clkb的电平为高电平的情况下，第一个D触发器开启，上一各移位寄存器输出的信号传输至该第一个D触发器，由于第二个D触发器的第三传输门TG3处于关断状态，因此该信号不能进入第二个D触发器；在时钟信号clk的电平为高电平、反相时钟信号clkb的电平为低电平的情况下，第一个D触发器关断，并将该信号锁存，此时，第二个D触发器开启并将该信号输出。由此便实现了从前一个移位寄存器到下一个移位寄存器的移位。
由于相关技术中移位寄存器的每个D触发器都需要两个传输门、一个反相器及一个与非门，而每个移位寄存器均需要两个D触发器，这样会使得电路构成较为复杂，同时需要占据较大的排版空间，难以实现窄边框设计。
而本公开的一些实施例所提供的的移位寄存器100，包括六个晶体管和三个电容器，结构简单。这样有利于提高移位寄存器100的制备良率，减少移位寄存器100在显示面板PNL中的占用面积。在将该移位寄存器100设置在边框区B内的情况下，有利于减小边框 区B的尺寸，进而有利于实现窄边框设计。
需要说明的是，本公开所提及的“电连接”，可以指的是直接电连接，也可以指的是间接电连接，具体可以根据实际需要而定。
在一些实施例中，如图8和图9所示，移位寄存器100还可以包括：电位稳定电路5。
在一些示例中，如图8和图9所示，上述电位稳定电路5与第一节点N1、第二电压信号端VGL及第四节点N4电连接。其中，该电位稳定电路5被配置为，在第二电压信号端VGL所传输的第二电压信号的控制下，将来自第一节点N1的输入信号传输至第四节点N4，并稳定第四节点N4的电压。
基于此，上述输出电路2与第四节点N4电连接，并通过电位稳定电路5与第一节点N1电连接。也即，该输出电路2和输入电路1之间的电连接为间接电连接，两者之间通过电位稳定电路5实现电连接。该输出电路2被配置为，在第四节点N4的电压的控制下，将在第二时钟信号端CB处接收的第二时钟信号传输至输出信号端Gout。
此处，第二电压信号端VGL被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)；这里将该直流低电平信号称为第二电压信号。本文中提及的“高电平”和“低电平”是相对而言的，对“高电平”的电压值和“低电平”的电压值并不进行限定。
示例性的，第二电压信号的电平为低电平，电位稳定电路5保持导通状态。在输入电路1导通并将输入信号传输至第一节点N1的情况下，电位稳定电路5可以将该输入信号传输至第四节点N4。在传输至第四节点N4的输入信号的电平为低电平的情况下，输出电路2可以在第四节点N4的电压的控制下导通，接收并传输第二时钟信号至输出信号端Gout。
在输入电路1关断的情况下，输入电路1无信号输出。此时，第一节点N1处于悬浮状态。
需要说明的是，在输出电路2导通、且第二时钟信号的电平为低电平的情况下，第四节点N4的电压容易因第一电容器C1的自举作用而进一步降低。在第四节点N4的电压的作用下，电位稳定电路5可以关断，避免第四节点N4通过输入电路1漏电，进而可以稳定第四节点N4的电压，保证输出电路2的稳定导通状态，进而可以确保输出信号的准确性。
此外，在电位稳定电路5关断后，还可以避免第一节点N1的电压受到第四节点N4的电压变化的影响而大幅降低，进而可以避免因第一节点N1的电压大幅降低二对输入电路1(也即第一晶体管T1)及第三控制电路7(也即第九晶体管T9)的工作性能产生不良影响的情况。此处，关于第三控制电路7(也即第九晶体管T9)可以参照下文中的说明，此处不再赘述。
下面结合图9，对电位稳定电路5的结构进行示意性说明。
在一些示例中，如图9所示，电位稳定电路5包括：第七晶体管T7。
示例性的，如图9所示，第七晶体管T7的控制极与第二电压信号端VGL电连接，第七晶体管T7的第一极与第一节点N1电连接，第七晶体管T7的第二极与第四节点N4电连接。
此处，由于第七晶体管T7的控制极与第二电压信号端VGL电连接，且第二电压信号为直流低电平信号，因此第七晶体管T7处于常开状态，并将来自第一节点N1的输入信号传输至第四节点N4。
示例性的，如图9所示，在输出电路2包括第二晶体管T2的情况下，第二晶体管T2的控制极与第四节点N4电连接，并通过第七晶体管T7与第一节点N1电连接。也即，第二晶体管T2的控制极与第一节点N1之间的电连接关系为间接电连接。
通过设置第七晶体管T7，可以避免第四节点N4通过第一晶体管T1漏电，进而可以使得第四节点N4的电压较为稳定，使得第二晶体管T2具有较为稳定的导通状态。而且，还可以使得第一节点N1的电压较为可控且稳定，避免因第一节点N1的电压的大幅变化而影响第一晶体管T1和第九晶体管T9的工作性能。
在一些实施例中，如图10和图11所示，移位寄存器100还可以包括：第二控制电路6。
在一些示例中，如图10和图11所示，上述第二控制电路6与第二节点N2、第一电压信号端VGH及第一节点N1电连接。其中，该第二控制电路6被配置为，在第二节点N2的电压的控制下，将第一电压信号传输至第一节点N1。
示例性的，在第二节点N2的电压为低电平的情况下，第二控制电路6可以在第二节点N2的电压的控制下导通，接收并传输第一电压信号至第一节点N1，对第一节点N1进行充电，使得第一节点N1的电压为高电平。
通过设置第二控制电路6，可以在第二节点N2的电压为低电平的情况下，使得第一节点N1的电压为高电平，进而使得第三节点N3处于悬浮状态，使得第三节点N3的电压由低电平的第二时钟信号控制。这样可以避免出现第一子控制电路31误将高电平的第一电压信号传输至第三节点N3的情况，避免出现第二子控制电路32误将高电平的第一电压信号传输至第二节点N2的情况，有利于确保第二节点N2的电压保持为低电平状态，进而有利于确保保持电路4处于较为稳定地导通状态，确保保持电路4能够保持对高电平的第一电压信号的稳定传输，确保输出信号端Gout对高电平的输出信号的稳定输出。
下面结合图11，对第二控制电路6的结构进行示意性说明。
在一些示例中，如图11所示，第二控制电路6包括：第八晶体管T8。
示例性的，如图11所示，第八晶体管T8的控制极与第二节点N2电连接，第八晶体管T8的第一极与第一电压信号端VGH电连接，第八晶体管T8的第二极与第一节点N1电连接。
例如，在第二节点N2的电压为低电平的情况下，第八晶体管T8可以在第二节点N2的电压的控制下导通，接收并传输第一电压信号至第一节点N1，对第一节点N1进行充电，使得第一节点N1的电压为高电平。
通过设置第八晶体管T8，可以在第二节点N2的电压为低电平的情况下，使得第一节点N1的电压为高电平，进而使得第三晶体管T3和第四晶体管T4保持关断状态。这样可以避免出现因第三晶体管T3误导通而导致第五晶体管T5关断、难以将低电平的第二时钟信号传输至第二节点N2的情况，避免出现因第四晶体管T4误导通而将高电平的第一电压信号传输至第二节点N2的情况，有利于确保第二节点N2的电压保持为低电平状态，进而有利于确保第六晶体管T6处于较为稳定地导通状态，确保第六晶体管T6能够保持对高电平的第一电压信号的稳定传输，确保输出信号端Gout对高电平的输出信号的稳定输出。
在一些实施例中，如图12和图13所示，移位寄存器100还可以包括：第三控制电路7。
在一些示例中，如图12和图13所示，上述第三控制电路7与第二时钟信号端CB、 第五节点N5及第一节点N1电连接。其中，该第二控制电路6与第五节点N5电连接，并通过第三控制电路7与第一节点N1电连接。也即，第二控制电路6与第一节点N1之间的电连接关系为间接电连接，两者通过第三控制电路7实现电连接。
基于此，第二控制电路6被配置为，在第二节点N2的电压的控制下，将第一电压信号传输至第五节点N5。第三控制电路7被配置为，在第二时钟信号的控制下，将来自第五节点N5的第一电压信号传输至第一节点N1。
示例性的，在第二节点N2的电压为低电平的情况下，第二控制电路6可以在第二节点N2的电压的控制下导通，接收并传输第一电压信号至第五节点N5。在第二时钟信号的电平为低电平的情况下，第三控制电路7可以在该第二时钟信号的控制下导通，将来自第五节点N5的第一电压信号传输至第一节点N1，对第一节点N1进行充电，使得第一节点N1的电压为高电平。
也就是说，在第二节点N2的电压为低电平、且第二时钟信号的电平为低电平的情况下，第一电压信号便可以依次通过第二控制电路6和第三控制电路7传输至第一节点N1，对第一节点N1的电压进行控制，避免对第二节点N2的电压产生影响。
此外，在刚开始第一阶段S1的情况下，第二节点N2的电压由低电平跳变为高电平，而第一时钟信号的电平和输入信号的电平均跳变为低电平，输入电路1会将该输入信号传输至第一节点N1，使得第一节点N1的电压由高电平跳变为低电平。在此过程中，第一节点N1的电压可能会不稳定。
通过在第二控制电路6和第一节点N1之间设置第三控制电路7，可以在刚开始第一阶段S1的情况下，确保第三控制电路7处于关断状态，进而可以在输入电路1将输入信号传输至第一节点N1的过程中，避免第一节点N1的电压受到第一电压信号的影响，确保第一节点N1的电压是由输入信号控制的，这样有利于提高移位寄存器100整体的可靠性。
下面结合图13，对第三控制电路7的结构进行示意性说明。
在一些示例中，如图13所示，第三控制电路7包括：第九晶体管T9。
示例性的，如图13所示，第九晶体管T9的控制极与第二时钟信号端CB电连接，第九晶体管T9的第一极与第五节点N5电连接，第九晶体管T9的第二极与第一节点N1电连接。其中，在第二控制电路6包括第八晶体管T8的情况下，第八晶体管T8的第二极与第五节点N5电连接，并通过第九晶体管T9与第一节点N1电连接。也即，第八晶体管T8的第二极与第一节点N1之间的电连接关系为间接电连接。
例如，在第二节点N2的电压为低电平的情况下，第八晶体管T8可以在第二节点N2的电压的控制下导通，接收并传输第一电压信号至第五节点N5。在第二时钟信号的电平为低电平的情况下，第九晶体管T9可以在该第二时钟信号的控制下导通，将来自第五节点N5的第一电压信号传输至第一节点N1，对第一节点N1进行充电，使得第一节点N1的电压为高电平。在第一时钟信号的电平为低电平的情况下，第二时钟信号的电平为高电平，第九晶体管T9可以在该第二时钟信号的控制下关断，避免来自第五节点N5的第一电压信号传输至第一节点N1。
需要说明的是，在开始第一阶段S1之前，第二节点N2的电压为低电平，第一电压信号可以通过第八晶体管T8传输至第一节点N1，使得第一节点N1的电压为高电平。在刚开始第一阶段S1时，第一晶体管T1在低电平的第一时钟信号的控制下导通，将低电平的输入信号传输至第一节点N1。此时，第一节点N1的电压难以确定，第三晶体管T3和第 四晶体管T4的导通状态也难以确定。
通过在第八晶体管T8和第一节点N1之间设置第九晶体管T9，可以在第一晶体管T1导通时，确保第九晶体管T9处于关断状态，避免将第一电压信号传输至第一节点N1，进而可以确保第一节点N1的电压在刚开始第一阶段S1时也是由低电平的输入信号控制的，确保第三晶体管T3和第四晶体管T4处于开启状态。这样有利于提高移位寄存器100整体的可靠性。
本公开的一些实施例所提供的的移位寄存器100，仅包括九个晶体管和三个电容器，便可以实现对输出信号的输出，并且在第一阶段S1中输出信号端Gout输出低电平的第二时钟信号后，能够利用第一控制电路3、第二控制电路6和第三控制电路7对第一节点N1和第四节点N4进行复位，在第二阶段S2能够利用电容器耦合晶体管控制极的方式，控制第二节点N2的电位，使得保持电路4能够较为稳定的输出高电平的第一电压信号，有利于提高输出信号的准确性。
上述移位寄存器100结构简单，有利于提高移位寄存器100的制备良率，减少移位寄存器100在显示面板PNL中的占用面积。在将该移位寄存器100设置在边框区B内的情况下，有利于减小边框区B的尺寸，进而有利于实现窄边框设计。
本公开的一些实施例所提供的扫描驱动电路1000中，多个移位寄存器100的级联关系可以包括多种，具体可以根据实际需要选择设置。
在一些实施例中，上述多个移位寄存器100中，除最后i个移位寄存器100外，第N个移位寄存器100的输出信号端Gout与第N+i个移位寄存器100的输入信号端STV电连接。其中，N和i均为正整数，且i＜N。
也即，第N个移位寄存器100所输出的输出信号，可以作为第N+i个移位寄存器100的输入信号。
在一些示例中，如图15所示，i＝1。此时，除最后1个移位寄存器100外，每个移位寄存器100的输出信号端Gout，可以与下一个移位寄存器100的输入信号端STV电连接。也即，除最后1个移位寄存器100外，每个移位寄存器100的输出信号，可以作为下一个移位寄存器100的输入信号。
在一些示例中，i＝2。此时，除最后2个移位寄存器100外，第N个移位寄存器100的输出信号端Gout与第N+2个移位寄存器100的输入信号端STV电连接。也即，上述多个移位寄存器100可以分为两组移位寄存器。其中一组移位寄存器包括奇数个移位寄存器，每个奇数个移位寄存器输出信号端Gout可以与下一个奇数个移位寄存器100的输入信号端STV电连接；另一组移位寄存器包括偶数个移位寄存器，每个偶数个移位寄存器输出信号端Gout可以与下一个偶数个移位寄存器100的输入信号端STV电连接。
在一些实施例中，如图15所示，扫描驱动电路1000还可以包括：至少一条第一时钟信号线201和至少一条第二时钟信号线202。
在一些示例中，扫描驱动电路1000可以包括：一条第一时钟信号线201和一条第二时钟信号线202。
在另一些示例中，扫描驱动电路1000可以包括：多条第一时钟信号线201和多条第二时钟信号线202。
此处，扫描驱动电路1000所包括的第一时钟信号线201的数量和第二时钟信号线202的数量，可以根据上述多个移位寄存器100的级联关系而定。
在一些示例中，如图15所示，在i＝1的情况下，扫描驱动电路1000则可以包括一条第一时钟信号线201和一条第二时钟信号线202。
基于此，如图15所示，该第一时钟信号线201可以与第2N-1个移位寄存器100的第一时钟信号端CK及第2N个移位寄存器100的第二时钟信号端CB电连接。该第二时钟信号线202可以与第2N-1个移位寄存器100的第二时钟信号端CB及第2N个移位寄存器100的第一时钟信号端CK电连接。
其中，第2N-1个移位寄存器100可以将第一时钟信号线201所传输的时钟信号作为第一时钟信号，可以将第二时钟信号线202所传输的时钟信号作为第二时钟信号。第2N个移位寄存器100可以将第二时钟信号线202所传输的时钟信号作为第一时钟信号，可以将第一时钟信号线201所传输的时钟信号作为第二时钟信号。
在一些示例中，如图15所示，扫描驱动电路1000还可以包括：起始信号线203。
其中，在i＝1的情况下，扫描驱动电路1000中第一个移位寄存器100的输入信号端可以与起始信号线203电连接，以将起始信号线203所传输的起始信号作为输入信号。
在一些示例中，如图15所示，扫描驱动电路1000还可以包括：第一电压信号线204和第二电压信号线205。
其中，各移位寄存器100的第一电压信号端VGH可以和第一电压信号线204电连接，以接收第一电压信号。各移位寄存器100的第二电压信号端VGL可以与第二电压信号线205电连接，以接收第二电压信号。
下面结合图14和图15，对图13所示的移位寄存器100的驱动方法进行示意性说明。
图15中所示的A1、A2、A3、A4……AN-1、AN分别表示第1个移位寄存器100、第2个移位寄存器100、第3个移位寄存器100、第4个移位寄存器100……第N-1个移位寄存器100、第N个移位寄存器100。
图14中示出了图13所示的移位寄存器100工作的时序图。在图14中，N1<1>、N2<1>、N3<1>和N4<1>分别表示第一个移位寄存器100的第一节点N1、第二节点N2、第三节点N3和第四节点N4。Gout<1>表示第一个移位寄存器100的输出信号端Gout。
示例性的，针对第1个移位寄存器100(即对应显示面板PNL的第一行子像素P)的驱动方法描述如下。该驱动方法包括第一阶段S1和第二阶段S2。其中，第一阶段S2包括输入阶段S11和扫描阶段S12，第二阶段S2包括第一保持阶段S21和第二保持阶段S22。
在输入阶段S11中，输入信号的电平为低电平，第一时钟信号的电平为低电平，第二时钟信号的电平为高电平。
响应于第一时钟信号，输入电路1中的第一晶体管T1开启，将输入信号传输至第一节点N1<1>，对第一节点N1<1>进行充电，使得第一节点N1<1>的电压为低电平。
在第一节点N1<1>的电压及第二时钟信号的控制下，第一控制电路3将第一电压信号传输至第二节点N2<1>，控制第二节点N2<1>的电压。具体的，第一控制电路3中的第三晶体管T3和第四晶体管T4在第一节点N1<1>的电压的控制下导通。第三晶体管T3将第一电压信号传输至第三节点N3<1>，对第三节点N3<1>进行充电，使得第三节点N3<1>的电压为高电平，进而使得第五晶体管T5关断。第四晶体管T4将第一电压信号传输至第二节点N2<1>，对第二节点N2<1>进行充电，使得第二节点N2<1>的电压为高电平。
在第二节点N2<1>的电压的控制下，保持电路4中的第六晶体管T6关断。此时，第 一电压信号同时对第三电容器C3进行充电。
第二控制电路6中的第八晶体管T8在第二节点N2<1>的电压的控制下关断。
第三控制电路7中的第九晶体管T9在第二时钟信号的控制下关断。
电位稳定电路5中的第七晶体管T7在第二电压信号的控制下保持导通状态，进而可以将第一节点N1<1>处的输入信号传输至第四节点N4<1>，使得第四节点N4<1>的电压为低电平。此时，同时对第一电容器C1进行充电。
在第一节点N1<1>(也即第四节点N4<1>)的电压的控制下，输出电路2中的第二晶体管T2开启，将第二时钟信号传输至输出信号端Gout<1>，作为输出信号从输出信号端Gout<1>输出。在此阶段中，第二时钟信号的电平为高电平，因此，输出信号的电平为高电平。
在扫描阶段S12中，输入信号的电平为高电平，第一时钟信号的电平为高电平，第二时钟信号的电平为低电平。
响应于第一时钟信号，输入电路1中的第一晶体管T1关断。第一节点N1<1>无放电路径，因此，第一节点N1<1>的电压基本保持不变，也即，第一节点N1<1>的电压保持为低电平。
在第一节点N1<1>的电压及第二时钟信号的控制下，第一控制电路3将第一电压信号传输至第二节点N2<1>，控制第二节点N2<1>的电压。具体的，第一控制电路3中的第三晶体管T3和第四晶体管T4在第一节点N1<1>的电压的控制下保持导通状态。第三节点N3<1>的电压仍为高电平，第五晶体管T5保持关断状态。第二节点N2<1>的电压仍为高电平，在该第二节点N2<1>的电压的控制下，保持电路4中的第六晶体管T6保持关断状态。此时，持续对第三电容器C3进行充电。
第二控制电路6中的第八晶体管T8在第二节点N2<1>的电压的控制下保持关断状态。
第三控制电路7中的第九晶体管T9在第二时钟信号的控制下开启。
第一电容器C1进行放电，使得第四节点N4<1>的电压保持为低电平。输出电路2中的第二晶体管T2在第一节点N1<1>(也即第四节点N4<1>)的电压的控制下保持导通状态，持续传输第二时钟信号至输出信号端Gout<1>。在此阶段中，第二时钟信号的电平为低电平，因此，输出信号的电平为低电平。
在第一保持阶段S21中，输入信号的电平为高电平，第一时钟信号的电平先保持为高电平、后跳变为低电平，第二时钟信号的电平为高电平。
在第一时钟信号的电平跳变为低电平之前，第一节点N1<1>的电压和第四节点N4<1>的电压保持为低电平。基于此，第二节点N2<1>的电压和第三节点N3<1>的电压仍保持为高电平。输出电路2中的第二晶体管T2保持导通状态，持续传输第二时钟信号至输出信号端Gout<1>。由于第二时钟信号的电平为高电平，因此，输出信号的电平为高电平。
在第一时钟信号的电平跳变为低电平后，响应于该第一时钟信号，输入电路1中的第一晶体管T1开启，将输入信号传输至第一节点N1<1>，对第一节点N1<1>进行充电，使得第一节点N1<1>的电压为高电平。
电位稳定电路5中的第七晶体管T7在第二电压信号的控制下保持导通状态，进而可以将第一节点N1<1>处的输入信号传输至第四节点N4<1>，使得第四节点N4<1>的电压为高电平。这样也便完成了对第一节点N1<1>和第四节点N4<1>的复位。此时，同时对第一电容器C1进行充电。
在该第一节点N1<1>(也即第四节点N4<1>)的电压的控制下，输出电路2中的第二晶体管T2关断。
在第一节点N1<1>的电压及第二时钟信号的控制下，第一控制电路3将第二时钟信号传输至第二节点N2<1>，控制第二节点N2<1>的电压。具体的，第一控制电路3中的第三晶体管T3和第四晶体管T4在第一节点N1<1>的电压的控制下关断。第三节点N3<1>处于悬浮状态。由于第二时钟信号的电平为高电平，第三节点N3<1>的电压可以在第二电容器C2的耦合作用下变为高电平，进而使得第五晶体管T5保持关断状态。第三电容器C3进行放电，使得第二节点N2<1>的电压仍保持为高电平。在该第二节点N2<1>的电压的控制下，保持电路4中的第六晶体管T6保持关断状态。
第二控制电路6中的第八晶体管T8在第二节点N2<1>的电压的控制下保持关断状态。
由于移位寄存器100的输出信号端Gout<1>连接有负载(也即子像素P中的像素驱动电路)，因此，输出信号端Gout<1>输出的输出信号的电平与第一时钟信号的电平跳变之前的阶段相同，也即，输出信号端Gout<1>输出的输出信号的电平仍为高电平。
在第二保持阶段S22中，输入信号的电平为高电平，第一时钟信号的电平为高电平，第二时钟信号的电平为低电平。
响应于第一时钟信号，输入电路1中的第一晶体管T1关断。第一节点N1<1>的电压和第四节点N4<1>的电压基本保持不变，也即，第一节点N1<1>的电压和第四节点N4<1>的电压保持为高电平。输出电路2中的第二晶体管T2在第一节点N1<1>(也即第四节点N4<1>)的电压的控制下，保持关断状态。
在第一节点N1<1>的电压及第二时钟信号的控制下，第一控制电路3将第二时钟信号传输至第二节点N2<1>，控制第二节点N2<1>的电压。具体的，第一控制电路3中的第三晶体管T3和第四晶体管T4在第一节点N1<1>的电压的控制下保持关断状态，使得第三节点N3<1>保持为悬浮状态。由于第二时钟信号的电平为低电平，第三节点N3<1>的电压可以在第二电容器C2的耦合作用下变为低电平，进而使得第五晶体管T5开启。第五晶体管T5将第二时钟信号传输至第二节点N2<1>，对第二节点N2<1>进行充电，使得第二节点N2<1>的电压为低电平。
第二控制电路6中的第八晶体管T8在第二节点N2<1>的电压的控制下开启，将第一电压信号传输至第五节点N5。
第三控制电路7中的第九晶体管T9在第二时钟信号的控制下开启，将来自第五节点N5的第一电压信号传输至第一节点N1<1>，对第一节点N1<1>进行充电，使得第一节点N1<1>的电压为高电平。
在上述第二节点N2<1>的电压的控制下，保持电路4中的第六晶体管T6开启，将第一电压信号传输至输出信号端Gout<1>。输出信号端Gout<1>所输出的输出信号的电平为高电平。
需要说明的是，移位寄存器100的驱动方法中，可以包括多个依次循环进行的S21阶段和S22阶段。在此过程中，第二控制电路6中的第八晶体管T8和第三控制电路7中的第九晶体管T9保持导通状态，保持电路4中的第六晶体管T6保持导通状态，并持续地将第一电压信号传输至输出信号端Gout<1>，进而使得输出信号端Gout<1>持续输出高电平的输出信号。其中，第二时钟信号的电平每从高电平跳变为低电平，第五晶体管T5的控制极的电平则会被耦合拉低一次，第五晶体管T5也便因此开启，将第二时钟信号传输至 第二节点N2<1>，同时对第三电容器C3进行充电，以使得第二节点N2<1>的电压能够保持为低电平。在输入信号的电平跳变为低电平后，此过程便结束。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器，包括：
    输入电路，与第一时钟信号端、输入信号端及第一节点电连接；所述输入电路被配置为，在所述第一时钟信号端所传输的第一时钟信号的控制下，将在所述输入信号端处接收的输入信号传输至所述第一节点；
    输出电路，与所述第一节点、第二时钟信号端及输出信号端电连接；所述输出电路被配置为，在所述第一节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述输出信号端；
    第一控制电路，与所述第一节点、第一电压信号端、所述第二时钟信号端及第二节点电连接；所述第一控制电路被配置为，在所述第一节点的电压及所述第二时钟信号的控制下，控制所述第二节点的电压；以及，
    保持电路，与所述第二节点、所述第一电压信号端及所述输出信号端电连接；所述保持电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述输出信号端。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一控制电路包括第一子控制电路和第二子控制电路；
    所述第一子控制电路与所述第一节点、所述第一电压信号端、所述第二时钟信号端及第三节点电连接；所述第一子控制电路被配置为，在所述第一节点的电压及所述第二时钟信号的控制下，控制所述第三节点的电压；
    所述第二子控制电路与所述第一节点、所述第三节点、所述第一电压信号端、所述第二时钟信号端及所述第二节点电连接；所述第二子控制电路被配置为，在所述第一节点的电压及所述第三节点的电压的控制下，控制所述第二节点的电压。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一子控制电路包括：第三晶体管和第二电容器；
    所述第三晶体管的控制极与所述第一节点电连接，所述第三晶体管的第一极与所述第一电压信号端电连接，所述第三晶体管的第二极与所述第三节点电连接；
    所述第二电容器的第一端与所述第二时钟信号端电连接，所述第二电容器的第二端与所述第三节点电连接。
  4. 根据权利要求2所述的移位寄存器，其中，所述第二子控制电路包括：第四晶体管和第五晶体管；
    所述第四晶体管的控制极与所述第一节点电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第二节点电连接；
    所述第五晶体管的控制极与所述第三节点电连接，所述第五晶体管的第一极与所述第二时钟信号端电连接，所述第五晶体管的第二极与所述第二节点电连接。
  5. 根据权利要求1～4中任一项所述的移位寄存器，还包括：电位稳定电路；
    所述电位稳定电路与所述第一节点、第二电压信号端及第四节点电连接；所述电位稳定电路被配置为，在所述第二电压信号端所传输的第二电压信号的控制下，将来自所述第一节点的输入信号传输至所述第四节点，并稳定所述第四节点的电压；
    其中，所述输出电路与所述第四节点电连接，并通过所述电位稳定电路与所述第一节点电连接；所述输出电路被配置为，在所述第四节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述输出信号端。
  6. 根据权利要求5所述的移位寄存器，其中，所述电位稳定电路包括：第七晶体管；
    所述第七晶体管的控制极与所述第二电压信号端电连接，所述第七晶体管的第一极与所述第一节点电连接，所述第七晶体管的第二极与所述第四节点电连接。
  7. 根据权利要求1～6中任一项所述的移位寄存器，还包括：第二控制电路；
    所述第二控制电路与所述第二节点、所述第一电压信号端及所述第一节点电连接；所述第二控制电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第一节点。
  8. 根据权利要求7所述的移位寄存器，其中，所述第二控制电路包括：第八晶体管；
    所述第八晶体管的控制极与所述第二节点电连接，所述第八晶体管的第一极与所述第一电压信号端电连接，所述第八晶体管的第二极与所述第一节点电连接。
  9. 根据权利要求7或8所述的移位寄存器，还包括：第三控制电路；
    所述第三控制电路与所述第二时钟信号端、第五节点及所述第一节点电连接；所述第二控制电路与所述第五节点电连接，并通过所述第三控制电路与所述第一节点电连接；
    所述第二控制电路被配置为，在所述第二节点的电压的控制下，将所述第一电压信号传输至所述第五节点；
    所述第三控制电路被配置为，在所述第二时钟信号的控制下，将来自所述第五节点的第一电压信号传输至所述第一节点。
  10. 根据权利要求9所述的移位寄存器，其中，所述第三控制电路包括：第九晶体管；
    所述第九晶体管的控制极与所述第二时钟信号端电连接，所述第九晶体管的第一极与所述第五节点电连接，所述第九晶体管的第二极与所述第一节点电连接；
    在所述第二控制电路包括第八晶体管的情况下，所述第八晶体管的第二极与所述第五节点电连接，并通过所述第九晶体管与所述第一节点电连接。
  11. 根据权利要求1～10中任一项所述的移位寄存器，其中，所述输入电路包括：第一晶体管；
    所述第一晶体管的控制极与所述第一时钟信号端电连接，所述第一晶体管的第一极与所述输入信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  12. 根据权利要求1～11中任一项所述的移位寄存器，其中，所述输出电路包括：第二晶体管和第一电容器；
    所述第二晶体管的控制极与所述第一节点电连接，所述第二晶体管的第一极与所述第二时钟信号端电连接，所述第二晶体管的第二极与所述输出信号端电连接；
    所述第一电容器的第一端与所述第一节点电连接，所述第一电容器的第二端与所述输出信号端电连接；
    在所述电位稳定电路包括第七晶体管的情况下，所述第二晶体管的控制极与所述第四节点电连接，并通过所述第七晶体管与所述第一节点电连接。
  13. 根据权利要求1～12中任一项所述的移位寄存器，其中，所述保持电路包括：第六晶体管和第三电容器；
    所述第六晶体管的控制极与所述第二节点电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述输出信号端电连接；
    所述第三电容器的第一端与所述第二节点电连接，所述第三电容器的第二端与所述第一电压信号端电连接。
  14. 根据权利要求1～13中任一项所述的移位寄存器，其中，所述移位寄存器所包括的多个晶体管的导通类型相同。
  15. 根据权利要求1～14中任一项所述的移位寄存器，其中，所述第一时钟信号和所述第二时钟信号互为反相信号。
  16. 一种如权利要求1～15中任一项所述的移位寄存器的驱动方法，包括：第一阶段和第二阶段；
    在所述第一阶段中，响应于在第一时钟信号端处接收的第一时钟信号，输入电路开启，将在输入信号端处接收的输入信号传输至第一节点；
    在所述第一节点的电压的控制下，输出电路导通，将在第二时钟信号端处接收的第二时钟信号传输至输出信号端；
    在所述第一节点的电压及所述第二时钟信号的控制下，第一控制电路将第一电压信号端所传输的第一电压信号传输至第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，保持电路关断；
    在所述第二阶段中，响应于在所述第一时钟信号端处接收的第一时钟信号，所述输入电路开启，将在所述输入信号端处接收的输入信号传输至所述第一节点；
    在所述第一节点的电压的控制下，所述输出电路关断；
    在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二时钟信号传输至所述第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，所述保持电路开启，将所述第一电压信号传输至所述输出信号端。
  17. 根据权利要求16所述的移位寄存器的驱动方法，其中，所述第一阶段包括输入阶段和扫描阶段；
    在所述输入阶段中，响应于所述第一时钟信号，所述输入电路开启，将所述输入信号传输至所述第一节点；
    在所述第一节点的电压的控制下，输出电路导通，将在所述第二时钟信号传输至所述输出信号端；
    在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第一电压信号传输至所述第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，所述保持电路关断；
    在所述扫描阶段中，响应于所述第一时钟信号，所述输入电路关断；
    所述第一节点的电压基本保持不变，所述输出电路在所述第一节点的电压的控制下保持导通状态，将所述第二时钟信号传输至所述输出信号端；
    在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第一电压信号传输至所述第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，所述保持电路关断；
    所述第二阶段包括：第一保持阶段和第二保持阶段；
    在所述第一保持阶段中，响应于所述第一时钟信号，所述输入电路开启，将所述输入信号传输至所述第一节点；
    在所述第一节点的电压的控制下，所述输出电路关断；
    在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二 时钟信号传输至所述第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，所述保持电路关断；
    在所述第二保持阶段中，响应于所述第一时钟信号，所述输入电路关断；
    所述第一节点的电压基本保持不变，所述输出电路在所述第一节点的电压的控制下保持关断状态；
    在所述第一节点的电压及所述第二时钟信号的控制下，所述第一控制电路将所述第二时钟信号传输至所述第二节点，控制所述第二节点的电压；
    在所述第二节点的电压的控制下，所述保持电路开启，将所述第一电压信号传输至所述输出信号端。
  18. 一种扫描驱动电路，包括：多个级联的如权利要求1～15中任一项所述的移位寄存器；
    除最后i个移位寄存器外，第N个移位寄存器的输出信号端与第N+i个移位寄存器的输入信号端电连接；其中，N和i均为正整数，且i＜N。
  19. 根据权利要求18所述的扫描驱动电路，还包括：至少一条第一时钟信号线和至少一条第二时钟信号线；
    在i＝1的情况下，
    一条第一时钟信号线与第2N-1个移位寄存器的第一时钟信号端及第2N个移位寄存器的第二时钟信号端电连接；
    一条第二时钟信号线与第2N-1个移位寄存器的第二时钟信号端及第2N个移位寄存器的第一时钟信号端电连接。
  20. 一种显示装置，包括：如权利要求18或19所述的扫描驱动电路。
PCT/CN2021/095584 2021-05-24 2021-05-24 移位寄存器及其驱动方法、扫描驱动电路、显示装置 WO2022246611A1 (zh)

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