WO2021203423A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021203423A1
WO2021203423A1 PCT/CN2020/084237 CN2020084237W WO2021203423A1 WO 2021203423 A1 WO2021203423 A1 WO 2021203423A1 CN 2020084237 W CN2020084237 W CN 2020084237W WO 2021203423 A1 WO2021203423 A1 WO 2021203423A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
insulating layer
gate
clock signal
Prior art date
Application number
PCT/CN2020/084237
Other languages
English (en)
French (fr)
Inventor
于鹏飞
白露
代洁
韩林宏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/442,793 priority Critical patent/US11688339B2/en
Priority to PCT/CN2020/084237 priority patent/WO2021203423A1/zh
Priority to EP20930514.3A priority patent/EP4134943B1/en
Priority to CN202080000514.0A priority patent/CN113785352B/zh
Publication of WO2021203423A1 publication Critical patent/WO2021203423A1/zh
Priority to US18/136,097 priority patent/US12087219B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines.
  • the gate line can be driven by a bonded integrated drive circuit.
  • the gate line driver circuit can also be directly integrated on the thin film transistor array substrate to form GOA (Gate Driver On Array) to drive the gate line .
  • a GOA including a plurality of cascaded shift register units can be used to provide switching state voltage signals (scanning signals) for multiple rows of gate lines of the pixel array, so as to control the sequential opening of multiple rows of gate lines and the data lines at the same time.
  • Data signals are provided to the pixel units of the corresponding rows in the pixel array, so as to form the gray voltages required by each gray scale of the displayed image in each pixel unit, and then display a frame of image.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, a shift register unit and a first clock signal line disposed on the base substrate, and the first clock signal line is on the substrate
  • the substrate extends in a first direction and is configured to provide a first clock signal to the shift register unit;
  • the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit;
  • the input circuit Is configured to input an input signal to the first node in response to the first clock signal;
  • the output circuit is configured to output an output signal to an output terminal;
  • the first control circuit is configured to respond to the electrical power of the first node
  • the first clock signal is leveled to control the level of the second node;
  • the output control circuit is configured to control the level of the output terminal under the control of the level of the second node;
  • the first The control circuit includes a first control transistor and a second control transistor.
  • the active layer of the first control transistor and the active layer of the second control transistor are a continuous control semiconductor layer. Extending in a first direction, the gate of the first control transistor and the gate of the second control transistor extend in a second direction different from the first direction and are arranged side by side in the first direction.
  • the included angle between the first direction and the second direction is between 70° and 90°.
  • the shift register unit further includes a voltage stabilizing circuit, the voltage stabilizing circuit is connected to the first node and the third node, and is configured to stabilize the The level of the third node; the output circuit is connected to the third node, and is configured to output the output signal to the output terminal under the control of the level of the third node.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first power line and a second power line, configured to provide a first voltage and a second voltage to the shift register unit, and the voltage stabilizing circuit includes A voltage stabilizing transistor, the second power supply line includes a protrusion protruding in the second direction, and the second pole of the second control transistor and the gate of the voltage stabilizing transistor are both connected to the second power supply line
  • the upper protrusion is connected to receive the second voltage; the first pole of the voltage stabilizing transistor is connected to the third node, and the second pole of the voltage stabilizing transistor is connected to the first node.
  • the input circuit includes an input transistor, and the active layer of the input transistor is a long strip extending along the second direction; the input transistor includes a first A gate, a second gate, and a connecting electrode connecting the first gate and the second gate, the connecting electrode including a first gate connected to the first gate extending along the first direction Part and a second part connected to the second gate, and a third part extending in the second direction and connecting the first part and the second part, and the third part of the connecting electrode is connected to the
  • the first clock signal line is connected to receive the first clock signal.
  • the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the input transistor are in the second The directions are set side by side.
  • the active layer of the first control transistor and the active layer of the second control transistor are located along the active layer of the input transistor along the second An imaginary line extending in the direction.
  • the first electrode of the input transistor is connected to the signal input electrode through a first connection wire extending along the second direction to receive the input signal.
  • the shift register unit further includes a wire transfer electrode, and the first electrode of the input transistor is electrically connected to the first terminal of the wire transfer electrode.
  • the active layer of the wire transfer electrode and the input transistor are located in different layers, the second end of the wire transfer electrode is connected to the first end of the first connection wire, and the wire The wire transfer electrode and the first connection wire are located on different layers, the second end of the first connection wire is electrically connected to the signal input electrode, and the wire transfer electrode and the signal input electrode are located The same layer.
  • the shift register unit further includes a first insulating layer, a second insulating layer, and a third insulating layer, and the first insulating layer is located on the input transistor.
  • the second insulation layer and the third insulation layer are located between the first connection trace and the routing transfer electrode; the input transistor
  • the first pole of the trace transfer electrode is on the same layer as the trace transfer electrode, and the second end of the trace transfer electrode is connected to the first terminal through a via hole penetrating the second insulating layer and the third insulating layer.
  • the first end of the connecting wire is connected, and the second end of the first connecting wire is electrically connected to the signal input electrode through a via hole penetrating the second insulating layer and the third insulating layer.
  • the display substrate further includes a second clock signal line configured to provide a second clock signal to the shift register unit
  • the shift register unit further includes A second control circuit
  • the second control circuit is connected to the first node and the second node, and is configured to, under the control of the level of the second node and the second clock signal, control the The level of the first node is controlled.
  • the second control circuit includes a first noise reduction transistor and a second noise reduction transistor; the active layer of the first noise reduction transistor and the second noise reduction transistor
  • the active layer of the noise reduction transistor is a continuous noise reduction semiconductor layer, the noise reduction semiconductor layer extends along the first direction and is arranged side by side with the active layer of the input transistor in the first direction,
  • the gate of the first noise reduction transistor and the gate of the second noise reduction transistor extend along the second direction and are arranged side by side in the first direction; the first electrode of the input transistor is connected to the At the first node, the gate of the first noise reduction transistor is connected to the second node.
  • the active layer of the input transistor is located along the active layer of the first noise reduction transistor and the active layer of the second noise reduction transistor.
  • the orthographic projection of the active layer of the voltage stabilizing transistor on the base substrate is One of the orthographic projection of the active layer of the second control transistor on the base substrate in the first direction and the orthographic projection of the active layer of the second noise reduction transistor on the base substrate between.
  • the gate of the second noise reduction transistor is electrically connected to the second clock signal line through a third connection wiring
  • the third connection wiring includes A third sub-connection trace and a fourth sub-connection trace
  • the third sub-connection trace is connected to the gate of the second noise reduction transistor and extends along the first direction
  • the third sub-connection The orthographic projection of the trace on the base substrate and the orthographic projection of the active layer of the second noise reduction transistor on the base substrate are arranged side by side in the second direction
  • the fourth sub-connector Line is connected to the third sub-connection trace and the second clock signal line and extends along the second direction
  • the orthographic projection of the fourth sub-connection trace on the base substrate is located in the first
  • the orthographic projection of the active layer of the second noise reduction transistor on the base substrate is away from the side of the orthographic projection of the active layer of the first noise reduction transistor on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a fourth connection trace, a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer is located at the active portion of the input transistor. Layer and the gate of the input transistor, the second insulating layer and the third insulating layer are located between the gate of the input transistor and the fourth connection trace; the third sub-connection The trace and the fourth sub-connection trace are integrally formed, and the third sub-connection trace passes through the fourth connection trace through the via hole penetrating the second insulation layer and the third insulation layer connect.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a fourth connection trace, a first insulating layer, a second insulating layer, and a third insulating layer.
  • the first insulating layer is located at the active portion of the input transistor.
  • Layer and the gate of the input transistor, the second insulating layer and the third insulating layer are located between the gate of the input transistor and the fourth connection trace; the third sub-connection The trace is connected to the fourth connection trace through the via hole penetrating the second insulation layer and the third insulation layer, and the fourth sub-connection trace is connected to the fourth connection trace by penetrating the second insulation layer and the third insulation layer.
  • the via hole of the third insulating layer is connected to the fourth connection trace.
  • the shift register unit further includes an intermediate transfer electrode, and the active layer of the first control transistor and the active layer of the second control transistor are connected to each other.
  • the active layer of the first noise reduction transistor and the active layer of the second noise reduction transistor are arranged side by side in the second direction, and the orthographic projection of the intermediate transfer electrode on the base substrate is located at the The orthographic projection of the active layer of the first control transistor and the active layer of the second control transistor on the base substrate and the active layer of the first noise reduction transistor and the second noise reduction transistor
  • the active layer is between the orthographic projections on the base substrate, and the gate of the first noise reduction transistor is connected to the first electrode of the first control transistor and the first electrode of the first control transistor through the intermediate transfer electrode.
  • the second node includes the intermediate transfer electrode.
  • the shift register unit further includes a first insulating layer and a second insulating layer, and the first insulating layer is in a direction perpendicular to the base substrate.
  • the second insulating layer is located in the first noise reduction transistor in a direction perpendicular to the base substrate.
  • the gate of the first noise reduction transistor is connected to the first end of the intermediate transfer electrode through a via hole penetrating the second insulating layer, the The first electrode of the first control transistor and the first electrode of the second control transistor are connected to the second end of the intermediate transfer electrode through a via hole penetrating the first insulating layer and the second insulating layer.
  • the second node includes the intermediate transfer electrode.
  • the shift register unit further includes a first insulating layer, a second insulating layer, a third insulating layer, and a second connecting wire, and the first insulating layer Located between the active layer of the first noise reduction transistor and the gate of the first noise reduction transistor in a direction perpendicular to the base substrate; the second insulating layer is perpendicular to the substrate The direction of the substrate is located between the gate of the first noise reduction transistor and the intermediate transfer electrode; the third insulating layer is located between the intermediate transfer electrode and the intermediate transfer electrode in the direction perpendicular to the base substrate.
  • the second connection trace includes a first sub-connection trace and a second sub-connection trace; the gate of the first noise reduction transistor passes through the second insulating layer
  • the via hole with the third insulating layer is connected to the first sub-connection trace, and the first end of the intermediate transfer electrode is connected to the first sub-connection through the via hole penetrating the third insulating layer Line connection, the first electrode of the first control transistor and the first electrode of the second control transistor are connected to the second sub-connection line and are located on the same layer, and the second end of the intermediate transfer electrode passes The via hole penetrating the third insulating layer is connected to the second sub-connection trace.
  • the second node includes the intermediate transfer electrode and the second connection trace.
  • the first electrode of the input transistor is connected to the signal input electrode to receive the input signal
  • the output control circuit includes an output control transistor and a first capacitor, wherein ,
  • the first pole and the second pole of the first capacitor include notches, and the orthographic projection of the signal input electrode on the base substrate falls within the orthographic projection of the first capacitor on the base substrate In the gap.
  • the output circuit includes an output transistor and a second capacitor, the first pole of the output transistor is connected to the fourth connection line, and the fourth connection
  • the trace is connected to the second clock signal line through the third connection trace, and the orthographic projection of the third sub-connection trace of the third connection trace on the base substrate is located in the second drop.
  • the orthographic projection of the active layer of the noise transistor on the base substrate is close to the side of the orthographic projection of the active layer of the output transistor on the base substrate.
  • the shape of the second capacitor is a rectangle.
  • the output control circuit when the output control circuit includes an output control transistor and a first capacitor, the output control transistor active layer and the output transistor active layer Are arranged integrally and extend along the first direction, the gate of the output control transistor and the gate of the output transistor extend along the second direction and are arranged side by side in the first direction, on the display substrate
  • the first pole of the output control transistor is electrically connected to the first power line to receive the first voltage.
  • the second electrode of the output transistor is connected to the signal input electrode of the lower-stage shift register unit adjacent to the shift register unit.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first power line, a second power line, a second clock signal line, a pixel array area, and a peripheral area.
  • the first power line and the second power source The line is configured to provide a first voltage and a second voltage to the shift register unit, the second clock signal line is configured to provide a second clock signal to the shift register unit, the first power line, The second power line, the first clock signal line, the second clock signal line, and the shift register unit are located in the peripheral area; the second power line, the first clock signal line And the orthographic projection of the second clock signal line on the base substrate is located on the side of the shift register unit on the base substrate away from the pixel array area; the first power supply The orthographic projection of the line on the base substrate is located on the side of the orthographic projection of the shift register unit on the base substrate close to the pixel array area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first power line, a second control circuit, a voltage stabilizing circuit, a first switching electrode, a second switching electrode, and a third switching electrode;
  • the first power line is configured to provide a first voltage to the shift register unit;
  • the second control circuit is connected to the first node and the second node, and is configured to be at the level of the second node and Controlling the level of the first node under the control of the second clock signal;
  • the voltage stabilizing circuit is connected to the first node and the third node, and is configured to stabilize the level of the third node;
  • the input circuit includes an input transistor, the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, the voltage stabilizing circuit includes a voltage stabilizing transistor, and the output control circuit includes an output control transistor and a first capacitor ,
  • the output circuit includes an output transistor and a second capacitor; the first switching electrode and the first electrode of the input transistor, the gate of the first control transistor, the
  • the first node includes the first transition electrode
  • the third node includes the second transition electrode
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate provided by any embodiment of the present disclosure.
  • the display device is an organic light emitting diode display device.
  • the display device provided by at least one embodiment of the present disclosure further includes pixel units arranged in an array, wherein the output signal output by the output circuit of the shift register unit is used as a gate scan signal to drive the pixel unit to emit light.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: providing the base substrate; forming a shift register unit, a first power line, a second power line, and a shift register unit on the base substrate.
  • the first clock signal line and the second clock signal line, forming the shift register unit includes: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, and a second conductive layer in a direction perpendicular to the base substrate.
  • the insulating layer, the second conductive layer, the third insulating layer, and the third conductive layer; the active layer of each transistor is located in the semiconductor layer, and the gate of each transistor and the first electrode of each capacitor are located in the first conductive layer.
  • the second pole of each capacitor is located on the second conductive layer, the first power line, the second power line, the first clock signal line, the second clock signal line and the The first electrode and the second electrode of each transistor are located in the third conductive layer; each transistor and each capacitor pass through the first insulating layer, the second insulating layer, or the third insulating layer.
  • the vias are connected to each other and to the first power line, the second power line, the first clock signal line, and the second clock signal line.
  • FIG. 1A is a schematic diagram of the overall circuit structure of a display panel
  • Figure 1B is a circuit diagram of a shift register unit
  • FIG. 1C is a signal timing diagram of the shift register unit shown in FIG. 1B during operation;
  • FIG. 1D is a schematic diagram of the layout of the shift register unit shown in FIG. 1B on the display substrate;
  • FIG. 2A is a schematic diagram of a layout of a display substrate provided by at least one embodiment of the present disclosure
  • 2B is a schematic diagram of the layout of another display substrate provided by at least one embodiment of the present disclosure.
  • 3A, 4A, 5A, and 6A respectively show plan views of the wiring of each layer of the shift register unit of the display substrate shown in FIG. 2A;
  • FIG. 3B, FIG. 4B, FIG. 5B, and FIG. 6B respectively show plan views of each layer wiring of the shift register unit of the display substrate shown in FIG. 2B;
  • 5C is a plan view of the vias between the wirings of each layer of the shift register unit of the display substrate shown in FIG. 2A;
  • 5D is a plan view of the vias between the wirings of each layer of the shift register unit of the display substrate shown in FIG. 2B;
  • FIG. 7A is a cross-sectional view of an example of the display substrate shown in FIG. 2A;
  • FIG. 7B is a cross-sectional view of some examples of the display substrate shown in FIG. 2A along the A-A' direction;
  • 7C is a cross-sectional view of some examples of the display substrate shown in FIG. 2B along the B-B' direction;
  • FIG. 7D is a cross-sectional view of some examples of the display substrate shown in FIG. 2A along the direction C-C';
  • Fig. 7E is a cross-sectional view of some examples of the display substrate shown in Fig. 2B along the D-D' direction;
  • FIG. 8 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a manufacturing method of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 1A is a schematic diagram of the overall circuit structure of a display panel.
  • 101 represents the overall outer frame of the display panel;
  • the display panel includes an effective display area (ie, pixel array area) 102 and a peripheral area located around the effective display area 102, the effective display area including an array arrangement
  • the peripheral area includes a shift register unit 104, a plurality of cascaded shift register units 104 form a gate drive circuit for the pixel units arranged in an array in the effective display area 102 of the display panel 101 103 provides, for example, a gate scan signal shifted row by row;
  • the peripheral area also includes a light-emitting control unit 105, a plurality of cascaded light-emitting control units 105 form a light-emitting control array, which is used to provide the effective display area 102 of the display panel 101
  • the pixel units 103 arranged in an array provide, for example, a light emission control signal shifted row by row.
  • each pixel unit 103 may include pixel circuits and light-emitting elements having circuit structures such as 7T1C, 8T2C, or 4T1C in the art.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • FIG. 1B is a circuit structure diagram of a shift register unit.
  • FIG. 1C is a signal timing diagram of the shift register unit shown in FIG. 1B during operation. The working process of the shift register unit will be briefly introduced below in conjunction with FIG. 1B and FIG. 1C.
  • the shift register unit 104 includes 8 transistors (input transistor T1, first control transistor T2, second control transistor T3, output control transistor T4, output transistor T5, first noise reduction transistor T6, Two noise reduction transistors T7 and a voltage stabilizing transistor T8) and two capacitors (the first capacitor C1 and the second capacitor C2).
  • the first pole of the input transistor T1 in the first-stage shift register unit 104 is connected to the input terminal IN, and the input terminal IN is configured to be connected to the trigger signal line GSTV to The trigger signal is received as an input signal, and the first pole of the input transistor T1 in the shift register unit 104 of other stages is electrically connected to the output terminal of the shift register unit 104 of the previous stage to receive the shift register unit 104 of the previous stage.
  • the output signal output by the output terminal GOUT is used as an input signal, thereby realizing a shifted output for performing, for example, progressive scanning on the array of pixel units in the active display area.
  • the shift register unit further includes a first clock signal terminal CK and a second clock signal terminal CB.
  • GCK represents the first sub-clock signal line
  • GCB represents the second sub-clock signal line, for example, when When the first clock signal terminal CK is connected to the first sub-clock signal line GCK to receive the first clock signal, the first sub-clock signal line GCK is the first clock signal line, and when the first clock signal terminal CK and the second sub-clock signal When the line GCB is connected to receive the first clock signal, the second sub-clock signal line GCB is the first clock signal line, which may be determined according to specific conditions, which is not limited in the embodiment of the present disclosure.
  • the second clock signal terminal CB is connected to the second sub-clock signal line GCB or the first sub-clock signal line GCK to receive the second clock signal.
  • the first clock signal terminal CK is connected to the first sub-clock signal line GCK to receive the first clock signal
  • the second clock signal terminal CB is connected to the second sub-clock signal line GCB to receive the second clock signal as an example. That is, the first sub-clock signal line GCK is used as the first clock signal line and the second sub-clock signal line GCB is used as the second clock signal line as an example for description, which is not limited in the embodiment of the present disclosure.
  • the first clock signal GCK and the second clock signal GCB may use pulse signals with a duty cycle greater than 50%, and the difference between the two is, for example, half a period;
  • VGH represents the first power line and the first voltage provided by the first power line
  • the first voltage is a DC high level
  • VGL represents the second power line and the second voltage provided by the second power line, for example, the second voltage is a DC low level
  • the first voltage is greater than the second voltage;
  • N1 , N2 and N3 respectively represent the first node, the second node and the third node in the circuit diagram.
  • the gate of the input transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first sub-clock signal line GCK) to receive the first clock signal, and the second clock signal terminal CK of the input transistor T1
  • the pole is connected to the input terminal IN, and the first pole of the input transistor T1 is connected to the first node N1.
  • the input terminal IN is connected to the trigger signal line GSTV to receive the trigger signal
  • the shift register unit is other than the first-stage shift register In the case of a stage shift register unit, the input terminal IN is connected to the output terminal GOUT of the upper stage shift register unit.
  • the gate of the first control transistor T2 is connected to the first node N1, the second electrode of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, and the first electrode of the first control transistor T2 is connected to the first node N1. Two nodes N2 are connected.
  • the gate of the second control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, and the second electrode of the second control transistor is connected to the second power line VGL to receive the second voltage.
  • the first pole is connected to the second node N2.
  • the gate of the output control transistor T4 is connected to the second node N2, the first electrode of the output control transistor T4 is connected to the first power line VGH to receive the first voltage, and the second electrode of the output control transistor T4 is connected to the output terminal GOUT.
  • the first pole of the first capacitor is connected to the second node N2, and the second pole of the first capacitor C1 is connected to the first power line VGH.
  • the gate of the output transistor T5 is connected to the third node N3, the first electrode of the output transistor T5 is connected to the second clock signal terminal CB, and the second electrode of the output transistor T5 is connected to the output terminal GOUT.
  • the first pole of the second capacitor C2 is connected to the third node N3, and the second pole of the second capacitor C2 is connected to the output terminal GOUT.
  • the gate of the first noise reduction transistor T6 is connected to the second node N2, the first electrode of the first noise reduction transistor T6 is connected to the first power supply line VGH to receive the first voltage, and the second electrode of the first noise reduction transistor T6 is connected to The second pole of the second noise reduction transistor T7 is connected.
  • the gate of the second noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second sub-clock signal line GCB) to receive the second clock signal.
  • the first noise reduction transistor T7 The pole is connected to the first node N1.
  • the gate of the voltage stabilizing transistor T8 is connected to the second power line VGL to receive the second voltage, the second electrode of the voltage stabilizing transistor T8 is connected to the first node N1, and the first electrode of the voltage stabilizing transistor T8 is connected to the third node N3.
  • the transistors in the shift register unit 104 shown in FIG. 1B are all described by using P-type transistors as an example. Cut off at high level (cutoff level). At this time, the first electrode of the transistor may be the source, and the second electrode of the transistor may be the drain.
  • the shift register unit includes, but is not limited to, the configuration of FIG. 1B.
  • each transistor in the shift register unit 104 can also adopt N-type transistors or a mixture of P-type transistors and N-type transistors.
  • the port polarity of the transistor can be connected according to the port polarity of the corresponding transistor in the embodiment of the present disclosure.
  • the transistors used in the shift register unit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as an example for description.
  • the active layer uses semiconductor materials, such as polysilicon (such as low-temperature polysilicon or high-temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc.
  • the gate, source, and drain are made of metal materials, such as metal aluminum Or aluminum alloy.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • the electrode of the capacitor may be a metal electrode or one of the electrodes may be a semiconductor material (for example, doped polysilicon).
  • FIG. 1C is a signal timing diagram of the shift register unit 104 shown in FIG. 1B during operation.
  • the working process of the shift register will be described in detail below in conjunction with Fig. 1B and Fig. 1C.
  • the working principle of the shift register unit 104 of the first stage is used for description, and the working principle of the shift register units 104 of the other stages is similar to it, and will not be repeated.
  • the working process of the shift register unit 104 includes 4 stages, namely the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4.
  • FIG. 1C shows each stage. The timing waveform of each signal in.
  • the first clock signal terminal CK receives a low-level first clock signal
  • the trigger signal line GSTV provides a low-level trigger signal
  • the input transistor T1 and the second control transistor T3 The turned-on input transistor T1 transmits the low-level trigger signal to the first node N1, so that the level of the first node N1 becomes low, so the first control transistor T2 and the output transistor T5 are turned on
  • the voltage stabilizing transistor T8 is always on in response to the second voltage (low level) provided by the second power line VGL
  • the level of the third node N3 is the same as the level of the first node N1, that is, low.
  • the low level is stored in the second capacitor C2.
  • the turned-on second control transistor T3 transmits the low-level second voltage VGL to the second node N2, and the turned-on first control transistor T2 transmits the low-level of the first clock signal to the second node N2, As a result, the level of the second node N2 becomes a low level and is stored in the first capacitor C1.
  • the output control transistor T4 is turned on in response to the low level of the second node N2, and the first power line VGH provides The high-level first voltage is output to the output terminal GOUT, and at the same time, the output transistor T5 is turned on in response to the low-level of the third node N3, and transmits the high-level second clock signal received by the second clock signal terminal CB to The output terminal GOUT, so at this stage, the shift register unit outputs a high level.
  • the second clock signal terminal CB receives a low-level second clock signal, so the second noise reduction transistor T7 is turned on, and the first clock signal terminal CK receives a high-level clock signal.
  • the first clock signal so the input transistor T1 and the second control transistor T3 are turned off. Due to the storage effect of the second capacitor C2, the first node N1 can continue to maintain the low level of the previous stage, so the first control transistor T2 and the output transistor T5 are turned on. Since the first control transistor T2 is turned on, the high-level first clock signal received by the first clock signal terminal CK is transmitted to the second node N2. Therefore, the second node N2 becomes a high level.
  • the first The noise reduction transistor T6 and the output control transistor T4 are turned off, thereby preventing the high level provided by the first power line VGH from being output to the output terminal GOUT and the first node N1.
  • the output transistor T5 since the output transistor T5 is turned on, at this stage, the output terminal GOUT outputs the low level received by the second clock signal terminal GB, for example, the low level is used to control the operation of the pixel unit 103 shown in FIG. 1A .
  • the first clock signal terminal CK receives the low-level first clock signal, so the input transistor T1 and the second control transistor T3 are turned on.
  • the trigger signal line GSTV provides The high level of is transmitted to the first node N1 and the third node N3, so the output transistor T5 and the first control transistor T2 are turned off.
  • the second clock signal terminal CB receives a high-level second clock signal, so the second noise reduction transistor T7 is turned off. Since the second control transistor T3 is turned on, the low level provided by the second power line VGL is transmitted to the second node N2 and stored in the first capacitor C1. Therefore, the output control transistor T4 and the first noise reduction transistor T6 are turned on Therefore, at this stage, the output terminal GOUT outputs the high level provided by the first power line VGH.
  • the first clock signal terminal CK receives a high-level first clock signal, so the input transistor T1 and the second control transistor T3 are turned off.
  • the second clock signal terminal CB receives a low-level second clock signal, so the second noise reduction transistor T7 is turned on. Due to the storage effect of the second capacitor C2, the level of the first node N1 maintains the high level of the previous stage, so that the first control transistor T2 and the output transistor T5 are turned off.
  • the second node N2 continues to maintain the low level of the previous stage, so that the first noise reduction transistor T6 is turned on, so that the high level provided by the first power line VGH is turned on
  • the first noise reduction transistor T6 and the second noise reduction transistor T7 are transmitted to the first node N1 and the third node N3, so that the first node N1 and the third node N3 continue to maintain a high level, effectively preventing the output Transistor T5 is turned on, thereby avoiding false output.
  • FIG. 1D is a schematic diagram of a layout of the shift register unit 104 shown in FIG. 1B on the display substrate.
  • the display substrate includes the input transistor T1 to the voltage stabilizing transistor T8 of the shift register unit 104, the first capacitor C1 to the second capacitor C2, the first sub-clock signal line GCK, and the second sub-clock signal line GCB. , The first power line VGH and the second power line VGL.
  • the input transistor T1 includes a "U"-shaped active layer and a linear (I-type) gate, which overlaps the arms of the "U"-shaped active layer.
  • double-gate transistors are realized, and they are arranged horizontally with the first noise reduction transistor T6 and the second noise reduction transistor T7, so that the arrangement takes up a lot of space regardless of whether it is in the horizontal direction or the vertical direction of the display panel.
  • the gate of the voltage stabilizing transistor T8 and the first pole of the second control transistor T3 are far apart, and are respectively connected to different positions of the second power line VGL, increasing the wiring complexity; the first control transistor T2 and The node between the second control transistor T3 is connected to the gate of the first noise reduction transistor T6 through a very long connecting wire, which causes space congestion and so on. Therefore, the arrangement and connection of the various transistors on the display substrate shown in FIG. 1D are likely to cause space congestion, which is not conducive to the realization of the narrow frame design of the display panel, and it is easy to generate signals due to unnecessary overlap and excessive parasitic capacitance. Problems such as interference affect the display quality of the display panel.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, a shift register unit and a first clock signal line disposed on the base substrate, the first clock signal line is along a first direction on the base substrate Extended and configured to provide a first clock signal to the shift register unit;
  • the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit;
  • the input circuit is configured to input the input signal in response to the first clock signal To the first node;
  • the output circuit is configured to output the output signal to the output terminal;
  • the first control circuit is configured to control the level of the second node in response to the level of the first node and the first clock signal;
  • the output control circuit is configured to Under the control of the level of the second node, the level of the output terminal is controlled;
  • the first control circuit includes a first control transistor and a second control transistor, an active layer of the first control transistor and an active layer of the second control transistor It is a continuous control semiconductor layer, the control semiconductor layer extends
  • At least one embodiment of the present disclosure also provides a display device corresponding to the above-mentioned display substrate and a manufacturing method of the display substrate.
  • the circuit connection and structural layout of the shift register unit of the display substrate provided by the above-mentioned embodiments of the present disclosure are optimized, and the length of the shift register unit in the second direction is compressed to a certain extent, which is conducive to the realization of the narrow frame design of the display panel , While ensuring the display quality of the display panel.
  • FIG. 2A is a schematic diagram of a layout of the shift register unit 104 shown in FIG. 1B on a display substrate.
  • the display substrate 1 includes: a base substrate 10 and a shift register unit 104 provided on the base substrate 10, a first power line VGH, a second power line VGL, and a plurality of clock signal lines (For example, the first sub-clock signal line GCK, the second sub-clock signal line GCB, and the trigger signal line GSTV shown in the figure).
  • the first power supply line VGH, the second power supply line VGL, and a plurality of clock signal lines extend in a first direction (for example, the vertical direction shown in FIG. 2A) on the base substrate 10, and are configured to be shifted toward
  • the register unit 104 respectively provides a first voltage, a second voltage, and a plurality of clock signals (for example, the trigger signal, the first clock signal, or the second clock signal described above).
  • first power line VGH, the second power line VGL, and a plurality of clock signal lines may be arranged in parallel along the first direction, or may cross a certain angle (for example, less than or equal to 20°).
  • a certain angle for example, less than or equal to 20°.
  • the first power line VGH is configured to provide a first voltage to the plurality of cascaded shift register units 104 included in the scan driving circuit
  • the second power line VGL is configured to provide a first voltage to the plurality of cascaded shift register units included in the scan driving circuit.
  • the register unit 104 provides the second voltage.
  • the first voltage is greater than the second voltage, for example, the first voltage is a DC high level, and the second voltage is a DC low level.
  • the base substrate 10 may be made of, for example, glass, plastic, quartz or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the display substrate 1 includes a pixel array area (ie, the effective display area 102 shown in FIG. 1A, hereinafter referred to as the pixel array area 102) and a peripheral area other than the pixel array area, for example, the above-mentioned first power supply line VGH ,
  • the second power line VGL, multiple clock signal lines and the shift register unit 104 are located in the peripheral area and on one side of the base substrate 10 (as shown in FIG. 1A, located on the side of the pixel array area 102 and the base substrate Between), for example, as shown in FIG. 1A, it is located on the left side of the base substrate, of course, it can also be located on the right or left and right sides of the base substrate 10.
  • the embodiment of the present disclosure does not limit this.
  • the second power line VGL and multiple clock signal lines are located on the side of the shift register unit 104 away from the pixel array area 102, for example, they are both located on the left side of the shift register unit 104 shown in FIG. 2A, that is, the shift register
  • the orthographic projection of the unit 104 on the base substrate 10 is located between the second power line VGL and the plurality of clock signal lines between the orthographic projection of the base substrate 10 and the pixel array area 102; for example, the first power line VGH is located in the shift register unit
  • the side 104 close to the pixel array area 102, that is, the orthographic projection of the first power line VGH on the base substrate 10 is located between the orthographic projection of the shift register unit 104 on the base substrate 10 and the pixel array area 102.
  • the pixel array area 102 includes a plurality of pixel units 103 arranged in an array.
  • each of the plurality of pixel units 103 includes a pixel circuit, for example, may further include a light-emitting element (not shown in the figure).
  • a plurality of cascaded shift register units 104 constitute a gate driving circuit.
  • the output terminals GOUT of the plurality of shift register units 104 are respectively connected to the gate scan signal terminals of each row of pixel circuits located in the pixel array area to provide output signals (for example, gate scan numbers) to the respective rows of pixel circuits, thereby Realize driving the light-emitting element to emit light.
  • the pixel circuit may be a pixel circuit including circuit structures such as 7T1C, 2T1C, 4T2C, 8T2C, etc. in the art, which will not be repeated here.
  • the first stage shift register unit 104 The clock terminal CK (as shown in FIG. 1B) is connected to the second sub-clock signal line GCB to receive the first clock signal, and the second clock signal terminal CB of the first-stage shift register unit 104 is connected to the first clock signal GCK to receive
  • the first clock signal terminal CK of the second-stage shift register unit is connected to the first sub-clock signal line GCK to receive the first clock signal
  • the second clock signal terminal CB of the second-stage shift register unit is connected to The second sub-clock signal line GCB is connected to receive the second clock signal
  • the first clock terminal CK of the X-th (X is an odd number greater than 1) stage shift register unit 104 is connected to the second sub-clock signal line GCB To receive the first clock signal, the second clock signal terminal CB of the X-th stage shift register
  • connection manner of the shift register units at various levels and the clock signal line may also adopt other connection manners in the art, which is not limited in the embodiment of the present disclosure.
  • the input terminal of the first-stage shift register unit 104 is connected to the trigger signal line GSTV to receive the trigger signal as an input signal
  • the input terminal of the second-stage shift register unit 104 is connected to the previous-stage shift register unit (that is, the first stage).
  • the output terminal GOUT of the shift register unit of the first stage is connected, and the connection mode of the shift register units of the other stages is similar.
  • the structure of the shift register unit of the first stage is taken as an example for description, which is not limited in the embodiment of the present disclosure.
  • the first clock terminal CK (as shown in FIG. 1B) of the first-stage shift register unit 104 is connected to the second sub-clock signal line GCB to receive the first clock signal
  • the second clock signal terminal CB of the first stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal. Therefore, in this example, the second sub-clock signal line GCB is used as the first clock signal line and the first clock signal line.
  • a sub-clock signal line GCK is the second clock signal line as an example for description, which is not limited in the embodiment of the present disclosure.
  • the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, and an output control circuit 1044; in other examples, the shift register unit 104 104 also includes a second control circuit 1045 and a voltage stabilizing circuit 1046.
  • the input circuit 1041 is configured to input an input signal to the first node N1 in response to the first clock signal.
  • the input circuit 1041 is connected to the input terminal IN, the first node N1, and the first clock signal terminal CK, and is configured to be turned on under the control of the first clock signal received by the first clock signal terminal CK to connect the input terminal IN with the first clock signal terminal CK.
  • a node N1 is connected to input the input signal to the first node N1.
  • the input circuit 1041 is implemented as the above-mentioned input transistor T1, and the connection mode of the input transistor T1 can refer to the above description, which will not be repeated here.
  • the output circuit 1043 is configured to output the output signal to the output terminal GOUT.
  • the output circuit 1043 is connected to the third node N3, the output terminal GOUT, and the second clock signal terminal CB, and is configured to be turned on under the control of the level of the third node N3, so that the second clock signal terminal CB and the output terminal GOUT Is connected to output the second clock signal at the output terminal GOUT, for example, outputting the low level of the second clock signal.
  • the output circuit 1043 is implemented as the above-mentioned output transistor T5 and the second capacitor C2, and the connection mode of the output transistor T5 and the second capacitor C2 can refer to the above description, which will not be repeated here.
  • the first control circuit 1042 is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal.
  • the first control circuit is connected to the first node N1, the second node N2, and the first clock signal terminal CK, and is configured to be turned on under the control of the level of the first node N1, so that the second node N2 is connected to the first clock signal terminal CK.
  • the signal terminal CK is connected to provide the first clock signal provided by the first clock signal terminal CK to the second node N2.
  • the first control circuit 1042 is implemented as the first control transistor T2 and the second control transistor T3 described above.
  • connection mode of the first control transistor T2 and the second control transistor T3 please refer to the above description, which will not be repeated here.
  • the first control circuit 1042 is not limited to be connected to the first node N1, and can also be connected to other independent voltage terminals (providing the same voltage as the first node N1) or a separately set one that is the same as the input circuit.
  • Circuit connection which is not limited in the embodiments of the present disclosure. The connections of other circuits of the shift register unit are similar to this, and will not be repeated here.
  • the output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2.
  • the output control circuit 1044 is connected to the second node N2, the first power line VGH, and the output terminal GOUT, and is configured to connect the output terminal GOUT to the first power line VGH under the control of the level of the second node N2, In this way, the first voltage provided by the first power line VGH is output to the output terminal GOUT to control the output terminal GOUT at a high level, thereby avoiding mis-output of the shift register unit in the non-output stage.
  • the output control circuit 1044 is implemented as the above-mentioned output control transistor T4 and the first capacitor C1, and the connection mode of the output control transistor T4 and the first capacitor C1 can refer to the above description, which will not be repeated here.
  • the second control circuit 1045 is connected to the first node N1 and the second node N2, and is configured to control the level of the first node N1 under the control of the level of the second node N2 and the second clock signal.
  • the second control circuit 1045 is connected to the first node N1, the second node N2, the first power line VGH, and the second clock signal terminal CB, and is configured to be at the level of the second node N2 and the second clock signal terminal CB received It is turned on under the control of the clock signal, so that the first power line VGH is connected to the first node N1, thereby charging the potential of the first node N1 to a high level, so as to prevent the output circuit 1042 from being turned on during the non-output stage, thereby avoiding mis-output .
  • the second control circuit 1045 is implemented as the first noise reduction transistor T6 and the second noise reduction transistor T7 described above, and the connection mode of the first noise reduction transistor T6 and the second noise reduction transistor T7 can refer to the above description. This will not be repeated here.
  • the voltage stabilizing circuit 1046 is connected to the first node N1 and the third node N3, and is configured to stabilize the level of the third node N3.
  • the voltage stabilizing circuit 1046 is connected to the first node N1, the third node N3, and the second power line VGL, and is configured to be turned on under the control of the second voltage provided by the second power line VGL, so that the first node N1 and The third node N3 is connected.
  • the voltage stabilizing circuit 1046 is implemented as a voltage stabilizing transistor T8.
  • the voltage stabilizing transistor T8 is always on under the control of the second voltage provided by the second power line VGL, so that the third node N3 is connected to the first node N1 through the voltage stabilizing transistor T8, thereby preventing the third node N3 from being connected to the first node N1.
  • the level of is leaked through the input transistor T1, the first control transistor T2, and the second noise reduction transistor T7 connected to the first node N1, and at the same time, the level of the third node N3 can reduce the stress on the first control transistor T1. This can help maintain the level of the third node N3, so that the output transistor T5 can be fully turned on during the output phase.
  • 3A, 4A, 5A, and 6A show plan views of the wiring of each layer of the shift register unit of the display substrate shown in Fig. 2A; Figs. 3B, 4B, 5B, and 6B show Fig. 2B, respectively Shown in is a plan view of the wiring of each layer of the shift register unit of the substrate.
  • 3A and 3B are plan views of a semiconductor layer of a display substrate provided in at least one embodiment of the present disclosure.
  • FIGS. 4A and 4B are plan views of a first conductive layer of a display substrate provided in at least one embodiment of the present disclosure.
  • FIGS. 5A and 5B are A plan view of a second conductive layer of a display substrate provided by at least one embodiment of the present disclosure.
  • FIGS. 6A and 6B are plan views of a third conductive layer of a display substrate provided by at least one embodiment of the present disclosure.
  • 7A is a cross-sectional view of an example of the display substrate shown in FIG. 2A;
  • FIG. 7B is a cross-sectional view of another example of the display substrate shown in FIG. 2A along the AA' direction;
  • FIG. 7C is a display substrate shown in FIG. 2B A cross-sectional view of an example along the BB ⁇ direction.
  • the interlayer insulating layer (for example, including the first insulating layer, the second insulating layer, the third insulating layer, etc.) may be located between the layer structures shown in FIGS. 3A to 6A or 3B to 6B.
  • the first insulating layer 350 (as shown in FIG. 7A) is located between the semiconductor layer 310 shown in FIG. 3A and the first conductive layer 320 shown in FIG. 4A or is located between the semiconductor layer 310 shown in FIG. 3B and the semiconductor layer 310 shown in FIG. 4B.
  • the second insulating layer 360 (as shown in FIG. 7A) is located between the first conductive layer 320 shown in FIG.
  • the third insulating layer 370 (as shown in FIG. 7A) is located between the second conductive layer 330 shown in FIG. 5A and the third conductive layer 330 shown in FIG. 6A. Between the conductive layers 340 or between the second conductive layer 330 shown in FIG. 5B and the third conductive layer 340 shown in FIG. 6B.
  • the display substrate further includes a fourth insulating layer 380 located on the third conductive layer 340 for protecting the third conductive layer 340.
  • the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other materials. Suitable materials are not limited in the embodiments of the present disclosure.
  • the display substrate shown in FIG. 2A takes the first two-stage shift register in the scan driving circuit and the layout design of the first power supply line, the second power supply line, and the signal line connected to it as an example for description, and the rest are
  • the layout implementation of the stage shift register can refer to the layout shown in FIG. 2A, which will not be repeated here.
  • other layouts can also be adopted, which is not limited in the embodiment of the present disclosure.
  • the shift registers of each level of the remaining scan driving circuits can also refer to the layout shown in FIG. 2A, and other layout implementations can also be adopted, which is not limited in the embodiment of the present disclosure.
  • the display substrate provided by at least one embodiment of the present disclosure will be described in detail below with reference to FIGS. 2A-7C.
  • the active layers of the input transistor T1 to the voltage stabilizing transistor T8 of the shift register unit 104 shown in FIG. 2A may be formed on the semiconductor layer 310 shown in FIG. 3A.
  • the active layers of the input transistor T1 to the voltage stabilizing transistor T8 of the shift register unit 104 shown in FIG. 2B may be formed on the semiconductor layer 310 shown in FIG. 3B.
  • the semiconductor layer 310 may be formed by patterning a semiconductor material.
  • the semiconductor layer 310 may be short rod-shaped or have a curved or bent shape as required, and may be used to fabricate the active layers of the input transistor T1 to the voltage stabilizing transistor T8.
  • Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the channel region has semiconductor characteristics; the source region and the drain region are on both sides of the channel region, and may be doped with impurities, and therefore have conductivity.
  • the source region is a part of the active layer
  • the metal electrode for example, located in the third conductive layer 340
  • the drain region is A part of the active layer
  • the metal electrode for example, located in the third conductive layer 340 in contact with the drain region corresponds to the drain (or called the second electrode) of the transistor.
  • the source region is connected to its corresponding metal electrode (first electrode) through vias that penetrate the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370, and the drain region is connected to the corresponding metal electrode (first electrode) through the first insulating layer 350,
  • the via holes of the second insulating layer 360 and the third insulating layer 370 are connected to their corresponding metal electrodes (second electrodes).
  • the active layer of the first control transistor T2 includes a source region S2, a drain region D2, and a channel region P2.
  • the first control transistor T2 also It includes a gate G2, where the gate G2 is located in the first conductive layer 320;
  • the active layer of the first noise reduction transistor T6 includes a source region S6, a drain region D6, and a trench In the track area P6, the first noise reduction transistor T6 further includes a gate G6, where the gate G6 is located on the first conductive layer 320, and other transistors are similar to this, and will not be repeated here.
  • the material of the semiconductor layer 310 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon and the like are not limited in the embodiments of the present disclosure.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • first electrode and the second electrode of each transistor can also be located in other conductive layers, and are connected to their corresponding active layers through vias in the insulating layer between them and the semiconductor layer.
  • the embodiment of the present disclosure does not limit this.
  • the first conductive layer 320 is disposed on the first insulating layer so as to be insulated from the semiconductor layer 310.
  • the first conductive layer 320 may include the first electrodes CE11 and CE12 of the first capacitor C1 to the second capacitor C2, the gates of the input transistor T1 to the voltage stabilizing transistor T8, and various traces directly connected to the gates (for example, , The first connection line L1 and the third connection line L2), the connection electrode, and the corresponding first insulating layer also serves as the gate insulating layer.
  • the gates of the input transistor T1 to the voltage stabilizing transistor T8 are the parts enclosed by dotted lines, that is, the parts where the semiconductor layer structure of each transistor overlaps the wiring on the first conductive layer 320.
  • the first conductive layer 320 may further include an intermediate transfer electrode 11.
  • the intermediate transfer electrode 11 is formed integrally with the gate G6 of the first noise reduction transistor T6.
  • the first connection trace L1 may not be located on the first conductive layer 320 shown in FIG. 4B, for example, located on the third conductive layer 340 shown in FIG. 6B, which is not limited in the embodiment of the present disclosure. , As long as the connection between the transistors can be achieved.
  • the second conductive layer 330 includes the second electrodes CE21 and CE22 of the first capacitor C1 to the second capacitor C2.
  • the second electrode CE21 and the first electrode CE11 at least partially overlap to form a first capacitor C1
  • the second electrode CE22 and the first electrode CE12 at least partially overlap to form a second capacitor C2.
  • the second conductive layer 330 shown in FIG. 5A further includes the intermediate transfer electrode 11.
  • the example shown in FIG. 5B is similar to the example shown in FIG. 5A, except that the second conductive layer 330 does not include the intermediate transfer electrode 11, that is, in the display substrate shown in FIG. 2B, the intermediate transfer electrode 11 It may not be located on the second conductive layer 330, for example, located on the first conductive layer 320 shown in FIG. 4B, which is not limited in the embodiment of the present disclosure.
  • the third conductive layer 340 includes a plurality of signal lines (for example, with the first The trigger signal line GSTV, the first sub-clock signal line GCK and the second sub-clock signal line GCB, the first power line VGH, the second power line VGL, the reference voltage line Vinit, etc. connected to the input end of the stage shift register unit 104 .
  • the third conductive layer 340 also includes a first switching electrode 17, a second switching electrode 18, a third switching electrode 16, a signal input electrode 13, and a first switching electrode 17 connecting various transistors, capacitors, and signal lines.
  • the second connecting line (including the first connecting sub-line L3 and the second connecting sub-line L4) and the fourth connecting line L5, etc.
  • a plurality of signal lines, a first power line VGH, and a second power line VGL pass through at least one via hole shown in FIG. 5C or FIG.
  • each transistor and capacitor are also connected through at least one via or bridged through a transfer electrode, which will not be repeated here.
  • the material of the third conductive layer 340 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, which is not limited in the embodiment of the present disclosure.
  • the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be repeated here.
  • FIG. 2A shows the relationship between the stacked position of the semiconductor layer 310 shown in FIG. 3A, the first conductive layer 320 shown in FIG. 4A, the second conductive layer 330 shown in FIG. 5A, and the third conductive layer 340 shown in FIG. 6A.
  • Schematic. 2B is the positional relationship between the semiconductor layer 310 shown in FIG. 3B, the first conductive layer 320 shown in FIG. 4B, the second conductive layer 330 shown in FIG. 5B, and the third conductive layer 340 shown in FIG. 6B.
  • the active layer of the input transistor T1 is a long strip extending in a second direction, and the second direction is different from the first direction.
  • the included angle between the first direction and the second direction is between 70° and 90°, and includes 70° and 90°.
  • the included angle between the first direction and the second direction is 70°, 90°, 80°, etc., which can be set according to actual conditions, and the embodiments of the present disclosure do not limit this.
  • the channel region of the active layer of the input transistor T1 has an "I" shape on the base substrate 10, and the channel length direction of the channel region is the second direction perpendicular to the first direction.
  • the direction for example, the horizontal direction in the figure
  • the embodiment of the present disclosure does not limit this, as long as the length of the display panel in the first direction can be shortened.
  • the channel length direction is the direction in which carriers flow from the first pole of the input transistor T1 to the second pole; two parallel (and, for example, electrically connected to each other) gates and the long active layer of the input transistor T1 ("I"-shaped active layers) are overlapped respectively, thereby obtaining "I"-shaped double-gate transistors.
  • a single gate overlaps the elongated active layer of the input transistor T1, which is not limited in the embodiment of the present disclosure.
  • the active layer of the input transistor T1 (it should be noted that here refers to the overall shape of the active layer of the input transistor T1) is changed from the "U"-shaped structure shown in FIG. 1D to a long strip extending in the second direction.
  • Shape for example, an "I"-shaped structure along the second direction, such as a " ⁇ "-shaped structure
  • the length of the display panel in the first direction that is, the vertical height of the display panel
  • the first noise reduction transistor T6 and the second noise reduction transistor T7 are arranged below the input transistor T1.
  • the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7 are formed by a continuous noise reduction semiconductor layer A11 (that is, integrated).
  • the noise semiconductor layer A11 extends in the first direction and is arranged side by side with the active layer of the input transistor T1 in the first direction, that is, the input transistor T1 and the first noise reduction transistor T6 and the second noise reduction transistor T7 are along the first direction Set up and down side by side.
  • the active layer of the input transistor T1 is located on an imaginary line extending along the first direction of the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7.
  • the active layer of the first noise reduction transistor T6 may partially overlap with the active layer of the second noise reduction transistor T7 in the first direction (as shown in FIGS. 2A and 3A).
  • the active layer of the first noise reduction transistor T6 can be on an imaginary line extending along the first direction of the active layer of the second noise reduction transistor T7;
  • the active layer of a noise reduction transistor T6 may also not overlap with the active layer of the second noise reduction transistor T7 in the first direction.
  • the active layer of the first noise reduction transistor T6 The layer can also be offset from the active layer of the second noise reduction transistor T7 by a certain distance in the first direction, as long as it does not affect the arrangement of other structures and excessively increase the width of the shift register unit. In the direction, the first noise reduction transistor T6 and the second noise reduction transistor T7 only need to be located below the input transistor T1, which is not limited in the embodiment of the present disclosure.
  • the input transistor T1, the first noise reduction transistor T6 and the second noise reduction transistor T7 are changed from the horizontally arranged structure in FIG.
  • the width in the second direction for example, the horizontal width shown in FIG. 1A, facilitates the realization of the narrow frame design of the display panel.
  • the gate of the first noise reduction transistor T6 and the gate of the second noise reduction transistor T7 extend in the second direction and are arranged side by side in the first direction, for example, the gate of the first noise reduction transistor T6 and the second noise reduction transistor T7
  • the gates of the noise transistor T7 may be parallel, for example, all extend in the second direction, or the extension direction of the gate of the first noise reduction transistor T6 and the extension direction of the gate of the second noise reduction transistor T7 may not be parallel, for example, intersect A certain angle, for example, the crossing angle is less than or equal to 20°, or the angle between the two and the horizontal line is less than or equal to 20°, the embodiment of the present disclosure does not limit this, as long as the first noise reduction transistor T6 and the second noise reduction transistor T7 is only required to be arranged in one piece and arranged up and down along the first direction.
  • the first pole of the input transistor T1, the gate of the first control transistor T2, the first pole of the second noise reduction transistor T7, and the second pole of the voltage stabilizing transistor T8 described below are all connected to the first node N1, for example .
  • the first pole of the input transistor T1, the gate of the first control transistor T2 and the first pole of the second noise reduction transistor T7 are connected through a via.
  • the second node N2 is connected to the gate of the first noise reduction transistor T6, the gate of the output control transistor T4, the first electrode of the first control transistor T2, the first electrode of the first capacitor C1, and the first electrode of the second control transistor T3.
  • the first poles of the control transistor T3 are connected through via holes.
  • the third node N3 is connected to the first pole of the voltage stabilizing transistor T8, the gate of the output transistor T5, and the first pole of the second capacitor C2, for example, the first pole of the voltage stabilizing transistor T8, the gate of the output transistor T5, and the first pole of the second capacitor C2.
  • the first poles of the two capacitors C2 are connected through via holes.
  • the shift register unit further includes a first switching electrode 17, a second switching electrode 18, and a third switching electrode 16.
  • the first transfer electrode 17 is connected to the first electrode of the input transistor T1, the gate of the first control transistor T2, the second electrode of the voltage stabilizing transistor T8, and the first electrode of the second noise reduction transistor T7.
  • the first transfer electrode 17 is connected to the gate of the first control transistor T2 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, and the first transfer electrode 17 is connected to the first electrode of the input transistor T1,
  • the second electrode of the voltage stabilizing transistor T8 and the first electrode of the second noise reduction transistor T7 are located on the same layer (for example, both are located on the third conductive layer 340) and are integrally arranged.
  • the first node N1 includes the first switching electrode 17, that is, the first switching electrode 17 serves as the first node N1, and the input transistor T1, the first control transistor T2, the voltage stabilizing transistor T8, and the second noise reduction transistor Connect the corresponding electrodes of T7.
  • the first transfer electrode 17 is located between the first control transistor T2, the second control transistor T3, the voltage stabilizing transistor T8, the first noise reduction transistor T6, and the second noise reduction transistor T7, and is bent and extended in the first direction.
  • the starting point is the first pole of the input transistor T1 and the ending point is the first pole of the second noise reduction transistor T7.
  • the first control transistor T2 and the second control transistor T3 are also arranged side by side along the first direction, that is, the first noise reduction transistor
  • the distance between T6 and the second noise reduction transistor T7 and the first control transistor T2 and the second control transistor T3 is small, so that the extension length of the first transfer electrode 17 in the first direction is greater than that in the second direction.
  • the extension length therefore, shortens the length of the first transfer electrode 17 connecting these transistors and the width in the second direction, thereby facilitating the realization of a narrow frame.
  • the second transfer electrode 18 is connected to the first electrode of the voltage stabilizing transistor T8 and the gate of the output transistor T5.
  • the second transfer electrode 18 is connected to the gate of the output transistor T5 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, and the second transfer electrode 18 is located at the same position as the first electrode of the voltage stabilizing transistor T8.
  • the layers (for example, all are located on the third conductive layer 340) and are integrally arranged.
  • the third node N3 includes the second switching electrode 18, that is, the second switching electrode 18 serves as the third node N3, connecting the voltage stabilizing transistor T8 and the output transistor T5.
  • the input transistor T1 includes a first gate G1, a second gate G1', and connection electrodes (G11-G13) connecting the first gate G1 and the second gate G1'.
  • the connecting electrodes (G11-G13) are located on the same layer as the first gate G1 and the second gate G1', including those extending in the first direction (for example, the vertical direction as shown in FIG. 4A) and the first gate G1.
  • the first gate G1 and the second gate G1 of the input transistor T1 are connected to the first clock signal line providing the first clock signal through the third part G13 of the connecting electrode to receive the first clock signal.
  • the first grid G1 and the second grid G1' are connected together through the connection electrodes (G11-G13), and then connected to the first clock signal line.
  • connection electrodes G11-G13
  • the connection method shown in FIG. 1D is adopted. The embodiment does not limit this.
  • the first clock signal line that provides the first clock signal is the second sub-clock signal line GCB
  • the first clock signal line GCK is the first sub-clock signal line GCK, which is not limited in the embodiment of the present disclosure.
  • the second electrode of the active layer of the first control transistor T2 may be directly connected to the second sub-clock signal line GCB through a wire.
  • the shift register unit further includes a transfer electrode 15.
  • the second electrode of the first control transistor T2 is not directly connected to the second sub-clock through the wiring.
  • the signal line GCB connection can also be connected to the third part G13 of the connecting electrode through the transfer electrode 15 so as to be connected to the second sub-clock signal line GCB at the same time as the third part G13 of the connecting electrode to receive the first clock signal.
  • the embodiment of the present disclosure does not limit this.
  • the active layer of the input transistor T1 is connected to the signal input electrode through the first connection trace L1 extending in the second direction to receive the input signal; the signal input electrode serves as the input terminal IN of the shift register unit 104, for example located at The signal input electrode 13 in the third conductive layer shown in FIG. 6A.
  • the signal input electrode 13 may be a separately provided electrode, for example, as shown in the third conductive layer of the first-stage shift register unit shown in FIG.
  • the second pole of T5 serves as the extended area of the output terminal GOUT of the output circuit 1043 as the signal input electrode 13, for example, the second pole of the output transistor T5 of the current stage shift register unit (that is, the active layer of the output transistor T5).
  • the metal electrode connected to the drain region of the output circuit 1043 is used as the output terminal GOUT of the output circuit 1043, and the lower shift register unit (for example, the second shift register unit) adjacent to the shift register unit (for example, the first shift register unit)
  • the signal input electrode of the bit register unit is connected as the input signal of the lower-level shift register unit, which is not limited in the embodiment of the present disclosure.
  • the shift register unit further includes a wiring transfer electrode 12.
  • the wire transfer electrode 12 is located on the third conductive layer 340.
  • the wiring transfer electrode 12 and the active layer of the input transistor T1 are located on different layers.
  • the first electrode of the input transistor T1 is electrically connected to the first terminal 121 of the wiring transfer electrode 12, for example, the input transistor T1
  • the first electrode and the wire transfer electrode 12 are located on the same layer, and are integrally formed.
  • the source region of the active layer of the input transistor T1 is connected to the first electrode of the input transistor T1 through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370, and the wiring transfer electrode
  • the second end 122 of 12 and the first end L11 of the first connection trace L1 located in the first conductive layer 320 shown in FIG.
  • the second end L12 of the first connection trace L1 extending in the second direction and the signal input electrode 13 (located on the third conductive layer 340) not in the same layer pass through the second insulating layer 360 It is electrically connected to the via hole of the third insulating layer 370, thereby realizing the connection between the input transistor T1 and the input terminal IN.
  • the wiring transfer electrode 12 and the signal input electrode 13 are located on the same layer.
  • the first connection trace L1 can also be formed on the third conductive layer 340, and is directly connected to the trace transfer electrode 12 and the signal input electrode 13 (that is, not connected through vias), That is, it is integrally formed.
  • the embodiment of the present disclosure does not limit this, as long as the connection between the input transistor T1 and the signal input electrode 13 can be realized.
  • the active layer of the first control transistor T2 and the active layer of the second control transistor T3 are formed by a continuous control semiconductor layer A12 (ie, integrally arranged), and the control semiconductor layer A12 Extending in the first direction, the gate of the first control transistor T2 and the gate of the second control transistor T3 extend in parallel in the second direction and overlap each other in the first direction, that is, the gate of the first control transistor T2 and the second control transistor T2
  • the gates of the control transistor T3 are arranged up and down on the first conductive layer 320 along the first direction.
  • A11 and A12 are named as different semiconductor layers, but the noise reduction semiconductor layer A11 and the control semiconductor layer A12 are both located on the same semiconductor layer 330 shown in FIG. 3A or 3B.
  • the orthographic projection of the second control transistor T3 on the base substrate 10 and the orthographic projection of the first control transistor T2 on the base substrate 10 are located in the second sub-connection in the first direction. Route both sides of L4.
  • the extension direction of the gate of the first control transistor T2 and the extension direction of the gate of the second control transistor T3 may not be parallel, for example, intersect at a certain angle, for example, the crossing angle is less than or equal to 20°, or the two The angle of the horizontal line is less than or equal to 20°, which is not limited in the embodiment of the present disclosure.
  • the active layer of the first control transistor T2 may partially overlap with the active layer of the second control transistor T3 in the first direction (as shown in FIGS. 2A and 3A). Shown) or completely overlapped (not shown in the figure), that is, the active layer of the first control transistor T2 may be on an imaginary line extending along the first direction of the active layer of the second control transistor T3; the first control transistor T2 The active layer of the first control transistor T3 may not overlap with the active layer of the second control transistor T3 in the first direction. For example, as shown in FIGS.
  • the active layer of the first control transistor T2 and the second control transistor T3 The active layer is staggered by a certain distance in the first direction, as long as it does not affect the arrangement of other structures and excessively increase the width of the shift register unit, and as long as the active layer of the first control transistor T2 is active in the first direction
  • the active layer of the second control transistor T3 and the second control transistor T3 only need to be located below the input transistor T1, which is not limited in the embodiment of the present disclosure.
  • the active layer of the first control transistor T2, the active layer of the second control transistor T2, and the active layer of the input transistor T1 are arranged side by side in the second direction.
  • the active layer of the first control transistor T2 and the active layer of the second control transistor T3 intersect an imaginary line extending in the second direction of the active layer of the input transistor T1, that is, the first control transistor T2
  • the active layer of and the active layer of the second control transistor T3 are located on an imaginary line extending along the second direction of the active layer of the input transistor T1.
  • the arrangement of the first control transistor T2 and the second control transistor T3 is changed from the structure shown in FIG.
  • the horizontal width of the peripheral area of the display panel and the distance from the transistor to the signal line and the second power line can be reduced, thereby facilitating the realization of a narrow frame design of the display panel.
  • the active layer of the input transistor T1 is also located on an imaginary line extending along the first direction of the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7.
  • the active layer of the first control transistor T2 and the active layer of the second control transistor T3, the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7 are relatively arranged side by side in the second direction Therefore, the distance between the active layer of the first control transistor T2 and the active layer of the second control transistor T3 and the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7 can be reduced. .
  • the shift register unit further includes an intermediate transfer electrode 11.
  • the gate of the first noise reduction transistor T6 is connected to the first control transistor T2 through the intermediate transfer electrode 11 in the second conductive layer 330 shown in FIG. 5A and the second connecting sub-line L4 in FIG. 6A.
  • One pole and the first pole of the second control transistor T3 are connected to the part between the active layer of the first control transistor T2 and the active layer of the second control transistor T3, and the intermediate transfer electrode 11 is on the base substrate
  • the orthographic projection on 10 and the orthographic projection of the active layer of the first control transistor T2 and the active layer of the second control transistor T3 on the base substrate 10 do not overlap in the first direction, that is, the intermediate transfer electrode 11 is on the backing
  • the orthographic projection on the base substrate 10 is the orthographic projection of the active layer of the first control transistor T2 and the active layer of the second control transistor T3 on the base substrate 10 and the orthographic projection of the first noise reduction transistor T6 on the base substrate 10 Between orthographic projections.
  • the arrangement of the first control transistor T2 and the second control transistor T3 is changed from the left-right arrangement in the second direction shown in FIG. 1D to the one shown in FIG. 2A.
  • the structure is arranged up and down in one direction.
  • the arrangement and position of the input transistor T1, the first noise reduction transistor T6, and the second noise reduction transistor T7 are also changed to a structure that is arranged up and down in the first direction, thereby shortening the first noise reduction.
  • the length of the electrode and the traces at the first control transistor T2 and the second control transistor T3 ie, the intermediate transfer electrode 11 greatly optimizes the problem of space congestion caused by dense and long traces.
  • the connection mode of the intermediate transfer electrode 11 is as shown in FIG. 7A or FIG. 7B.
  • the intermediate transfer electrode 11 is located on the second conductive layer 11.
  • the first insulating layer 350 is located on the active layer of the first noise reduction transistor T6 in the direction perpendicular to the base substrate 10 (for example, located on the semiconductor layer 310, including the source region S6, the drain Between the region D6 and the channel region P6) and the gate G6 of the first noise reduction transistor T6;
  • the second insulating layer 360 is located between the gate G6 and the gate G6 of the first noise reduction transistor T6 in the direction perpendicular to the base substrate 10 Between the transfer electrodes 11.
  • the gate of the first noise reduction transistor T6 is connected to the first end 111 of the intermediate transfer electrode 11 through a via H22 penetrating the second insulating layer 360, and the first control transistor
  • the first pole S21 of T2 and the intermediate transfer electrode 11 are located on the same layer, and are connected to the second end 112 of the intermediate transfer electrode 11, that is, the intermediate transfer electrode 11 and the first electrode S21 of the first control transistor T2 are integrally arranged to achieve
  • the gate of the first noise reduction transistor T6 is connected to the first electrode of the first control transistor T2.
  • the first electrode S21 of the first control transistor T2 and the source region S2 of the active layer of the first control transistor T2 pass through the first insulating layer 350 and the second insulating layer 360. Connect via H11.
  • the second node N2 includes the intermediate transfer electrode 11.
  • FIG. 7A only shows that the first electrode S21 of the first control transistor T2 is connected to the second end 112 of the intermediate transfer electrode 11, because the first electrode of the first control transistor T2 It is connected to the first electrode of the second control transistor T3, so the first electrode of the second control transistor T3 is also connected to the second end 112 of the intermediate transfer electrode 11, which is not limited in the embodiment of the present disclosure.
  • the following embodiments are the same as this, and will not be repeated here.
  • the shift register unit 104 further includes a second connection line.
  • the second connection line includes a first connection sub-line L3 and a second connection sub-line L3.
  • Route L4 the third insulating layer 370 is located between the intermediate transfer electrode 11 and the second connection trace L3/L4 in a direction perpendicular to the base substrate 10.
  • the gate G6 of the first noise reduction transistor T6 is connected to the first connector trace L3 through the via hole H4 penetrating the second insulating layer 360 and the third insulating layer 370, and the first end 111 of the intermediate transfer electrode 11 passes through The via hole H3 penetrating the third insulating layer 370 is connected to the first connector trace L3.
  • the source region S2 of the active layer of the first control transistor T2 passes through the via hole H1 penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370 and the first electrode S21 of the first control transistor T2.
  • the first pole S21 of the first control transistor T2 is connected to the second connector trace L4, the first pole S21 of the first control transistor T2 is located on the same layer and is integrally arranged, and the second end of the intermediate transfer electrode 11 passes through
  • the via hole H2 of the third insulating layer 370 is connected to the second connector wiring L4, thereby realizing the connection between the gate of the first noise reduction transistor T6 and the first electrode of the first control transistor T2.
  • the second node N2 includes the intermediate transfer electrode 11 and the second connecting wire.
  • the second connection trace includes only the first connection sub-line L3 or the second connection sub-line L4.
  • the second connection trace includes only the second connection sub-line L4 as an example for introduction, of course, the embodiment of the present disclosure does not limit this.
  • the intermediate transfer electrode 11 may be located on the first conductive layer 320 and formed integrally with the gate of the first noise reduction transistor T6.
  • the source region S2 of the active layer of the first control transistor T2 passes through the via hole H1 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370 and the first control transistor T2.
  • the first electrode S21 of the transistor T2 is connected, the first electrode S21 of the first control transistor T2 is connected to the second connector wiring L4, and the first electrode S21 of the first control transistor T2 and the second connector wiring L4 are located in the same layer And integrally arranged, the second end 112 of the intermediate transfer electrode 11 is connected to the second connecting sub-line L4 through the via H2 penetrating the third insulating layer 370, thereby realizing the gate of the first noise reduction transistor T6 and the first control Connection of the first pole of the transistor T2.
  • the second node N2 includes the intermediate transfer electrode 11 and the second connecting sub-line L4.
  • the second power supply line VGL includes a protrusion 14 protruding in the second direction.
  • the active layer of the voltage stabilizing transistor T8 is located between the active layer of the second control transistor T3 and the active layer of the second noise reduction transistor T7 in the second direction, and the second electrode of the second control transistor T3 is connected to the voltage stabilizing transistor.
  • the gates of the transistors T8 are all connected to the protrusion 14 on the second power line VGL.
  • the second pole of the second control transistor T3 and the protrusion 14 on the second power line VGL are located on the same layer and are integrally formed to stabilize the voltage.
  • the gate of the transistor T8 is connected to the protrusion 14 not on the second power line VGL in the same layer, for example, through a via hole penetrating the second insulating layer 360 and the third insulating layer 370 to receive the second voltage;
  • the second electrode of the second control transistor T3 and the via hole of the drain region of the active layer of the second control transistor T3, and the via hole for connecting the gate of the voltage stabilizing transistor T8 and the protrusion 14 are respectively connected to the protrusion 14
  • the different sides overlap for example, overlap with the upper and lower sides of the protrusion 14 in the first direction as shown in FIG. 2A), for example, are located at different diagonals of the protrusion 14 (for example, as shown in FIG. 2A, respectively overlap with the protrusion 14).
  • the upper left corner and the lower right corner of the portion 14 in the first direction overlap).
  • the first control transistor T2 and the second control transistor T3 are arranged side by side along the second direction shown in FIG. 1D to the structure shown in FIG. 2A arranged up and down in the first direction.
  • the width of the peripheral area of the display panel in the second direction can be reduced, so that the distance between other transistors (for example, the voltage stabilizing transistor T8) and the second power line VGL can be shortened.
  • the second electrode of the second control transistor T3 (For example, the source) and the gate of the voltage stabilizing transistor T8 are commonly connected to the protrusion 14 on the second power line VGL, so they are closer in space, thereby reducing the length of the trace, which is beneficial to the narrow frame of the display panel The realization.
  • the first pole CE11 and the second pole CE12 of the first capacitor C1 include notches, and the signal input electrode 13 connected to the first connection line L1 extending in the second direction is formed in the first In the gap of a capacitor C1, for example, the orthographic projection of the signal input electrode 13 on the base substrate falls into the gap of the orthographic projection of the first capacitor C1 on the base substrate, so that the first electrode CE11 of the first capacitor C1 and The shape of the second electrode CE12 is complementary to the signal input electrode 13, which makes full use of the space on the display substrate, thereby facilitating the realization of the narrow frame design of the display panel.
  • the size/size of the first capacitor C1 will generally not change.
  • the size change can fluctuate by 10% to 20%, and the specific shape can be other according to The structure is designed and arranged, which is not limited in the embodiments of the present disclosure.
  • a third connecting wire L2 (located in The orthographic projection of the first conductive layer 320) on the base substrate 10 and the orthographic projection of the active layer of the second noise reduction transistor T7 on the base substrate 10 overlap in the first direction, and at least partially overlap with the second noise reduction
  • the gate of the transistor T7 is parallel, that is, the third connection trace L2 runs from the side of the active layer of the second noise reduction transistor T7 away from the signal line (for example, the second noise reduction transistor T7 shown in FIG. 2A has The right side of the source layer) through.
  • the third connection trace L2 includes a third sub-connection trace L21 and a fourth sub-connection trace L22.
  • the orthographic projection of the base substrate 10 and the orthographic projection of the active layer of the second noise reduction transistor T7 on the base substrate 10 are arranged side by side in the second direction, and the fourth sub-connection trace L22 is connected to the third sub-connection trace L21. And extend along the second direction.
  • the third connection trace L2 is a gate trace, that is, the third sub-connection trace L21 and the fourth sub-connection trace L22 are directly connected (no need to pass Hole connection) and integrally formed, for example, the fourth sub-connection line L22 is connected to the first sub-clock signal line GCK that provides the second clock signal.
  • the third connection trace L2 includes two gate traces connected by vias, one is the third sub-connection trace L21, and the other is the fourth sub-connection. Route L22. The connection relationship between the third sub-connection trace L21 and the fourth sub-connection trace L22 will be described in detail below.
  • the third sub-connection trace L21 that connects the fourth sub-connection trace L22 and the gate of the second noise reduction transistor T7 is also connected to the first pole of the output transistor T5 which is not in the same layer through a via hole.
  • the first pole of the output transistor T5 is connected to the second clock signal terminal CB, for example, the second clock signal terminal CB is connected to the first sub-clock signal line GCK.
  • the first pole of the output transistor T5 is electrically connected to the third sub-connection trace L21, and the third sub-connection trace L21 is located on the side of the active layer of the second noise reduction transistor T7 close to the output transistor T5.
  • the orthographic projection of the via on the base substrate 10 is the orthographic projection of the active layer of the second noise reduction transistor T7 on the base substrate 10 and the orthographic projection of the active layer of the output transistor T5 on the base substrate 10 between.
  • the fourth sub-connection trace L22 is on the first conductive layer 320, and its orthographic projection on the base substrate 10 is located on the orthographic projection and the first projection of the voltage stabilizing transistor T8 of the X-th stage shift register unit on the base substrate 10.
  • the input transistor T1 of the X+1 stage shift register unit is between the orthographic projections on the base substrate 10.
  • the gate of the output transistor T5 is electrically connected to the first electrode of the voltage stabilizing transistor T8, and the second electrode of the output transistor T5 is connected to the output terminal GOUT.
  • the first electrode S51 of the output transistor T5 passes through the first insulating layer 350, the second insulating layer 360, and the third insulating layer.
  • the via H7 of the layer 370 is connected to the source region S5 of the output transistor T5, and the first electrode S51 of the output transistor T5 is connected to the fourth connection line L5, for example, the first electrode S51 of the output transistor T5 is connected to the fourth connection line L5 is located on the same layer and is integrally formed.
  • the fourth connection trace L5 is connected to the third sub-connection trace L21 through the vias H5 and H6 passing through the second insulating layer 360 and the third insulation layer 370, and the third sub-connection traces
  • the line L21 is connected to the gate of the second noise reduction transistor T7 and to the fourth sub-connection wire L22, so that the first pole S51 of the output transistor T5 is connected to the gate G7 of the second noise reduction transistor T7, and is connected to The first sub-clock signal line GCK to receive the second clock signal.
  • the first pole of the output transistor T5 is connected to the fourth connection line L5, and the first pole S51 of the output transistor T5 With the fourth connection trace L5, the first end L51 of the fourth connection trace L5 passes through the via H8 and the via H9 which penetrate the second insulating layer 360 and the third insulating layer 370 and the third terminal located on the second conductive layer 320.
  • the sub-connection trace L21 is connected, and the second end L52 of the fourth connection trace L5 passes through the via holes H5 and H6 through the second insulating layer 360 and the third insulating layer 370 to the fourth sub-line located in the second conductive layer 320.
  • the connecting trace L22 is connected, and the third sub-connecting trace L21 is directly connected to the gate G7 of the second noise reduction transistor T7 and is integrally formed, thereby realizing the first pole of the output transistor T5 and the gate G7 of the second noise reduction transistor T7 Connected and connected to the first sub-clock signal line GCK through the fourth connection line L5 and the fourth sub-connection line L22 to receive the second clock signal.
  • the active layer of the output control transistor T4 and the active layer of the output transistor T5 are formed by a first output semiconductor layer A13 and a second output semiconductor layer A14 (that is, the output control transistor The T4 active layer and the active layer of the output transistor T5 are integrally provided) and extend along the first direction.
  • the active layer of the output control transistor T4 is located on an imaginary line of the active layer of the output transistor T5 in the first direction.
  • the active layer of the output control transistor T4 includes A13 of the third semiconductor layer and the fourth semiconductor layer.
  • the upper half of A14 in the first direction, and the active layer of the output transistor T5 includes the lower half of the third semiconductor layer A13 and the fourth semiconductor layer A14 in the first direction.
  • the proportions of the active layer of the output control transistor T4 and the active layer of the output transistor T5 in the third semiconductor layer A13 and the fourth semiconductor layer A14, respectively can be set according to actual conditions, and the embodiments of the present disclosure do not do this. limit.
  • the gate of the output control transistor T4 and the gate of the output transistor T5 extend in the second direction and overlap each other in the first direction, that is, the output control transistor T4 and the output transistor T5 are arranged up and down in the first direction.
  • the gate of the output control transistor T4 is located on an imaginary line where the gate of the output transistor T5 is in the first direction.
  • the first pole of the output control transistor T4 is electrically connected to the first power supply line VGH.
  • connection traces are provided on both sides of the second noise reduction transistor T7
  • at least one embodiment of the present disclosure provides a change in the connection trace of the second noise reduction transistor T7.
  • the arrangement of the wires that is, the wires only pass between the output transistor T5 and the second noise reduction transistor T7 reduces the complexity of the wires, avoids the problem of space congestion, and facilitates the realization of a narrow frame design of the display panel.
  • the line width of the traces of each layer is generally 3 micrometers, for example, and the spacing between the traces on the same layer is, for example, greater than 3 micrometers.
  • the line spacing is related to the accuracy of the exposure machine, for example, the higher the accuracy of the exposure machine, the smaller the spacing can be, which can be specifically determined according to the actual situation, which is not limited in the embodiments of the present disclosure.
  • necessary spacing must be left between the traces of the same layer to avoid the traces sticking and signal short-circuiting in the actual process.
  • the distance between the orthographic projection of the traces of the first conductive layer 320 on the base substrate 10 and the orthographic projection of the traces of the second conductive layer 330 on the base substrate 10 is generally 1.5 microns, for example, .
  • the gate of the transistor in the first conductive layer 320 should exceed its active layer on the semiconductor layer 31 by more than 2 micrometers, for example.
  • the "U"-shaped double gate of the first transistor T1 extends beyond the first transistor T1 on both sides of the strip-shaped active layer of the first transistor T1 in the first direction.
  • the strip-shaped active layer is, for example, 2 micrometers or more.
  • the length in the first direction of the part (for example, the first part G11 and the second part G12) that does not overlap with the strip-shaped active layer of the first transistor T1 is 2 microns or more, the embodiment of the present disclosure does not limit this.
  • the distance between the orthographic projection of the active layer of each transistor on the semiconductor layer 310 on the base substrate 10 and the orthographic projection of the gate traces on the first conductive layer 320 on the base substrate 10 is 1.5. Micrometer or more, so as to avoid the channel effect between the gate wiring and the active layer of each transistor on the semiconductor layer 310.
  • the distance between the orthographic projection of the semiconductor layer 310 on the base substrate 10 and the orthographic projection of the second conductive layer 330 on the base substrate 10 is not limited, and can be overlapped.
  • a certain distance between traces of different layers is kept as much as possible (this distance is smaller than the distance of traces in the same layer), which can reduce unnecessary overlap and avoid interference caused by excessive parasitic capacitance.
  • the width of each trace of the third conductive layer 340 should enclose its corresponding via. For example, it may exceed the size of the via (for example, the diameter of the via) by more than 1 micron.
  • the size of the via is 2.0-2.5 micrometers
  • the width of each trace of the third conductive layer 340 that covers the via hole is 4-5 micrometers.
  • the trace width of the output control transistor T4 and the output transistor T5 corresponding to the via hole is 1 micron above and below the via hole, for example 4.0-4.5 microns, because the output control transistor T4 and the output transistor T5 correspond to more via holes , And the width of the traces in the third conductive layer 340 connected to other transistors only needs to meet the requirement of covering the vias by more than 1 micron at the position of the vias. For example, the width of the traces between the vias can be thinner.
  • the spacing between the first sub-clock signal line GCK, the second sub-clock signal line GCB, the first power line VGH, and the second power line VGL located on the third conductive layer 340 is more than 3 microns, and the first The sub-clock signal line GCK and the second sub-clock signal line GCB have a line width of 9 microns or more in order to meet the driving capability requirements.
  • the line width of the second power line VGL can be 6, 9 or 10 microns.
  • the line width of the first power line VGH The line width is, for example, 10 microns, the line width of the reference voltage line Vinit is, for example, 15 microns, the second voltage provided by the second power line VGL is generally -7V, for example, and the reference voltage provided by the basic voltage line Vinit is, for example, -3V, because the reference The voltage line Vinit needs to drive the pixel array of the entire display panel, and the first power line VGH and the second power line VGL only need to drive the gate driving circuit located in the peripheral area of the display panel, so the line width of the reference voltage line Vinit is larger than that of the first The line width of the power line VGH and the line width of the second power line VGL are slightly wider.
  • the thickness of the first conductive layer 320 and the second conductive layer 330 is 2000-300 angstroms
  • the thickness of the third conductive layer 340 is 5000-8000 angstroms, which is not limited in the embodiments of the present disclosure.
  • the second power line VGL is provided with a protrusion to shorten the connection line connecting the gate of the voltage stabilizing transistor T8 and the active layer of the second control transistor T3.
  • the active layer of the control transistor T3 is too long, and the resistance of the doped conductor will be larger.
  • the shape of the traces of the first node N1 on the third conductive layer 340 ie, the intermediate transfer electrode 11
  • the orthographic projections on the substrate 10 overlap and are arranged in gaps, so as to avoid crosstalk caused by overlapping traces.
  • the first transfer electrode 17, the second transfer electrode 18, and the third transfer electrode 16 are located on the third conductive layer 340.
  • the first transfer electrode 17 is an electrode for connecting the input transistor T1, the first control transistor T2, the second noise reduction transistor T7, and the voltage stabilizing transistor T8 shown in FIG. 1B.
  • the first node N1 includes the first node N1.
  • the second switching electrode 18 is an electrode for connecting the voltage stabilizing transistor T8 and the output transistor T5, and the third node N3 includes the second switching electrode 18.
  • the intermediate transfer electrode 11 is an electrode used to connect the first control transistor T2, the second control transistor T3, and the first noise reduction transistor T6, and may be located on the second conductive layer 330 or the first conductive layer 320.
  • the intermediate transfer electrode 11 is located in the second conductive layer 330 and the connection method shown in FIG.
  • the wire transfer electrode 12 is located on the first conductive layer 320 and is a transfer electrode connected to the first connection wire L1 located on the third conductive layer 340, or both are located on the same layer. No restrictions.
  • each of the above-mentioned transfer electrodes and the connecting wires play the role of connection or jumper connection.
  • the circuit connection and structural layout of the shift register unit of the display substrate provided by the above-mentioned embodiments of the present disclosure are optimized, which reduces the length of the shift register unit to a certain extent, which is beneficial to realize the narrow frame design of the display panel, and at the same time ensures the display The display quality of the panel.
  • FIG. 8 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 2 includes a display substrate 1 provided in any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 2A or FIG. 2B.
  • the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device 2 may also include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a manufacturing method of a display substrate provided by at least one embodiment of the present disclosure.
  • the manufacturing method can be used to manufacture the display substrate provided by any embodiment of the present disclosure.
  • it can be used to make the display substrate shown in FIG. 2A.
  • the manufacturing method of the display substrate includes step S110 to step S120.
  • Step S110 Provide a base substrate.
  • Step S120 sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the base substrate.
  • forming the semiconductor layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, and the third conductive layer respectively includes forming corresponding material layers (for example, a semiconductor material layer, an insulating layer). Material layer or conductive material layer), and then use a patterning process to respectively form corresponding pattern structures (for example, active layers, electrode patterns, traces, vias, etc.).
  • the patterning process is, for example, a photolithography process, including: coating a photoresist layer on the material layer that needs to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain The photoresist pattern is used to etch the structure layer, and then the photoresist pattern is optionally removed.
  • a photolithography process including: coating a photoresist layer on the material layer that needs to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain The photoresist pattern is used to etch the structure layer, and then the photoresist pattern is optionally removed.
  • the base substrate 10 can be made of, for example, glass, plastic, quartz, or other suitable materials, which is not limited in the embodiment of the present disclosure.
  • a shift register unit for example, a shift register unit, a first power supply line, a second power supply line, a first clock signal line, and a second clock signal line are formed on the base substrate.
  • forming the shift register unit includes: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second insulating layer in a direction perpendicular to the base substrate. Three insulating layers and a third conductive layer.
  • the first power supply line VGH, the second power supply line VGL, multiple clock signal lines for example, the trigger signal line GSTV, the first sub-clock signal line GCK, and the second sub-clock signal line GCB, etc.
  • the shift register unit 104 The first pole and the second pole of each transistor included in the transistor, as well as the connection traces and transfer electrodes that connect each transistor and the capacitor, are located on the third conductive layer 340.
  • each transistor is located on the semiconductor layer 310, and the gate of each transistor And the first electrode of each capacitor included in the shift register unit is located on the first conductive layer 320, and the second electrode of each capacitor is formed on the second conductive layer 330; each transistor and each capacitor pass through the first insulating layer 310, the second electrode
  • the via holes of the second insulating layer 320 or the third insulating layer 330 are respectively connected to the first power line VGH, the second power line VGL, a plurality of clock signal lines, connection wires and transfer electrodes.
  • connection structure of the respective transistors and capacitors of the shift register unit 104 with the first power supply line VGH, the second power supply line VGL, multiple clock signal lines, and connection traces and transfer electrodes, please refer to FIGS. 2A-7E. The description will not be repeated here.
  • the process of the method for manufacturing the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel.
  • the flow of the manufacturing method described above includes multiple operations appearing in a specific order, it should be clearly understood that the order of the multiple operations is not limited.
  • the production method described above can be executed once or multiple times according to predetermined conditions.

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Abstract

一种显示基板及其制作方法、显示装置。该显示基板包括：衬底基板以及设置在衬底基板上的移位寄存器单元和第一时钟信号线，第一时钟信号线在衬底基板上沿第一方向延伸，且配置为向移位寄存器单元提供第一时钟信号；移位寄存器单元包括输入电路、输出电路、第一控制电路和输出控制电路；第一控制电路包括第一控制晶体管和第二控制晶体管，第一控制晶体管的有源层和第二控制晶体管的有源层为一个连续的控制半导体层，控制半导体层沿第一方向延伸，第一控制晶体管的栅极和第二控制晶体管的栅极沿不同于第一方向的第二方向延伸且在第一方向上并排设置。该显示基板优化了线路结构的布局，有利于实现显示面板的窄边框设计。

Description

显示基板及其制作方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制作方法、显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与栅线交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
发明内容
本公开至少一实施例提供一种显示基板，包括：衬底基板以及设置在所述衬底基板上的移位寄存器单元和第一时钟信号线，所述第一时钟信号线在所述衬底基板上沿第一方向延伸，且配置为向所述移位寄存器单元提供第一时钟信号；所述移位寄存器单元包括输入电路、输出电路、第一控制电路和输出控制电路；所述输入电路配置为响应于所述第一时钟信号将输入信号输入至第一节点；所述输出电路配置为将输出信号输出至输出端；所述第一控制电路配置为响应于所述第一节点的电平和所述第一时钟信号，控制第二节点的电平；所述输出控制电路配置为在所述第二节点的电平的控制下，对所述输出端的电平进行控制；所述第一控制电路包括第一控制晶体管和第二控制晶体管，所述第一控制晶体管的有源层和所述第二控制晶体管的有源层为一个连续的控制半导体层，所述控制半导体层沿所述第一方向延伸，所述第一控制晶体管的栅极和所述第二控制晶体管的栅极沿不同于所述第一方向的第二方向延伸且在所述第一方向上并排设置。
例如，在本公开至少一实施例提供的显示基板中，所述第一方向与所述第二方向的夹角在70°到90°之间。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括稳压电路，所述稳压电路与所述第一节点和第三节点连接，且配置为稳定所述第三节点的电平；所述输出电路与所述第三节点连接，且配置为在所述第三节点的电平的控制下，将所述输出信号输出至所述输出端。
例如，本公开至少一实施例提供的显示基板，还包括第一电源线和第二电源线，被配 置为向所述移位寄存器单元提供第一电压和第二电压，所述稳压电路包括稳压晶体管，所述第二电源线包括在所述第二方向上突出的突出部，所述第二控制晶体管的第二极和所述稳压晶体管的栅极均与所述第二电源线上的突出部连接以接收所述第二电压；所述稳压晶体管的第一极连接所述第三节点，所述稳压晶体管的第二极连接所述第一节点。
例如，在本公开至少一实施例提供的显示基板中，所述输入电路包括输入晶体管，所述输入晶体管的有源层为沿所述第二方向延伸的长条形；所述输入晶体管包括第一栅极、第二栅极和连接所述第一栅极和所述第二栅极的连接电极，所述连接电极包括沿所述第一方向延伸的与所述第一栅极连接的第一部分和与所述第二栅极连接的第二部分，以及沿所述第二方向延伸且连接所述第一部分和所述第二部分的第三部分，所述连接电极的第三部分与所述第一时钟信号线连接以接收所述第一时钟信号。
例如，在本公开至少一实施例提供的显示基板中，所述第一控制晶体管的有源层、所述第二控制晶体管的有源层和所述输入晶体管的有源层在所述第二方向并排设置。
例如，在本公开至少一实施例提供的显示基板中，所述第一控制晶体管的有源层、所述第二控制晶体管的有源层位于所述输入晶体管的有源层沿所述第二方向延伸的假想线上。
例如，在本公开至少一实施例提供的显示基板中，所述输入晶体管的第一极通过沿所述第二方向延伸的第一连接走线与信号输入电极连接以接收所述输入信号。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括走线转接电极，所述输入晶体管的第一极与所述走线转接电极的第一端电连接，所述走线转接电极与所述输入晶体管的有源层位于不同层，所述走线转接电极的第二端与所述第一连接走线的第一端连接，所述走线转接电极与所述第一连接走线位于不同层，所述第一连接走线的第二端与所述信号输入电极电连接，所述走线转接电极与所述信号输入电极位于同一层。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层位于所述输入晶体管的有源层和所述第一连接走线之间，所述第二绝缘层和所述第三绝缘层位于所述第一连接走线和所述走线转接电极之间；所述输入晶体管的第一极与所述走线转接电极位于同一层，所述走线转接电极的第二端通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述第一连接走线的第一端连接，所述第一连接走线的第二端通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述信号输入电极电连接。
例如，在本公开至少一实施例提供的显示基板中，所述显示基板还包括第二时钟信号线，配置为向所述移位寄存器单元提供第二时钟信号，所述移位寄存器单元还包括第二控制电路，所述第二控制电路与所述第一节点和所述第二节点连接，且配置为在所述第二节点的电平和所述第二时钟信号的控制下，对所述第一节点的电平进行控制。
例如，在本公开至少一实施例提供的显示基板中，所述第二控制电路包括第一降噪晶体管和第二降噪晶体管；所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层为 一个连续的降噪半导体层，所述降噪半导体层沿所述第一方向延伸，且与所述输入晶体管的有源层在所述第一方向上并排设置，所述第一降噪晶体管的栅极和所述第二降噪晶体管的栅极沿所述第二方向延伸并在所述第一方向上并排设置；所述输入晶体管的第一极连接所述第一节点，所述第一降噪晶体管的栅极连接所述第二节点。
例如，在本公开至少一实施例提供的显示基板中，所述输入晶体管的有源层位于所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层沿所述第一方向延伸的假想线上。
例如，在本公开至少一实施例提供的显示基板中，在所述移位寄存器单元包括稳压晶体管的情况下，所述稳压晶体管的有源层在所述衬底基板上的正投影在所述第一方向上位于所述第二控制晶体管的有源层在所述衬底基板上的正投影和所述第二降噪晶体管的有源层在所述衬底基板上的正投影之间。
例如，在本公开至少一实施例提供的显示基板中，所述第二降噪晶体管的栅极通过第三连接走线电连接到所述第二时钟信号线，所述第三连接走线包括第三子连接走线和第四子连接走线，所述第三子连接走线与所述第二降噪晶体管的栅极连接且沿所述第一方向延伸，且所述第三子连接走线在所述衬底基板的正投影与所述第二降噪晶体管的有源层在所述衬底基板上的正投影在所述第二方向上并排设置，所述第四子连接走线与所述第三子连接走线和所述第二时钟信号线连接且沿所述第二方向延伸，所述第四子连接走线在所述衬底基板上的正投影位于所述第二降噪晶体管的有源层在所述衬底基板上的正投影远离所述第一降噪晶体管的有源层在所述衬底基板上的正投影的一侧。
例如，本公开至少一实施例提供的显示基板，还包括第四连接走线、第一绝缘层、第二绝缘层和第三绝缘层；所述第一绝缘层位于所述输入晶体管的有源层和所述输入晶体管的栅极之间，所述第二绝缘层和所述第三绝缘层位于所述输入晶体管的栅极和所述第四连接走线之间；所述第三子连接走线和所述第四子连接走线一体化形成，所述第三子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接。
例如，本公开至少一实施例提供的显示基板，还包括第四连接走线、第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层位于所述输入晶体管的有源层和所述输入晶体管的栅极之间，所述第二绝缘层和所述第三绝缘层位于所述输入晶体管的栅极和所述第四连接走线之间；所述第三子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接，所述第四子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括中间转接电极，所述第一控制晶体管的有源层和所述第二控制晶体管的有源层与所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层在所述第二方向上并排设置，所述中间转接电极在所述衬底基板的正投影位于所述第一控制晶体管的有源层和所述第二控制晶体管的有源层在所述衬底基板上的正投影与所述第一降噪晶体管的有源层和所述第二降噪晶体管 的有源层在所述衬底基板上的正投影之间，所述第一降噪晶体管的栅极通过所述中间转接电极连接至所述第一控制晶体管的第一极和所述第二控制晶体管的第一极。
例如，在本公开至少一实施例提供的显示基板中，所述第二节点包括所述中间转接电极。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括第一绝缘层和第二绝缘层，所述第一绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的有源层和所述第一降噪晶体管的栅极之间；所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的栅极和所述中间转接电极之间；所述第一降噪晶体管的栅极通过贯穿所述第二绝缘层的过孔与所述中间转接电极的第一端连接，所述第一控制晶体管的第一极和所述第二控制晶体管的第一极通过贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述中间转接电极的第二端连接。
例如，在本公开至少一实施例提供的显示基板中，所述第二节点包括所述中间转接电极。
例如，在本公开至少一实施例提供的显示基板中，所述移位寄存器单元还包括第一绝缘层、第二绝缘层、第三绝缘层和第二连接走线，所述第一绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的有源层和所述第一降噪晶体管的栅极之间；所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的栅极和所述中间转接电极之间；所述第三绝缘层在垂直于所述衬底基板的方向上位于所述中间转接电极和所述第二连接走线之间，所述第二连接走线包括第一子连接走线和第二子连接走线；所述第一降噪晶体管的栅极通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述第一子连接走线连接，所述中间转接电极的第一端通过贯穿所述第三绝缘层的过孔和所述第一子连接走线连接，所述第一控制晶体管的第一极和所述第二控制晶体管的第一极与所述第二子连接走线连接且位于同一层，所述中间转接电极的第二端通过贯穿所述第三绝缘层的过孔与所述第二子连接走线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第二节点包括所述中间转接电极和所述第二连接走线。
例如，在本公开至少一实施例提供的显示基板中，所述输入晶体管的第一极与信号输入电极连接以接收所述输入信号，所述输出控制电路包括输出控制晶体管和第一电容，其中，所述第一电容的第一极和第二极包括缺口，所述信号输入电极在所述衬底基板上的正投影落入所述第一电容在所述衬底基板上的正投影的缺口中。
例如，在本公开至少一实施例提供的显示基板中，所述输出电路包括输出晶体管和第二电容，所述输出晶体管的第一极与所述第四连接走线连接，所述第四连接走线通过所述第三连接走线连接到所述第二时钟信号线，第三连接走线的所述第三子连接走线在所述衬底基板上的正投影位于所述第二降噪晶体管的有源层在所述衬底基板上的正投影靠近所述输出晶体管的有源层在所述衬底基板上的正投影的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述第二电容的形状为矩形。
例如，在本公开至少一实施例提供的显示基板中，在所述输出控制电路包括输出控制晶体管和第一电容的情况下，所述输出控制晶体管有源层和所述输出晶体管的有源层一体设置并沿所述第一方向延伸，所述输出控制晶体管的栅极和所述输出晶体管的栅极沿所述第二方向延伸且在所述第一方向上并排设置，在所述显示基板包括第一电源线的情况下，所述输出控制晶体管的第一极电连接到所述第一电源线以接收第一电压。
例如，在本公开至少一实施例提供的显示基板中，所述输出晶体管的第二极与和所述移位寄存器单元相邻的下级移位寄存器单元的信号输入电极连接。
例如，本公开至少一实施例提供的显示基板，还包括第一电源线、第二电源线、第二时钟信号线、像素阵列区和周边区域，所述第一电源线和所述第二电源线被配置为向所述移位寄存器单元提供第一电压和第二电压，所述第二时钟信号线被配置为向所述移位寄存器单元提供第二时钟信号，所述第一电源线、所述第二电源线、所述第一时钟信号线、所述第二时钟信号线和所述移位寄存器单元位于所述周边区域内；所述第二电源线、所述第一时钟信号线和所述第二时钟信号线在所述衬底基板上的正投影位于所述移位寄存器单元在所述衬底基板上的正投影远离所述像素阵列区的一侧；所述第一电源线在所述衬底基板上的正投影位于所述移位寄存器单元在所述衬底基板上的正投影靠近所述像素阵列区的一侧。
例如，本公开至少一实施例提供的显示基板，还包括：第一电源线、第二控制电路、稳压电路、第一转接电极、第二转接电极和第三转接电极；所述第一电源线配置为向所述移位寄存器单元提供第一电压；所述第二控制电路与所述第一节点和所述第二节点连接，且配置为在所述第二节点的电平和第二时钟信号的控制下，对所述第一节点的电平进行控制；所述稳压电路与所述第一节点和第三节点连接，且配置为稳定所述第三节点的电平；所述输入电路包括输入晶体管，所述第二控制电路包括第一降噪晶体管和第二降噪晶体管，所述稳压电路包括稳压晶体管，所述输出控制电路包括输出控制晶体管和第一电容，所述输出电路包括输出晶体管和第二电容；所述第一转接电极与所述输入晶体管的第一极、所述第一控制晶体管的栅极、所述稳压晶体管的第二极和所述第二降噪晶体管的第一极连接，所述第一转接电极与所述第一控制晶体管的栅极不在同一层；所述第二转接电极与所述稳压晶体管的第一极和所述输出晶体管的栅极连接，所述第二转接电极与所述输出晶体管的栅极不在同一层；所述第三转接电极与所述第一降噪晶体管的第一极和所述输出控制晶体管的第一极连接，并与所述第一电源线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一节点包括所述第一转接电极，所述第三节点包括所述第二转接电极。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的显示基板。
例如，在本公开至少一实施例提供的显示装置中，所述显示装置为有机发光二极管显示装置。
例如，本公开至少一实施例提供的显示装置，还包括阵列排布的像素单元，其中，所述移位寄存器单元的输出电路输出的输出信号作为栅极扫描信号以驱动所述像素单元发光。
本公开至少一实施例还提供一种的显示基板的制作方法，包括：提供所述衬底基板；在所述衬底基板上形成移位寄存器单元、第一电源线、第二电源线、所述第一时钟信号线和第二时钟信号线，形成所述移位寄存器单元包括：在垂直于所述衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层；各个晶体管的有源层位于所述半导体层，所述各个晶体管的栅极和各个电容的第一极位于所述第一导电层，所述各个电容的第二极位于所述第二导电层，所述第一电源线、所述第二电源线、所述第一时钟信号线、所述第二时钟信号线和所述各个晶体管的第一极和第二极位于所述第三导电层；所述各个晶体管和所述各个电容通过贯穿所述第一绝缘层、所述第二绝缘层或所述第三绝缘层的过孔互相连接以及与所述第一电源线、所述第二电源线、所述第一时钟信号线和所述第二时钟信号线连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为一种显示面板的整体电路架构示意图；
图1B为一种移位寄存器单元的电路图；
图1C为图1B所示的移位寄存器单元工作时的信号时序图；
图1D为图1B中所示的移位寄存器单元在显示基板上的布局示意图；
图2A为本公开至少一实施例提供的一种显示基板的布局示意图；
图2B为本公开至少一实施例提供的另一种显示基板的布局示意图；
图3A、图4A、图5A和图6A分别示出了图2A中所示显示基板的移位寄存器单元的各层布线的平面图；
图3B、图4B、图5B和图6B分别示出了图2B中所示显示基板的移位寄存器单元的各层布线的平面图；
图5C为图2A所示的显示基板的移位寄存器单元的各层布线之间的过孔的平面图；
图5D为图2B所示的显示基板的移位寄存器单元的各层布线之间的过孔的平面图；
图7A为图2A所示的显示基板的一个示例的剖面图；
图7B为图2A所示的显示基板沿A-A`方向的一些示例的剖面图；
图7C为图2B所示的显示基板沿B-B`方向的一些示例的剖面图；
图7D为图2A所示的显示基板的沿C-C`方向的一些示例的剖面图；
图7E为图2B所示的显示基板的沿D-D`方向的一些示例的剖面图；
图8为本公开至少一实施例提供的一种显示装置的示意图；以及
图9为本公开至少一实施例提供的一种显示基板的制作方法的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
图1A为一种显示面板的整体电路架构的示意图。例如，如图1A所示，101表示显示面板的整体外框线；显示面板包括有效显示区(即像素阵列区)102以及位于有效显示区102周边的周边区域，该有效显示区包括阵列排布的像素单元103；该周边区域包括移位寄存器单元104，多个级联的移位寄存器单元104组成栅极驱动电路，用于向显示面板101的有效显示区102中的阵列排布的像素单元103提供例如逐行移位的栅极扫描信号；该周边区域还包括发光控制单元105，多个级联的发光控制单元105组成发光控制阵列，用于向显示面板101的有效显示区102中的阵列排布的像素单元103提供例如逐行移位的发光控制信号。
如图1A所示，与数据驱动芯片IC连接的数据线D1-DN(N为大于1的整数)纵向穿过有效显示区102，以为阵列排布的像素单元103提供数据信号；与移位寄存器单元104和发光控制单元105连接的栅线G1-GM(M为大于1的整数)横穿有效显示区102，以为阵列排布的像素单元提供栅极扫描信号和发光控制信号。例如，各个像素单元103可以包括本领域内的具有7T1C、8T2C或4T1C等电路结构的像素电路和发光元件，像素电路在通过数据线传输的数据信号和通过栅线传输的栅极扫描信号和发光控制信号的控制下工作，以驱动发光元件发光从而实现显示等操作。该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
图1B为一种移位寄存器单元的电路结构图。图1C为图1B所示的移位寄存器单元工作时的信号时序图。下面结合图1B和图1C对该移位寄存器单元的工作过程进行简要地介绍。
如图1B所示，该移位寄存器单元104包括8个晶体管(输入晶体管T1、第一控制晶体管T2、第二控制晶体管T3、输出控制晶体管T4、输出晶体管T5、第一降噪晶体管T6、第二降噪晶体管T7以及稳压晶体管T8)以及2个电容(第一电容C1和第二电容C2)。例如，当多个移位寄存器单元104级联时，第一级移位寄存器单元104中的输入晶体管T1的第一极和输入端IN连接，输入端IN被配置为与触发信号线GSTV连接以接收触发信号作为输入信号，而其它各级移位寄存器单元104中的输入晶体管T1的第一极和上一级移位寄存器单元104的输出端电连接，以接收上一级移位寄存器单元104的输出端GOUT输出的输出信号作为输入信号，由此实现移位输出，以用于对有源显示区的像素单元的阵列进行例如逐行扫描。
另外，如图1B所示，该移位寄存器单元还包括第一时钟信号端CK和第二时钟信号端CB，GCK表示第一子时钟信号线，GCB表示第二子时钟信号线，例如，当第一时钟信号端CK和第一子时钟信号线GCK连接以接收第一时钟信号时，第一子时钟信号线GCK为第一时钟信号线，当第一时钟信号端CK和第二子时钟信号线GCB连接以接收第一时钟信号时，第二子时钟信号线GCB为第一时钟信号线，可视具体情况而定，本公开的实施例对此不作限制。第二时钟信号端CB和第二子时钟信号线GCB或第一子时钟信号线GCK连接以接收第二时钟信号。下面以第一时钟信号端CK和第一子时钟信号线GCK连接以接收第一时钟信号，第二时钟信号端CB和第二子时钟信号线GCB连接以接收第二时钟信号为例进行介绍，即第一子时钟信号线GCK作为第一时钟信号线和第二子时钟信号线GCB作为第二时钟信号线为例进行说明，本公开的实施例对此不作限制。例如，第一时钟信号GCK以及第二时钟信号GCB可以采用占空比大于50％的脉冲信号，并且二者例如相差半个周期；VGH表示第一电源线以及第一电源线提供的第一电压，例如，第一电压为直流高电平，VGL表示第二电源线以及第二电源线提供的第二电压，例如，第二电压为直流低电平，且第一电压大于第二电压；N1、N2以及N3分别表示电路示意图中的第一节点、第二节点以及第三节点。
如图1B所示，输入晶体管T1的栅极和第一时钟信号端CK(第一时钟信号端CK和第一子时钟信号线GCK连接)连接以接收第一时钟信号，输入晶体管T1的第二极和输入端IN连接，输入晶体管T1的第一极和第一节点N1连接。例如，当该移位寄存器单元为第一级移位寄存器单元时，输入端IN与触发信号线GSTV连接以接收触发信号，当该移位寄存器单元为除第一级移位寄存器以外的其他各级移位寄存器单元时，输入端IN与其上级移位寄存器单元的输出端GOUT连接。
第一控制晶体管T2的栅极和第一节点N1连接，第一控制晶体管T2的第二极和第一时钟信号端CK连接以接收第一时钟信号，第一控制晶体管T2的第一极和第二节点N2连 接。
第二控制晶体管T3的栅极和第一时钟信号端CK连接以接收第一时钟信号，第二控制晶体管的第二极和第二电源线VGL连接以接收第二电压，第二控制晶体管T3的第一极和第二节点N2连接。
输出控制晶体管T4的栅极和第二节点N2连接，输出控制晶体管T4的第一极和第一电源线VGH连接以接收第一电压，输出控制晶体管T4的第二极和输出端GOUT连接。
第一电容的第一极和第二节点N2连接，第一电容C1的第二极和第一电源线VGH连接。
输出晶体管T5的栅极和第三节点N3连接，输出晶体管T5的第一极和第二时钟信号端CB连接，输出晶体管T5的第二极和输出端GOUT连接。
第二电容C2的第一极和第三节点N3连接，第二电容C2的第二极和输出端GOUT连接。
第一降噪晶体管T6的栅极和第二节点N2连接，第一降噪晶体管T6的第一极和第一电源线VGH连接以接收第一电压，第一降噪晶体管T6的第二极和第二降噪晶体管T7的第二极连接。
第二降噪晶体管T7的栅极和第二时钟信号端CB(第二时钟信号端CB和第二子时钟信号线GCB连接)连接以接收第二时钟信号，第二降噪晶体管T7的第一极和第一节点N1连接。
稳压晶体管T8的栅极和第二电源线VGL连接以接收第二电压，稳压晶体管T8的第二极和第一节点N1连接，稳压晶体管T8的第一极和第三节点N3连接。
图1B中所示的移位寄存器单元104中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平时导通(导通电平)，而在接入高电平时截止(截止电平)。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。
该移位寄存器单元包括但不限于图1B的配置方式，例如，移位寄存器单元104中的各个晶体管也可以采用N型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性进行连接即可。
需要说明的是，该移位寄存器单元中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，在本公开的实施例中，电容的电极可以采用金属电极或其中一个电极采用半导体材料(例如掺杂的多晶硅)。
图1C为图1B所示的移位寄存器单元104工作时的信号时序图。下面结合图1B和图 1C对该移位寄存器的工作过程进行详细地介绍。例如，以第一级移位寄存器单元104的工作原理进行说明，其余各级移位寄存器单元104的工作原理与其类似，不再赘述。如图1C所示，该移位寄存器单元104的工作过程包括4个阶段，分别为第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4，图1C示出了每个阶段中各个信号的时序波形。
在第一阶段t1，如图1C所示，第一时钟信号端CK接收低电平的第一时钟信号，触发信号线GSTV提供低电平的触发信号，所以输入晶体管T1和第二控制晶体管T3被导通，导通的输入晶体管T1将低电平的触发信号传输至第一节点N1，从而使得第一节点N1的电平变为低电平，所以第一控制晶体管T2和输出晶体管T5导通，由于稳压晶体管T8响应于第二电源线VGL提供的第二电压(低电平)一直处于导通状态，所以第三节点N3的电平与第一节点N1的电平相同，即低电平，同时，将该低电平存储至第二电容C2中。另外，导通的第二控制晶体管T3将低电平的第二电压VGL传输至第二节点N2，导通的第一控制晶体管T2将第一时钟信号的低电平传输至第二节点N2，从而使得第二节点N2的电平变为低电平，并存储在第一电容C1中，所以输出控制晶体管T4响应于第二节点N2的低电平导通，将第一电源线VGH提供的高电平的第一电压输出至输出端GOUT，同时，输出晶体管T5响应于第三节点N3的低电平导通，将第二时钟信号端CB接收的高电平的第二时钟信号传输至输出端GOUT，从而在此阶段，移位寄存器单元输出高电平。
在第二阶段t2，如图1C所示，第二时钟信号端CB接收低电平的第二时钟信号，所以第二降噪晶体管T7被导通，第一时钟信号端CK接收高电平的第一时钟信号，所以输入晶体管T1和第二控制晶体管T3被截止。由于第二电容C2的存储作用，所以第一节点N1可以继续保持上一阶段的低电平，所以第一控制晶体管T2以及输出晶体管T5被导通。由于第一控制晶体管T2导通，所以第一时钟信号端CK接收的高电平的第一时钟信号被传输至第二节点N2，所以，第二节点N2变为高电平，因此，第一降噪晶体管T6和输出控制晶体管T4截止，从而避免第一电源线VGH提供的高电平输出至输出端GOUT和第一节点N1。同时，由于输出晶体管T5导通，所以，在此阶段，输出端GOUT输出第二时钟信号端GB接收的低电平，例如，该低电平用于控制图1A中所示的像素单元103工作。
在第三阶段t3，如图1C所示，第一时钟信号端CK接收低电平的第一时钟信号，所以输入晶体管T1以及第二控制晶体管T3被导通，此时，触发信号线GSTV提供的高电平传输至第一节点N1和第三节点N3，所以输出晶体管T5和第一控制晶体管T2截止。第二时钟信号端CB接收高电平的第二时钟信号，所以第二降噪晶体管T7被截止。由于第二控制晶体管T3导通，所以第二电源线VGL提供的低电平传输至第二节点N2并存储在第一电容C1中，因此，输出控制晶体管T4和第一降噪晶体管T6导通，所以，在此阶段，输出端GOUT输出第一电源线VGH提供的高电平。
在第四阶段t4，如图1C所示，第一时钟信号端CK接收高电平的第一时钟信号，所以输入晶体管T1以及第二控制晶体管T3被截止。第二时钟信号端CB接收低电平的第二时钟信号，所以第二降噪晶体管T7被导通。由于第二电容C2的存储作用，所以第一节点 N1的电平保持上一阶段的高电平，从而使得第一控制晶体管T2和输出晶体管T5被截止。由于第一电容C1的存储作用，第二节点N2继续保持上一阶段的低电平，从而使得第一降噪晶体管T6被导通，从而使得第一电源线VGH提供的高电平通过导通的第一降噪晶体管T6以及第二降噪晶体管T7被传输至第一节点N1和第三节点N3，从而使得第一节点N1和第三节点N3继续保持为高电平，有效地防止了输出晶体管T5导通，从而避免了误输出。
图1D为图1B中所示的移位寄存器单元104在显示基板上的一种布局示意图。如图1D所示，该显示基板包括移位寄存器单元104的输入晶体管T1至稳压晶体管T8、第一电容C1至第二电容C2以及第一子时钟信号线GCK、第二子时钟信号线GCB、第一电源线VGH和第二电源线VGL。
例如，如图1D所示，输入晶体管T1包括“U”型的有源层和直线型(I型)栅极，该直线型栅极与该“U”型的有源层的双臂交叠从而实现双栅晶体管，且与第一降噪晶体管T6和第二降噪晶体管T7为水平排列，从而不论是在显示面板的水平方向上还是垂直方向上，该排列方式都占用了较大的空间；稳压晶体管T8的栅极和第二控制晶体管T3的第一极的距离较远，且分别连接在第二电源线VGL的不同的位置，增加了走线复杂度；第一控制晶体管T2与第二控制晶体管T3之间的节点通过一根很长的连接走线连接至第一降噪晶体管T6栅极，造成了空间拥挤等等。因此，图1D所示的显示基板上各个晶体管的排列方式和连接方式容易造成空间拥挤，不利于显示面板的窄边框设计的实现，且容易由于不必要的交叠使得寄生电容过大而产生信号窜扰等问题，影响显示面板的显示质量。
本公开至少一实施例提供一种显示基板，包括：衬底基板以及设置在衬底基板上的移位寄存器单元和第一时钟信号线，第一时钟信号线在衬底基板上沿第一方向延伸，且配置为向移位寄存器单元提供第一时钟信号；移位寄存器单元包括输入电路、输出电路、第一控制电路和输出控制电路；输入电路配置为响应于第一时钟信号将输入信号输入至第一节点；输出电路配置为将输出信号输出至输出端；第一控制电路配置为响应于第一节点的电平和第一时钟信号，控制第二节点的电平；输出控制电路配置为在第二节点的电平的控制下，对输出端的电平进行控制；第一控制电路包括第一控制晶体管和第二控制晶体管，第一控制晶体管的有源层和第二控制晶体管的有源层为一个连续的控制半导体层，控制半导体层沿第一方向延伸，第一控制晶体管的栅极和第二控制晶体管的栅极沿不同于第一方向的第二方向延伸且在第一方向上并排设置。
本公开至少一实施例还提供一种对应于上述显示基板的显示装置和显示基板的制作方法。
本公开上述实施例提供的显示基板优化了的移位寄存器单元的线路连接和结构布局，在一定程度上压缩了移位寄存器单元在第二方向上的长度，有利于实现显示面板的窄边框设计，同时保证了显示面板的显示质量。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
本公开至少一实施例提供一种显示基板。图2A为图1B中所示的移位寄存器单元104 在显示基板上的一种布局示意图。
例如，如图2A所示，该显示基板1包括：衬底基板10和设置在衬底基板10上的移位寄存器单元104、第一电源线VGH、第二电源线VGL以及多条时钟信号线(例如，图中所示的第一子时钟信号线GCK、第二子时钟信号线GCB和触发信号线GSTV)。例如，第一电源线VGH、第二电源线VGL和多条时钟信号线在衬底基板10上沿第一方向(例如，图2A中所示的竖直方向)延伸，且配置为向移位寄存器单元104分别提供第一电压、第二电压和多个时钟信号(例如，上面所述的触发信号、第一时钟信号或第二时钟信号等)。
需要注意的是，第一电源线VGH、第二电源线VGL以及多条时钟信号线可以沿第一方向平行设置，也可以交叉一定的角度(例如，小于等于20°)，本公开的实施例对此不作限制。
例如，第一电源线VGH配置为向扫描驱动电路包括的多个级联的移位寄存器单元104提供第一电压，第二电源线VGL配置为向扫描驱动电路包括的多个级联的移位寄存器单元104提供第二电压。例如，第一电压大于第二电压，例如第一电压为直流高电平，第二电压为直流低电平。
例如，该衬底基板10可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
例如，显示基板1包括像素阵列区(即图1A所示的有效显示区102，下面称作像素阵列区102)和除所述像素阵列区之外的周边区域，例如，上述第一电源线VGH、第二电源线VGL、多条时钟信号线和移位寄存器单元104位于周边区域内且位于衬底基板10的一侧(如图1A所示，位于像素阵列区102与衬底基板的侧边之间)，例如，如图1A所示，位于衬底基板的左侧，当然也可以位于衬底基板10的右侧或左右双侧，本公开的实施例对此不作限制。
例如，第二电源线VGL和多条时钟信号线位于移位寄存器单元104远离像素阵列区102的一侧，例如，均位于图2A所示的移位寄存器单元104的左侧，即移位寄存器单元104在衬底基板10的正投影位于第二电源线VGL和多条时钟信号线在衬底基板10的正投影与像素阵列区102之间；例如，第一电源线VGH位于移位寄存器单元104靠近像素阵列区102的一侧，即第一电源线VGH在衬底基板10的正投影位于移位寄存器单元104在衬底基板10的正投影和像素阵列区102之间。
需要注意的是，上述走线位置仅是示例性的，只要能满足走线的设置便于与移位寄存器单元的连接即可，本公开的实施例对此不作限制。
例如，像素阵列区102包括阵列排布的多个像素单元103。例如，多个像素单元103的每个包括像素电路，例如还可以进一步包括发光元件(图中未示出)。
例如，多个级联的移位寄存器单元104组成栅极驱动电路。例如，该多个移位寄存器单元104的输出端GOUT分别与位于像素阵列区的各行像素电路的栅极扫描信号端连接以向该各行像素电路提供输出信号(例如，栅极扫描号)，从而实现驱动发光元件发光。例 如，该像素电路可以是本领域内的例如包括7T1C、2T1C、4T2C、8T2C等电路结构的像素电路，在此不再赘述。
图2A中仅示出了栅极驱动电路中的第一级移位寄存器单元104和第二级移位寄存器单元104，例如，如图2A所示，第一级移位寄存器单元104的第一时钟端CK(如图1B所示)和第二子时钟信号线GCB连接以接收第一时钟信号，第一级移位寄存器单元104的第二时钟信号端CB和第一时钟信号GCK连接以接收第二时钟信号，第二级移位寄存器单元的第一时钟信号端CK和第一子时钟信号线GCK连接以接收第一时钟信号，第二级移位寄存器单元的第二时钟信号端CB和第二子时钟信号线GCB连接以接收第二时钟信号，以此类推，第X(X为大于1的奇数)级移位寄存器单元104的第一时钟端CK和第二子时钟信号线GCB连接以接收第一时钟信号，第X级移位寄存器单元104的第二时钟信号端CB和第一时钟信号GCK连接以接收第二时钟信号，第X+1级移位寄存器单元的第一时钟信号端CK和第一子时钟信号线GCK连接以接收第一时钟信号，第X+1级移位寄存器单元的第二时钟信号端CB和第二子时钟信号线GCB连接以接收第二时钟信号。需要注意的是，各级移位寄存器单元和时钟信号线的连接方式还可以采用本领域内的其他的连接方式，本公开的实施例对此不作限制。例如，第一级移位寄存器单元104的输入端和触发信号线GSTV连接以接收触发信号作为输入信号，第二级移位寄存器单元104的输入端和上一级移位寄存器单元(即，第一级移位寄存器单元)的输出端GOUT连接，其余各级移位寄存器单元的连接方式与此类似。下面以第一级移位寄存器单元的结构为例进行说明，本公开的实施例对此不作限制。
例如，在图2A所示的示例中，由于第一级移位寄存器单元104的第一时钟端CK(如图1B所示)和第二子时钟信号线GCB连接以接收第一时钟信号，第一级移位寄存器单元104的第二时钟信号端CB和第一时钟信号GCK连接以接收第二时钟信号，所以在该示例中，以第二子时钟信号线GCB为第一时钟信号线和第一子时钟信号线GCK为第二时钟信号线为例进行说明，本公开的实施例对此不作限制。
例如，如图1B所示，在一些示例中，该移位寄存器单元104包括输入电路1041、输出电路1043、第一控制电路1042和输出控制电路1044；在另一些示例中，该移位寄存器单元104还包括第二控制电路1045和稳压电路1046。
输入电路1041配置为响应于第一时钟信号将输入信号输入至第一节点N1。例如，输入电路1041和输入端IN、第一节点N1以及第一时钟信号端CK连接，配置为在第一时钟信号端CK接收的第一时钟信号的控制下导通，将输入端IN与第一节点N1连接，从而将输入信号输入至第一节点N1。例如，输入电路1041实现为上面所述的输入晶体管T1，输入晶体管T1的连接方式可参考上面的描述，在此不再赘述。
输出电路1043配置为将输出信号输出至输出端GOUT。例如，输出电路1043和第三节点N3、输出端GOUT以及第二时钟信号端CB连接，配置为在第三节点N3的电平的控制下导通，使得第二时钟信号端CB和输出端GOUT连接，从而在输出端GOUT输出第二 时钟信号，例如，输出第二时钟信号的低电平。例如，输出电路1043实现为上面所述的输出晶体管T5和第二电容C2，输出晶体管T5和第二电容C2的连接方式可参考上面的描述，在此不再赘述。
第一控制电路1042配置为响应于第一节点N1的电平和第一时钟信号，控制第二节点N2的电平。例如，第一控制电路和第一节点N1、第二节点N2以及第一时钟信号端CK连接，配置为在第一节点N1的电平的控制下导通，使得第二节点N2和第一时钟信号端CK连接，从而将第一时钟信号端CK提供的第一时钟信号提供至第二节点N2。例如，第一控制电路1042实现为上面所述的第一控制晶体管T2和第二控制晶体管T3，第一控制晶体管T2和第二控制晶体管T3的连接方式可参考上面的描述，在此不再赘述。需要注意的是，第一控制电路1042不限于与第一节点N1连接，还可以与其他独立的电压端(提供与第一节点N1的电压相同的电压)或者单独设置的一个与输入电路相同的电路连接，本公开的实施例对此不作限制。移位寄存器单元的其他电路的连接与此类似，在此不再赘述。
输出控制电路1044配置为在第二节点N2的电平的控制下，对输出端GOUT的电平进行控制。例如，输出控制电路1044和第二节点N2、第一电源线VGH以及输出端GOUT连接，且配置为在第二节点N2的电平的控制下，使得输出端GOUT与第一电源线VGH连接，从而将第一电源线VGH提供的第一电压输出至输出端GOUT，以将输出端GOUT控制在高电平，从而避免移位寄存器单元在非输出阶段的误输出。例如，输出控制电路1044实现为上面所述的输出控制晶体管T4和第一电容C1，输出控制晶体管T4和第一电容C1的连接方式可参考上面的描述，在此不再赘述。
第二控制电路1045与第一节点N1和第二节点N2连接，且配置为在第二节点N2的电平和第二时钟信号的控制下，对第一节点N1的电平进行控制。第二控制电路1045与第一节点N1、第二节点N2、第一电源线VGH和第二时钟信号端CB连接，配置为在第二节点N2的电平和第二时钟信号端CB接收的第二时钟信号的控制下导通，使得第一电源线VGH和第一节点N1连接，从而将第一节点N1的电位充电至高电平，以避免在非输出阶段输出电路1042导通，从而避免误输出。例如，第二控制电路1045实现为上面所述的第一降噪晶体管T6和第二降噪晶体管T7，第一降噪晶体管T6和第二降噪晶体管T7的连接方式可参考上面的描述，在此不再赘述。
稳压电路1046与第一节点N1和第三节点N3连接，且配置为稳定第三节点N3的电平。例如，稳压电路1046与第一节点N1、第三节点N3和第二电源线VGL连接，且配置为在第二电源线VGL提供的第二电压的控制下导通，使得第一节点N1和第三节点N3连接。例如，稳压电路1046实现为稳压晶体管T8，具体介绍可参考上面图1B中关于稳压晶体管T8的描述，在此不再赘述。
例如，稳压晶体管T8在第二电源线VGL提供的第二电压的控制下一直处于导通状态，使得第三节点N3通过该稳压晶体管T8与第一节点N1连接，从而防止第三节点N3的电平通过与第一节点N1连接的输入晶体管T1、第一控制晶体管T2以及第二降噪晶体管T7 漏电，同时还可以减小第三节点N3的电平对第一控制晶体管T1的应力，从而可以有助于保持第三节点N3的电平，使得输出晶体管T5在输出阶段可以充分打开。
图3A、图4A、图5A和图6A分别示出了图2A所示显示基板的移位寄存器单元的各层布线的平面图；图3B、图4B、图5B和图6B分别示出了图2B中所示显示基板的移位寄存器单元的各层布线的平面图。图3A和图3B为本公开至少一实施例提供显示基板的半导体层的平面图，图4A和图4B为本公开至少一实施例提供显示基板的第一导电层的平面图，图5A和图5B为本公开至少一实施例提供的显示基板的第二导电层的平面图，图6A和图6B为本公开至少一实施例提供的显示基板的第三导电层的平面图。图7A为为图2A所示的显示基板的一个示例的剖面图；图7B为图2A所示的显示基板沿A-A`方向的另一个示例的剖面图；图7C为图2B所示的显示基板沿B-B`方向的一个示例的剖面图。
例如，层间绝缘层(例如，包括第一绝缘层、第二绝缘层、第三绝缘层等)可以位于图3A至图6A或图3B至图6B所示的层结构之间。例如，第一绝缘层350(如图7A所示)位于图3A所示的半导体层310和图4A所示的第一导电层320之间或位于图3B所示的半导体层310和图4B所示的第一导电层320之间，第二绝缘层360(如图7A所示)位于图4A所示的第一导电层320和图5A所示的第二导电层330之间或图4B所示的第一导电层320和图5B所示的第二导电层330之间，第三绝缘层370(如图7A所示)位于图5A所示的第二导电层330和图6A所示的第三导电层340之间或位于图5B所示的第二导电层330和图6B所示的第三导电层340之间。
例如，如图7A、7B和7C所示，该显示基板还包括第四绝缘层380，该第四绝缘层380位于第三导电层340上，用于保护第三导电层340。
例如，第一绝缘层350、第二绝缘层360、第三绝缘层370以及第四绝缘层380的材料可以包括例如SiNx、SiOx、SiNxOy等无机绝缘材料、例如有机树脂等有机绝缘材料，或其它适合的材料，本公开的实施例对此不作限定。
需要注意的是，图2A所示的显示基板以扫描驱动电路中的前两级移位寄存器和与其连接的第一电源线、第二电源线以及信号线的布局设计为例进行说明，其余各级移位寄存器的布局实施方式可以参考图2A中所示的布局方式，在此不再赘述，当然也可以采用其他的布局方式，本公开的实施例对此不作限制。当然，其余各个扫描驱动电路的各级移位寄存器也可以参考图2A中所示的布局方式，也可以采用其他的布局实式，本公开的实施例对此不作限制。
下面结合图2A-图7C对本公开至少一实施例提供的显示基板进行详细地介绍。
例如，图2A中所示的移位寄存器单元104的输入晶体管T1至稳压晶体管T8的有源层可以形成在图3A所示的半导体层310上。图2B中所示的移位寄存器单元104的输入晶体管T1至稳压晶体管T8的有源层可以形成在图3B所示的半导体层310上。半导体层310可采用半导体材料图案化形成。例如，如图3A和图3B所示，根据需要，该半导体层310可以短棒状或具有弯曲或弯折的形状，可用于制作上述输入晶体管T1至稳压晶体管T8的 有源层。各有源层可包括源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区。例如，沟道区具有半导体特性；源极区域和漏极区域在沟道区的两侧，并且可掺杂有杂质，并因此具有导电性。例如，该源极区域为有源层的一部分，与该源极区域接触的金属电极(例如，位于第三导电层340)对应于晶体管的源极(或叫做第一极)，漏极区域为有源层的一部分，与该漏极区域接触的金属电极(例如，位于第三导电层340)对应于晶体管的漏极(或叫做第二极)。例如，源极区域通过贯穿第一绝缘层350、第二绝缘层360以及第三绝缘层370的过孔与其对应的金属电极(第一极)连接，漏极区域通过贯穿第一绝缘层350、第二绝缘层360以及第三绝缘层370的过孔与其对应的金属电极(第二极)连接。
例如，如图7A所示，以第一控制晶体管T2为例，该第一控制晶体管T2的有源层包括源极区域S2、漏极区域D2和沟道区P2，该第一控制晶体管T2还包括栅极G2，其中，栅极G2位于第一导电层320；以第一降噪晶体管T6为例，该第一降噪晶体管T6的有源层包括源极区域S6、漏极区域D6和沟道区P6，该第一降噪晶体管T6还包括栅极G6，其中，栅极G6位于第一导电层320，其余晶体管与此类似，在此不再赘述。
例如，半导体层310的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
需要注意的是，在另一些示例中，各个晶体管的第一极和第二极也可以位于其他导电层，通过位于其和半导体层中间的绝缘层中的过孔与其对应的有源层连接，本公开的实施例对此不作限制。
图4A和图4B示出了该显示基板的第一导电层320，第一导电层320设置在第一绝缘层上，从而与半导体层310绝缘。例如，第一导电层320可包括第一电容C1至第二电容C2的第一电极CE11、CE12以及输入晶体管T1至稳压晶体管T8的栅极和与栅极直接连接的各条走线(例如，第一连接走线L1和第三连接走线L2)、连接电极，相应地第一绝缘层也作为栅极绝缘层。如图4A所示，输入晶体管T1至稳压晶体管T8的栅极为用虚线圈起来的部分，即为各个晶体管的半导体层结构与第一导电层320上的走线交叠的部分。
如图4B所示，该第一导电层320还可以包括中间转接电极11，例如，在该示例中，该中间转接电极11与第一降噪晶体管T6的栅极G6一体形成。例如，在该示例中，第一连接走线L1可以不位于图4B所示的第一导电层320，例如，位于图6B所示的第三导电层340，本公开的实施例对此不作限制，只要能实现晶体管之间的连接即可。
图5A和图5B示出了该显示基板的第二导电层330，第二导电层330包括第一电容C1至第二电容C2的第二电极CE21、CE22。第二电极CE21与第一电极CE11至少部分重叠以形成第一电容C1，第二电极CE22与第一电极CE12至少部分重叠以形成第二电容C2。例如，图5A中所示的第二导电层330还包括中间转接电极11。
例如，图5B所示的示例与图5A所示的示例类似，区别仅在于该第二导电层330不包括中间转接电极11，即在图2B所示的显示基板中，中间转接电极11还可以不位于该第二导电层330，例如，位于图4B所示的第一导电层320，本公开的实施例对此不作限制。
图6A和图6B示出了该显示基板的第一级移位寄存器单元和第二级移位寄存器单元的第三导电层340，第三导电层340包括多条信号线(例如，与第一级移位寄存器单元104的输入端连接的触发信号线GSTV、第一子时钟信号线GCK和第二子时钟信号线GCB)、第一电源线VGH、第二电源线VGL以及基准电压线Vinit等。需要注意的是，该第三导电层340还包括连接各个晶体管、电容以及信号线之间的第一转接电极17、第二转接电极18、第三转接电极16、信号输入电极13、第二连接走线(包括第一连接子走线L3和第二连接子走线L4)以及第四连接走线走线L5等。
如图2A至图6B所示，多条信号线、第一电源线VGH、第二电源线VGL通过图5C或图5D所示的至少一个过孔与其余各层中需要与其连接的晶体管以及电容连接，各个晶体管、电容之间也通过至少一个过孔连接，或通过转接电极桥接，在此不再赘述。
例如，上述第三导电层340的材料可以包括钛、钛合金、铝、铝合金、铜、铜合金或其他任意适合的复合材料，本公开的实施例对此不作限定。例如，第一导电层320和第二导电层330的材料可以与第三导电层340的材料相同，在此不再赘述。
图2A为上述图3A所示的半导体层310、图4A所示的第一导电层320、图5A所示的第二导电层330和图6A所示的第三导电层340的层叠位置关系的示意图。图2B为上述图3B所示的半导体层310、图4B所示的第一导电层320、图5B所示的第二导电层330和图6B所示的第三导电层340的层叠位置关系的示意图。
如图2A、图3A或图2B、图3B所示，在至少一个示例中，输入晶体管T1的有源层为沿第二方向延伸的长条形，第二方向不同于所述第一方向。例如，第一方向与所述第二方向的夹角在70°到90°之间，并包括70°和90°。例如，第一方向与所述第二方向的夹角为70°、90°或80°等，可根据实际情况设定，本公开的实施例对此不作限制。例如，在一些示例中，该输入晶体管T1的有源层的沟道区域在衬底基板10上呈“I”字型，且沟道区域的沟道长度方向为垂直于第一方向的第二方向(例如，图中的横向)，当然本公开的实施例对此不作限制，只要能缩短显示面板的在第一方向上的长度即可。例如，该沟道长度方向为载流子由输入晶体管T1的第一极流向第二极的方向；两个并列(且例如彼此电连接)栅极与输入晶体管T1的长条形的有源层(“I”字型有源层)分别重叠，由此得到“I”字型双栅晶体管。当然，也可以是单个栅极与输入晶体管T1的长条形的有源层重叠，本公开的实施例对此不作限制。
由于输入晶体管T1的有源层(需要注意的是，这里指的是输入晶体管T1的有源层的整体形状)由图1D所示的“U”型结构变更为沿第二方向延伸的长条形(例如，沿第二方向的“I”字型结构，例如，“一”字型)，所以可以缩短显示面板的在第一方向上的长度，即显示面板的垂直高度，有利于其他晶体管(例如，第一降噪晶体管T6和第二降噪晶体 管T7)排列在输入晶体管T1下方。
例如，如图3A或图3B所示，第一降噪晶体管T6的有源层和第二降噪晶体管T7的有源层由一个连续的降噪半导体层A11形成(即一体设置)，该降噪半导体层A11沿第一方向延伸，且与输入晶体管T1的有源层在第一方向上并排设置，即，输入晶体管T1和第一降噪晶体管T6和第二降噪晶体管T7沿第一方向上下并排设置。例如，输入晶体管T1的有源层位于第一降噪晶体管T6的有源层和第二降噪晶体管T7的有源层沿第一方向延伸的假想线上。
例如，如图2A、2B和图3A所示，第一降噪晶体管T6的有源层可以与第二降噪晶体管T7的有源层在第一方向上部分重叠(如图2A和图3A所示)或完全重叠(如图2B和图3B所示)，即第一降噪晶体管T6的有源层可以在第二降噪晶体管T7的有源层沿第一方向延伸的假想线上；第一降噪晶体管T6的有源层也可以与第二降噪晶体管T7的有源层在第一方向上不重叠，例如，如图2A和图3A所示，第一降噪晶体管T6的有源层也可以与第二降噪晶体管T7的有源层在第一方向上错开一定的距离，只要不影响其他结构的排布以及过多增加移位寄存器单元的宽度即可，且只要在第一方向上第一降噪晶体管T6和第二降噪晶体管T7位于输入晶体管T1的下面即可，本公开的实施例对此不作限制。
在本公开实施例中，输入晶体管T1与第一降噪晶体管T6和第二降噪晶体管T7由图1D中的水平并列设置的结构变为上下罗列的结构，可以减少显示面板的周边区域的沿第二方向的宽度，例如，图1A所示的水平宽度，从而有利于显示面板的窄边框设计的实现。
例如，第一降噪晶体管T6的栅极和第二降噪晶体管T7的栅极沿第二方向延伸并在第一方向上并排设置，例如，第一降噪晶体管T6的栅极和第二降噪晶体管T7的栅极可以平行，例如，均沿第二方向延伸，也可以第一降噪晶体管T6的栅极的延伸方向和第二降噪晶体管T7的栅极的延伸方向不平行，例如相交一定的角度，例如，该交叉角度小于等于20°，或者二者与水平线的角度小于等于20°，本公开的实施例对此不做限制，只要第一降噪晶体管T6和第二降噪晶体管T7一体设置且为沿第一方向上下排列的结构即可。
例如，输入晶体管T1的第一极、第一控制晶体管T2的栅极、第二降噪晶体管T7的第一极和下面描述的稳压晶体管T8的第二极均与第一节点N1连接，例如，输入晶体管T1的第一极、第一控制晶体管T2的栅极和第二降噪晶体管T7的第一极之间通过过孔连接。第二节点N2与第一降噪晶体管T6的栅极、输出控制晶体管T4的栅极、第一控制晶体管T2的第一极、第一电容C1的第一极和第二控制晶体管T3的第一极连接，例如，如图2A所示，第一降噪晶体管T6的栅极、输出控制晶体管T4的栅极、第一控制晶体管T2的第一极、第一电容C1的第一极和第二控制晶体管T3的第一极之间通过过孔连接。第三节点N3与稳压晶体管T8的第一极、输出晶体管T5的栅极和第二电容C2的第一极连接，例如，稳压晶体管T8的第一极、输出晶体管T5的栅极和第二电容C2的第一极之间通过过孔连接。
例如，如图6A所示，该移位寄存器单元还包括第一转接电极17、第二转接电极18 和第三转接电极16。
例如，第一转接电极17与输入晶体管T1的第一极、第一控制晶体管T2的栅极、稳压晶体管T8的第二极和第二降噪晶体管T7的第一极连接。例如，第一转接电极17通过贯穿第二绝缘层360和第三绝缘层370的过孔与第一控制晶体管T2的栅极连接，第一转接电极17与输入晶体管T1的第一极、稳压晶体管T8的第二极和第二降噪晶体管T7的第一极位于同一层(例如，均位于第三导电层340)且一体设置。例如，第一节点N1包括第一转接电极17，即，第一转接电极17充当了第一节点N1，将输入晶体管T1、第一控制晶体管T2、稳压晶体管T8和第二降噪晶体管T7的相应电极连接起来。
例如，第一转接电极17为位于第一控制晶体管T2、第二控制晶体管T3、稳压晶体管T8和第一降噪晶体管T6、第二降噪晶体管T7之间且沿第一方向弯折延伸的折线，其起点为输入晶体管T1的第一极，终点为第二降噪晶体管T7的第一极。由于第一降噪晶体管T6和第二降噪晶体管T7与输入晶体管T1沿第一方向并排设置，第一控制晶体管T2和第二控制晶体管T3也沿第一方向并排设置，即第一降噪晶体管T6和第二降噪晶体管T7与第一控制晶体管T2和第二控制晶体管T3之间的间距较小，使得该第一转接电极17在第一方向上的延伸长度大于在第二方向上的延伸长度，因此，缩短了连接这些晶体管的第一转接电极17的长度和在第二方向上的宽度，从而有利于实现窄边框。
例如，第二转接电极18与稳压晶体管T8的第一极和输出晶体管T5的栅极连接。例如，第二转接电极18通过贯穿第二绝缘层360和第三绝缘层370的过孔与输出晶体管T5的栅极连接，第二转接电极18与稳压晶体管T8的第一极位于同一层(例如，均位于第三导电层340)且一体设置。例如，第三节点N3包括第二转接电极18，即，第二转接电极18充当了第三节点N3，将稳压晶体管T8和输出晶体管T5连接起来。
例如，如图4A所示，输入晶体管T1包括第一栅极G1、第二栅极G1`和连接第一栅极G1和第二栅极G1`的连接电极(G11-G13)。连接电极(G11-G13)与第一栅极G1和第二栅极G1`位于同一层，包括沿第一方向(例如，如图4A所示的竖直方向)延伸的与第一栅极G1连接的第一部分G11和与第二栅极G1`连接的第二部分G12，以及沿第二方向(例如，如图4A所示的水平方向)延伸且连接第一部分G11和第二部分G12的第三部分G13，输入晶体管T1的第一栅极G1和第二栅极G1`通过连接电极的第三部分G13与提供第一时钟信号的第一时钟信号线连接以接收第一时钟信号。
例如，第一栅极G1和第二栅极G1`先通过连接电极(G11-G13)连接在一起，再连接到第一时钟信号线。例如，还可以采用将输入晶体管T1的栅极和第二控制晶体管T3的栅极连接在一起，在整体连接至第一时钟信号线，例如，采用图1D中所示的连接方式，本公开的实施例对此不作限制。
例如，如图2A所示，对于第一级移位寄存器单元，该提供第一时钟信号的第一时钟信号线为第二子时钟信号线GCB，对于第二级移位寄存器单元该第一时钟信号的第一时钟信号线为第一子时钟信号线GCK，本公开的实施例对此不作限制。
例如，在一些示例中，第一控制晶体管T2的有源层第二极可以直接通过走线与第二子时钟信号线GCB连接的。例如，如图6A所示，在另一些示例中，该移位寄存器单元还包括转接电极15，在该示例中，第一控制晶体管T2的第二极并非直接通过走线与第二子时钟信号线GCB连接，也可以通过转接电极15连接至连接电极的第三部分G13连接，以与连接电极的第三部分G13同时连接至第二子时钟信号线GCB以接收第一时钟信号。本公开的实施例对此不做限制。
例如，输入晶体管T1的有源层通过沿第二方向延伸的第一连接走线L1与信号输入电极连接以接收输入信号；该信号输入电极作为移位寄存器单元104的输入端IN，例如为位于图6A所示的第三导电层中的信号输入电极13。例如，该信号输入电极13可以是单独提供的电极，例如，如图6A所示的第一级移位寄存器单元的第三导电层所示，也可以是输出晶体管T5的第二极(输出晶体管T5的第二极作为输出电路1043的输出端GOUT)的延伸区域作为该信号输入电极13，例如，当前级移位寄存器单元的输出晶体管T5的第二极(即与输出晶体管T5的有源层的漏极区域连接的金属电极)作为输出电路1043的输出端GOUT，且与移位寄存器单元(例如，第一级移位寄存器单元)相邻的下级移位寄存器单元(例如，第二级移位寄存器单元)的信号输入电极连接以作为下级移位寄存器单元的输入信号，本公开的实施例对此不作限制。
例如，如图2A、图4A和图6A所示，移位寄存器单元还包括走线转接电极12。例如，该走线转接电极12位于第三导电层340。例如，走线转接电极12与输入晶体管T1的有源层位于不同层，例如，输入晶体管T1的第一极与走线转接电极12的第一端121电连接，例如，输入晶体管T1的第一极与走线转接电极12位于同一层，且一体设置形成。例如，输入晶体管T1的有源层的源极区域通过贯穿第一绝缘层350、第二绝缘层360和第三绝缘层370的过孔与输入晶体管T1的第一极连接，走线转接电极12的第二端122与不在相同层的沿第二方向延伸的第一连接走线L1(位于图4A所示的第一导电层320)的第一端L11通过贯穿第二绝缘层360和第三绝缘层370的过孔连接，沿第二方向延伸的第一连接走线L1的第二端L12与不在相同层的信号输入电极13(位于第三导电层340)通过贯穿第二绝缘层360和第三绝缘层370的过孔电连接，从而实现输入晶体管T1和输入端IN的连接。例如，走线转接电极12与信号输入电极13位于同一层。
例如，如图2B和6B所示，该第一连接走线L1还可以形成在第三导电层340，与走线转接电极12和信号输入电极13直接连接(即不通过过孔连接)，即一体形成，本公开的实施例对此不作限制，只要能够实现输入晶体管T1和信号输入电极13的连接即可。
例如，在本公开的一些实施例中，第一控制晶体管T2的有源层和第二控制晶体管T3的有源层由一个连续的控制半导体层A12形成(即一体设置)，该控制半导体层A12沿第一方向延伸，第一控制晶体管T2的栅极和第二控制晶体管T3的栅极沿第二方向平行延伸且在第一方向上彼此重叠，即第一控制晶体管T2的栅极和第二控制晶体管T3的栅极在第一导电层320上沿第一方向上下排列设置。需要注意的是，为了表述清楚、简洁，将A11 和A12命名为不同的半导体层，但降噪半导体层A11和控制半导体层A12均位于图3A或图3B所示的同一半导体层330。
例如，如图2A和图4A所示，第二控制晶体管T3在衬底基板10上的正投影和第一控制晶体管T2在衬底基板10上的正投影在第一方向上位于第二子连接走线L4的两侧。当然，第一控制晶体管T2的栅极的延伸方向和第二控制晶体管T3的栅极的延伸方向也可以不平行，例如相交一定的角度，例如，该交叉角度小于等于20°，或者二者与水平线的角度小于等于20°，本公开的实施例对此不做限制。
例如，如图2A、2B和图3A、图3B所示，第一控制晶体管T2的有源层可以与第二控制晶体管T3的有源层在第一方向上部分重叠(如图2A和图3A所示)或完全重叠(图中未示出)，即第一控制晶体管T2的有源层可以在第二控制晶体管T3的有源层沿第一方向延伸的假想线上；第一控制晶体管T2的有源层也可以与第二控制晶体管T3的有源层在第一方向上不重叠，例如，如图2A和图3A所示，第一控制晶体管T2的有源层与第二控制晶体管T3的有源层在第一方向上错开一定的距离，只要不影响其他结构的排布以及过多增加移位寄存器单元的宽度即可，且只要在第一方向上第一控制晶体管T2的有源层和第二控制晶体管T3的有源层位于输入晶体管T1的下面即可，本公开的实施例对此不作限制。
例如，第一控制晶体管T2的有源层、第二控制晶体管T2的有源层和输入晶体管T1的有源层在第二方向并排设置。例如，在一些示例中，第一控制晶体管T2的有源层和第二控制晶体管T3的有源层与输入晶体管T1的有源层沿第二方向延伸的假想线相交，即第一控制晶体管T2的有源层和第二控制晶体管T3的有源层位于输入晶体管T1的有源层沿第二方向延伸的假想线上。例如，在本公开的实施例中，对移位寄存器单元中除第一控制晶体管T2和第二控制晶体管T3之外的其他晶体管不作限制，只要能够满足电路的连接关系即可。
由此，在本公开的实施例中，第一控制晶体管T2和第二控制晶体管T3的排列方式由图1D所示的沿第二方向左右排列的结构变为沿第一方向上下排列的结构，可以减小显示面板的周边区域的水平宽度以及减小晶体管到信号线和第二电源线的距离，从而有利于实现显示面板的窄边框设计。
例如，在本公开的一些实施例中，输入晶体管T1的有源层还位于第一降噪晶体管T6的有源层和第二降噪晶体管T7的有源层在沿第一方向延伸的假想线上，第一控制晶体管T2的有源层和第二控制晶体管T3的有源层与第一降噪晶体管T6的有源层和第二降噪晶体管T7的有源层在第二方向相对并排设置，从而可以减小第一控制晶体管T2的有源层、第二控制晶体管T3的有源层距第一降噪晶体管T6的有源层和第二降噪晶体管T7的有源层之间的间距。
例如，在一些示例中，该移位寄存器单元还包括中间转接电极11。第一降噪晶体管T6的栅极通过图5A中所示的位于第二导电层330中的中间转接电极11和图6A中的第二 连接子走线L4连接至第一控制晶体管T2的第一极和第二控制晶体管T3的第一极，即与第一控制晶体管T2的有源层和第二控制晶体管T3的有源层之间的部分连接，且中间转接电极11在衬底基板10上的正投影与第一控制晶体管T2的有源层和第二控制晶体管T3的有源层在衬底基板10上的正投影在第一方向上不重叠，即中间转接电极11在衬底基板10上的正投影位于第一控制晶体管T2的有源层和第二控制晶体管T3的有源层在衬底基板10上的正投影以及第一降噪晶体管T6在衬底基板10上的正投影之间。
由此，在本公开的实施例中，第一控制晶体管T2和第二控制晶体管T3的排列方式由图1D所示的沿第二方向的左右排列的结构变为图2A中所示的沿第一方向的上下排列的结构，输入晶体管T1和第一降噪晶体管T6以及第二降噪晶体管T7的排列方式和位置也改变为沿第一方向的上下排列的结构，从而缩短了第一降噪晶体管T6在衬底基板10上的正投影至第一控制晶体管T2和第二控制晶体管T3在衬底基板10上的正投影之间的距离，从而大大缩短了连接第一降噪晶体管T6的栅极和第一控制晶体管T2和第二控制晶体管T3处的走线(即中间转接电极11)的长度，很大程度上优化了由于走线密集和过长造成的空间拥挤的问题。
例如，在一些示例中，中间转接电极11的连接方式如图7A或图7B所示。例如，在该示例中，中间转接电极11位于第二导电层11。例如，如图7A所示，第一绝缘层350在垂直于衬底基板10的方向上位于第一降噪晶体管T6的有源层(例如，位于半导体层310，包括源极区域S6、漏极区域D6和沟道区P6)和第一降噪晶体管T6的栅极G6之间；第二绝缘层360在垂直于衬底基板10的方向上位于第一降噪晶体管T6的栅极G6和中间转接电极11之间。
例如，如图7A所示，在一些示例中，第一降噪晶体管T6的栅极通过贯穿第二绝缘层360的过孔H22与中间转接电极11的第一端111连接，第一控制晶体管T2第一极S21与中间转接电极11位于同一层，且与中间转接电极11的第二端112连接，即中间转接电极11与第一控制晶体管T2第一极S21一体设置，从而实现第一降噪晶体管T6的栅极与第一控制晶体管T2的第一极的连接。第一控制晶体管T2第一极S21与第一控制晶体管T2的有源层的源极区域S2(即第一控制晶体管T2的第一极)通过贯穿第一绝缘层350和第二绝缘层360的过孔H11连接。例如，在一些示例中，第二节点N2包括中间转接电极11。需要注意的是，为了表述清楚、简洁，图7A中仅示出了第一控制晶体管T2第一极S21与中间转接电极11的第二端112连接，由于第一控制晶体管T2的第一极和第二控制晶体管T3的第一极连接，所以第二控制晶体管T3的第一极也与中间转接电极11的第二端112连接，本公开的实施例对此不作限制。以下实施例与此相同，不再赘述。
例如，如图5C和7B所示，在另一些示例中，该移位寄存器单元104还包括第二连接走线，例如，第二连接走线包括第一连接子走线L3和第二连接子走线L4。例如，第三绝缘层370在垂直于衬底基板10的方向上位于中间转接电极11和第二连接走线L3/L4之间。
例如，第一降噪晶体管T6的栅极G6通过贯穿第二绝缘层360和第三绝缘层370的过 孔H4与第一连接子走线L3连接，中间转接电极11的第一端111通过贯穿第三绝缘层370的过孔H3和第一连接子走线L3连接。
例如，第一控制晶体管T2的有源层的源极区域S2通过贯穿第一绝缘层350、第二绝缘层360和第三绝缘层370的过孔H1与第一控制晶体管T2的第一极S21连接，第一控制晶体管T2的第一极S21与第二连接子走线L4连接，第一控制晶体管T2的第一极S21位于同一层且一体设置，中间转接电极11的第二端通过贯穿第三绝缘层370的过孔H2与第二连接子走线L4连接，从而实现第一降噪晶体管T6的栅极与第一控制晶体管T2的第一极的连接。
例如，在该示例中，第二节点N2包括中间转接电极11和第二连接走线。
例如，在另一些示例中，第二连接走线仅包括第一连接子走线L3或第二连接子走线L4。例如，在图2B和7C所示的示例中，以第二连接走线仅包括第二连接子走线L4为例进行介绍，当然本公开的实施例对此不作限制。
例如，如图5C和7C所示，在该示例中，中间转接电极11可以位于第一导电层320，且与第一降噪晶体管T6的栅极一体形成。
例如，如图7C所示，第一控制晶体管T2的有源层的源极区域S2通过贯穿第一绝缘层350、第二绝缘层360和第三绝缘层370的过孔H1与即第一控制晶体管T2的第一极S21连接，第一控制晶体管T2的第一极S21与第二连接子走线L4连接，第一控制晶体管T2的第一极S21与第二连接子走线L4位于同一层且一体设置，中间转接电极11的第二端112通过贯穿第三绝缘层370的过孔H2与第二连接子走线L4连接，从而实现第一降噪晶体管T6的栅极与第一控制晶体管T2的第一极的连接。
例如，在该示例中，第二节点N2包括中间转接电极11和第二连接子走线L4。
例如，如图6A所示，第二电源线VGL包括在第二方向上突出的突出部14。稳压晶体管T8的有源层在第二方向上位于第二控制晶体管T3的有源层和第二降噪晶体管T7的有源层之间，且第二控制晶体管T3的第二极和稳压晶体管T8的栅极均与第二电源线VGL上的突出部14连接，例如第二控制晶体管T3的第二极与第二电源线VGL上的突出部14位于同一层，且一体形成，稳压晶体管T8的栅极与不在相同层的第二电源线VGL上的突出部14例如通过贯穿第二绝缘层360和第三绝缘层370的过孔连接以接收第二电压；例如，用于连接第二控制晶体管T3的第二极和第二控制晶体管T3的有源层的漏极区域的过孔，与用于连接稳压晶体管T8的栅极和突出部14的过孔，分别与突出部14的不同侧重叠(例如如图2A所示分别与突出部14的沿第一方向的上侧和下侧重叠)，例如分别位于突出部14的不同对角(例如如图2A所示分别与突出部14的沿第一方向的左上角和右下角重叠)。
在本公开的实施例中，第一控制晶体管T2和第二控制晶体管T3由图1D所示的沿第二方向的左右并列设置改为图2A中所示的沿第一方向的上下罗列的结构，可以缩小显示面板的周边区在第二方向的宽度，从而可以拉近其他晶体管(例如，稳压晶体管T8)与第二电源线VGL的距离，同时，由于第二控制晶体管T3的第二极(例如，源极)与稳压晶 体管T8的栅极共同连接到第二电源线VGL上的突出部14，所以在空间上更靠近，从而减小了走线长度，有利于显示面板的窄边框的实现。
例如，如图2A和图5A所示，第一电容C1的第一极CE11和第二极CE12包括缺口，与沿第二方向延伸的第一连接走线L1连接的信号输入电极13形成在第一电容C1的缺口中，例如，信号输入电极13在衬底基板上的正投影落入第一电容C1在衬底基板上的正投影的缺口中，使得第一电容C1的第一极CE11和第二极CE12的形状与信号输入电极13互补，充分利用了显示基板上的空间，从而有利于实现显示面板的窄边框设计。
需要注意的是，第一电容C1的电容的形状虽然变了，但是第一电容C1的尺寸/大小一般不会变化，例如，尺寸变化可以上下浮动10％～20％，其具体形状根据可以其他结构来设计安排，本公开的实施例对此不作限制。
例如，如图2A和图4A所示，连接提供第二时钟信号的时钟信号线(例如第一子时钟信号线GCK)与第二降噪晶体管T7的栅极的第三连接走线L2(位于第一导电层320)在衬底基板10上的正投影与第二降噪晶体管T7的有源层在衬底基板10上的正投影在第一方向上重叠，且至少部分与第二降噪晶体管T7的栅极平行，即该第三连接走线L2从第二降噪晶体管T7的有源层的远离信号线的一侧(例如，如图2A所示的第二降噪晶体管T7的有源层的右侧)通过。
例如，如图2A和图4A所示，第三连接走线L2包括第三子连接走线L21和第四子连接走线L22，第三子连接走线L21沿第一方向延伸，且在衬底基板10的正投影与第二降噪晶体管T7的有源层在衬底基板10上的正投影沿第二方向相对并排设置，第四子连接走线L22与第三子连接走线L21连接且沿第二方向延伸。
例如，在一些示例中，如图4A所示，第三连接走线L2为一条栅极走线，即该第三子连接走线L21和第四子连接走线L22是直接连接(不需要过孔连接)且一体形成的，例如，第四子连接走线L22与提供第二时钟信号的第一子时钟信号线GCK连接。例如，在另一示例中，如图4B所示，第三连接走线L2包括两条通过过孔连接的栅极走线，一条是第三子连接走线L21，另一条是第四子连接走线L22。第三子连接走线L21和第四子连接走线L22的连接关系将在下面进行详细地介绍。
例如，连接第四子连接走线L22与第二降噪晶体管T7的栅极的第三子连接走线L21也与不在相同层的输出晶体管T5输出晶体管T5的第一极通过过孔连接，以将输出晶体管T5的第一极连接到第二时钟信号端CB，例如，第二时钟信号端CB与第一子时钟信号线GCK连接。例如，输出晶体管T5的第一极与第三子连接走线L21电连接，第三子连接走线L21位于第二降噪晶体管T7的有源层靠近输出晶体管T5的一侧。例如，该过孔在衬底基板10上的正投影位于第二降噪晶体管T7的有源层在衬底基板10上的正投影和输出晶体管T5有源层在衬底基板10上的正投影之间。例如，第四子连接走线L22在第一导电层320，其在衬底基板10上的正投影位于第X级移位寄存器单元的稳压晶体管T8在衬底基板10上的正投影和第X+1级移位寄存器单元的输入晶体管T1在衬底基板10上的正投影 之间。
例如，输出晶体管T5的栅极与稳压晶体管T8的第一极电连接，输出晶体管T5的第二极连接输出端GOUT。
例如，在一些示例中，如图2A、图4A、图5C和图7D所示，所示，输出晶体管T5的第一极S51通过贯穿第一绝缘层350、第二绝缘层360和第三绝缘层370的过孔H7与输出晶体管T5的源极区域S5连接，输出晶体管T5的第一极S51与第四连接走线L5连接，例如，输出晶体管T5的第一极S51与第四连接走线L5位于同一层且一体形成，第四连接走线L5通过贯穿第二绝缘层360和第三绝缘层370的过孔H5和过孔H6与第三子连接走线L21连接，第三子连接走线L21与第二降噪晶体管T7的栅极以及与第四子连接走线L22连接，从而实现输出晶体管T5的第一极S51与第二降噪晶体管T7的栅极G7连接，并一起连接至第一子时钟信号线GCK以接收第二时钟信号。
例如，在另一些示例中，如图2B、图4B、图5D、图6B和图7E所示，输出晶体管T5的第一极与第四连接走线L5连接，输出晶体管T5的第一极S51与第四连接走线L5，第四连接走线L5的第一端L51通过贯穿第二绝缘层360和第三绝缘层370的过孔H8和过孔H9与位于第二导电层320的第三子连接走线L21连接，第四连接走线L5的第二端L52通过贯穿第二绝缘层360和第三绝缘层370的过孔H5和过孔H6与位于第二导电层320的第四子连接走线L22连接，第三子连接走线L21与第二降噪晶体管T7的栅极G7直接连接且一体形成，从而实现输出晶体管T5的第一极与第二降噪晶体管T7的栅极G7连接，并通过第四连接走线L5和第四子连接走线L22一起连接至第一子时钟信号线GCK以接收第二时钟信号。
例如，如图2A、图3A和图4A所示，输出控制晶体管T4有源层和输出晶体管T5的有源层由一个第一输出半导体层A13和第二输出半导体层A14形成(即输出控制晶体管T4有源层和输出晶体管T5的有源层一体设置)并沿第一方向延伸。例如，输出控制晶体管T4的有源层位于输出晶体管T5的有源层在第一方向上的假想线上，例如，输出控制晶体管T4的有源层包括第三半导体层的A13和第四半导体层A14的沿第一方向的上半部分，输出晶体管T5的有源层包括第三半导体层A13和第四半导体层A14的沿第一方向的下半部分。需要注意的是，输出控制晶体管T4的有源层和输出晶体管T5的有源层分别占第三半导体层A13和第四半导体层A14的比例可根据实际情况设置，本公开的实施例对此不作限制。例如，输出控制晶体管T4的栅极和输出晶体管T5的栅极沿第二方向延伸且在第一方向上彼此重叠,即输出控制晶体管T4和输出晶体管T5沿第一方向上下排列设置。例如，输出控制晶体管T4的栅极位于输出晶体管T5的栅极在第一方向上的假想线上。例如，输出控制晶体管T4的第一极电连接到第一电源线VGH。
在本公开的实施例中，相对于图1D示出的第二降噪晶体管T7的两侧均设置连接走线的情况，本公开至少一实施例提供的变更第二降噪晶体管T7的连接走线的设置(即，走线仅从输出晶体管T5和第二降噪晶体管T7的之间通过)降低了走线复杂度，避免了出现 空间拥挤的问题，有利于实现显示面板的窄边框设计。
例如，在本公开一些实施例中，各层走线的线宽例如一般为3微米，位于同层的走线之间的间距例如大于3微米。例如，该走线间距例如与曝光机的精度有关，曝光机的精度越高，间距可以越小，具体可根据实际情况确定，本公开的实施例对此不作限制。在本公开的实施例中，同层的走线之间须留有必要的间距，以避免在实际工艺中导致走线粘连、信号短路。
第一导电层320的各条走线在衬底基板10上的正投影和第二导电层330的各条走线在衬底基板10上的正投影之间的间距例如一般为1.5微米，例如，第一导电层320中的晶体管的栅极要超出其在半导体层31上的有源层例如2微米以上。例如，如图2A、3和4所示，第一晶体管T1的“U”型双栅极在第一方向上在第一晶体管T1的条形的有源层的两侧均超出第一晶体管T1的条形的有源层例如2微米以上，例如，不与第一晶体管T1的条形的有源层重叠的部分(例如，第一部分G11和第二部分G12)在第一方向上的长度为2微米以上，本公开的实施例对此不作限制。
例如，半导体层310上各个晶体管的有源层在衬底基板10上的正投影与第一导电层320上的各条栅极走线在衬底基板10上的正投影之间的间距为1.5微米以上，从而可以避免栅极走线与半导体层310上各个晶体管的有源层之间产生沟道效应。例如，半导体层310在衬底基板10上的正投影与第二导电层330在衬底基板10上的正投影之间的间距无限制，可以重叠设置。例如，在本公开的一些实施例中，不同层走线之间尽可能保留一定间距(此间距小于同层走线间距)，可减少不必要的交叠，避免寄生电容过大产生窜扰。
例如，第三导电层340的各条走线的宽度要包住其对应的过孔，例如，可以超过过孔的尺寸(例如，过孔的直径)1微米以上，例如，过孔的尺寸为2.0～2.5微米，第三导电层340的包住过孔的各条走线的宽度为4～5微米。例如，输出控制晶体管T4和输出晶体管T5的与过孔对应的走线线宽为上下超过过孔1微米，例如为4.0～4.5微米，因为输出控制晶体管T4和输出晶体管T5对应的过孔较多，而连接其他晶体管的位于第三导电层340走线的宽度只需要在过孔位置满足包住过孔超过1微米的要求即可，例如，过孔之间的走线宽度可以细一点。
例如，位于第三导电层340的第一子时钟信号线GCK、第二子时钟信号线GCB、第一电源线VGH、第二电源线VGL等走线之间的间距为3微米以上，第一子时钟信号线GCK和第二子时钟信号线GCB为了满足驱动能力要求其线宽在9微米以上，第二电源线VGL的线宽为6、9或10微米都可以，第一电源线VGH的线宽例如为10微米，基准电压线Vinit的线宽例如为15微米，第二电源线VGL提供的第二电压例如一般为-7V，基本电压线Vinit提供的基准电压例如为-3V，因为基准电压线Vinit要驱动整个显示面板的像素阵列，而第一电源线VGH和第二电源线VGL只需要驱动位于显示面板的周边区域的栅极驱动电路，所以基准电压线Vinit的线宽较第一电源线VGH的线宽和第二电源线VGL的线宽宽一点。
例如，在一些示例中，第一导电层320和第二导电层330的厚度为2000～300埃，第三导电层340的厚度为5000～8000埃，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，第二电源线VGL上设置有突出部是为了缩短连接稳压晶体管T8的栅极的连接走线和第二控制晶体管T3的有源层，如果第二控制晶体管T3的有源层太长，掺杂的导体电阻会较大。例如，在本公开的一些实施例中，第一节点N1的在第三导电层340的走线(即中间转接电极11)的形状设计是为了尽量不与其他层走线和电极在衬底基板10上的正投影重叠，安排在空隙的位置，从而避免走线交叠产生串扰。
需要注意的是，在本公开的实施例中，例如，第一转接电极17、第二转接电极18、第三转接电极16位于第三导电层340。例如，第一转接电极17是用于连接例如图1B中所示的输入晶体管T1、第一控制晶体管T2、第二降噪晶体管T7和稳压晶体管T8的电极，例如第一节点N1包括第一转接电极17。例如，第二转接电极18是用于连接稳压晶体管T8和输出晶体管T5的电极，第三节点N3包括第二转接电极18。例如，中间转接电极11是用于连接第一控制晶体管T2、第二控制晶体管T3和第一降噪晶体管T6的电极，可位于第二导电层330，也可位于第一导电层320，当中间转接电极11位于第二导电层330且采用图7B所示的连接方式时，第二节点N2包括中间转接电极11和与该中间转接电极11连接的位于第三导电层340的第三子连接走线L3和第四子连接走线L4。例如，走线转接电极12位于第一导电层320，是与位于第三导电层340的第一连接走线L1连接的转接电极，或者二者位于同一层，本公开的实施例对此不作限制。
例如，通过设置上述转接电极和连接走线，可以避免同一层的走线密集而导致的走线粘连、信号短路等问题。例如，上述各个转接电极和连接走线起连接或跳线连接的作用。
本公开上述实施例提供的显示基板优化了的移位寄存器单元的线路连接和结构布局，在一定程度上压缩了移位寄存器单元的长度，有利于实现显示面板的窄边框设计，同时保证了显示面板的显示质量。
本公开至少一实施例还提供一种显示装置。图8为本公开至少一实施例提供的一种显示装置的示意图。如图8所示，该显示装置2包括本公开任一实施例提供显示基板1，例如，图2A或图2B中所示的显示基板1。
需要说明的是，该显示装置2可以为OLED面板、OLED电视、QLED面板、QLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置2还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置的全部组成单元。为实现该显示装置的基板功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示装置2的技术效果可以参考本公开的实施例中提供的显 示基板1的技术效果，这里不再赘述。
本公开至少一实施例还提供了一种显示基板的制作方法。图9为本公开至少一实施例提供的一种显示基板的制作方法的流程图。例如，该制作方法可以用于制作本公开任一实施例提供的显示基板。例如，可以用于制作图2A中所示的显示基板。
如图9所示，该显示基板的制作方法包括步骤S110至步骤S120。
步骤S110：提供衬底基板。
步骤S120：在垂直于衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层。
例如，形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层分别包括形成对应的材料层(例如，半导体材料层、绝缘材料层或导电材料层)，然后使用构图工艺分别形成对应的图案结构(例如，有源层、电极图案、走线、过孔等)。该构图工艺例如为光刻工艺，例如包括：在需要被构图的材料层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。
对于步骤S110，例如，该衬底基板10可以采用例如玻璃、塑料、石英，或其他适合的材料，本公开的实施例对此不作限制。
例如，在衬底基板上形成移位寄存器单元、第一电源线、第二电源线、第一时钟信号线和第二时钟信号线。
对于步骤S120，例如，形成所述移位寄存器单元包括：在垂直于衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层。
例如，第一电源线VGH、第二电源线VGL、多条时钟信号线(例如，触发信号线GSTV、第一子时钟信号线GCK和第二子时钟信号线GCB等)；移位寄存器单元104中包括的各个晶体管的第一极和第二极以及连接各个晶体管和电容的连接走线、转接电极等位于第三导电层340各个晶体管的有源层位于半导体层310、各个晶体管的栅极和移位寄存器单元中包括的各个电容的第一极位于第一导电层320，以及各个电容的第二极形成在第二导电层330；各个晶体管和各个电容通过贯穿第一绝缘层310、第二绝缘层320或第三绝缘层330的过孔分别与第一电源线VGH、第二电源线VGL、多条时钟信号线以及连接走线和转接电极连接。
关于移位寄存器单元104的各个晶体管和电容与第一电源线VGH、第二电源线VGL、多条时钟信号线以及连接走线和转接电极的连接结构的设置可参考图2A-图7E的描述，在此不再赘述。
需要说明的是，本公开的多个实施例中，该显示基板的制作方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文描述的制作方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述 的制作方法可以执行一次，也可以按照预定条件执行多次。
关于上述实施例提供的显示基板的制作方法的技术效果可以参考本公开的实施例中提供的显示基板的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (35)

  1. 一种显示基板，包括：衬底基板以及设置在所述衬底基板上的移位寄存器单元和第一时钟信号线，其中，
    所述第一时钟信号线在所述衬底基板上沿第一方向延伸，且配置为向所述移位寄存器单元提供第一时钟信号；
    所述移位寄存器单元包括输入电路、输出电路、第一控制电路和输出控制电路；
    所述输入电路配置为响应于所述第一时钟信号将输入信号输入至第一节点；
    所述输出电路配置为将输出信号输出至输出端；
    所述第一控制电路配置为响应于所述第一节点的电平和所述第一时钟信号，控制第二节点的电平；
    所述输出控制电路配置为在所述第二节点的电平的控制下，对所述输出端的电平进行控制；
    其中，所述第一控制电路包括第一控制晶体管和第二控制晶体管，
    所述第一控制晶体管的有源层和所述第二控制晶体管的有源层为一个连续的控制半导体层，所述控制半导体层沿所述第一方向延伸，所述第一控制晶体管的栅极和所述第二控制晶体管的栅极沿不同于所述第一方向的第二方向延伸且在所述第一方向上并排设置。
  2. 根据权利要求1所述的显示基板，其中，所述第一方向与所述第二方向的夹角在70°到90°之间。
  3. 根据权利要求1或2所述的显示基板，其中，所述移位寄存器单元还包括稳压电路，
    所述稳压电路与所述第一节点和第三节点连接，且配置为稳定所述第三节点的电平；
    所述输出电路与所述第三节点连接，且配置为在所述第三节点的电平的控制下，将所述输出信号输出至所述输出端。
  4. 根据权利要求3所述的显示基板，还包括第一电源线和第二电源线，被配置为向所述移位寄存器单元提供第一电压和第二电压，所述稳压电路包括稳压晶体管，所述第二电源线包括在所述第二方向上突出的突出部，
    所述第二控制晶体管的第二极和所述稳压晶体管的栅极均与所述第二电源线上的突出部连接以接收所述第二电压；
    其中，所述稳压晶体管的第一极连接所述第三节点，所述稳压晶体管的第二极连接所述第一节点。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述输入电路包括输入晶体管，所述输入晶体管的有源层为沿所述第二方向延伸的长条形；
    所述输入晶体管包括第一栅极、第二栅极和连接所述第一栅极和所述第二栅极的连接电极，其中，
    所述连接电极包括沿所述第一方向延伸的与所述第一栅极连接的第一部分和与所述第二栅极连接的第二部分，以及沿所述第二方向延伸且连接所述第一部分和所述第二部分的第三部分，所述连接电极的第三部分与所述第一时钟信号线连接以接收所述第一时钟信号。
  6. 根据权利要求5所述的显示基板，其中，所述第一控制晶体管的有源层、所述第二控制晶体管的有源层和所述输入晶体管的有源层在所述第二方向并排设置。
  7. 根据权利要求6所述的显示基板，其中，所述第一控制晶体管的有源层、所述第二控制晶体管的有源层位于所述输入晶体管的有源层沿所述第二方向延伸的假想线上。
  8. 根据权利要求5-7任一所述的显示基板，其中，所述输入晶体管的第一极通过沿所述第二方向延伸的第一连接走线与信号输入电极连接以接收所述输入信号。
  9. 根据权利要求8所述的显示基板，其中，所述移位寄存器单元还包括走线转接电极，
    其中，所述输入晶体管的第一极与所述走线转接电极的第一端电连接，所述走线转接电极与所述输入晶体管的有源层位于不同层，所述走线转接电极的第二端与所述第一连接走线的第一端连接，所述走线转接电极与所述第一连接走线位于不同层，所述第一连接走线的第二端与所述信号输入电极电连接，所述走线转接电极与所述信号输入电极位于同一层。
  10. 根据权利要求9所述的显示基板，其中，所述移位寄存器单元还包括第一绝缘层、第二绝缘层和第三绝缘层，
    其中，所述第一绝缘层位于所述输入晶体管的有源层和所述第一连接走线之间，所述第二绝缘层和所述第三绝缘层位于所述第一连接走线和所述走线转接电极之间；
    所述输入晶体管的第一极与所述走线转接电极位于同一层，所述走线转接电极的第二端通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述第一连接走线的第一端连接，所述第一连接走线的第二端通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述信号输入电极电连接。
  11. 根据权利要求5-10任一所述的显示基板，其中，所述显示基板还包括第二时钟信号线，配置为向所述移位寄存器单元提供第二时钟信号，所述移位寄存器单元还包括第二控制电路，
    其中，所述第二控制电路与所述第一节点和所述第二节点连接，且配置为在所述第二节点的电平和所述第二时钟信号的控制下，对所述第一节点的电平进行控制。
  12. 根据权利要求11所述的显示基板，其中，所述第二控制电路包括第一降噪晶体管和第二降噪晶体管；其中，
    所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层为一个连续的降噪半导体层，所述降噪半导体层沿所述第一方向延伸，且与所述输入晶体管的有源层在所述第一方向上并排设置，
    所述第一降噪晶体管的栅极和所述第二降噪晶体管的栅极沿所述第二方向延伸并在所述第一方向上并排设置；
    其中，所述输入晶体管的第一极连接所述第一节点，所述第一降噪晶体管的栅极连接所述第二节点。
  13. 根据权利要求12所述的显示基板，其中，所述输入晶体管的有源层位于所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层沿所述第一方向延伸的假想线上。
  14. 根据权利要求12或13所述的显示基板，其中，在所述移位寄存器单元包括稳压晶体管的情况下，所述稳压晶体管的有源层在所述衬底基板上的正投影在所述第一方向上位于所述第二控制晶体管的有源层在所述衬底基板上的正投影和所述第二降噪晶体管的有源层在所述衬底基板上的正投影之间。
  15. 根据权利要求12-14任一所述的显示基板，其中，所述第二降噪晶体管的栅极通过第三连接走线电连接到所述第二时钟信号线，所述第三连接走线包括第三子连接走线和第四子连接走线，所述第三子连接走线与所述第二降噪晶体管的栅极连接且沿所述第一方向延伸，且所述第三子连接走线在所述衬底基板的正投影与所述第二降噪晶体管的有源层在所述衬底基板上的正投影在所述第二方向上并排设置，所述第四子连接走线与所述第三子连接走线和所述第二时钟信号线连接且沿所述第二方向延伸，所述第四子连接走线在所述衬底基板上的正投影位于所述第二降噪晶体管的有源层在所述衬底基板上的正投影远离所述第一降噪晶体管的有源层在所述衬底基板上的正投影的一侧。
  16. 根据权利要求15所述的显示基板，还包括第四连接走线、第一绝缘层、第二绝缘层和第三绝缘层，
    其中，所述第一绝缘层位于所述输入晶体管的有源层和所述输入晶体管的栅极之间，所述第二绝缘层和所述第三绝缘层位于所述输入晶体管的栅极和所述第四连接走线之间；
    其中，所述第三子连接走线和所述第四子连接走线一体化形成，所述第三子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接。
  17. 根据权利要求15所述的显示基板，还包括第四连接走线、第一绝缘层、第二绝缘层和第三绝缘层，
    其中，所述第一绝缘层位于所述输入晶体管的有源层和所述输入晶体管的栅极之间，所述第二绝缘层和所述第三绝缘层位于所述输入晶体管的栅极和所述第四连接走线之间；
    其中，所述第三子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接，所述第四子连接走线通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与的所述第四连接走线连接。
  18. 根据权利要求12-17任一所述的显示基板，其中，所述移位寄存器单元还包括中间转接电极，
    其中，所述第一控制晶体管的有源层和所述第二控制晶体管的有源层与所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层在所述第二方向上并排设置，
    所述中间转接电极在所述衬底基板的正投影位于所述第一控制晶体管的有源层和所述第二控制晶体管的有源层在所述衬底基板上的正投影与所述第一降噪晶体管的有源层和所述第二降噪晶体管的有源层在所述衬底基板上的正投影之间，
    所述第一降噪晶体管的栅极通过所述中间转接电极连接至所述第一控制晶体管的第一极和所述第二控制晶体管的第一极。
  19. 根据权利要求18所述的显示基板，其中，所述第二节点包括所述中间转接电极。
  20. 根据权利要求18或19所述的显示基板，其中，所述移位寄存器单元还包括第一绝缘层和第二绝缘层，其中，
    所述第一绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的有源层和所述第一降噪晶体管的栅极之间；
    所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的栅极和所述中间转接电极之间；
    所述第一降噪晶体管的栅极通过贯穿所述第二绝缘层的过孔与所述中间转接电极的第一端连接，所述第一控制晶体管的第一极和所述第二控制晶体管的第一极通过贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述中间转接电极的第二端连接。
  21. 根据权利要求20所述的显示基板，其中，所述第二节点包括所述中间转接电极。
  22. 根据权利要求18或19所述的显示基板，其中，所述移位寄存器单元还包括第一绝缘层、第二绝缘层、第三绝缘层和第二连接走线，
    其中，所述第一绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的有源层和所述第一降噪晶体管的栅极之间；
    所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一降噪晶体管的栅极和所述中间转接电极之间；
    所述第三绝缘层在垂直于所述衬底基板的方向上位于所述中间转接电极和所述第二连接走线之间，所述第二连接走线包括第一子连接走线和第二子连接走线；
    所述第一降噪晶体管的栅极通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述第一子连接走线连接，所述中间转接电极的第一端通过贯穿所述第三绝缘层的过孔和所述第一子连接走线连接，
    所述第一控制晶体管的第一极和所述第二控制晶体管的第一极与所述第二子连接走线连接且位于同一层，所述中间转接电极的第二端通过贯穿所述第三绝缘层的过孔与所述第二子连接走线连接。
  23. 根据权利要求22所述的显示基板，其中，所述第二节点包括所述中间转接电极和所述第二连接走线。
  24. 根据权利要求1-23任一所述的显示基板，其中，所述输入晶体管的第一极与信号输入电极连接以接收所述输入信号，
    所述输出控制电路包括输出控制晶体管和第一电容，其中，所述第一电容的第一极和 第二极包括缺口，所述信号输入电极在所述衬底基板上的正投影落入所述第一电容在所述衬底基板上的正投影的缺口中。
  25. 根据权利要求16或17所述的显示基板，其中，所述输出电路包括输出晶体管和第二电容，所述输出晶体管的第一极与所述第四连接走线连接，所述第四连接走线通过所述第三连接走线连接到所述第二时钟信号线，第三连接走线的所述第三子连接走线在所述衬底基板上的正投影位于所述第二降噪晶体管的有源层在所述衬底基板上的正投影靠近所述输出晶体管的有源层在所述衬底基板上的正投影的一侧。
  26. 根据权利要求25所述的显示基板，其中，所述第二电容的形状为矩形。
  27. 根据权利要求25所述的显示基板，其中，在所述输出控制电路包括输出控制晶体管和第一电容的情况下，所述输出控制晶体管有源层和所述输出晶体管的有源层一体设置并沿所述第一方向延伸，
    所述输出控制晶体管的栅极和所述输出晶体管的栅极沿所述第二方向延伸且在所述第一方向上并排设置，
    在所述显示基板包括第一电源线的情况下，所述输出控制晶体管的第一极电连接到所述第一电源线以接收第一电压。
  28. 根据权利要求26所述的显示基板，其中，所述输出晶体管的第二极与和所述移位寄存器单元相邻的下级移位寄存器单元的信号输入电极连接。
  29. 根据权利要求1-28任一所述的显示基板，还包括第一电源线、第二电源线、第二时钟信号线、像素阵列区和周边区域，其中，
    所述第一电源线和所述第二电源线被配置为向所述移位寄存器单元提供第一电压和第二电压，
    所述第二时钟信号线被配置为向所述移位寄存器单元提供第二时钟信号，
    所述第一电源线、所述第二电源线、所述第一时钟信号线、所述第二时钟信号线和所述移位寄存器单元位于所述周边区域内；
    所述第二电源线、所述第一时钟信号线和所述第二时钟信号线在所述衬底基板上的正投影位于所述移位寄存器单元在所述衬底基板上的正投影远离所述像素阵列区的一侧；
    所述第一电源线在所述衬底基板上的正投影位于所述移位寄存器单元在所述衬底基板上的正投影靠近所述像素阵列区的一侧。
  30. 根据权利要求1-29任一所述的显示基板，还包括：第一电源线、第二控制电路、稳压电路、第一转接电极、第二转接电极和第三转接电极；
    其中，所述第一电源线配置为向所述移位寄存器单元提供第一电压；
    所述第二控制电路与所述第一节点和所述第二节点连接，且配置为在所述第二节点的电平和第二时钟信号的控制下，对所述第一节点的电平进行控制；
    所述稳压电路与所述第一节点和第三节点连接，且配置为稳定所述第三节点的电平；
    所述输入电路包括输入晶体管，所述第二控制电路包括第一降噪晶体管和第二降噪晶 体管，所述稳压电路包括稳压晶体管，所述输出控制电路包括输出控制晶体管和第一电容，所述输出电路包括输出晶体管和第二电容；其中，
    所述第一转接电极与所述输入晶体管的第一极、所述第一控制晶体管的栅极、所述稳压晶体管的第二极和所述第二降噪晶体管的第一极连接，其中，所述第一转接电极与所述第一控制晶体管的栅极不在同一层；
    所述第二转接电极与所述稳压晶体管的第一极和所述输出晶体管的栅极连接，其中，所述第二转接电极与所述输出晶体管的栅极不在同一层；
    所述第三转接电极与所述第一降噪晶体管的第一极和所述输出控制晶体管的第一极连接，并与所述第一电源线连接。
  31. 根据权利要求29所述的显示基板，其中，所述第一节点包括所述第一转接电极，所述第三节点包括所述第二转接电极。
  32. 一种显示装置，包括如权利要求1-31任一所述的显示基板。
  33. 根据权利要求32所述的显示装置，其中，所述显示装置为有机发光二极管显示装置。
  34. 根据权利要求33所述的显示装置，还包括阵列排布的像素单元，其中，所述移位寄存器单元的输出电路输出的输出信号作为栅极扫描信号以驱动所述像素单元发光。
  35. 一种如权利要求1-31任一所述的显示基板的制作方法，包括：
    提供所述衬底基板；
    在所述衬底基板上形成移位寄存器单元、第一电源线、第二电源线、所述第一时钟信号线和第二时钟信号线，其中，形成所述移位寄存器单元包括：
    在垂直于所述衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层；
    其中，各个晶体管的有源层位于所述半导体层，所述各个晶体管的栅极和各个电容的第一极位于所述第一导电层，所述各个电容的第二极位于所述第二导电层，所述第一电源线、所述第二电源线、所述第一时钟信号线、所述第二时钟信号线和所述各个晶体管的第一极和第二极位于所述第三导电层；
    所述各个晶体管和所述各个电容通过贯穿所述第一绝缘层、所述第二绝缘层或所述第三绝缘层的过孔互相连接以及与所述第一电源线、所述第二电源线、所述第一时钟信号线和所述第二时钟信号线连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114120905A (zh) * 2021-11-12 2022-03-01 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240114226A1 (en) * 2020-12-30 2024-04-04 Meta Platforms Technologies, Llc Integrated sensing and display system
CN117413310A (zh) * 2022-03-24 2024-01-16 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089476A1 (en) * 2001-01-06 2002-07-11 Samsung Electronics Co., Ltd. TFT LCD driver capable of reducing current consumption
CN105355180A (zh) * 2015-12-01 2016-02-24 深圳市华星光电技术有限公司 显示面板与控制电路
CN105931606A (zh) * 2016-05-27 2016-09-07 厦门天马微电子有限公司 栅极驱动结构和显示装置
CN107103889A (zh) * 2017-06-29 2017-08-29 惠科股份有限公司 一种显示面板的驱动电路、驱动电路的驱动方法和显示装置
CN108182921A (zh) * 2018-01-03 2018-06-19 上海中航光电子有限公司 一种阵列基板、显示面板与显示装置
CN108563082A (zh) * 2018-04-27 2018-09-21 京东方科技集团股份有限公司 电路基板、显示装置及驱动方法
CN209401289U (zh) * 2019-01-23 2019-09-17 北京京东方技术开发有限公司 驱动单元、栅极驱动电路、阵列基板及显示装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7369111B2 (en) * 2003-04-29 2008-05-06 Samsung Electronics Co., Ltd. Gate driving circuit and display apparatus having the same
CN1822385B (zh) * 2005-01-31 2013-02-06 株式会社半导体能源研究所 显示装置及含有其的电子设备
US9153341B2 (en) 2005-10-18 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Shift register, semiconductor device, display device, and electronic device
CN104867439B (zh) * 2015-06-24 2017-04-05 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN105742294B (zh) 2016-03-23 2019-01-15 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
KR102664040B1 (ko) * 2016-12-22 2024-05-14 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 구비한 표시 장치
CN110114718B (zh) * 2017-01-16 2023-10-10 株式会社半导体能源研究所 显示装置及其制造方法
CN106910453A (zh) 2017-05-09 2017-06-30 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
CN107481668B (zh) * 2017-09-01 2020-07-24 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN107644882B (zh) * 2017-10-25 2020-06-05 上海中航光电子有限公司 阵列基板、显示面板和显示装置
CN108257567A (zh) 2018-01-31 2018-07-06 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、触控显示装置
CN108564914B (zh) * 2018-04-24 2021-08-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110660362B (zh) 2018-06-28 2021-01-22 京东方科技集团股份有限公司 移位寄存器及栅极驱动电路
KR102509929B1 (ko) * 2018-09-05 2023-03-14 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN109375832B (zh) 2018-12-29 2022-01-07 厦门天马微电子有限公司 触控显示面板和触控显示装置
CN109712551B (zh) 2019-01-31 2020-07-28 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示装置及其控制方法
CN110416226B (zh) 2019-07-29 2022-02-22 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置
CN110767665B (zh) 2019-11-29 2022-05-31 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
KR102703434B1 (ko) * 2020-01-16 2024-09-09 삼성디스플레이 주식회사 스테이지 회로 및 이를 포함하는 스캔 구동부
CN113785350B (zh) 2020-04-10 2023-06-16 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113939914B (zh) 2020-04-30 2022-12-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089476A1 (en) * 2001-01-06 2002-07-11 Samsung Electronics Co., Ltd. TFT LCD driver capable of reducing current consumption
CN105355180A (zh) * 2015-12-01 2016-02-24 深圳市华星光电技术有限公司 显示面板与控制电路
CN105931606A (zh) * 2016-05-27 2016-09-07 厦门天马微电子有限公司 栅极驱动结构和显示装置
CN107103889A (zh) * 2017-06-29 2017-08-29 惠科股份有限公司 一种显示面板的驱动电路、驱动电路的驱动方法和显示装置
CN108182921A (zh) * 2018-01-03 2018-06-19 上海中航光电子有限公司 一种阵列基板、显示面板与显示装置
CN108563082A (zh) * 2018-04-27 2018-09-21 京东方科技集团股份有限公司 电路基板、显示装置及驱动方法
CN209401289U (zh) * 2019-01-23 2019-09-17 北京京东方技术开发有限公司 驱动单元、栅极驱动电路、阵列基板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4134943A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114120905A (zh) * 2021-11-12 2022-03-01 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置

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