WO2024021099A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024021099A1
WO2024021099A1 PCT/CN2022/109192 CN2022109192W WO2024021099A1 WO 2024021099 A1 WO2024021099 A1 WO 2024021099A1 CN 2022109192 W CN2022109192 W CN 2022109192W WO 2024021099 A1 WO2024021099 A1 WO 2024021099A1
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WIPO (PCT)
Prior art keywords
pixel
opening
spacer
display panel
sub
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Application number
PCT/CN2022/109192
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English (en)
French (fr)
Inventor
祝文秀
王红丽
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/109192 priority Critical patent/WO2024021099A1/zh
Priority to CN202280002475.7A priority patent/CN117795680A/zh
Publication of WO2024021099A1 publication Critical patent/WO2024021099A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED display devices have a series of advantages such as high brightness, full viewing angle, fast response speed, and flexible display.
  • OLED display devices can be divided into passive matrix OLED (Passive Matrix OLED, referred to as PMOLED) and active matrix OLED (Active Matrix OLED, referred to as AMOLED) according to the driving method.
  • PMOLED Passive Matrix OLED
  • AMOLED Active Matrix OLED
  • AMOLED display devices have higher luminous efficiency and can be used as high-resolution, large-size display devices.
  • a display panel includes a base substrate, a pixel defining layer, a plurality of pixels and a plurality of spacers.
  • the pixel defining layer is disposed on the base substrate.
  • the pixel defining layer includes a plurality of pixel openings, and the plurality of pixel openings include a first pixel opening, a second pixel opening, and a third pixel opening.
  • a plurality of pixels are arranged on the substrate, and the plurality of pixels are arranged in M rows and N columns.
  • the rows include N pixels arranged along the first direction, and the columns include M pixels arranged along the second direction. M ⁇ 2, N ⁇ 2.
  • the first direction and the second direction intersect.
  • the pixel includes a plurality of sub-pixels with different emitting colors
  • the plurality of sub-pixels include: a first sub-pixel located at the first pixel opening, a second sub-pixel located at the second pixel opening, and a third sub-pixel located at the third pixel opening.
  • sub-pixels; the first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in sequence along the third direction, and the third direction intersects both the first direction and the second direction.
  • two adjacent sub-pixels with the same emitting color are separated by at least two sub-pixels with other emitting colors, and the at least two sub-pixels have different emitting colors.
  • a plurality of spacers are also included.
  • the plurality of spacers are located on the side of the pixel defining layer away from the base substrate, and are located in the area where parts of the pixel defining layer other than the plurality of pixel openings are located. .
  • the plurality of spacers include a plurality of first spacers.
  • the first spacer is located between two third pixel openings arranged along the first direction and adjacent to each other. and is located between the first pixel opening and the second pixel opening arranged along the second direction and adjacent to each other.
  • At least one of the first pixel opening, the second pixel opening and the third pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion.
  • the corner-cut portion is located at a position of the pixel opening close to the first spacer; the orthographic projection of the corner-cut portion on the base substrate does not overlap with the orthographic projection of the first spacer on the base substrate.
  • a pixel opening having a chamfered portion has a first sidewall and a second sidewall adjacent to the chamfered portion.
  • the chamfered portion forms a first vertex angle and a second vertex angle with the first side wall and the second side wall respectively, and the first vertex angle is 0.9 to 1.1 times of the second vertex angle.
  • the pixel opening with the chamfered portion further includes a fifth sidewall opposite to the second sidewall along the third direction, and a sixth side opposite to the first sidewall along the fourth direction.
  • Wall, the fourth direction intersects the third direction.
  • the difference between the size of the fifth side wall along the fourth direction and the size of the second side wall along the fourth direction is the first difference
  • the size of the sixth side wall along the third direction is the same as the size of the first side wall along the third direction.
  • the difference in size is the second difference, and the first difference is equal to the second difference.
  • two adjacent pixel openings having chamfered portions and corresponding to sub-pixels with the same emitting color have a line connecting their respective geometric centers parallel to the first direction.
  • two adjacent pixel openings that have a chamfered portion and correspond to sub-pixels with the same emitting color have a line connecting their respective geometric centers parallel to the second direction.
  • two adjacent pixel openings having cut-angle portions and corresponding to sub-pixels with the same emitting color have a line connecting their respective geometric centers parallel to the first direction.
  • two adjacent pixel openings having chamfered portions and corresponding to sub-pixels with the same emitting color have a line connecting their respective geometric centers parallel to the second direction.
  • two adjacent pixel openings having chamfered portions and corresponding to sub-pixels with the same emitting color have the chamfered portions located at the same corners. location.
  • the shapes and sizes of two adjacent pixel openings are consistent.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel in the pixel all extend along a fourth direction, and the fourth direction and the third direction form an included angle of 80° to 100°.
  • the first pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion. The first spacer and the orthogonal projection of the first pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel.
  • the first pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the first pixel opening is substantially parallel to the first direction.
  • the first pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion.
  • the first spacer and the orthogonal projection of the first pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel.
  • the first pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the first pixel opening is substantially parallel to the first direction.
  • the second pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion.
  • the first spacer and the orthogonal projection of the second pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel.
  • the second pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the second pixel opening is substantially parallel to the first direction.
  • the second pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion.
  • the first spacer and the orthogonal projection of the second pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel.
  • the second pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the second pixel opening is substantially parallel to the first direction.
  • the third pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion. Orthographic projections of the first spacer and the third pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel.
  • the third pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the third pixel opening is substantially parallel to the second direction.
  • the third pixel opening adjacent to the first spacer is a pixel opening having a cut corner portion. Orthographic projections of the first spacer and the third pixel opening with the chamfered portion on the pixel defining layer have sides close to each other and substantially parallel. And, the third pixel opening adjacent to the first spacer is a pixel opening having a chamfered portion, and the chamfered portion of the third pixel opening is substantially parallel to the second direction.
  • the shape of the orthographic projection of the first spacer on the pixel definition layer includes one or more of a triangle, a rectangle, a square, a parallelogram, a trapezoid, a hexagon, an ellipse, and a circle. pattern type.
  • the plurality of pixel openings are divided into a plurality of opening groups arranged along a fourth direction, and the fourth direction intersects the third direction.
  • the plurality of spacers includes at least one second spacer.
  • the second spacer is in the shape of a strip and extends along the third direction between two adjacent opening groups.
  • two adjacent opening groups include a first opening group and a second opening group, and the length of the first opening group along the third direction is greater than the length of the second opening group along the third direction.
  • the length of the second spacer along the third direction is less than or equal to the length of the first opening group along the third direction, and is greater than or equal to the length of the second opening group along the third direction.
  • the orthographic projections of the second spacer and the first opening group on the pixel definition layer are flush with each other at both ends.
  • the display panel includes a display area with contour lines, and a plurality of spacers are located in the display area.
  • the plurality of spacers include a plurality of third spacers; the third spacers are located between two adjacent pixel openings close to the outline.
  • the orthographic projection of the third spacer on the pixel definition layer has an edge close to and substantially parallel to the contour line.
  • one of the two adjacent pixel openings close to the contour line and the orthographic projection of the third spacer on the pixel defining layer have sides that are close to each other and parallel to each other.
  • the shape of the orthographic projection of the third spacer on the pixel definition layer includes one or more pattern types of triangle, rectangle, square, parallelogram, trapezoid and ellipse.
  • the plurality of pixel openings are divided into a plurality of opening groups arranged along a fourth direction; the fourth direction intersects the third direction.
  • the plurality of spacers further includes at least one fourth spacer.
  • the fourth spacer is located between an opening group located at the outermost edge of the display panel and the contour line among the plurality of opening groups.
  • the fourth spacer and the orthographic projection of an opening group located at the outermost edge of the display panel on the pixel defining layer have sides that are close to each other and are substantially parallel.
  • the orthographic projection and the outline of the fourth spacer on the pixel definition layer have sides that are close to each other and substantially parallel.
  • the shapes of the orthographic projections of the first spacer and the third spacer on the pixel definition layer are different.
  • the orthographic projection shapes of the first spacer and the fourth spacer on the pixel definition layer are different.
  • the display panel includes a first spacer, a third spacer and a fourth spacer: orthographic projections of the first spacer and the third spacer on the pixel definition layer.
  • the shapes are different.
  • the shapes of the orthographic projections of the first spacer and the fourth spacer on the pixel definition layer are different.
  • the shape and size of the orthographic projection of the first spacer and the third spacer on the pixel definition layer All consistent.
  • a display device in yet another aspect, includes the display panel according to any of the above embodiments.
  • Figure 1 is a front view of a display device provided in accordance with some embodiments.
  • Figure 2 is a structural diagram of a display panel provided according to some embodiments.
  • Figure 3A is a stacking relationship diagram of multiple layers included in the display panel shown in Figure 2;
  • Figure 3B is a structural diagram of the active pattern layer in Figure 3A;
  • Figure 3C is a structural diagram of the first conductive pattern layer in Figure 3A;
  • Figure 3D is a structural diagram of the active pattern layer and the first conductive pattern layer in Figure 3A;
  • Figure 3E is a structural diagram of the third conductive pattern layer in Figure 3A;
  • Figure 3F is a structural diagram of the active pattern layer, the first conductive pattern layer and the third conductive pattern layer in Figure 3A;
  • Figure 3G is an equivalent circuit diagram of a pixel driving circuit R provided according to an embodiment
  • Figure 4A is an arrangement diagram of multiple pixel openings in the pixel definition layer shown in Figure 3A;
  • Figure 4B is an arrangement diagram of multiple pixels in the light-emitting device layer shown in Figure 3A;
  • Figure 5 is a structural diagram of a pixel in the light-emitting device layer shown in Figure 3A;
  • Figure 6 is an arrangement diagram of multiple pixels of the light emitting device layer of the comparative embodiment
  • FIG. 7A is a schematic diagram of the display panel DP of the comparative embodiment showing the form of horizontal lines;
  • FIG. 7B is a schematic diagram of the display panel DP of the comparative embodiment showing a vertical line form
  • FIG. 8A is a schematic diagram of the display panel DP of the comparative embodiment showing a diagonal shape
  • FIG. 8B is a schematic diagram of the display panel DP of the comparative embodiment showing another diagonal line form
  • Figure 9A is a schematic diagram of a display panel DP displaying a horizontal line form according to some embodiments.
  • Figure 9B is a schematic diagram of the display panel DP displaying a vertical line form according to some embodiments.
  • FIG. 10A is a schematic diagram of a display panel DP showing a diagonal line shape according to some embodiments.
  • Figure 10B is a schematic diagram of the display panel DP showing another diagonal line form according to some embodiments.
  • Figure 10C is a connection structure diagram of sub-pixels and pixel driving circuits
  • Figure 10D is an alternative structural diagram of Figure 10C
  • Figure 11A is an alternative structural diagram of Figure 4A
  • Figure 11B is an alternative structural diagram of Figure 4B
  • Figure 11C is a perspective view of the second pixel opening in Figure 11A;
  • Figure 11D is a structural diagram of a pixel opening with a corner cutout
  • Figure 12A is an alternative structural diagram of Figure 5;
  • Figure 12B is an alternative structural diagram of Figure 12A
  • Figure 13A is a structural diagram of the pixel opening with a corner cutout in Figure 12B;
  • Figure 13B is an enlarged view of H in Figure 12B;
  • Figure 14 is another alternative structural diagram of Figure 12A;
  • Figure 15 is another alternative structural diagram of Figure 12A;
  • Figure 16 is another alternative structural diagram of Figure 12A
  • Figure 17 is another alternative structural diagram of Figure 12A;
  • Figure 18 is another alternative structural diagram of Figure 12A;
  • Figure 19 is another alternative structural diagram of Figure 12A.
  • Figure 20 is another alternative structural diagram of Figure 12A;
  • Figure 21 is another alternative structural diagram of Figure 12A
  • Figure 22 is a possible shape structure diagram of the orthographic projection of the first spacer on the pixel definition layer
  • Figure 23 is another alternative structural diagram of Figure 12A
  • Figure 24 is another alternative structural diagram of Figure 12A
  • Figure 25 is another alternative structural diagram of Figure 12A
  • Figure 26 is another alternative structural diagram of Figure 25.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Figure 1 is a front view of a display device provided in accordance with some embodiments.
  • an embodiment of the present invention provides a display device.
  • the display device may be any device that displays text or images, whether moving (eg, video) or stationary (eg, still images).
  • the display device may be, for example (but not limited to) a monitor, a television, a mobile phone (such as a mobile phone), a wireless device, a Personal Digital Assistant (PDA), a computer (such as a handheld or portable computer), a global positioning system (Global Positioning System, referred to as GPS) receiver/navigator, camera, Moving Picture Experts Group 4 (referred to as MP4) video player, video camera, game console, watch, clock, calculator, monitor, Vehicle-mounted displays (for example, odometer displays, cockpit controllers, cockpit displays or displays for rear-view cameras in vehicles, etc.), navigators, electronic photo frames, electronic billboards, electronic signs, projectors, architectural structures, packaging and aesthetic structures (e.g., for a display of an image of a piece of jewelry), etc. Any of these.
  • the above-mentioned display device includes a display panel DP.
  • the above-mentioned display device may also include at least one of a frame, a display driver chip (Display Driver Integrated Circuit, DDIC for short), a circuit board, and the like.
  • the circuit board can be a flexible printed circuit board (FPC) or a PCB (Printed Circuit Board).
  • the circuit board can be coupled with the DDIC and configured to transmit electrical signals to the DDIC.
  • the DDIC is configured to provide a data signal to the display panel DP; for example, configured to generate a data signal based on the received electrical signal; and send the data signal to the display panel DP.
  • display panels DP, DDIC and circuit boards can be installed into the space enclosed by the frame.
  • the display panel DP is a screen with a display function, which can be coupled to the DDIC mentioned above, and is configured to receive the data signal sent by the DDIC and display the corresponding image.
  • the display panel DP can be an OLED display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display panel, a micro-LED (including: miniLED or microLED) display panel, etc.
  • the display panel DP has a display area AA and a non-display area SA.
  • the display area AA is the area on the display panel DP used for displaying pictures
  • the non-display area SA is the area on the display panel DP except the display area AA. area.
  • the non-display area SA may be located on at least one side (eg, one side, or multiple sides) of the display area AA.
  • the non-display area SA may be arranged around the display area AA.
  • the display area AA may be a rectangle, or a shape similar to a rectangle such as a rounded rectangle. Based on this, the display area AA has two sides whose extension directions cross each other (for example, are perpendicular to each other). For convenience of description, the extending directions of these two sides are respectively regarded as the X-axis and Y-axis to establish a rectangular coordinate system. Among them, the X-axis and Y-axis are interchangeable.
  • Figure 2 is a structural diagram of a display panel provided according to some embodiments.
  • the display panel DP is provided with a plurality of pixels 600 in the display area AA.
  • the plurality of pixels 600 are arranged in M rows and N columns, and the rows include N pixels 600 arranged along the first direction X.
  • a column includes M pixels 600 arranged along the second direction Y. And M ⁇ 2, N ⁇ 2. And both M and N are integers.
  • the first direction X and the second direction Y intersect, for example, are perpendicular to each other.
  • the first direction X is the direction indicated by the X-axis, so the reference sign of the X-axis is used.
  • the second direction Y is the direction indicated by the Y-axis, so the reference sign of the Y-axis is used.
  • pixels in the same row including all sub-pixels in the pixels in the same row
  • pixels in different rows are driven in a time-sharing manner.
  • M rows of pixels can be driven row by row. For example, after the first row of pixels is driven, the second row of pixels is driven, and so on, until the M row of pixels is driven.
  • a (eg, each) pixel 600 includes a plurality of sub-pixels.
  • a sub-pixel is the smallest unit of the display panel DP for displaying images.
  • Each sub-pixel can display a single color, such as red (R), green (G) or blue (B).
  • the brightness (gray scale) of sub-pixels of different colors in each pixel 600 can be adjusted, and multiple colors can be displayed through color combination and superposition, thereby achieving full-color display of the display panel.
  • the pixel 600 may include a first sub-pixel 610, a second sub-pixel 620, and a third sub-pixel 630.
  • the first sub-pixel 610, the second sub-pixel 620 and the third sub-pixel 630 emit light in different colors and are arranged in sequence along the third direction E.
  • the third sub-pixel 630 may be a blue sub-pixel; one of the first sub-pixel 610 and the second sub-pixel 620 may be a red sub-pixel, and the other may be a green sub-pixel.
  • the first sub-pixel 610 is a red sub-pixel
  • the second sub-pixel 620 is a green sub-pixel.
  • the emission colors of the first sub-pixel 610 and the second sub-pixel 620 can be interchanged.
  • one (eg, each) sub-pixel may include a light emitting device.
  • the light-emitting device can be an organic light-emitting diode, a micro organic light-emitting diode (Micro OLED), a quantum dot organic light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), or a mini light-emitting diode (Mini Light).
  • a micro organic light-emitting diode Micro OLED
  • QLED quantum dot organic light-emitting diode
  • Mini Light mini light-emitting diode
  • Mini LED Micro Light-Emitting Diode
  • Micro LED Micro Light-Emitting Diode
  • the red sub-pixel may include a light-emitting device for emitting red light
  • the green sub-pixel may include a light-emitting device for emitting green light
  • the blue sub-pixel may include a light-emitting device for emitting blue light.
  • the first sub-pixel 610, the second sub-pixel 620 and the third sub-pixel 630 in one (for example, each) pixel 600 are sequentially arranged along the third direction E.
  • the first sub-pixel 610 , the second sub-pixel 620 and the third sub-pixel 630 of the pixel 600 are arranged in sequence.
  • the third sub-pixel 630 , the second sub-pixel 620 and the first sub-pixel 610 of the pixel 600 are arranged in sequence.
  • the third direction E intersects both the first direction X and the second direction Y.
  • the angle between the third direction E and the second direction Y is 40° to 50°.
  • the display panel DP may further include a plurality of pixel driving circuits R located in the display area AA.
  • Each pixel driving circuit R may be coupled to a sub-pixel (eg, a light-emitting device) and configured to drive the sub-pixel to emit light.
  • the number of rows of the pixel driving circuit R and the number of rows of the pixels may be the same, which are both M.
  • the number of columns of the pixel driving circuit R is W times the number of columns of pixels.
  • Each row ie, each row of pixel driving circuits R
  • the C pixel driving circuits R are respectively coupled to sub-pixels included in N pixels located in the same row. Among them, the pixel driving circuit R located in the same row can be written with data signals at the same time, thereby driving the pixels located in the same row to emit light.
  • the pixel driving circuit R may include electronic components such as a plurality of transistors and capacitors.
  • each of the pixel driving circuits R may include three transistors and a capacitor, forming 3T1C (ie, one driving transistor, two switching transistors and one capacitor).
  • 3T1C ie, one driving transistor, two switching transistors and one capacitor
  • the transistor can be a thin film transistor (TFT), a field effect transistor (metal oxide semiconductor, MOS) or other switching devices with the same characteristics.
  • the transistor may include a control electrode, a first electrode, and a second electrode.
  • the control electrode is the gate electrode of the transistor
  • the first electrode is one of the source electrode and the drain electrode of the transistor
  • the second electrode is the other one of the source electrode and the drain electrode of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. Therefore, the source of the transistor is called the first electrode, or it can also be called the third electrode. Two poles.
  • the display panel DP may also include a plurality of signal lines. These signal lines may be coupled to the plurality of pixel driving circuits R mentioned above and configured to transmit corresponding electrical signals to each pixel driving circuit R.
  • the multiple signal lines include multiple scan signal lines GL, multiple data lines DL, multiple reset signal lines Rst, multiple enable signal lines (also called light emission control signal lines) EM, multiple initialization signal lines Vinit and One or a combination of multiple power supply voltage signal lines VDD.
  • the plurality of scan signal lines GL, the plurality of enable signal lines EM and the plurality of initialization signal lines Vinit may be arranged along the first direction X
  • the plurality of data lines DL and the plurality of power supply voltage signal lines VDD may be arranged along the second direction Arrangement in direction Y.
  • Each pixel driving circuit R may be electrically connected to the scanning signal line GL, the data line DL, the reset signal line Rst, the enable signal line EM, the initialization signal line Vinit and the power supply voltage signal line VDD.
  • FIG. 3A is a stacking relationship diagram of multiple layers included in the display panel shown in FIG. 2 .
  • the display panel DP includes: a base substrate 100 and a pixel driving circuit layer 200 that are stacked in sequence. and light emitting device layer 300.
  • the pixel driving circuit layer 200 includes a plurality of pixel driving circuits R mentioned above.
  • the light-emitting device layer 300 includes a plurality of light-emitting devices 320 for constituting a plurality of pixels 600.
  • the structure of the above-mentioned base substrate 100 can be selected and arranged according to actual needs.
  • a plurality of pixels 600 are provided on the base substrate 100 (shown in FIG. 3A).
  • the base substrate 100 may be a rigid substrate.
  • the rigid substrate may include, for example, a glass substrate lining PMMA (Polymethyl methacrylate, polymethyl methacrylate).
  • PMMA Polymethyl methacrylate, polymethyl methacrylate
  • the above-mentioned display panel DP may be a rigid display panel.
  • the base substrate 100 may be a flexible substrate.
  • the flexible substrate may include, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or a PI (Polyimide) substrate. , polyimide) substrate.
  • the above-mentioned display panel DP may be a flexible display panel.
  • the base substrate 100 may have a one-layer structure or a multi-layer structure.
  • the substrate may include at least one flexible substrate and at least one buffer layer, and the flexible substrate and the buffer layer are alternately stacked.
  • the pixel driving circuit layer 200 may include: an active pattern layer 210 , a first conductive pattern layer 220 , and a second conductive pattern layer 230 that are stacked in sequence.
  • the pixel driving circuit layer 200 may further include an insulating layer 240 that separates these pattern layers. These layers may form multiple pixel driving circuits R.
  • the "pattern layer” may be a layer structure containing a specific pattern formed by using the same film formation process to form at least one film layer, and then performing a patterning process on the at least one film layer.
  • the patterning process may include multiple glue coating, exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be in Different heights (or thicknesses).
  • the "conductive pattern layer” is a pattern layer with conductive properties, which is made of conductive materials.
  • the "conductive pattern layer” is made of a transparent conductive material. For example, at least one of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), etc.
  • the "conductive pattern layer” can also be made of metal materials, for example, it can be at least one of aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), etc.
  • FIG. 3B is a structural diagram of the active pattern layer in FIG. 3A.
  • the active pattern layer 210 may be made of polycrystalline silicon (P-Si), and the active pattern layer 210 includes the active pattern of each transistor of the pixel driving circuit R (which may also be called a channel region).
  • P-Si polycrystalline silicon
  • the active pattern layer 210 includes the active pattern of each transistor of the pixel driving circuit R (which may also be called a channel region).
  • the first conductive pattern layer 220 includes a plurality of gate patterns Cp.
  • the second conductive pattern layer 230 includes a plurality of source electrodes and a plurality of drain electrodes. Among them, a corresponding active pattern, a gate pattern Cp, a source electrode, and a drain electrode may constitute a transistor, and multiple transistors may constitute a pixel driving circuit R.
  • the pixel driving circuit layer may further include a third conductive pattern layer 250 located between the first conductive pattern layer 220 and the second conductive pattern layer 230 .
  • the first conductive pattern layer 220 further includes a first capacitor plate Cst1
  • the third conductive pattern layer 250 further includes a second capacitor plate Cst2; the first capacitor plate Cst1 and the second capacitor plate Cst2 are arranged oppositely to form Capacitor Cst in the pixel driving circuit R.
  • the second capacitor plate Cst2 may also be included in the second conductive pattern layer 230 .
  • FIG. 3C is a structural diagram of the first conductive pattern layer in FIG. 3A.
  • FIG. 3D is a structural diagram of the active pattern layer and the first conductive pattern layer in FIG. 3A.
  • the first conductive pattern layer 220 and the third conductive pattern layer 250 include a plurality of signal lines.
  • the first conductive pattern layer 220 includes a plurality of signal lines and the first plate Cst1 of the capacitor.
  • the plurality of signal lines may be, for example, the scan signal line GL, the reset signal line Rst, and the enable signal line EM.
  • the plurality of signal lines located in the first conductive pattern layer 220 pass through the active patterns of each transistor.
  • the overlapping position of the multiple signal lines located in the first conductive pattern layer 220 and the active patterns of each transistor is the gate pattern Cp of each transistor. .
  • the first reset signal line Rst1 passes through the first active pattern AL1 , and the overlapping portion of the first reset signal line Rst1 and the first active pattern AL1 is the first gate pattern Cp1 .
  • the scanning signal line GL passes through the second active pattern AL2 and the fourth active pattern AL4, and the overlapping portion of the scanning signal line GL and the second active pattern AL2 is the second gate pattern Cp2.
  • the overlapping portion of the scanning signal line GL and the fourth active pattern AL4 is the fourth gate pattern Cp4.
  • the first plate Cst1 passes through the third active pattern AL3, and the overlapping portion of the first plate Cst1 and the third active pattern AL3 is the third gate pattern Cp3.
  • the enable signal line EM passes through the fifth active pattern AL5 and the sixth active pattern AL6.
  • the overlapping portion of the enable signal line EM and the fifth active pattern AL5 is the fifth gate pattern Cp5.
  • the enable signal line EM and the fifth active pattern AL5 is the sixth gate pattern Cp6.
  • the second reset signal line Rst2 passes through the seventh active pattern AL7, and the overlapping portion of the second reset signal line Rst2 and the seventh active pattern AL7 is the seventh gate pattern Cp7.
  • FIG. 3E is a structural diagram of the third conductive pattern layer in FIG. 3A.
  • the third conductive pattern layer 250 includes a plurality of signal lines and the second plate Cst2 of the capacitor.
  • the plurality of signal lines include an initialization signal line Vinit.
  • the initialization signal line Vinit includes a first initialization signal line Vinit1 and a second initialization signal line Vinit2.
  • each signal line of the first conductive pattern layer 220 passes through the active pattern of the corresponding transistor, which refers to each signal line of the first conductive pattern layer 220.
  • it can be a scanning signal line GL (not shown in the figure) on the substrate.
  • the orthographic projection overlaps with the orthographic projection of the second active pattern AL2 (not shown in the figure) on the substrate.
  • the following takes the 7T1C mode pixel driving circuit R as an example for introduction.
  • FIG. 3F is a structural diagram of the active pattern layer, the first conductive pattern layer and the third conductive pattern layer in FIG. 3A.
  • FIG. 3G is an equivalent circuit diagram of a pixel driving circuit R provided according to an embodiment.
  • the pixel driving circuit R in the 7T1C mode includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first enabling transistor T5, a second enabling transistor Transistor T6, second reset transistor T7 and capacitor Cst.
  • control electrode of the first reset transistor T1 is electrically connected to the first reset signal line Rst1.
  • the first pole of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1.
  • the second pole of the first reset transistor T1 is electrically connected to the first node N1.
  • the control electrode of the compensation transistor T2 is electrically connected to the scanning signal line GL.
  • the first pole of the compensation transistor T2 is electrically connected to the third node N3.
  • the second pole of the compensation transistor T2 is electrically connected to the first node N1.
  • the control electrode of the driving transistor T3 is electrically connected to the first node N1, and the first electrode of the driving transistor T3 is electrically connected to the second node N2.
  • the second pole of the driving transistor T3 is electrically connected to the third node N3.
  • the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1.
  • the second plate Cst2 of the capacitor Cst is electrically connected to the first voltage signal terminal VDD.
  • the first voltage signal terminal VDD is electrically connected to the power supply voltage signal line VDD.
  • the control electrode of the writing transistor T4 is electrically connected to the scanning signal line GL.
  • the first pole of the write transistor T4 is electrically connected to the data line DL.
  • the second pole of the write transistor T4 is electrically connected to the second node N2.
  • the control electrode of the first enable transistor T5 is electrically connected to the enable signal line EM.
  • the first pole of the first enable transistor T5 is electrically connected to the power supply voltage signal line VDD.
  • the second pole of the first enabling transistor T5 is electrically connected to the second node N2.
  • the control electrode of the second enable transistor T6 is electrically connected to the enable signal line EM.
  • the first pole of the second enable transistor T6 is electrically connected to the third node N3.
  • the second electrode of the second enabling transistor T6 is electrically connected to the anode of the light emitting device 320 .
  • the control electrode of the second reset transistor T7 is electrically connected to the second reset signal line Rst2.
  • the first pole of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2.
  • the second electrode of the second reset transistor T7 is electrically connected to the connection point N4 between the second electrode of the second enable transistor T6 and the anode of the light emitting device 320 .
  • the cathode of the light emitting device 320 is electrically connected to the second voltage signal line VSS.
  • the second voltage signal line VSS transmits a low-level signal. For example, the voltage of the low-level signal may be zero.
  • each of the above transistors is: in the data writing stage, the compensation transistor T2 and the writing transistor T4 are turned on under the control of the scanning signal received at the scanning signal line GL, and write the data signal received at the data signal terminal v. Entering the first node N1, threshold voltage compensation is formed for the driving transistor T3. When turned off, the voltage of the first node N1 is the sum of the data signal and the threshold voltage of the driving transistor T3. The voltage of the first node N1 can control the size of the driving current through the driving transistor T3.
  • the compensation transistor T2 and the write transistor T4 are turned off under the control of the first scan signal, and the first enable transistor T5 and the second enable transistor T6 are controlled by the enable signal received at the enable signal line EM.
  • the driving transistor T3 is turned on and generates a driving current, and transmits the driving current to the light-emitting device 320.
  • the light-emitting device 320 emits light under the control of the driving current.
  • the size of the driving current affects the brightness of the light, that is to say, the first node N1
  • the voltage can control the brightness of the light-emitting device 320, that is, it can control the gray scale of the sub-pixels, thereby affecting the quality of the entire display screen.
  • first node N1, the second node N2 and the third node N3 in the embodiment of the present invention do not represent actual existing components, but represent the meeting points of relevant circuit connections in the layout of the pixel driving circuit R, that is, It is said that the first node N1, the second node N2 and the third node N3 are nodes equivalent to the meeting points of electrical connections of relevant lines in the circuit diagram.
  • the light emitting device layer 300 may include a pixel defining layer 310 and a plurality of light emitting devices 320 .
  • the pixel defining layer 310 has a plurality of pixel openings K, and one pixel opening K defines the position of one light-emitting device 320.
  • the light-emitting device 320 includes a first electrode (eg, anode) 321, a light-emitting layer 322, and a second electrode (eg, cathode) 323 that are stacked in sequence.
  • a first electrode eg, anode
  • a second electrode eg, cathode
  • the structure of the first electrode 321 may be a composite structure composed of a transparent conductive oxide film/a metal film/a transparent conductive oxide film stacked in sequence.
  • the material of the above-mentioned transparent conductive oxide film is, for example, any one of ITO (Indium tin oxide) and IZO (Indium zinc oxide), and the material of the above-mentioned metal film is, for example, gold (Au), silver Any one of (Ag), nickel (Ni) and platinum (Pt).
  • the structure of the first electrode 321 may also be a single-layer structure, and the material of the single-layer structure may be any one of ITO, IZO, Au, Ag, Ni, and Pt.
  • one pixel opening K exposes a part of a first electrode 321 .
  • At least a part of a light-emitting layer 322 is located in a pixel opening K and forms an electrical connection with the corresponding first electrode 321 . That is, each light-emitting layer 322 forms an electrical connection with the corresponding first electrode 321 through a portion or the entirety thereof located within the corresponding pixel opening K.
  • the arrangement manner of the light-emitting layer 322 is related to the preparation process of the light-emitting layer 322 .
  • a part of the light-emitting layer 322 may be located within the corresponding pixel opening K, and the other part overlaps the pixel defining layer 310 around the pixel opening K.
  • the entire light-emitting layer 322 may also be located within the corresponding pixel opening K.
  • the entire luminescent layer 322 may be located within the corresponding pixel opening K.
  • the second electrode 323 is located on a side of the pixel defining layer 310 away from the base substrate 100 .
  • the second electrodes 323 of each light-emitting device may be electrically connected to each other to form an integrated structure.
  • the material of the second electrode 323 may be any one of aluminum (Al), silver (Ag), and magnesium (Mg), or any one of magnesium-silver alloy and aluminum-lithium alloy.
  • the light-emitting device layer 300 may also include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer provided between the first electrode 321 and the light-emitting layer 322, and provided between the second electrode 323 and the light-emitting layer. At least one of an electron injection layer, an electron transport layer, and a hole blocking layer between 322.
  • the display panel DP may further include: a first flat layer PLN1 located between the light-emitting device layer 300 and the pixel driving circuit layer 200 , and the first flat layer PLN1 and the light-emitting device layer 300 direct contact.
  • the first electrode 321 of the light emitting device 320 is disposed on a side surface of the first flat layer PLN1 away from the base substrate 100 .
  • the first electrode 321 of a light emitting device layer 300 may be electrically connected to a pixel driving circuit R through the first flat layer PLN1.
  • the display panel DP may further include: a fourth conductive pattern layer 260 located between the first flat layer PLN1 and the pixel driving circuit layer 200 .
  • the fourth conductive pattern layer 260 may include a plurality of connection portions 261 .
  • the first electrode 321 of a light emitting device 320 may be electrically connected to a pixel driving circuit R through a connecting portion 261.
  • the display panel DP may further include: a second flat layer PLN2 and a passivation layer PVX located on a side of the pixel driving circuit layer 200 away from the base substrate 100 .
  • the second flat layer PLN2 may be made of organic insulating material.
  • the passivation layer PVX can be made of inorganic insulating materials.
  • the display panel DP further includes: an encapsulation layer 400 disposed on a side of the light-emitting device layer 300 away from the base substrate 100 .
  • the encapsulation layer 400 includes a first inorganic insulation layer 410 , an organic insulation layer 420 and a second inorganic insulation layer 430 that are stacked in sequence.
  • the first inorganic insulating layer 410 and the second inorganic insulating layer 430 can be made of inorganic materials of nitride, oxide, oxynitride, nitrate, carbide or any combination thereof.
  • the organic insulation layer 420 can be made of acrylic, hexamethyldisiloxane, polyacrylate, polycarbonate, polystyrene and other materials.
  • the display panel DP further includes a light-shielding layer 700 and a filter pattern layer 800 disposed on the side of the pixel defining layer 310 away from the base substrate 100 .
  • a plurality of filter openings L are opened on the light shielding layer 700 .
  • the filter pattern layer 800 includes a plurality of filter patterns 810 .
  • a filter opening L corresponds to a filter pattern 810, that is to say, the filter opening L and the filter pattern 810 have overlapping portions in the thickness direction of the display panel DP.
  • the filter opening L is used to define the position of the filter pattern 810 .
  • the display panel DP further includes a touch layer TL.
  • the display panel DP is a touch display panel, a product with touch function and image display function.
  • the touch layer TL is configured to provide a touch signal, and the touch signal can reflect the user's touch position on the display panel DP.
  • the touch layer TL can be coupled with the touch chip to provide touch signals to the touch chip.
  • the touch layer TL may be located on the display side of the display panel DP.
  • the touch layer TL may be a component independent of the display panel DP; for example, the display panel DP and the touch layer TL are both formed separately, and then the two are bonded together through an adhesive such as optical glue.
  • the above encapsulation layer 400 can serve as the display surface of the display panel DP.
  • the touch layer TL can be formed on the packaging layer 400 through photolithography or other processes.
  • the touch layer TL may also be a structure integrated on the display panel DP. For example, using the display panel DP as a substrate, the touch layer TL is formed on the display surface of the display panel DP. At this time, the touch layer TL is in direct contact with the display surface of the display panel DP, or may be in direct contact with the display surface of the display panel DP. There are other functional layers between the surfaces.
  • the touch layer TL may also be located inside the display panel.
  • the display panel includes a first substrate and a second substrate arranged oppositely, and the touch layer TL may be located between the first substrate and the second substrate.
  • the display panel DP further includes a buffer layer 500 .
  • the buffer layer 500 is disposed on the side of the light shielding layer 700 away from the base substrate 100 .
  • the touch layer TL is disposed on the buffer layer 500 and can be in contact with the buffer layer 500 .
  • the buffer layer 500 may be made of organic insulating material or inorganic insulating material.
  • the light emitting device layer in FIG. 3A will be described in detail below.
  • FIG. 4A is an arrangement diagram of multiple pixel openings in the pixel defining layer shown in FIG. 3A; and FIG. 4A shows the lower port of each pixel opening K.
  • FIG. 4B is an arrangement diagram of multiple pixels in the light-emitting device layer shown in FIG. 3A; and FIG. 4B shows the light-emitting area of each sub-pixel in the pixel.
  • FIG. 5 is a structural diagram of a pixel in the light-emitting device layer shown in FIG. 3A.
  • the plurality of pixel openings K on the pixel definition layer 310 include a plurality of first pixel openings K1 , a plurality of second pixel openings K2 and a plurality of third pixel openings. K3. Based on the correspondence between one pixel opening K and the position of one sub-pixel, a group of pixel openings corresponding to the position of one pixel 600 is called an opening unit O in this article.
  • the pixel 600 includes a plurality of sub-pixels with different emitting colors.
  • the plurality of sub-pixels include: a first sub-pixel 610 located at the first pixel opening K1, a second sub-pixel 620 located at the second pixel opening K2 and a third pixel opening K3.
  • the third sub-pixel 630 at .
  • the first sub-pixel 610, the second sub-pixel 620 and the third sub-pixel 630 are arranged in sequence along the third direction E.
  • the opening unit O includes a first pixel opening K1 , a plurality of second pixel openings K2 and a plurality of third pixel openings K3 that are sequentially arranged along the third direction E.
  • each pixel 600 includes a first sub-pixel 610, a second sub-pixel 620 and a third sub-pixel 630.
  • multiple pixel openings K may be divided into multiple opening groups KI, and all pixel openings K in each opening group KI are arranged along the third direction E.
  • each opening group KI is composed of an integer number (that is, at least one, such as one, or a plurality) of opening units O.
  • these opening units O are arranged in a row along the third direction E.
  • the pixel openings K of the same type are also located in the same row; for example, each first pixel opening K1 is arranged along the first direction X, Similarly, the second pixel openings K2 are also arranged along the first direction X, and similarly, the third pixel openings K3 are also arranged along the first direction X.
  • each first pixel opening K1 is arranged along the second direction Y, and similarly, each second pixel opening K2 Also arranged along the second direction Y, similarly, each third pixel opening K3 is also arranged along the second direction Y.
  • an embodiment of the present invention provides a display panel DP.
  • the area of the first pixel opening K1 of the display panel DP is smaller than the area of the second pixel opening K2. This means that the area of the orthographic projection of the first pixel opening K1 on the base substrate 100 is smaller than the area of the orthogonal projection of the second pixel opening K2 on the base substrate 100 .
  • the area of the second pixel opening K2 is smaller than the area of the third pixel opening K3. This means that the area of the orthographic projection of the second pixel opening K2 on the base substrate 100 is smaller than the area of the orthogonal projection of the third pixel opening K3 on the base substrate 100 .
  • the area of the opening area of the first sub-pixel 610 is smaller than the area of the opening area of the second sub-pixel 620 .
  • the area of the opening area of the second sub-pixel 620 is smaller than the area of the opening area of the third sub-pixel 630 .
  • each sub-pixel group S is composed of an integer number (that is, at least one, such as one, or a plurality) of pixels 600.
  • these pixels 600 are arranged in a row along the third direction E.
  • FIG. 6 is an arrangement diagram of multiple pixels of the light emitting device layer of the comparative embodiment.
  • a plurality of pixels 600' of the display panel DP (not shown in the figure) are arranged along the first direction X and the second direction Y to form M rows and N columns, each column including a plurality of The pixels 600' are arranged along the second direction Y, and one (eg, each) pixel 600' includes a red sub-pixel 610', a green sub-pixel 620' and a blue sub-pixel 630'.
  • the red sub-pixels 610' and the green sub-pixels 620' are arranged sequentially along the second direction Y, and the blue sub-pixels 630' are arranged on one side of the red sub-pixels 610' and the green sub-pixels 620' (for example, in the first direction X the side indicated).
  • the extension direction of the sub-pixel group S' is consistent with the second direction Y.
  • the blue sub-pixel 630' in a pixel 600' is constant, if the blue sub-pixel 630' is made elongated (for example, the size of the blue sub-pixel 630' along the second direction Y is the length, The size along the first direction Therefore, the ratio of the length to the width of the blue sub-pixel 630' needs to be smaller. However, in this way, along the second direction Y, the spacing between the blue sub-pixels 630' becomes larger, causing the space of the spacing to be unused, thereby causing the pixel density unit (Pixels Per Inch, PPI) to decrease.
  • PPI pixel density unit
  • the first sub-pixel 610 , the second sub-pixel 620 and the third sub-pixel 630 of a pixel 600 are arranged in sequence along the third direction E.
  • a plurality of pixels arranged along the third direction E is a sub-pixel group S.
  • the spacing between two adjacent sub-pixels in a sub-pixel group S can be configured as needed.
  • the distance between the first sub-pixel 610 and the second sub-pixel 620, and the distance between the second sub-pixel 620 and the third sub-pixel 630 is approximately equal.
  • the spacing between two adjacent sub-pixels can be approximately equal. Of course it doesn't have to be equal. It can be seen that this embodiment does not cause the problem of excessive spacing between two adjacent sub-pixels, so that the space can be fully utilized for the layout of sub-pixels, thereby improving the PPI.
  • FIG. 7A is a schematic diagram of the display panel DP of the comparative embodiment displaying a horizontal line form.
  • the display panel DP when the display panel DP needs to display a horizontal line, at least one row (one row or multiple consecutive rows) of pixels corresponding to the horizontal line is lit by the pixel driving circuit R of the row.
  • the plurality of pixels 600 in these rows there are a first sub-pixel 610 (for example, a red sub-pixel) and a third sub-pixel 630 (for example, a blue sub-pixel) close to the upper edge of the displayed horizontal line.
  • the human eye is not sensitive to the recognition of blue (third sub-pixel 630), and the third sub-pixel 630 is farther from the lower edge than the first sub-pixel 610. Therefore, the upper edge of the displayed horizontal line will be red. Close to the lower edge of the displayed horizontal line, there are a second color pixel 620 (for example, a green sub-pixel) and a third sub-pixel 630 (for example, a blue sub-pixel).
  • a second color pixel 620 for example, a green sub-pixel
  • a third sub-pixel 630 for example, a blue sub-pixel
  • FIG. 7B is a schematic diagram of the display panel DP of the comparative embodiment displaying a vertical line form.
  • the human eye since the human eye has poor ability to recognize blue (for example, the luminous color of the blue sub-pixel 630 ′), the human eye can see red (for example, the luminous color of the red sub-pixel 610 ′). luminescence color) and green (eg, the luminescence color of green sub-pixel 620'). In this way, when horizontal and vertical lines are displayed, the vertical lines are thinner and the horizontal lines are thicker.
  • FIG. 8A is a schematic diagram showing a diagonal shape of the display panel DP of the comparative embodiment.
  • FIG. 8B is a schematic diagram of the display panel DP of the comparative embodiment showing another diagonal line shape.
  • the display panel DP displays a diagonal line shape
  • the displayed diagonal lines are composed of dots, and each dot is displayed and emitted by pixels
  • this comparative embodiment The arrangement of the pixels in the example causes a step between two adjacent pixels, so the comparison example will have a step-like feeling when the diagonal line is displayed.
  • FIG. 9A is a schematic diagram of a display panel DP displaying a horizontal line form according to some embodiments.
  • the display panel DP displays a horizontal line form, among the multiple pixels 600 in a row, except for the first sub-pixel 610 (for example, a red sub-pixel) at the upper edge of the display horizontal line , and there is a second sub-pixel 620 (for example, a green sub-pixel) slightly farther from the upper edge than the first sub-pixel 610.
  • human eyes are more sensitive to red and green. Therefore, when the horizontal line form is displayed, both the first sub-pixel 610 and the second sub-pixel 620 can be seen at the upper edge of the displayed horizontal line.
  • FIG. 9B is a schematic diagram of the display panel DP displaying a vertical line form according to some embodiments.
  • the display panel DP displays a vertical line form
  • red and green can be seen.
  • the width of the two is the same.
  • FIG. 10A is a schematic diagram of a display panel DP showing a diagonal line shape according to some embodiments.
  • FIG. 10B is a schematic diagram of the display panel DP showing another diagonal line shape according to some embodiments.
  • the first sub-pixel 610 , the second sub-pixel 620 and the third sub-pixel 600 of the plurality of pixels 600 The sub-pixels 630 are all arranged along the diagonal display direction. Furthermore, the first sub-pixel 610, the second sub-pixel 620 and the third sub-pixel 630 have no overlapping portions along the diagonal display direction. Therefore, when the display panel DP displays a diagonal line shape, the pixels 600 are continuous, so that the displayed diagonal line does not have a step-like feel.
  • the arrangement of the pixels 600 in this embodiment can increase the area of the third sub-pixel 630, and ultimately achieve the effect of increasing the aperture ratio of the third sub-pixel 630.
  • the display panel DP displays a horizontal line shape
  • the display panel DP displays a diagonal line shape
  • the pixels 600 are continuous, so that the displayed diagonal line does not have a step-like feel.
  • Figure 10C is a connection structure diagram of sub-pixels and pixel driving circuits.
  • Figure 10D is an alternative structural diagram of Figure 10C.
  • each sub-pixel has a coupling point D coupled to the pixel driving circuit R.
  • the sub-pixel includes a first electrode (eg, anode) 321 and a second electrode (eg, cathode) 323 that are oppositely arranged.
  • the first electrode 321 is located on a side of the sub-pixel close to the base substrate 100 .
  • the first electrode 321 of the sub-pixel and the corresponding pixel driving circuit R have an overlapping portion, and a via hole GK is opened in the overlapping portion (the via hole of the first sub-pixel 610 is denoted as GK1, and the via hole of the second sub-pixel 610 is denoted as GK1.
  • the via hole of 620 is marked as GK2, and the via hole of the third sub-pixel 630 is marked as GK3).
  • the first electrode 321 of the sub-pixel and the pixel driving circuit R are electrically connected at the position of the via hole GK.
  • the coupling point D refers to the location of the via GK.
  • the distance between the geometric center (also called the geometric center of gravity) of each coupling point D of at least two sub-pixels with different emitting colors and their respective corresponding pixel openings K is different.
  • the distance between the coupling point D and the pixel opening K refers to the distance along the second direction Y from the geometric center of the coupling point D to the point on the pixel opening K that is closest to the coupling point D.
  • the coupling point of the first sub-pixel 610 is marked as D1
  • the coupling point of the second sub-pixel 620 is marked as D2
  • the coupling point of the third sub-pixel 630 is marked as D3.
  • the distance between the coupling point D1 and the first pixel opening K1 is marked as CM1
  • the distance between the coupling point D2 and the second pixel opening K2 is marked as CM2
  • the distance between the coupling point D3 and the third pixel opening K3 is marked respectively.
  • CM3 At least two of D1, D2 and D3 have different distances from their respective corresponding pixel openings (for example, the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3).
  • D1, D2 and D3 have different distances from their respective corresponding pixel openings K.
  • CM1 is larger than CM2 and CM3, and CM2 and CM3 are approximately equal.
  • CM3 is larger than CM1 and CM2, and CM1 and CM2 are approximately equal.
  • the first electrode 321 includes a connecting portion TA and a main body portion TB that are connected as one body.
  • the pixel opening K exposes at least a portion of the main body portion TB.
  • a portion of the main body portion TB overlaps with the orthographic projection of the pixel opening K on the base substrate 100 , and the other portion does not overlap.
  • the orthographic projection of the main body portion TB on the base substrate is located within the orthographic projection of the pixel opening K on the base substrate 100 .
  • the coupling point D of the sub-pixel is located in the area where the connection portion TA is located.
  • the main body part TB has the same shape as the corresponding pixel opening K, and the outline LK of the main body part TB is one circle outwardly expanded from the pixel opening K corresponding to the main body part TB.
  • the connecting portion TA and the main body portion TB have the outline LK of the main body portion TB as a dividing line.
  • connection portion TA corresponding to at least two sub-pixels with different emitting colors (for example, two or three of the first sub-pixel 610, the second sub-pixel 620 and the third sub-pixel 630 with different emitting colors),
  • the maximum size in the second direction Y is different.
  • the connection portion corresponding to the first sub-pixel 610 is referred to as the first connection portion TA1
  • the connection portion corresponding to the second sub-pixel 620 is referred to as the second connection portion TA2
  • the connection portion corresponding to the third sub-pixel 630 is referred to as the first connection portion TA1.
  • the maximum dimension of the first connecting part TA1 in the second direction Y is denoted as the first maximum dimension ZC1
  • the maximum dimension of the second connecting part TA2 in the second direction Y is denoted as the third connecting part TA3.
  • the second maximum dimension ZC2 and the maximum dimension of the third connection portion TA3 in the second direction Y are recorded as the third maximum dimension ZC3.
  • the first maximum size ZC1 is larger than the second maximum size ZC2 and the third maximum size ZC3.
  • the second largest size ZC2 and the third largest size ZC3 are approximately equal.
  • the third maximum size ZC3 is larger than the second maximum size ZC2 and the first maximum size ZC1.
  • the second maximum dimension ZC2 and the first maximum dimension ZC1 are approximately equal.
  • Figure 11A is an alternative structural diagram of Figure 4A.
  • Figure 11B is an alternative structural diagram of Figure 4B.
  • embodiments of the present invention provide a display panel DP.
  • On the display panel DP at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 included in an opening unit O is a pixel opening with a cut corner portion.
  • the pixel opening having the corner cutout portion will be referred to as the corner cutout opening QK.
  • an opening unit O includes a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3. Any one or two of the three are corner-cut openings QK, and the remaining pixel openings are not corner-cut openings. QK; or, all three are QK with cut corners.
  • FIG. 11C is a perspective view of the second pixel opening in FIG. 11A.
  • the chamfered opening QK has a chamfered portion QK1.
  • the lower port XD of the chamfered opening QK is substantially polygonal, and the chamfered portion QK1 of the chamfered opening QK makes at least one (eg, one, or multiple) corner position of the polygon recessed.
  • the lower port of the corner cutout QK is basically rectangular and is recessed at two corner locations.
  • the lower port XD of the corner-cut opening QK refers to the exposed lower surface of the pixel opening K (for example, the first pixel opening K1. Also, the second pixel opening K2.
  • the upper port SD of the corner-cut opening QK refers to the port corresponding to the upper surface of the pixel opening K (for example, the first pixel opening K1.
  • the third pixel opening K3. the shape of the upper port SD of the chamfered opening QK is substantially the same as that of the lower port XD, and the chamfered portion QK1 of the chamfered opening QK also makes at least one (for example, one, or multiple) corners of the upper port SD Recessed location.
  • the orthographic projection of the upper port SD of the chamfered opening QK on the substrate substrate covers the orthographic projection of the lower port XD of the chamfered corner opening QK on the substrate substrate, that is, the size of the upper port SD of the chamfered corner opening QK is larger than Dimensions of the lower port XD of the cutaway opening QK. Based on this, the chamfered portion QK1 of the chamfered opening QK is arranged obliquely.
  • the chamfered portions QK1 are multiple in a row, and the plurality of chamfered portions QK1 are connected together to form an arc-shaped edge.
  • the edges of the first pixel opening K1 , the second pixel opening K2 and the third pixel opening K3 of the display panel DP are arc-shaped transitions with less sharp vertex angles, the first sub-pixel 610 and the second pixel opening K3 can be reduced in size.
  • the sub-pixel 620 and the third sub-pixel 630 have a jagged visual effect.
  • the first pixel opening K1 and the second pixel opening K2 are both pixel openings with a corner cutout (corner cutout QK).
  • the chamfered corner portion QK1 of the first pixel opening K1 and the chamfered corner portion QK1 of the second pixel opening K2 are respectively located on the side of the first pixel opening K1 and the second pixel opening K2 away from each other.
  • the two corner chamfered portions of the first pixel opening K1 are respectively referred to as the first chamfered corner portion QK(a) and the second chamfered corner portion QK(b).
  • the two chamfered portions of the second pixel opening K2 are respectively referred to as the third chamfered portion QK(c) and the fourth chamfered portion QK(d).
  • the first pixel opening K1 may have one of a first corner portion QK(a) and a second corner portion QK(b), and the second pixel opening K2 may have a third corner portion QK(c) and a fourth corner portion QK(b). Corner part QK(d).
  • the first pixel opening K1 has a first corner portion QK(a)
  • the second pixel opening K2 has a third corner portion QK(c).
  • the first pixel opening K1 has a first corner portion QK(a), and the second pixel opening K2 has a fourth corner portion QK(d). Since the light-emitting area of each sub-pixel in a pixel 600 has approximately the same shape as the corresponding pixel opening K in an opening unit O, the sharp vertex angle in the outline of the pixel 600 is reduced, thereby reducing the size of the display panel. The image presented has a jagged visual effect.
  • one of the first sub-pixel 610 and the second sub-pixel 620 is a red sub-pixel, and the other is a green sub-pixel.
  • the first sub-pixel 610 is a red sub-pixel
  • the second sub-pixel 620 is a green sub-pixel.
  • the first sub-pixel 610 is a green sub-pixel
  • the second sub-pixel 620 is a red sub-pixel. Because the human eye is more sensitive to red and green than to blue. Therefore, if the pixel opening K corresponding to the red sub-pixel and the green sub-pixel both has a corner cutout portion QK1; further, the cutoff corner portions QK1 of the two subpixels can be respectively located on the side away from each other. This can further reduce the visual effect of jagged images on the display panel.
  • FIG. 11D is a structural diagram of a pixel opening with a chamfered portion.
  • the pixel opening (cut corner opening QK) having a corner portion has an axially symmetric structure.
  • the symmetry axis ZL of the pixel opening having the chamfered portion (the chamfered opening QK) is parallel to the third direction E.
  • the light-emitting area of the sub-pixel corresponding to the pixel opening (cut corner opening QK) having a corner portion may also have an axially symmetric structure.
  • the pixel opening (corner opening QK) having a corner cutout also has a third side wall QK4 and a fourth sidewall QK5 adjacent to the corner cutout QK1 .
  • the chamfered portion QK1 forms a third vertex angle ⁇ 3 and a fourth vertex angle ⁇ 4 with the third side wall QK4 and the fourth side wall QK5 respectively.
  • the third vertex angle ⁇ 3 is 0.9 to 1.1 times the fourth vertex angle ⁇ 4.
  • the shape of the orthographic projection of the pixel opening (corner opening QK) with the chamfered portion on the substrate 100 is an axially symmetrical figure, so the orthographic projection of the corresponding sub-pixel on the substrate 100 is also an axially symmetrical figure, This makes the display effect of the display panel more beautiful.
  • FIG. 12A is an alternative structural diagram of FIG. 5 .
  • Figure 12B is an alternative structural diagram of Figure 12A.
  • a plurality of spacers 900 are located on a side of the pixel defining layer 310 away from the base substrate 100 .
  • the plurality of spacers 900 are located in a region of the pixel defining layer 310 where portions other than the plurality of pixel openings K (for example, the first pixel opening K1 , the second pixel opening K2 and the third pixel opening K3 ) are located.
  • the bottom surface of the spacer 900 is in contact with the top surface of the pixel defining layer 310 .
  • the pixel defining layer 310 is formed first, and then the spacer 900 is formed on the pixel defining layer 310; and then the light emitting layer 322 is formed.
  • the orthographic projection of the spacer 900 on the pixel defining layer 310 is surrounded by the outline P and the second and third pixel openings K2 and K3 adjacent to each other.
  • the orthographic projection of the spacer 900 on the pixel definition layer 310 is surrounded by the outline P and two third pixel openings K3 and one second pixel opening K2 that are adjacent to each other.
  • the orthographic projection of the spacer 900 on the pixel defining layer 310 is surrounded by the first pixel opening K1 , the second pixel opening K2 and the third pixel opening K3 that are adjacent to each other.
  • the orthographic projection of the spacer 900 on the pixel definition layer 310 is surrounded by the outline P and two first pixel openings K1 and one second pixel opening K2 adjacent to each other.
  • the orthographic projection of the spacer 900 on the pixel defining layer 310 is surrounded by the first pixel opening K1 , the second pixel opening K2 and the two third pixel openings K3 that are adjacent to each other.
  • the orthographic projection of A on B in this article refers to the projection of A on the plane of B in the direction perpendicular to the plane of B.
  • the orthographic projection of the spacer 900 on the pixel defining layer 310 refers to the projection of the spacer 900 on the pixel defining layer 310 along the thickness direction of the pixel defining layer 310 .
  • the spacer 900 in this embodiment is used to support a high-precision metal mask (Fine Metal Mask, FMM) when evaporating luminescent materials, and the spacer 900 in this embodiment is adapted to the arrangement of sub-pixels.
  • FMM Fe Metal Mask
  • spacers 900 are provided between the contour line P and the sub-pixels close to the contour line P. This increases the number of spacers 900 while fully utilizing the space, thereby improving the stability of the FMM support. sex.
  • inventions of the present invention provide a display panel DP.
  • the plurality of spacers 900 of the display panel DP include a plurality of first spacers 910 .
  • the first spacer 910 is located between two third pixel openings K3 arranged along the first direction X and adjacent to each other.
  • the first spacer 910 is located between the first pixel opening K1 and the second pixel opening K2 which are arranged along the second direction Y and adjacent to each other.
  • the position where the first spacer 910 is located is called the first position W1.
  • the first position W1 is: two third pixel openings K3 arranged along the first direction X and adjacent to each other, and the first pixel opening K1 and the second pixel opening K2 arranged along the second direction Y and adjacent to each other. at the intersection position.
  • the first spacer 910 is surrounded by the two third pixel openings K3, the first pixel opening K1 and the second pixel opening K2 at the first position W1.
  • a first spacer 910 is provided at each first position W1.
  • these first spacers 910 are arranged in an array. In this way, the first spacers 910 are arranged more evenly, which is beneficial to improving the support stability of the FMM.
  • the first pixel opening K1 , the second pixel opening K2 and the third pixel opening K3 adjacent to the first spacer 910 At least one of them is a pixel opening having a corner portion (corner opening QK).
  • the corner-cut portion is located at a position where the pixel opening is close to the first spacer 910 (that is, at the first position W1) and has a corner-cut portion QK1.
  • the first pixel opening K1, the second pixel opening K2 and the two third pixel openings K3 near the first position W1 can all be the pixel opening QK with a corner cutout, and each of them can have a cutout corner section QK1.
  • the first pixel opening K1 and the second pixel opening K2 close to the first position W1 can both be pixel openings with corner cutting portions (corner cutting openings QK), and both have corner cutting portions QK1; the third pixel opening K3 is not QK with corner cutout.
  • the first pixel opening K1 close to the first position W1 is a corner opening QK and has a corner portion QK1; the second pixel opening K2 and the third pixel opening K3 are not the corner opening QK.
  • the second pixel opening K2 close to the first position W1 is a corner opening QK and has a corner portion QK1; the first pixel opening K1 and the third pixel opening K3 are not the corner opening QK.
  • the two third pixel openings K3 close to the first position W1 are corner-cut openings QK, and both have corner-cut portions QK1; the first pixel opening K1 and the second pixel opening K2 are not corner-cut openings QK.
  • the orthographic projection of the cut corner portion QK1 on the base substrate 100 does not overlap with the orthographic projection of the first spacer 910 on the base substrate 100 .
  • the chamfered portion of the first pixel opening K1 and the chamfered portion of the second pixel opening K2 close to the first position W1 do not overlap with the orthographic projection of the first spacer 910 on the base substrate.
  • the chamfered portions of the two third pixel openings K3 close to the first position W1 do not overlap with the orthographic projection of the first spacer 910 on the base substrate.
  • the chamfered portion of the first pixel opening K1 and the chamfered portion of the second pixel opening K2 close to the first position W1 do not overlap with the orthographic projection of the first spacer 910 on the substrate.
  • At least one of the first pixel opening K1 , the second pixel opening K2 and the third pixel opening K3 adjacent to the first spacer 910 is a pixel opening with a cut-off portion (cut-corner opening QK ), thus causing the first pixel opening K1, the second pixel opening K2 and the third pixel opening K3 to make corresponding adaptive adjustments to the first spacer 910, thereby increasing the area of the first spacer 910, thereby improving the Stability of FMM support.
  • FIG. 13A is a structural diagram of the pixel opening with a corner cutout in FIG. 12B .
  • a pixel opening (corner opening QK) with a corner cutout for example, the first pixel opening K1 is a corner cutout opening QK.
  • the second pixel opening K2 is the corner-cut opening QK.
  • the third pixel opening K3 is the corner-cut opening QK.
  • the chamfered portion forms a first vertex angle ⁇ 1 and a second vertex angle ⁇ 2 with the first side wall QK2 and the second side wall QK3 respectively, and the first vertex angle ⁇ 1 is 0.9 to 1.1 times the second vertex angle ⁇ 2.
  • the pixel opening K (corner opening QK) having the corner portion QK1 also includes a fifth sidewall QK6 opposite to the second sidewall QK3 along the third direction E, and , the sixth side wall QK7 is opposite to the first side wall QK2 along the fourth direction F, and the fourth direction F intersects the third direction E. For example, perpendicular to each other.
  • the difference between the dimension of the fifth side wall QK6 along the fourth direction F (marked as the third dimension U3) and the dimension of the second side wall QK3 along the fourth direction F (marked as the second dimension U2) is the first difference
  • the difference between the size of the sixth side wall QK7 along the third direction E (marked as the fourth dimension U4) and the size of the first side wall QK2 along the third direction E (marked as the first dimension U1) is the second difference
  • the first size U1, the second size U2, the third size U3 and the fourth size U4 all refer to the size of the lower port of the pixel opening K.
  • the line connecting the geometric centers is parallel to the first direction X.
  • a line connecting the geometric centers of two adjacent first pixel openings K1 in the first direction X is parallel to the first direction X.
  • a line connecting the geometric centers of two adjacent second pixel openings K2 in the first direction X is parallel to the first direction X.
  • a line connecting the geometric centers of two adjacent third pixel openings K3 in the first direction X is parallel to the first direction X.
  • two adjacent (for example, every two adjacent, or two partially adjacent) pixel openings for example, two adjacent sub-pixels having the cut-angle portion QK1 and corresponding to the same emitting color) , two adjacent first pixel openings K1.
  • two adjacent third pixel openings K3, the line connecting their respective geometric centers is parallel to the second direction Y.
  • two adjacent third pixel openings K3) the line connecting their respective geometric centers is parallel to the first direction X.
  • two adjacent (for example, every two adjacent, or partially adjacent two) pixel openings (for example, two adjacent ones) having the cut-angle portion QK1 and corresponding to sub-pixels with the same emitting color are opened in the second direction Y.
  • two adjacent third pixel openings K3), the line connecting their respective geometric centers is parallel to the second direction Y.
  • each of the pixel openings includes a corner portion QK1 located at the same corner position.
  • the pixel opening K has a first corner J1, a second corner J2, a third corner J3 and a fourth corner J4.
  • the corner portions QK1 of each adjacent two first pixel openings K1 are located at the second corner portion J2 of the first pixel opening K1.
  • the corner portions QK1 of each adjacent two third pixel openings K3 are located at the first corner J1 and the fourth corner J4 of the third pixel opening K3.
  • a part of the corner cutting portions QK1 of two adjacent third pixel openings K3 are located at the first corner J1 and the fourth corner J4 of the third pixel opening K3.
  • the two adjacent pixel openings (for example, the two adjacent first pixels) Opening K1.
  • two adjacent third pixel openings K3) have the same shape and size.
  • the first sub-pixel 610 , the second sub-pixel 620 and the third sub-pixel 630 in the pixel 600 all extend along the fourth direction F.
  • the fourth direction F and the third direction E form an angle of 80° to 100°.
  • Figure 13B is an enlarged view of position H in Figure 12B.
  • Figure 14 is another alternative structural diagram of Figure 12A.
  • Figure 15 is another alternative structural diagram of Figure 12A.
  • Figure 16 is another alternative structural diagram of Figure 12A.
  • Figure 17 is another alternative structural diagram of Figure 12A.
  • Figure 18 is yet another alternative structural diagram of Figure 12A.
  • Figure 19 is yet another alternative structural diagram of Figure 12A.
  • Figure 20 is another alternative structural diagram of Figure 12A.
  • Figure 21 is yet another alternative structural diagram of Figure 12A.
  • the first pixel opening K1 adjacent to the first spacer 910 is a pixel opening with a corner cutout (corner cutout QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the first pixel opening K1 on the pixel defining layer 310 (not shown in the figure) have sides that are close to each other and are substantially parallel. That is to say, the orthographic projection of the corner opening QK of the first pixel opening K1 on the pixel defining layer 310 has the first side B1 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a second side B2 close to the first position W1.
  • the first side B1 and the second side B2 are approximately parallel.
  • the first pixel opening K1 adjacent to the first spacer 910 is a pixel opening having a cut-corner portion (cut-corner opening QK).
  • the chamfered portion of the first pixel opening K1 is substantially parallel to the first direction X. That is, the corner opening QK of the first pixel opening K1 close to the first position W1 is substantially parallel to the first direction X.
  • the first pixel opening K1 adjacent to the first spacer 910 is a pixel opening having a cut-corner portion (cut-corner opening QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the first pixel opening K1 on the pixel defining layer 310 have sides close to each other and substantially parallel. That is to say, the orthographic projection of the corner opening QK of the first pixel opening K1 on the pixel defining layer 310 has the first side B1 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a second side B2 close to the first position W1.
  • the first side B1 and the second side B2 are approximately parallel.
  • the first pixel opening K1 adjacent to the first spacer 910 is a pixel opening having a cut-corner portion (cut-corner opening QK).
  • the chamfered portion of the first pixel opening K1 is substantially parallel to the first direction X. That is, the corner opening QK of the first pixel opening K1 close to the first position W1 is substantially parallel to the first direction X.
  • This embodiment can improve the stability of the FMM support. The reasons are referred to the previous embodiments and will not be described again here.
  • the second pixel opening K2 adjacent to the first spacer 910 is a pixel opening with a corner cutout (corner cutout QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the second pixel opening K2 on the pixel defining layer 310 have sides close to each other and substantially parallel. That is to say, the orthographic projection of the corner opening QK of the second pixel opening K2 on the pixel defining layer 310 has the third side B3 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a fourth side B4 close to the first position W1.
  • the third side B3 and the fourth side B4 are approximately parallel.
  • the second pixel opening K2 adjacent to the first spacer 910 is a pixel opening having a chamfered portion (corner chamfered opening QK), and the chamfered corner portion of the second pixel opening K2 is substantially parallel to the first direction. That is, the corner opening QK of the second pixel opening K2 close to the first position W1 is substantially parallel to the first direction X.
  • the second pixel opening K2 adjacent to the first spacer 910 is a pixel opening having a cut-corner portion (cut-corner opening QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the second pixel opening K2 on the pixel defining layer 310 have sides close to each other and substantially parallel. That is to say, the orthographic projection of the corner opening QK of the second pixel opening K2 on the pixel defining layer 310 has the third side B3 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a fourth side B4 close to the first position W1.
  • the third side B3 and the fourth side B4 are approximately parallel.
  • the second pixel opening K2 adjacent to the first spacer 910 is a pixel opening having a cut corner portion (cut corner opening QK), and the cut corner portion of the second pixel opening K2 is substantially parallel to the first direction. That is, the corner opening QK of the second pixel opening K2 close to the first position W1 is substantially parallel to the first direction X.
  • the third pixel opening K3 adjacent to the first spacer 910 is a pixel opening with a corner cutout (corner cutout QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the third pixel opening K3 on the pixel defining layer 310 have sides that are close to each other and are substantially parallel. That is to say, the orthographic projection of the corner opening QK of the third pixel opening K3 on the pixel defining layer 310 has the fifth side B5 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a sixth side B6 close to the first position W1.
  • the fifth side B5 and the sixth side B6 are approximately parallel.
  • the third pixel opening K3 adjacent to the first spacer 910 is a pixel opening having a chamfered portion (corner chamfered opening QK), and the chamfered corner portion of the third pixel opening K3 is substantially parallel to the second direction Y. . That is, the corner opening QK of the third pixel opening K3 close to the first position W1 is substantially parallel to the second direction Y.
  • the third pixel opening K3 adjacent to the first spacer 910 is a pixel opening having a cut-corner portion (cut-corner opening QK).
  • the first spacer 910 and the orthographic projection of the corner opening QK of the third pixel opening K3 on the pixel defining layer 310 have sides that are close to each other and are substantially parallel. That is to say, the orthographic projection of the corner opening QK of the third pixel opening K3 on the pixel defining layer 310 has the fifth side B5 close to the first position W1.
  • the orthographic projection of the first spacer 910 on the pixel definition layer 310 has a sixth side B6 close to the first position W1.
  • the fifth side B5 and the sixth side B6 are approximately parallel.
  • the third pixel opening K3 adjacent to the first spacer 910 is a pixel opening having a corner portion (corner opening QK), and the corner portion of the third pixel opening K3 is substantially parallel to the second direction Y. That is, the corner opening QK of the third pixel opening K3 close to the first position W1 is substantially parallel to the second direction Y.
  • Figure 22 is a possible shape structure diagram of the orthographic projection of the first spacer on the pixel definition layer.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 includes a rectangle (A1 to A5 in Figure 22 ), square (A6 ⁇ A7 in Figure 22), parallelogram (A8 ⁇ A9 in Figure 22), rhombus (A9 in Figure 22), trapezoid (A10 ⁇ A11 in Figure 22), five One or more pattern types include hexagons, hexagons (A12-A13 in Figure 22), ovals (A14 in Figure 22), and circles (A15 in Figure 22).
  • the orthographic projection of a first spacer 910 on the pixel defining layer 310 is of a rectangular pattern type, it means that the shape of the orthographic projection of the first spacer 910 on the pixel defining layer 310 is generally a rectangle.
  • it can be a standard rectangle (A1 in Figure 22), or a quasi-rectangle with chamfers or rounded corners (A2-A5 in Figure 22).
  • the orthographic projection of a first spacer 910 on the pixel defining layer 310 belongs to the square pattern type, it means that the shape of the orthographic projection of the first spacer 910 on the pixel defining layer 310 is approximately a square.
  • it can be a standard square (A6 in Figure 22), or a quasi-square with chamfers or rounded corners (A7 in Figure 22).
  • Figure 12B shows some possible shapes of the orthographic projection of the first spacer 910 on the pixel definition layer 310, but the shape of the pixel opening K protected by this embodiment is not limited thereto.
  • Figure 23 is another alternative structural diagram of Figure 12A.
  • Figure 24 is another alternative structural diagram of Figure 12A.
  • embodiments of the present invention provide a display panel DP.
  • the display area AA of the display panel DP has a contour line P, and a plurality of spacers 900 are located in the display area AA.
  • the plurality of spacers 900 include a plurality of third spacers 930.
  • the third spacers 930 are located at two adjacent pixel openings K (for example, two adjacent third pixel openings K3) close to the outline P. For example, adjacent A second pixel opening K2 and a first pixel opening K1. Another example, between two adjacent first pixel openings K1).
  • the display area AA has a first contour line P1 extending along the first direction X and a second contour line P2 extending along the second direction Y.
  • the third spacer 930 is divided into a first spacer group Z1 extending along the first direction X and a second spacer group Z2 extending along the second direction Y. Both the first spacer group Z1 and the second spacer group Z2 include at least one third spacer 930 .
  • the third spacer 930 in the first spacer group Z1 is located between two adjacent pixel openings K close to the first contour line P1.
  • the third spacer 930 in the second spacer group Z2 is located between two adjacent pixel openings K close to the second contour line P2.
  • the third spacers 930 can be arranged in as large a space as possible, and the spacers 900 can be arranged both inside and on the edge of the display area AA, thus improving the efficiency of the spacers.
  • the layout density of objects 900 is improved to improve the stability of FMM support.
  • the orthographic projection of the third spacer 930 on the pixel definition layer 310 has an edge close to and substantially parallel to the contour line P.
  • the orthographic projection of the third spacer 930 in the first spacer group Z1 on the pixel definition layer 310 has a seventh side B7, and the seventh side B7 is substantially parallel to the first contour line P1.
  • the orthographic projection of the third spacer 930 in the second spacer group Z2 on the pixel definition layer 310 has an eighth side B8, and the eighth side B8 is substantially parallel to the second contour line P2.
  • the area of the third spacer 930 is increased as much as possible, so that the third spacer 930 supports the stability of the FMM.
  • the orthographic projection of one of the two adjacent pixel openings K close to the contour line P and the third spacer 930 on the pixel defining layer 310 Both have sides that are close to each other and parallel to each other.
  • the position where the third spacer 930 is disposed is called the second position W2.
  • the second position W2 is located between the two adjacent pixel openings K and the contour line P. That is to say, near the second position W2, the orthographic projections of one or two of the two adjacent pixel openings K and the third spacer 930 on the pixel defining layer 310 have sides that are close to each other and parallel to each other.
  • the orthographic projection of the third spacer 930 on the pixel defining layer 310 near the second position W2 has a ninth side B9 and a tenth side B10.
  • the ninth side B9 and the tenth side B10 are respectively parallel to one side of the orthographic projection of the two adjacent pixel openings K near the second position W2 on the pixel definition layer 310 .
  • the effects achieved by this embodiment can be referred to the embodiment, and will not be described again here.
  • the shape of the orthographic projection of the third spacer 930 on the pixel definition layer 310 includes triangle, rectangle, One or more pattern types of square, parallelogram, trapezoid, and oval. In the same space, use the space as much as possible to arrange the third spacers 930 .
  • embodiments of the present invention provide a display panel DP.
  • the shapes of the orthographic projections of the first spacer 910 and the third spacer 930 on the pixel definition layer 310 are different.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a rectangle.
  • the shape of the orthographic projection of the third spacer 930 on the pixel definition layer 310 is a triangle.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a trapezoid.
  • the shape of the orthographic projection of the third spacer 930 on the pixel definition layer 310 is a rectangle.
  • the orthographic projection of the first spacer 910 and the fourth spacer 940 on the pixel definition layer 310 The shapes are different.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a rectangle.
  • the shape of the orthographic projection of the fourth spacer 940 on the pixel definition layer 310 is a triangle.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a trapezoid.
  • the shape of the orthographic projection of the fourth spacer 940 on the pixel definition layer 310 is a triangle.
  • the first spacer 910 and the third spacer 930 are defined in pixels
  • the shape of the orthographic projection on layer 310 is different.
  • the shapes of the orthographic projections of the first spacer 910 and the fourth spacer 940 on the pixel definition layer 310 are different.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a rectangle.
  • the shape of the orthographic projection of the third spacer 930 and the fourth spacer 940 on the pixel definition layer 310 is a triangle.
  • the shape of the orthographic projection of the first spacer 910 on the pixel definition layer 310 is a trapezoid.
  • the shape of the orthographic projection of the third spacer 930 and the fourth spacer 940 on the pixel definition layer 310 is a rectangle.
  • embodiments of the present invention provide a display panel DP.
  • the display panel DP includes the first spacer 910 and the third spacer 930: the orthographic projections of the first spacer 910 and the third spacer 930 on the pixel definition layer 310 have the same shape and size. consistent.
  • the orthographic projections of the first spacer 910 and the third spacer 930 on the pixel definition layer 310 are rectangles with the same size.
  • embodiments of the present invention provide a display panel DP.
  • the plurality of pixel openings K of the display panel DP are divided into a plurality of opening groups KI arranged along the fourth direction F.
  • the fourth direction F is perpendicular to the third direction E.
  • the plurality of spacers 900 also includes at least one fourth spacer 940 .
  • the fourth spacer 940 is located between an opening group located at the outermost edge of the display panel DP and the contour line P among the plurality of opening groups KI.
  • the opening group KI located at the outermost edge of the display panel DP is called the third opening group KI3.
  • the fourth spacer 940 is located between the third opening group KI3 and the contour line P. In this way, the fourth spacer 940 is surrounded by the third opening group KI3 and the contour line P.
  • a fourth spacer 940 is provided between the third opening group KI3 and the contour line P, thereby utilizing the space in this area to increase the density of the spacer 900 and improve the stability of the FMM support.
  • the fourth spacer 940 and the orthographic projection of an opening group KI located at the edge of the display panel on the pixel definition layer 310 are close to each other and approximately parallel sides. That is to say, the orthographic projections of the fourth spacer 940 and the third opening group KI3 on the pixel definition layer 310 both have sides that are close to each other and are substantially parallel.
  • the orthographic projection of the fourth spacer 940 on the pixel definition layer 310 has an eleventh side B11.
  • the orthographic projection of the third opening group KI3 on the pixel definition layer 310 has a twelfth side B12.
  • the eleventh side B11 and the twelfth side B12 are close to each other and substantially parallel.
  • the orthographic projection of the fourth spacer 940 on the pixel definition layer 310 and the contour line P have sides that are close to each other and are substantially parallel.
  • the orthographic projection of the fourth spacer 940 on the pixel definition layer 310 has a thirteenth side B13.
  • the thirteenth side B13 and the contour line P are close to each other and substantially parallel.
  • FIG. 25 is another alternative structural diagram of Figure 12A.
  • multiple pixel openings K are divided into multiple opening groups KI arranged along the fourth direction F.
  • One (e.g., each) opening group KI includes at least one (e.g., one.
  • the plurality of spacers 900 includes at least one (for example, one. For example, a plurality of) second spacers 920 .
  • the second spacer 920 is elongated and extends along the third direction E between two adjacent opening groups KI.
  • the elongated second spacers 920 make the arrangement of the second spacers 920 more uniform, further improving the stability of supporting the FMM.
  • two adjacent opening groups KI include a first opening group KI1 and a second opening group KI2.
  • the length L1 of the first opening group KI1 along the third direction E is greater than the length L2 of the second opening group KI2 along the third direction E.
  • the length L3 of the second spacer 920 along the third direction E is less than or equal to the length L1 of the first opening group KI1 along the third direction E, and is greater than or equal to the length L2 of the second opening group KI2 along the third direction E.
  • the orthographic projections of the second spacer 920 and the first opening group KI1 on the pixel defining layer 310 have both ends flush. That is to say, the orthographic projections of the two ends of the second spacer 920 and the two ends of the first opening group KI1 on the pixel definition layer 310 are flush.
  • the second spacer 920 can support the FMM in the entire length of the first opening group KI1, thereby improving the stability of supporting the FMM.
  • the arrangement of the second spacers 920 is made more uniform, further improving the stability of the FMM support.
  • Figure 26 is another alternative structural diagram of Figure 25.
  • the plurality of spacers 900 include second spacers 920 , third spacers 930 and fourth spacers 940 .
  • the third spacer 930 and the fourth spacer 940 reference may be made to the foregoing embodiments and will not be described again here.

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Abstract

本公开的实施例提供了一种显示面板及显示装置。该显示面板包括衬底基板、设置在衬底基板上像素界定层、设置在衬底基板上的多个像素和多个隔垫物。像素界定层上包括第一像素开口、第二像素开口和第三像素开口。多个像素排列成M行N列，行包括沿第一方向排列的N个像素，列包括沿第二方向排列的M个像素。像素包括位于第一像素开口处的第一子像素、位于第二像素开口处的第二子像素和位于第三像素开口处的第三子像素。第一子像素、第二子像素和第三子像素发光颜色不同且沿第三方向依次排列。多个隔垫物位于像素界定层远离衬底基板的一侧，且位于除多个像素开口以外的区域。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置具有高亮度、全视角、响应速度快、可柔性显示等一系列优点。OLED显示装置按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，简称PMOLED)和有源矩阵型OLED(Active Matrix OLED，简称AMOLED)。其中，AMOLED显示装置发光效能更高，可用作高分辨率的大尺寸显示装置。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底基板、像素界定层、多个像素和多个隔垫物。像素界定层设置在衬底基板上，像素界定层上包括多个像素开口，多个像素开口包括第一像素开口、第二像素开口和第三像素开口。多个像素设置在衬底基板上，多个像素排列成M行N列，行包括沿第一方向排列的N个像素，列包括沿第二方向排列的M个像素，M≥2，N≥2，第一方向和第二方向交叉。其中，像素包括发光颜色不同的多个子像素，多个子像素包括：位于第一像素开口处的第一子像素、位于第二像素开口处的第二子像素和位于第三像素开口处的第三子像素；第一子像素、第二子像素和第三子像素沿第三方向依次排列，第三方向与第一方向和第二方向均交叉。
在所述第三方向上，发光颜色相同且位置相邻的两个子像素由其他发光颜色的至少两个子像素间隔开，所述至少两个子像素的发光颜色各不相同。
在一些可能的实施方式中，还包括多个隔垫物，多个隔垫物位于像素界定层远离衬底基板的一侧，且位于像素界定层中除多个像素开口以外的部分所在的区域。
在一些可能的实施方式中，多个隔垫物包括多个第一隔垫物。第一隔垫物位于沿第一方向排列且彼此相邻的两个第三像素开口之间。且位于沿第二方向排列且彼此相邻的第一像素开口和第二像素开口之间。
在一些可能的实施方式中，与第一隔垫物相邻的第一像素开口、第二像素开口和第三像素开口中的至少一者为具有切角部分的像素开口。切角部分位于像素开口靠近第一隔垫物的位置处；切角部分在衬底基板上的正投影与第一隔垫物在衬底基板上的正投影不交叠。
在一些可能的实施方式中，具有切角部分的像素开口具有与切角部分相 邻的第一侧壁和第二侧壁。切角部分与第一侧壁和第二侧壁分别形成第一顶角和第二顶角，第一顶角为第二顶角的0.9倍～1.1倍。
在一些可能的实施方式中，具有切角部分的像素开口还包括与沿第三方向与第二侧壁相对的第五侧壁，以及，沿第四方向与第一侧壁相对的第六侧壁，第四方向与第三方向交叉。第五侧壁沿第四方向的尺寸与第二侧壁沿第四方向的尺寸的差值为第一差值，第六侧壁沿第三方向的尺寸与第一侧壁沿第三方向的尺寸的差值为第二差值，第一差值等于第二差值。
在一些可能的实施方式中，在第一方向上，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于第一方向。
示例性地，在第二方向上，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于第二方向。
示例性地，在第一方向，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于第一方向。以及，在第二方向，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于第二方向。
在一些可能的实施方式中，在第一方向或第二方向上，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自包含的切角部分位于各自相同的角部位置处。
在一些可能的实施方式中，相邻两个像素开口的形状和大小均一致。
在一些可能的实施方式中，像素中的第一子像素、第二子像素和第三子像素均沿第四方向延伸，第四方向与第三方向呈80°～100°的夹角。在一些可能的实施方式中，与第一隔垫物相邻的第一像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第一像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。
示例性地，与第一隔垫物相邻的第一像素开口为具有切角部分的像素开口，第一像素开口的切角部分大致平行于第一方向。
又示例性地，与第一隔垫物相邻的第一像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第一像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。以及，与第一隔垫物相邻的第一像素开口为具有切角部分的像素开口，第一像素开口的切角部分大致平行于第一方 向。
在一些可能的实施方式中，与第一隔垫物相邻的第二像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第二像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。
示例性地，与第一隔垫物相邻的第二像素开口为具有切角部分的像素开口，第二像素开口的切角部分大致平行于第一方向。
又示例性地，与第一隔垫物相邻的第二像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第二像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。以及，与第一隔垫物相邻的第二像素开口为具有切角部分的像素开口，第二像素开口的切角部分大致平行于第一方向。
在一些可能的实施方式中，与第一隔垫物相邻的第三像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第三像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。
示例性地，与第一隔垫物相邻的第三像素开口为具有切角部分的像素开口，第三像素开口的切角部分大致平行于第二方向。
又示例性地，与第一隔垫物相邻的第三像素开口为具有切角部分的像素开口。第一隔垫物与具有切角部分的第三像素开口在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。以及，与第一隔垫物相邻的第三像素开口为具有切角部分的像素开口，第三像素开口的切角部分大致平行于第二方向。
在一些可能的实施方式中，第一隔垫物在像素界定层上的正投影的形状包括三角形、长方形、正方形、平行四边形、梯形、六边形、椭圆形和圆形中的一种或多种图案类型。
在一些可能的实施方式中，多个像素开口分成沿第四方向排布的多个开口组，第四方向与第三方向交叉。多个隔垫物包括至少一个第二隔垫物。第二隔垫物为长条状，且在相邻两开口组之间沿第三方向延伸。
在一些可能的实施方式中，相邻两开口组包括第一开口组和第二开口组，第一开口组沿第三方向的长度大于第二开口组沿第三方向的长度。第二隔垫物沿第三方向的长度小于等于第一开口组沿第三方向的长度，且大于等于第二开口组沿第三方向的长度。
在一些可能的实施方式中，第二隔垫物和第一开口组在像素界定层上的正投影，两者的两端齐平。
在一些可能的实施方式中，显示面板包括具有轮廓线的显示区，多个隔垫物位于显示区中。多个隔垫物包括多个第三隔垫物；第三隔垫物位于靠近轮廓线的相邻两像素开口之间。
在一些可能的实施方式中，第三隔垫物在像素界定层上的正投影具有靠近且大致平行于轮廓线的边。
在一些可能的实施方式中，靠近轮廓线的相邻两像素开口中的一像素开口与第三隔垫物在像素界定层上的正投影，二者具有彼此靠近且相互平行的边。
在一些可能的实施方式中，第三隔垫物在像素界定层上的正投影的形状包括三角形、长方形、正方形、平行四边形、梯形和椭圆形中的一种或多种图案类型。
在一些可能的实施方式中，多个像素开口分成沿第四方向排布的多个开口组；第四方向与第三方向交叉。多个隔垫物还包括至少一个第四隔垫物，第四隔垫物位于多个开口组中位于显示面板最边缘的一开口组与轮廓线之间。
在一些可能的实施方式中，第四隔垫物与位于显示面板最边缘的一开口组在像素界定层上的正投影，两者具有彼此靠近且大致平行的边。
在一些可能的实施方式中，第四隔垫物在像素界定层上的正投影与轮廓线具有彼此靠近且大致平行的边。
在一些可能的实施方式中，在显示面板包括第一隔垫物和第三隔垫物的情况下：第一隔垫物和第三隔垫物在像素界定层上的正投影的形状不同。
示例性地，在显示面板包括第一隔垫物和第四隔垫物的情况下：第一隔垫物和第四隔垫物在像素界定层上的正投影的形状不同。
又示例性地，在显示面板包括第一隔垫物、第三隔垫物和第四隔垫物的情况下：第一隔垫物和第三隔垫物在像素界定层上的正投影的形状不同。第一隔垫物和第四隔垫物在像素界定层上的正投影的形状不同。
在一些可能的实施方式中，在显示面板包括第一隔垫物和第三隔垫物的情况下：第一隔垫物和第三隔垫物在像素界定层上的正投影的形状和大小均一致。
再一方面，提供一种显示装置。该显示装置包括如上述任一实施例的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施 例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作结构图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例提供的显示装置的正视图；
图2为根据一些实施例提供的显示面板的结构图；
图3A为图2示出的显示面板包含的多个层的叠置关系图；
图3B为图3A中有源图案层的结构图；
图3C为图3A中的第一导电图案层的结构图；
图3D为图3A中的有源图案层和第一导电图案层的结构图；
图3E为图3A中的第三导电图案层的结构图；
图3F为图3A中的有源图案层、第一导电图案层和第三导电图案层的结构图；
图3G为根据实施例提供的一种像素驱动电路R的等效电路图；
图4A为图3A示出的像素界定层中多个像素开口的排布图；
图4B为图3A示出的发光器件层中多个像素的排布图；
图5为图3A示出的发光器件层中一像素的结构图；
图6为对比实施例的发光器件层的多个像素的排布图；
图7A为对比实施例的显示面板DP显示横线形态的示意图；
图7B为对比实施例的显示面板DP显示竖线形态的示意图；
图8A为对比实施例的显示面板DP显示斜线形态的示意图；
图8B为对比实施例的显示面板DP显示另一种斜线形态的示意图；
图9A为根据一些实施例的显示面板DP显示横线形态的示意图；
图9B为根据一些实施例的显示面板DP显示竖线形态的示意图；
图10A为根据一些实施例的显示面板DP显示斜线形态的示意图；
图10B为根据一些实施例的显示面板DP显示另一种斜线形态的示意图；
图10C为子像素与像素驱动电路的连接结构图；
图10D为图10C的一种可替换的结构图；
图11A为图4A的一种可替换的结构图；
图11B为图4B的一种可替换的结构图；
图11C为图11A中第二像素开口的立体图；
图11D为具有切角部分的像素开口的结构图；
图12A为图5的一种可替换的结构图；
图12B为图12A的一种可替换的结构图；
图13A为图12B中具有切角部分的像素开口的结构图；
图13B为图12B中H处的放大图；
图14为图12A的又一种可替换的结构图；
图15为图12A的又一种可替换的结构图；
图16为图12A的又一种可替换的结构图；
图17为图12A的又一种可替换的结构图；
图18为图12A的又一种可替换的结构图；
图19为图12A的又一种可替换的结构图；
图20为图12A的又一种可替换的结构图；
图21为图12A的又一种可替换的结构图；
图22为第一隔垫物在像素界定层上的正投影可能的形状结构图；
图23为图12A的又一种可替换的结构图；
图24为图12A的又一种可替换的结构图；
图25为图12A的又一种可替换的结构图；
图26为图25的又一种可替换的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
图1为根据一些实施例提供的显示装置的正视图。参见图1，本发明的实施例提供了一种显示装置。
在一些可能的实施方式中，显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。显示装置例如(但不限于)可以是显示器、电视机、移动电话(例如手机)、无线装置、个人数据助理(Personal Digital Assistant，简称PDA)、计算机(例如手持式或便携式计算机)、全球定位系统(Global Positioning System，简称GPS)接收器/导航器、相机、动态图像专家组(Moving Picture Experts Group 4，简称MP4)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、监视器、车载显示器(例如，里程表显示器、座舱控制器、座舱显示器或车辆中后视相机的显示器等)、导航仪、电子相框、电子广告牌、电子指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等中的任一种。
在一些可能的实施方式中，参见图1，上述显示装置包括显示面板DP。示例性地，上述显示装置还可以包括框架、显示驱动芯片(Display Driver Integrated Circuit，简称DDIC)和电路板等中的至少一者。其中，电路板可以是柔性线路板(Flexible Printed Circuit，FPC)或PCB(Printed Circuit Board，印刷线路板)。
其中，电路板可以与DDIC耦接，被配置为向DDIC传输电信号。DDIC被配置为向显示面板DP提供数据信号；例如，被配置为基于接收到的电信号，生成数据信号；并将数据信号发送至显示面板DP。此外，显示面板DP、DDIC和电路板均可以安装到框架所围成的空间中。
显示面板DP为具有显示功能的屏幕，可以与上文中的DDIC耦接，被配置为接收DDIC发送的数据信号，并显示相应的图像。例如，显示面板DP可以是OLED显示面板，QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板，微LED(包括：miniLED或microLED)显示面板等。
继续参见图1，显示面板DP具有显示区AA和非显示区SA，其中显示区AA为显示面板DP上用于显示画面的区域，非显示区SA为显示面板DP上除了显示区AA之外的区域。非显示区SA可以位于显示区AA的至少一侧(例如一侧，又如多侧)。例如，非显示区SA可以围绕显示区AA一周设置。
示例性地，显示区AA可以是矩形，也可以是圆角矩形等与矩形类似的形状。基于此，显示区AA具有延伸方向相互交叉(例如相互垂直)的两条边。为了方便描述，将这两条边的延伸方向分别作为X轴和Y轴而建立直角坐标系。其中，X轴和Y轴可以互换。
图2为根据一些实施例提供的显示面板的结构图。参见图2，显示面板DP在显示区AA内设置有多个像素600。多个像素600排列成M行N列，行包括沿第一方向X排列的N个像素600。列包括沿第二方向Y排列的M个像素600。并且M≥2，N≥2。并且M和N均为整数。第一方向X和第二方向Y交叉，例如相互垂直。例如，第一方向X为X轴所指示的方向，故使用X轴的附图标记。第二方向Y为Y轴所指示的方向，故使用Y轴的附图标记。示例性地，在显示面板DP显示一帧图像的过程中，同一行的像素(包括同一行的像素中的所有子像素)可以被同时驱动(例如点亮)，不同行的像素被分时驱动。例如，M行像素可被逐行驱动，例如，在第1行像素被驱动完成后，再驱动第2行像素，依次类推，直至第M行像素驱动完成。
一(例如每个)像素600包括多个子像素。子像素是显示面板DP进行画面显示的最小单元，每个子像素可显示一种单一的颜色，例如红色(R)、绿色(G)或蓝色(B)。每个像素600中不同颜色的子像素的亮度(灰阶)可被调节，通过颜色组合和叠加可以实现多种颜色的显示，从而实现显示面板的全彩化显示。示例性地，该像素600可以包括第一子像素610、第二子像素620和第三子像素630。其中，第一子像素610、第二子像素620和第三子像素630发光颜色不同且沿第三方向E依次排列。例如，第三子像素630可以为蓝色子像素；第一子像素610和第二子像素620中的一者为红色子像素，另一者为绿色子像素。在一种示例中，第一子像素610为红色子像素，第二子像素620为绿色子像素。当然，第一子像素610和第二子像素620的发光颜色可以互换。
示例性地，一(例如每个)子像素可以包括发光器件。例如，发光器件可以为有机发光二极管、微型有机发光二极管(Micro Organic Light-Emitting Diode，Micro OLED)、量子点有机发光二级管(Quantum Dot Light Emitting Diodes，QLED)、迷你型发光二极管(Mini Light-Emitting Diode，Mini LED)或微型发光二极管(Micro Light-Emitting Diode，Micro LED)等。例如，红色子像素可以包括用于发红光的发光器件，绿色子像素可以包括用于发绿光的发光器件，蓝色子像素可以包括用于发蓝光的发光器件。
一(例如每个)像素600中的第一子像素610、第二子像素620和第三子像素630沿第三方向E依次排列。例如，从图2的左上到右下，该像素600的第一子像素610、第二子像素620和第三子像素630依次排列。又如，从图2的左上到右下，该像素600的第三子像素630、第二子像素620和第一子像素610依次排列。第三方向E与第一方向X和第二方向Y均交叉。例如，第 三方向E与第二方向Y的夹角为40°～50°。例如，40°、42°、45°、48°和50°等中的一者。
显示面板DP还可以包括位于显示区AA中的多个像素驱动电路R。每个像素驱动电路R可以与一子像素(例如发光器件)耦接，被配置为驱动该子像素发光。
多个像素驱动电路R可以呈阵列分布，例如排列成M行C列，其中，C＝W*N。其中，W为一像素中包含的子像素个数；例如，图2中，一像素包含三个子像素，则W为3。像素驱动电路R的行数和像素的行数可以相同，均为M。像素驱动电路R的列数是像素的列数的W倍。每行(即每个像素驱动电路R行)包括沿第一方向X排列的C个像素驱动电路R，这C个像素驱动电路R分别与位于同一行的N个像素包含的子像素耦接。其中，位于同一行的像素驱动电路R可以被同时写入数据信号，从而驱动位于同一行的像素发光。
像素驱动电路R可以包括多个晶体管和电容器等电子元件。例如，像素驱动电路R均可以包括三个晶体管和一个电容器，构成3T1C(即一个驱动晶体管、两个开关晶体管和一个电容器)。还可以包括三个以上的晶体管和至少一个电容器，如4T1C(即一个驱动晶体管、三个开关晶体管和一个电容器)、5T1C(即一个驱动晶体管、四个开关晶体管和一个电容器)或7T1C(即一个驱动晶体管、六个开关晶体管和一个电容器)等。其中，晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(metal oxide semiconductor，简称MOS)或其他特性相同的开关器件。
在本发明的一些实施例中，晶体管可以包括控制极、第一极和第二极。其中，控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，于是晶体管的源极被称为第一极，也可以被称为第二极。
在一些实施例中，如图2所示，显示面板DP还可以包括多条信号线。这些信号线可以与上文中的多个像素驱动电路R耦接，被配置为向各个像素驱动电路R传输相应的电信号。多条信号线包括多条扫描信号线GL、多条数据线DL、多条复位信号线Rst、多条使能信号线(还可称为发光控制信号线)EM、多条初始化信号线Vinit和多条电源电压信号线VDD中的一种或多种的组合。示例性地，多条扫描信号线GL、多条使能信号线EM和多条初始化信号线Vinit可以沿第一方向X布置，多条数据线DL和多条电源电压信号线 VDD可以沿第二方向Y布置。其中，每个像素驱动电路R可以与扫描信号线GL、数据线DL、复位信号线Rst、使能信号线EM、初始化信号线Vinit和电源电压信号线VDD电均连接。
图3A为图2示出的显示面板包含的多个层的叠置关系图。为了实现图2中示出的结构(包括上述像素、像素驱动电路R和信号线)，示例性地，参见图3A，显示面板DP包括：依次层叠设置的衬底基板100、像素驱动电路层200和发光器件层300。其中，像素驱动电路层200包括上文中的多个像素驱动电路R。发光器件层300包括多个发光器件320，用于构成多个像素600。
上述衬底基板100的结构可以根据实际需要选择设置。多个像素600设置在衬底基板100(在图3A中示出)上。
例如，衬底基板100可以为刚性衬底。该刚性衬底例如可以包括玻璃衬底衬PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)。在此情况下，上述显示面板DP可以为刚性显示面板。
又如，衬底基板100可以为柔性衬底。该柔性衬底例如可以包括PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底。在此情况下，上述显示面板DP可以为柔性显示面板。
其中，衬底基板100可以为一层结构，还可以为多层结构。例如，衬底可以包括至少一个柔性衬底和至少一个缓冲层，柔性衬底和缓冲层交替层叠设置。
示例性地，继续参见图3A所示，像素驱动电路层200可以包括：依次层叠设置的有源图案层210、第一导电图案层220、第二导电图案层230。像素驱动电路层200还可以包括将这些图案层间隔开的绝缘层240。这些层可以形成多个像素驱动电路R。
在本公开的实施例中，“图案层”可以是采用同一成膜工艺形成至少一个膜层，然后利用对这至少一个膜层执行构图工艺形成的包含特定图案的层结构。根据特定图案的不同，该构图工艺可能包括多次涂胶、曝光、显影或刻蚀工艺，而形成的层结构中的特定图案可以是连续的也可以是不连续的，这些特定图案还可能处于不同的高度(或者厚度)。“导电图案层”是具有导电性能的图案层，其通过导电材料制作。示例性地，“导电图案层”通过透明导电材料制成。例如可以选自氧化铟锡(ITO)、铝掺杂氧化锌(AZO)等中的至少一者，其既能导电又在可见光范围内具有较高的光透过率。“导电图案层”还可以采用 金属材料制成，例如，可以是铝(Al)、银(Ag)、铜(Cu)、铬(Cr)等中的至少一者。
图3B为图3A中有源图案层的结构图。参见图3B，有源图案层210可以采用多晶硅(P-Si)，有源图案层210包括像素驱动电路R的各晶体管的有源图案(还可以称为沟道区)。例如：第一有源图案AL1、第二有源图案AL2、第三有源图案AL3、第四有源图案AL4、第五有源图案AL5、第六有源图案AL6和第七有源图案AL7。
第一导电图案层220包括多个栅极图案Cp。第二导电图案层230包括多个源极和多个漏极。其中，相对应的一个有源图案、一个栅极图案Cp、一个源极和一个漏极例如可以构成一个晶体管，多个晶体管可以构成一个像素驱动电路R。
此外，像素驱动电路层还可以包括位于第一导电图案层220和第二导电图案层230之间的第三导电图案层250。例如，第一导电图案层220还包括第一电容极板Cst1，第三导电图案层250还包括第二电容极板Cst2；第一电容极板Cst1和第二电容极板Cst2相对设置，而形成像素驱动电路R中的电容器Cst。在另一些示例中，第二电容极板Cst2也可以包含在第二导电图案层230中。
图3C为图3A中的第一导电图案层的结构图。图3D为图3A中的有源图案层和第一导电图案层的结构图。参见图3C和图3D，示例性地，第一导电图案层220和第三导电图案层250包括多条信号线。其中，第一导电图案层220包括多条信号线和电容器的第一极板Cst1。多条信号线例如可以为扫描信号线GL、复位信号线Rst和使能信号线EM。位于第一导电图案层220的多条信号线经过各晶体管的有源图案，位于第一导电图案层220的多条信号线与各晶体管的有源图案交叠位置为各晶体管的栅极图案Cp。
示例性地，参见图3B～图3D，第一复位信号线Rst1经过第一有源图案AL1，第一复位信号线Rst1与第一有源图案AL1交叠部分为第一栅极图案Cp1。
扫描信号线GL经过第二有源图案AL2和第四有源图案AL4，扫描信号线GL与第二有源图案AL2交叠部分为第二栅极图案Cp2。扫描信号线GL与第四有源图案AL4交叠部分为第四栅极图案Cp4。
第一极板Cst1经过第三有源图案AL3，第一极板Cst1与第三有源图案AL3交叠部分为第三栅极图案Cp3。
使能信号线EM经过第五有源图案AL5和第六有源图案AL6，使能信号 线EM与第五有源图案AL5的交叠部分为第五栅极图案Cp5，使能信号线EM与第六有源图案AL6的交叠部分为第六栅极图案Cp6。
第二复位信号线Rst2经过第七有源图案AL7，第二复位信号线Rst2与第七有源图案AL7的交叠部分为第七栅极图案Cp7。
图3E为图3A中的第三导电图案层的结构图。参见图3E，在一些实施例中，第三导电图案层250包括多条信号线和电容器的第二极板Cst2。其中，多条信号线包括初始化信号线Vinit。初始化信号线Vinit包括第一初始化信号线Vinit1和第二初始化信号线Vinit2。
需要说明的是，本发明中的“经过”是指前者在衬底上的正投影与后者在衬底上的正投影有重叠。例如第一导电图案层220的各信号线经过对应晶体管的有源图案，是指第一导电图案层220的各信号线，例如可以为扫描信号线GL(图中未示出)在衬底上正投影与第二有源图案AL2(图中未示出)在衬底上正投影有重叠。
以下以7T1C模式的像素驱动电路R为例做介绍。
图3F为图3A中的有源图案层、第一导电图案层和第三导电图案层的结构图。图3G为根据实施例提供的一种像素驱动电路R的等效电路图。参见图3F和图3G，示例性地，7T1C模式的像素驱动电路R包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一使能晶体管T5、第二使能晶体管T6、第二复位晶体管T7和电容器Cst。
其中，第一复位晶体管T1的控制极与第一复位信号线Rst1电连接。第一复位晶体管T1的第一极与第一初始化信号线Vinit1电连接。第一复位晶体管T1的第二极与第一节点N1电连接。
补偿晶体管T2的控制极与扫描信号线GL电连接。补偿晶体管T2的第一极与第三节点N3电连接。补偿晶体管T2的第二极与第一节点N1电连接。
驱动晶体管T3的控制极和第一节点N1电连接，驱动晶体管T3的第一极和第二节点N2电连接。驱动晶体管T3的第二极和第三节点N3电连接。
电容器Cst的第一极板Cst1与第一节点N1电连接。电容器Cst的第二极板Cst2与第一电压信号端VDD电连接。第一电压信号端VDD与电源电压信号线VDD电连接。
写入晶体管T4的控制极与扫描信号线GL电连接。写入晶体管T4的第一极与数据线DL电连接。写入晶体管T4的第二极与第二节点N2电连接。
第一使能晶体管T5的控制极与使能信号走线EM电连接。第一使能晶体管T5的第一极与电源电压信号线VDD电连接。第一使能晶体管T5的第二极 与第二节点N2电连接。
第二使能晶体管T6的控制极与使能信号走线EM电连接。第二使能晶体管T6的第一极与第三节点N3电连接。第二使能晶体管T6的第二极与发光器件320的阳极电连接。
第二复位晶体管T7的控制极与第二复位信号线Rst2电连接。第二复位晶体管T7的第一极与第二初始化信号线Vinit2电连接。第二复位晶体管T7的第二极与第二使能晶体管T6的第二极与发光器件320阳极的连接点N4处电连接。发光器件320的阴极与第二电压信号线VSS电连接。其中，第二电压信号线VSS传输低电平信号，例如低电平信号的电压可以为零。
以上各晶体管的具体工作过程为：在数据写入阶段，补偿晶体管T2和写入晶体管T4在扫描信号线GL处接收的扫描信号控制下导通，将在数据信号端v处接收的数据信号写入第一节点N1，对驱动晶体管T3形成阈值电压补偿。截止时，第一节点N1的电压为数据信号和驱动晶体管T3的阈值电压之和，第一节点N1的电压能够控制通过驱动晶体管T3的驱动电流的大小。
在发光阶段，补偿晶体管T2和写入晶体管T4在第一扫描信号的控制下截止，第一使能晶体管T5和第二使能晶体管T6在使能信号走线EM处接收的使能信号的控制下导通，驱动晶体管T3导通并产生驱动电流，将驱动电流传输至发光器件320，发光器件320在驱动电流控制下发光，驱动电流的大小影响发光的亮度，也就是说，第一节点N1的电压可以控制发光器件320的亮度，即可以控制子像素的灰阶，进而影响整个显示画面的质量。
需要说明的是，本发明实施例的第一节点N1、第二节点N2和第三节点N3并非表示实际存在的部件，而是表示像素驱动电路R的版图中相关线路连接的汇合点，也就是说，第一节点N1、第二节点N2和第三节点N3是由电路图中相关线路电连接的汇合点等效而成的节点。
继续参见图3A，发光器件层300可以包括像素界定层310和多个发光器件320。像素界定层310具有多个像素开口K，一像素开口K限定一个发光器件320的位置。
示例性地，发光器件320包括依次层叠设置的第一电极(例如阳极)321、发光层322以及第二电极(例如阴极)323。
例如，第一电极321的结构可以为由透明导电氧化物薄膜/金属薄膜/透明导电氧化物薄膜依次层叠构成的复合结构。其中，上述透明导电氧化物薄膜的材料例如为ITO(Indium tin oxide氧化铟锡)和IZO(Indium zinc oxide氧化铟锌)中的任意一种，上述金属薄膜的材料例如为金(Au)、银(Ag)、镍(Ni)和铂(Pt) 中的任意一种。
又如，第一电极321的结构也可以为单层结构，单层结构的材料可以为ITO、IZO、Au、Ag、Ni、Pt中的任意一种。
继续参见图3A，示例性地，上述像素界定层310的多个像素开口K中，一个像素开口K暴露一个第一电极321的一部分。一个发光层322的至少一部分位于一个像素开口K内，与相应的第一电极321形成电连接。也即，每个发光层322通过其位于相应像素开口K内的一部分或者整体与相应的第一电极321形成电连接。
此处，发光层322的设置方式与发光层322的制备工艺相关。例如，在采用蒸镀工艺形成发光层322的情况下，发光层322的一部分可以位于相应的像素开口K内，另一部分搭接在像素开口K周围的像素界定层310上。当然，发光层322的全部也可以位于相应的像素开口K内。在采用喷墨打印技术形成发光层322的情况下，发光层322全部可以位于相应的像素开口K内。
继续参见图3A，示例性地，第二电极323位于像素界定层310远离衬底基板100的一侧。各发光器件的第二电极323可以相互电连接，呈一体结构。
例如，第二电极323的材料可以为铝(Al)、银(Ag)和镁(Mg)中的任意一种，或者镁银合金和铝锂合金中的任意一种。
当然，发光器件层300还可以包括设置在第一电极321和发光层322之间的空穴注入层、空穴传输层、电子阻挡层中的至少一者，设置在第二电极323和发光层322之间的电子注入层、电子传输层、空穴阻挡层中的至少一者。
继续参见图3A，在一些可能的实施方式中，显示面板DP还可以包括：位于发光器件层300与像素驱动电路层200之间的第一平坦层PLN1，第一平坦层PLN1与发光器件层300直接接触。
继续参见图3A，在显示面板DP还包括第一平坦层PLN1的情况下，发光器件320的第一电极321设置在第一平坦层PLN1远离衬底基板100的一侧表面上。一个发光器件层300的第一电极321可以穿过第一平坦层PLN1与一个像素驱动电路R电连接。
继续参见图3A，在一些可能的实施方式中，显示面板DP还可以包括：位于第一平坦层PLN1与像素驱动电路层200之间的第四导电图案层260。该第四导电图案层260可以包括多个连接部261。
在像素驱动电路层200还包括第四导电图案层260的情况下，一个发光器件320的第一电极321可以通过一个连接部261与一个像素驱动电路R电连接。
继续参见图3A，在一些可能的实施方式中，显示面板DP还可以包括：位于像素驱动电路层200远离衬底基板100的一侧的第二平坦层PLN2和钝化层PVX。第二平坦层PLN2可以是有机绝缘材料制成。钝化层PVX可以是无机绝缘材料制成。
继续参见图3A，在一些可能的实施方式中，显示面板DP还包括：设置在发光器件层300远离衬底基板100一侧的封装层400。
继续参见图3A，示例性地，封装层400包括依次层叠设置的第一无机绝缘层410、有机绝缘层420和第二无机绝缘层430。
示例性地，第一无机绝缘层410和第二无机绝缘层430，可采用氮化物、氧化物、氮氧化物、硝酸盐、碳化物或其任何组合的无机材料制作而成。有机绝缘层420可采用腈纶、六甲基二硅氧皖、聚丙烯酸酯类、聚碳酸脂类、聚苯乙烯等材料制作而成。
继续参见图3A，在一些可能的实施方式中，该显示面板DP还包括设置在像素界定层310离衬底基板100一侧的遮光层700和滤光图案层800。遮光层700上开设有多个滤光开口L。滤光图案层800包括多个滤光图案810。一滤光开口L对应一滤光图案810，也就是说滤光开口L与滤光图案810在显示面板DP的厚度方向具有重叠的部分。滤光开口L用以限定滤光图案810位置。
继续参见图3A，在一些可能的实施方式中，显示面板DP还包括触控层TL。这样显示面板DP为触控显示面板，具有触控功能和图像显示功能的产品。继续参见图3A，触控层TL被配置为提供触摸信号，触摸信号可以反映出用户在显示面板DP上的触摸位置。触控层TL可以与触控芯片耦接，以将触控信号提供给触控芯片。
在一些可能的实现方式中，触控层TL可以位于在显示面板DP的显示侧。触控层TL可以是独立于显示面板DP的一个部件；示例性地，显示面板DP与触控层TL二者均单独形成，之后二者通过诸如光学胶之类的粘合剂粘合在一起。例如，上文中的封装层400可以作为显示面板DP的显示面。触控层TL可以通过光刻等工艺形成在封装层400上。又示例性地，触控层TL也可以是集成在显示面板DP上的结构。示例性地，以显示面板DP作为衬底，在显示面板DP的显示面上形成触控层TL，此时触控层TL与显示面板DP的显示面直接接触，也可以与显示面板DP的显示面之间设置有其他功能层。
在另一些可能的实现方式中，触控层TL也可以位于显示面板的内部。示例性地，显示面板包括相对设置的第一基板和第二基板，触控层TL可以位于 第一基板和第二基板之间。
继续参见图3A，在一些可能的实施方式中，显示面板DP还包括缓冲层500。缓冲层500设置在遮光层700远离衬底基板100的一侧。触控层TL设置在缓冲层500上，可以与缓冲层500接触。缓冲层500可以由有机绝缘材料或无机绝缘材料制成。
下文将对图3A中的发光器件层进行详细描述。
图4A为图3A示出的像素界定层中多个像素开口的排布图；且图4A示出了每个像素开口K的下端口。图4B为图3A示出的发光器件层中多个像素的排布图；且图4B示出了像素中每个子像素的发光区。图5为图3A示出的发光器件层中一像素的结构图。
参见图4A～图5，上文介绍的显示面板DP中，像素界定层310上的多个像素开口K包括多个第一像素开口K1、多个第二像素开口K2和多个第三像素开口K3。基于一像素开口K与一子像素的位置对应，本文中将与一个像素600位置对应的一组像素开口称为一开口单元O。像素600包括发光颜色不同的多个子像素，多个子像素包括：位于第一像素开口K1处的第一子像素610、位于第二像素开口K2处的第二子像素620和位于第三像素开口K3处的第三子像素630。第一子像素610、第二子像素620和第三子像素630沿第三方向E依次排列。相应地，该开口单元O包括沿第三方向E依次排列的第一像素开口K1、多个第二像素开口K2和多个第三像素开口K3。
在第三方向E上，发光颜色相同且位置相邻的两个子像素由其他发光颜色的至少两个子像素间隔开，该至少两个子像素的发光颜色各不相同。例如，在第三方向E上，相邻两第一子像素610由一第二子像素620和一第三子像素630间隔开。又如，在第三方向E上，相邻两第二子像素620由一第三子像素630和一第一子像素610间隔开。相邻两第三子像素630由一第一子像素610和一第二子像素620间隔开。这样，每个像素600中包括了一第一子像素610、一第二子像素620和一第三子像素630。
继续参见图4A，多个像素开口K可分成多个开口组KI，每个开口组KI中的所有像素开口K沿第三方向E排列。示例性地，每个开口组KI由整数个(即至少一个，例如一个，又如多个)开口单元O组成。在一开口组KI包括多个开口单元O的情况下，这些开口单元O沿第三方向E排成一排。
示例性地，位于同一行的开口单元O(对应于同一行像素的所有开口单元)中，同一类型的像素开口K也位于同一行；例如，各第一像素开口K1沿第一方向X排列，同样地，各第二像素开口K2也沿第一方向X排列，同 样地，各第三像素开口K3也沿第一方向X排列。又示例性地，位于同一列的开口单元中O中，同一类型的像素开口K也位于同一列；例如，各第一像素开口K1沿第二方向Y排列，同样地，各第二像素开口K2也沿第二方向Y排列，同样地，各第三像素开口K3也沿第二方向Y排列。
参见图4A，本发明的实施例提供了一种显示面板DP。该显示面板DP的第一像素开口K1的面积小于第二像素开口K2的面积。意指，第一像素开口K1在衬底基板100上的正投影的面积小于第二像素开口K2在衬底基板100上的正投影的面积。此外，第二像素开口K2的面积小于第三像素开口K3的面积。意指，第二像素开口K2在衬底基板100的上正投影的面积小于第三像素开口K3在衬底基板100上的正投影的面积。相应地，第一子像素610的开口区的面积小于第二子像素620的开口区的面积。第二子像素620的开口区的面积小于第三子像素630的开口区的面积。
继续参见图4B，多个子像素可分成多个子像素组S，每个子像素组S中的所有子像素沿第三方向E排列。示例性地，每个子像素组S由整数个(即至少一个，例如一个，又如多个)像素600组成。在一子像素组S包括多个像素600的情况下，这些像素600沿第三方向E排成一排。
图6为对比实施例的发光器件层的多个像素的排布图。参见图6，在一种对比实施例中，显示面板DP(图中未示出)的多个像素600′沿第一方向X和第二方向Y排列形成M行N列，每一列包括多个沿第二方向Y排布的像素600′，一(例如，每个)像素600′包括红色子像素610′、绿色子像素620′和蓝色子像素630′。红色子像素610′和绿色子像素620′沿第二方向Y依次排布，蓝色子像素630′排布在红色子像素610′和绿色子像素620′的一侧(例如，第一方向X所指的一侧)。其中，子像素组S′的延伸方向与第二方向Y一致。在一像素600′中蓝色子像素630′的面积一定的前提下，若将蓝色子像素630′做的细长(例如，蓝色子像素630′沿第二方向Y的尺寸为长度，沿第一方向X的尺寸为宽度。当蓝色子像素630′做的细长时，其长度与宽度的比值较大)，则影响显示效果。因此，蓝色子像素630′的长度和宽度的比值需要做小一些。但是，这样一来，沿第二方向Y，蓝色子像素630′之间的间距就变大，导致该间距的空间无法被利用，进而导致像素密度单位(Pixels Per Inch，PPI)降低。
参见图4A～图4B，而本实施例中，一像素600的第一子像素610、第二子像素620和第三子像素630沿第三方向E依次排列。沿第三方向E排列的多个像素为子像素组S。这样，一子像素组S中相邻两子像素之间的间距可以根据需要配置。例如，第一子像素610与第二子像素620，第二子像素620与 第三子像素630的间距大致相等。相邻两子像素之间的间距可以大致相等。当然也可以不相等。由此可见，本实施例不会出现相邻两子像素之间的间距过大的问题，从而可以充分利用空间进行子像素的布设，进而提高PPI。
图7A为对比实施例的显示面板DP显示横线形态的示意图。参见图7A，上述对比实施例中，当显示面板DP需显示一横线时，该横线对应的至少一行(一行或连续的多行)像素被该行像素驱动电路R点亮。由于这些行的多个像素600中，靠近显示的横线的上边缘的有第一子像素610(例如，红色子像素)和第三子像素630(例如，蓝色子像素)，但是，人眼对蓝色(第三子像素630)的识别不敏感，并且第三子像素630相比第一子像素610距离下边缘的距离较远。所以显示的横线的上边缘会泛红。而靠近显示的横线的下边缘的有第二色像素620(例如，绿色子像素)和第三子像素630(例如，蓝色子像素)。但是，人眼对蓝色(第三子像素630)的识别不敏感，并且第三子像素630相比绿色子像素620′距离下边缘的距离较远，所以显示的横线的下边缘会泛绿。
图7B为对比实施例的显示面板DP显示竖线形态的示意图。参见图7A～图7B，上述对比实施例中，由于人眼对蓝色(例如蓝色子像素630′的发光颜色)识别能力差，所以人眼可以看到红色(例如红色子像素610′的发光颜色)和绿色(例如绿色子像素620′的发光颜色)。这样，当显示横线和竖线形态时，显示的竖线较细而显示的横线较粗。
图8A为对比实施例的显示面板DP显示斜线形态的示意图。图8B为对比实施例的显示面板DP显示另一种斜线形态的示意图。参见图8A～图8B，另外，上述对比实施例中，当显示面板DP显示斜线形态时，由于显示的斜线是由点构成，而每个点是由像素进行显示发光的，本对比实施例中的像素的排布使得相邻两像素存在台阶，所以本对比实施例在显示的斜线状态时会出现台阶感。
图9A为根据一些实施例的显示面板DP显示横线形态的示意图。参见图9A，在本实施例中，当显示面板DP显示横线形态时，由于一行多个像素600中，处于显示横线的上边缘的除了第一子像素610(例如，红色子像素)外，还有较第一子像素610离上边缘稍远一点的第二子像素620(例如，绿色子像素)。并且，人眼对红色和绿色比较敏感。所以，在显示横线形态时，在显示的横线的上边缘，既能看到第一子像素610，又能看到第二子像素620。从而，不会在显示的横线的上边缘出现泛红或泛绿的色偏。另外，一行多个像素600中，处于显示横线的下边缘的除了第三子像素630(例如，蓝色子像素) 外，还有较第三子像素630离下边缘稍远一点的第二子像素620(例如，绿色子像素)。并且，人眼对蓝色不敏感，并且，第二子像素620距离下边缘稍远。所以，在显示横线形态时，在显示的横线的上边缘，既能看到第三子像素630，又能看到第二子像素620。从而，不会在显示的横线的上边缘出现泛红或泛绿的色偏。
图9B为根据一些实施例的显示面板DP显示竖线形态的示意图。参见图9A～图9B，在本实施例中，当显示面板DP显示竖线形态时，由于人眼对蓝色不敏感，所以可以看到红色和绿色，则在本显示的横线和显示的竖线形态时，两者的宽度一致。
图10A为根据一些实施例的显示面板DP显示斜线形态的示意图。图10B为根据一些实施例的显示面板DP显示另一种斜线形态的示意图。参见图10A～图10B，在本实施例中，当显示面板DP显示斜线形态时，由于一子像素组S中，多个像素600的第一子像素610、第二子像素620和第三子像素630均沿斜线的显示方向排布。并且，第一子像素610、第二子像素620和第三子像素630，三者沿斜线的显示方向没有交叉重叠部分。所以当显示面板DP显示斜线形态时，像素600是连续的，从而显示的斜线不会出现台阶感。
由此可见，本实施例的像素600的排布方式，能够使得第三子像素630的面积增大，最终达到提高第三子像素630的开口率的效果。另外，当显示面板DP显示横线形态时，在显示的横线的边缘不会出现泛红或者泛绿的色偏。其次，当显示面板DP显示斜线形态时，像素600是连续的，从而显示的斜线不会出现台阶感。
图10C为子像素与像素驱动电路的连接结构图。图10D为图10C的一种可替换的结构图。参见图2、图3A以及图10C～图10D，在一些可能的实施方式中，子像素均具有与像素驱动电路R耦接的耦接点D。子像素包括相对设置的第一电极(例如阳极)321和第二电极(例如阴极)323，第一电极321位于子像素中靠近衬底基板100的一侧。子像素的第一电极321和与其对应的像素驱动电路R具有重叠的部分，并且在两者重叠的部分开设有过孔GK(将第一子像素610的过孔记为GK1，第二子像素620的过孔记为GK2，第三子像素630的过孔记为GK3)。子像素的第一电极321和像素驱动电路R在过孔GK位置处电连接。耦接点D指的是过孔GK所在的位置处。
在第二方向Y上，至少两个发光颜色不同的子像素各自的耦接点D的几何中心(也可以称为几何重心)与各自对应的像素开口K之间的距离不同。 耦接点D距像素开口K的距离指的是，沿第二方向Y，耦接点D的几何中心到像素开口K上距耦接点D最近的点的距离。为了便于下文描述，将第一子像素610的耦接点记为D1、第二子像素620的耦接点记为D2，第三子像素630的耦接点记为D3。将沿第二方向Y，耦接点D1距第一像素开口K1的距离记为CM1，耦接点D2距第二像素开口K2的距离记为CM2，耦接点D3距第三像素开口K3的距离分别记为CM3。D1、D2和D3，三者中的至少两者到各自对应的像素开口(例如，第一像素开口K1，第二像素开口K2，第三像素开口K3。)的距离不同。例如，D1、D2和D3，三者距各自对应的像素开口K的距离各不同。又如，如图10C所示，CM1大于CM2和CM3，CM2和CM3大致相等。又如，如图10D所示，CM3大于CM1和CM2，CM1和CM2大致相等。
参见图2、图3A以及图10C～图10D，在一些可能的实施方式中，第一电极321包括连接为一体的连接部TA和主体部TB。像素开口K露出主体部TB的至少一部分，例如，主体部TB的一部分与像素开口K在衬底基板100上的正投影重叠，另一部分不交叠。又如，主体部TB在衬底基板上的正投影位于像素开口K在衬底基板100上的正投影之内。子像素的耦接点D位于连接部TA所在的区域中。主体部TB和与其所对应的像素开口K的形状一致，并且主体部TB的轮廓线LK为与该主体部TB对应的像素开口K向外扩大一圈。连接部TA与主体部TB以主体部TB的轮廓线LK为分界线。
与至少两个发光颜色不同的子像素(例如，发光颜色不同的第一子像素610、第二子像素620和第三子像素630中的两者或三者)对应的两个连接部TA，在第二方向Y上的最大尺寸不同。为了便于下文描述，将第一子像素610对应的连接部记为第一连接部TA1、将第二子像素620对应的连接部记为第二连接部TA2、将第三子像素630对应的连接部记为第三连接部TA3、将第一连接部TA1在第二方向Y上的最大尺寸记为第一最大尺寸ZC1、将第二连接部TA2在第二方向Y上的最大尺寸记为第二最大尺寸ZC2以及将第三连接部TA3在第二方向Y上的最大尺寸记为第三最大尺寸ZC3。例如，如图10C所示，第一最大尺寸ZC1大于第二最大尺寸ZC2和第三最大尺寸ZC3。第二最大尺寸ZC2和第三最大尺寸ZC3大致相等。又如，如图10D所示，第三最大尺寸ZC3大于第二最大尺寸ZC2和第一最大尺寸ZC1。第二最大尺寸ZC2和第一最大尺寸ZC1大致相等。
图11A为图4A的一种可替换的结构图。图11B为图4B的一种可替换的 结构图。参见图11A～图11B，本发明的实施例提供了一种显示面板DP。该显示面板DP上，一开口单元O包含的第一像素开口K1、第二像素开口K2和第三像素开口K3中的至少一者为具有切角部分的像素开口。为了便于下文描述，将具有切角部分的像素开口称为切角开口QK。例如，一开口单元O包含第一像素开口K1、第二像素开口K2和第三像素开口K3，三者中任意一者或任意两者为切角开口QK，而其余的像素开口不是切角开口QK；或者，三者均为切角开口QK。
例如，图11C为图11A中第二像素开口的立体图。参见图11C，切角开口QK具有切角部分QK1。例如，切角开口QK的下端口XD基本上为多边形，该切角开口QK的切角部分QK1使得该多边形的至少一个(例如一个，又如多个)角部位置处凹进。例如，切角开口QK的下端口基本上是矩形，并在两个角部位置处凹进。其中，切角开口QK的下端口XD指的是像素开口K(例如，第一像素开口K1。又如，第二像素开口K2。又如，第三像素开口K3。)下表面所暴露出的第一电极321的端口。切角开口QK的上端口SD指的是像素开口K(例如，第一像素开口K1。又如，第二像素开口K2。又如，第三像素开口K3。)上表面所对应的端口。相应地，切角开口QK的上端口SD与下端口XD的形状大致相同，该切角开口QK的切角部分QK1也同样使得上端口SD的至少一个(例如一个，又如多个)角部位置处凹进。
示例性地，切角开口QK的上端口SD在衬底基板上的正投影覆盖切角开口QK的下端口XD在衬底基板上的正投影，即切角开口QK的上端口SD的尺寸大于切角开口QK的下端口XD的尺寸。基于此，该切角开口QK的切角部分QK1斜向布置。
在一些示例中，切角部分QK1为连续的多个，多个切角部分QK1收尾相连形成弧形的边缘。当显示面板DP的第一像素开口K1、第二像素开口K2和第三像素开口K3的边缘为圆弧形过渡，具有较少的尖锐的顶角，这样能够降低第一子像素610、第二子像素620和第三子像素630的锯齿感的视觉效果。
继续参见图11A～图11B，在一些可能的实施方式中，在一开口单元O中，第一像素开口K1和第二像素开口K2均为具有切角部分的像素开口(切角开口QK)。第一像素开口K1的切角部分QK1和第二像素开口K2的切角部分QK1分别位于第一像素开口K1和第二像素开口K2背离彼此的一侧。为了便于下文描述，将第一像素开口K1的两个切角部分分别称为第一切角部分QK(a)和第二切角部分QK(b)。将第二像素开口K2的两个切角部分分别称为第三切角部分QK(c)和第四切角部分QK(d)。第一像素开口K1可以具有第一切角部 分QK(a)和第二切角部分QK(b)中的一个，第二像素开口K2可以具有第三切角部分QK(c)和第四切角部分QK(d)。例如，第一像素开口K1具有第一切角部分QK(a)，第二像素开口K2具有第三切角部分QK(c)。又如，第一像素开口K1具有第一切角部分QK(a)，第二像素开口K2具有第四切角部分QK(d)。由于一个像素600中各个子像素的发光区与一开口单元O中相应的像素开口K的形状大致相同，因此这样一来，就减少了该像素600的轮廓中的尖锐顶角，从而降低显示面板呈现的画面存在锯齿的视觉效果。
基于此，第一子像素610和第二子像素620中的一者为红色子像素，另一者为绿色子像素。例如，第一子像素610为红色子像素，第二子像素620为绿色子像素。又如，第一子像素610为绿色子像素，第二子像素620为红色子像素。由于相对于蓝色，人眼对红色和绿色比较敏感。因此，若红色子像素和绿色子像素对应的像素开口K，二者均具有切角部分QK1；进一步地，二者的切角部分QK1可以分别位于背离彼此的一侧。这样能够进一步降低显示面板呈现的画面存在锯齿的视觉效果。
图11D为具有切角部分的像素开口的结构图。参见图11D，在一些可能的实施方式中具有切角部分的像素开口(切角开口QK)为轴对称结构。具有切角部分的像素开口(切角开口QK)的对称轴ZL平行于第三方向E。相应地，具有切角部分的像素开口(切角开口QK)对应的子像素的发光区也可以为轴对称结构。
继续参见图11D，在一些可能的实施方式中，具有切角部分的像素开口(切角开口QK)还具有与切角部分QK1相邻的第三侧壁QK4和第四侧壁QK5。切角部分QK1与第三侧壁QK4和第四侧壁QK5分别形成第三顶角α3和第四顶角α4。第三顶角α3为第四顶角α4的0.9倍～1.1倍。具有切角部分的像素开口(切角开口QK)在衬底基板100上的正投影的形状为轴对称图形，这样与其对应的子像素在衬底基板100上的正投影也为轴对称图形，从而使得显示面板的显示效果更美观。
图12A为图5的一种可替换的结构图。图12B为图12A的一种可替换的结构图。参见图3A以及图12A～图12B，在一些可能的实施方式中，多个隔垫物900位于像素界定层310远离衬底基板100的一侧。并且，多个隔垫物900位于像素界定层310中除多个像素开口K(例如，第一像素开口K1、第二像素开口K2和第三像素开口K3)以外的部分所在的区域。例如，隔垫物900的底面与像素界定层310的顶面接触。示例性地，先形成像素界定层310，然后在像素界定层310上形成隔垫物900；进而再形成发光层322。
例如，隔垫物900在像素界定层310上的正投影被轮廓线P以及彼此相邻的第二像素开口K2和第三像素开口K3包围。
又如，隔垫物900在像素界定层310上的正投影被轮廓线P和彼此相邻的两个第三像素开口K3以及一个第二像素开口K2包围。
又如，隔垫物900在像素界定层310上的正投影被彼此相邻的第一像素开口K1、第二像素开口K2和第三像素开口K3包围。
又如，隔垫物900在像素界定层310上的正投影被轮廓线P和彼此相邻的两个第一像素开口K1以及一个第二像素开口K2包围。
又如，隔垫物900在像素界定层310上的正投影被彼此相邻第一像素开口K1、第二像素开口K2和两个第三像素开口K3包围。
其中，本文中“A在B上的正投影”，是指沿垂直于B所在平面的方向上，A在B所在平面上的投影。例如，隔垫物900在像素界定层310上的正投影，是指沿像素界定层310的厚度方向，隔垫物900在像素界定层310上的投影。
本实施例的隔垫物900用于在蒸镀发光材料时支撑高精度金属掩膜板(Fine Metal Mask，FMM)，并且本实施例的隔垫物900与子像素的排布相适应。另外，本实施例在轮廓线P与靠近轮廓线P的子像素之间设有隔垫物900，这样在充分利用空间的情况下增加隔垫物900的布设数量，从而提高对FMM支撑的稳定性。
继续参见图12A～图12B，本发明的实施例提供了一种显示面板DP。该显示面板DP的多个隔垫物900包括多个第一隔垫物910。第一隔垫物910位于沿第一方向X排列且彼此相邻的两个第三像素开口K3之间。并且第一隔垫物910位于沿第二方向Y排列且彼此相邻的第一像素开口K1和第二像素开口K2之间。为了方便下文描述，将第一隔垫物910所在的位置称为第一位置W1。也就是说第一位置W1为：沿第一方向X排列且彼此相邻的两个第三像素开口K3与沿第二方向Y排列且彼此相邻的第一像素开口K1和第二像素开口K2交叉的位置处。这样，第一隔垫物910在第一位置处W1，被该两个第三像素开口K3、该第一像素开口K1和该第二像素开口K2包围。示例性地，每一处的第一位置W1处均设有一第一隔垫物910。另外，这些第一隔垫物910呈阵列排布。这样，第一隔垫物910排布的更均匀，有利于提高对FMM支撑稳定性。
继续参见图12A～图12B，在一些可能的实施方式中，在第一位置W1处，与第一隔垫物910相邻的第一像素开口K1、第二像素开口K2 和第三像素开口K3中的至少一者为具有切角部分的像素开口(切角开口QK)。切角部分位于像素开口靠近第一隔垫物910的位置处(即第一位置W1处)具有切角部分QK1。例如，靠近第一位置W1处第一像素开口K1、第二像素开口K2以及两个第三像素开口K3，四者均可以为具有切角部分的所述像素开口QK、均具有切角部分QK1。又如，靠近第一位置W1处的第一像素开口K1和第二像素开口K2均可以为具有切角部分的像素开口(切角开口QK)，且均具有切角部分QK1；第三像素开口K3不是切角开口QK。又如，靠近第一位置W1处的第一像素开口K1为切角开口QK，且具有切角部分QK1；第二像素开口K2和第三像素开口K3不是切角开口QK。又如，靠近第一位置W1处的第二像素开口K2为切角开口QK，且具有切角部分QK1；第一像素开口K1和第三像素开口K3不是切角开口QK。又如，靠近第一位置W1处的两个第三像素开口K3为切角开口QK，且均具有切角部分QK1；第一像素开口K1和第二像素开口K2不是切角开口QK。
另外，沿切角部分QK1在衬底基板100上的正投影与第一隔垫物910在衬底基板100上的正投影不交叠。例如，在靠近第一位置W1处的第一像素开口K1的切角部分和第二像素开口K2的切角部分均与第一隔垫物910在衬底基板上的正投影不交叠。在靠近第一位置W1处的两个第三像素开口K3的切角部分与第一隔垫物910在衬底基板上的正投影不交叠。又如，在靠近第一位置W1处的第一像素开口K1的切角部分和第二像素开口K2的切角部分均与第一隔垫物910在衬底基板上的正投影不交叠。
本实施例中，与第一隔垫物910相邻的第一像素开口K1、第二像素开口K2和第三像素开口K3中的至少一者为具有切角部分的像素开口(切角开口QK)，这样使得第一像素开口K1、第二像素开口K2和第三像素开口K3与第一隔垫物910做相应的适应性调整，从而使得第一隔垫物910的面积增大，从而提高对FMM支撑的稳定性。
图13A为图12B中具有切角部分的像素开口的结构图。参见图12A～图13A，在一些可能的实施方式中，具有切角部分的像素开口(切角开口QK)(例如，第一像素开口K1为切角开口QK。又如，第二像素开口K2为切角开口QK。又如，第三像素开口K3为切角开口QK。)具有与切角部分QK1相邻的第一侧壁QK2和第二侧壁QK3。切角部分与第一侧壁QK2和第二侧壁QK3分别形成第一顶角α1和第二顶角α2，第一顶角α1为第二顶角α2的0.9倍～1.1倍。
参见图13A，在一些可能的实施方式中，具有切角部分QK1的像素开口K(切角开口QK)还包括与沿第三方向E与第二侧壁QK3相对的第五侧壁QK6，以及，沿第四方向F与第一侧壁QK2相对的第六侧壁QK7，第四方向F与第三方向E交叉。例如，相互垂直。第五侧壁QK6沿第四方向F的尺寸(标记为第三尺寸U3)与第二侧壁QK3沿第四方向F的尺寸(标记为第二尺寸U2)的差值为第一差值，第六侧壁QK7沿第三方向E的尺寸(标记为第四尺寸U4)与第一侧壁QK2沿第三方向E的尺寸(标记为第一尺寸U1)的差值为第二差值，第一差值等于第二差值。即U3-U2＝U4-U1。其中，第一尺寸U1、第二尺寸U2、第三尺寸U3和第四尺寸U4均指像素开口K的下端口的尺寸。
参见图12B，在第一方向X上，具有切角部分QK1且对应于发光颜色相同的子像素的相邻两个(例如每相邻两个，又如部分相邻两个)像素开口，各自的几何中心的连线平行于第一方向X。例如，在第一方向X上相邻两第一像素开口K1的几何中心的连线平行于第一方向X。又如，在第一方向X上相邻两第二像素开口K2的几何中心的连线平行于第一方向X。又如，在第一方向X上相邻两第三像素开口K3的几何中心的连线平行于第一方向X。
示例性地，在第二方向Y上，具有切角部分QK1且对应于发光颜色相同的子像素的相邻两个(例如每相邻两个，又如部分相邻两个)像素开口(例如，相邻两第一像素开口K1。又如，相邻两第二像素开口K2。又如，相邻两第三像素开口K3)，各自的几何中心的连线平行于第二方向Y。
示例性地，在第一方向X，具有切角部分QK1且对应于发光颜色相同的子像素的相邻两个(例如每相邻两个，又如部分相邻两个)像素开口(例如，相邻两第一像素开口K1。又如，相邻两第二像素开口K2。又如，相邻两第三像素开口K3)，各自的几何中心的连线平行于第一方向X。以及，在第二方向Y上，具有切角部分QK1且对应于发光颜色相同的子像素的相邻两个(例如每相邻两个，又如部分相邻两个)像素开口(例如，相邻两第一像素开口K1。又如，相邻两第二像素开口K2。又如，相邻两第三像素开口K3)，各自的几何中心的连线平行于第二方向Y。
参见图12B以及图13A，在一些可能的实施方式中，在第一方向X或第二方向Y上，具有切角部分QK1且对应于发光颜色相同的子像素的相邻两个(例如每相邻两个，又如部分相邻两个)像素开口，该像素开口各自包含的切角部分QK1位于各自相同的角部位置处。像素开口K具有第一角部J1、第 二角部J2、第三角部J3和第四角部J4。例如，在第一方向X或者第二方向X上，每相邻两第一像素开口K1的切角部分QK1均位于第一像素开口K1的第二角部J2位置处。又如，在第一方向X上，每相邻两第三像素开口K3的切角部分QK1均位于第三像素开口K3的第一角部J1和第四角部J4位置处。又如，在第二方向Y上，一部分的相邻两第三像素开口K3的切角部分QK1均位于第三像素开口K3的第一角部J1和第四角部J4位置处。
参见图12B，示例性地，在上述相邻两个像素开口各自包含的切角部分QK1位于各自相同的角部位置处的情况下，相邻两个像素开口(例如，相邻两第一像素开口K1。又如，相邻两第二像素开口K2。又如，相邻两第三像素开口K3)的形状和大小均一致。参见图12B，在一些可能的实施方式中，像素600中的所述第一子像素610、所述第二子像素620和所述第三子像素630均沿第四方向F延伸，第四方向F与第三方向E呈80°～100°的夹角。
图13B为图12B中H处的放大图。图14为图12A的又一种可替换的结构图。图15为图12A的又一种可替换的结构图。图16为图12A的又一种可替换的结构图。图17为图12A的又一种可替换的结构图。图18为图12A的又一种可替换的结构图。图19为图12A的又一种可替换的结构图。图20为图12A的又一种可替换的结构图。图21为图12A的又一种可替换的结构图。
参见图12A～图21，在一些可能的实施方式中，与第一隔垫物910相邻的第一像素开口K1为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第一像素开口K1的切角开口QK在像素界定层310(图中未示出)上的正投影，两者具有彼此靠近且大致平行的边。也就是说，第一像素开口K1的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第一边B1。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第二边B2。第一边B1和第二边B2大致平行。
示例性地，与第一隔垫物910相邻的第一像素开口K1为具有切角部分的像素开口(切角开口QK)。第一像素开口K1的切角部分大致平行于第一方向X。也就是说，在靠近第一位置W1处的第一像素开口K1的切角开口QK大致平行于第一方向X。
又示例性地，与第一隔垫物910相邻的第一像素开口K1为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第一像素开口 K1的切角开口QK在像素界定层310上的正投影，两者具有彼此靠近且大致平行的边。也就是说，第一像素开口K1的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第一边B1。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第二边B2。第一边B1和第二边B2大致平行。
以及，与第一隔垫物910相邻的第一像素开口K1为具有切角部分的像素开口(切角开口QK)。第一像素开口K1的切角部分大致平行于第一方向X。也就是说，在靠近第一位置W1处的第一像素开口K1的切角开口QK大致平行于第一方向X。
本实施例，能够提高对FMM支撑的稳定性，原因参照前述实施例，在此不再赘述。
继续参见图12A～图21，在一些可能的实施方式中，与第一隔垫物910相邻的第二像素开口K2为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第二像素开口K2的切角开口QK在像素界定层上310的正投影，两者具有彼此靠近且大致平行的边。也就是说，第二像素开口K2的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第三边B3。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第四边B4。第三边B3和第四边B4大致平行。
示例性地，与第一隔垫物910相邻的第二像素开口K2为具有切角部分的像素开口(切角开口QK)，第二像素开口K2的切角部分大致平行于第一方向。也就是说，在靠近第一位置W1处的第二像素开口K2的切角开口QK大致平行于第一方向X。
又示例性地，与第一隔垫物910相邻的第二像素开口K2为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第二像素开口K2的切角开口QK在像素界定层上310的正投影，两者具有彼此靠近且大致平行的边。也就是说，第二像素开口K2的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第三边B3。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第四边B4。第三边B3和第四边B4大致平行。
以及，与第一隔垫物910相邻的第二像素开口K2为具有切角部分的像素开口(切角开口QK)，第二像素开口K2的切角部分大致平行于第一方向。也就是说，在靠近第一位置W1处的第二像素开口K2的切角开口QK大致平行于第一方向X。本实施例的有益效果参照前述实施例， 在此不再赘述。
继续参见图12A～图21，在一些可能的实施方式中，与第一隔垫物910相邻的第三像素开口K3为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第三像素开口K3的切角开口QK在像素界定层310上的正投影，两者具有彼此靠近且大致平行的边。也就是说，第三像素开口K3的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第五边B5。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第六边B6。第五边B5和第六边B6大致平行。
示例性地，与第一隔垫物910相邻的第三像素开口K3为具有切角部分的像素开口(切角开口QK)，第三像素开口K3的切角部分大致平行于第二方向Y。也就是说，在靠近第一位置W1处的第三像素开口K3的切角开口QK大致平行于第二方向Y。
又示例性地，与第一隔垫物910相邻的第三像素开口K3为具有切角部分的像素开口(切角开口QK)。第一隔垫物910与第三像素开口K3的切角开口QK在像素界定层310上的正投影，两者具有彼此靠近且大致平行的边。也就是说，第三像素开口K3的切角开口QK在像素界定层310上的正投影具有靠近第一位置W1处的第五边B5。第一隔垫物910在像素界定层310上的正投影具有靠近第一位置W1处的第六边B6。第五边B5和第六边B6大致平行。
以及，与第一隔垫物910相邻的第三像素开口K3为具有切角部分的像素开口(切角开口QK)，第三像素开口K3的切角部分大致平行于第二方向Y。也就是说，在靠近第一位置W1处的第三像素开口K3的切角开口QK大致平行于第二方向Y。本实施例的有益效果参照前述实施例，在此不再赘述。
图22为第一隔垫物在像素界定层上的正投影可能的形状结构图。参见图12A～图12B以及图14～图22，在一些可能的实施方式中，第一隔垫物910在像素界定层310上的正投影的形状包括为长方形(如图22中的A1～A5)、正方形(如图22中的A6～A7)、平行四边形(如图22中的A8～A9)、菱形(如图22中的A9)、梯形(如图22中的A10～A11)、五边形、六边形(如图22中的A12～A13)、椭圆形(如图22中的A14)和圆形(如图22中的A15)中的一种或多种图案类型。例如，若一第一隔垫物910在像素界定层310上的正投影属于长方形这种图案类型，则表示该第一隔垫物910在像素界定层310上的正投影的形状大致为长方形，例如，可以 是标准的长方形(如图22中的A1)，也可以是带有倒角或圆角的类长方形(如图22中的A2～A5)。又如，若一第一隔垫物910在像素界定层310上的正投影属于正方形这种图案类型，则表示该第一隔垫物910在像素界定层310上的正投影的形状大致为正方形，例如，可以是标准的正方形(如图22中的A6)，也可以是带有倒角或圆角的类正方形(如图22中的A7)。
图12B中给出了一些第一隔垫物910在像素界定层310上的正投影的可能的形状，但本实施例保护的像素开口K的形状不限于此。
图23为图12A的又一种可替换的结构图。图24为图12A的又一种可替换的结构图。参见图23～图24，本发明的实施例提供了一种显示面板DP。该显示面板DP的显示区AA具有轮廓线P，多个隔垫物900位于显示区AA中。多个隔垫物900包括多个第三隔垫物930，第三隔垫930位于靠近轮廓线P的相邻两像素开口K(例如，相邻两第三像素开口K3。又如，相邻的一第二像素开口K2和一第一像素开口K1。又如，相邻两第一像素开口K1)之间。
需要说明的是，显示区AA具有沿第一方向X延伸的第一轮廓线P1和沿第二方向Y延伸的第二轮廓线P2。第三隔垫物930分成沿第一方向X延伸的第一隔垫物组Z1和沿第二方向Y延伸的第二隔垫物组Z2。第一隔垫物组Z1和第二隔垫物组Z2均包括至少一个第三隔垫物930。例如，第一隔垫物组Z1中的第三隔垫物930位于靠近第一轮廓线P1的相邻两像素开口K之间。又如，第二隔垫物组Z2中的第三隔垫物930位于靠近第二轮廓线P2的相邻两像素开口K之间。
本实施例，在允许的情况下，能够尽可能大的利用空间对第三隔垫物930进行排布，在显示区AA的内部和边缘均可以排布隔垫物900，这样提高了隔垫物900的布设密度，从而提高对FMM支撑的稳定性。
继续参见图23～图24，在一些可能的实施方式中，第三隔垫物930在像素界定层310上的正投影具有靠近且大致平行于轮廓线P的边。例如，第一隔垫物组Z1中的第三隔垫物930在像素界定层310上的正投影具有第七边B7，第七边B7大致平行于第一轮廓线P1。又如，第二隔垫物组Z2中的第三隔垫物930在像素界定层310上的正投影具有第八边B8，第八边B8大致平行于第二轮廓线P2的。
本实施例，在相同的排布空间内，尽可能的增加第三隔垫物930的面积，从而第三隔垫物930对FMM支撑的稳定性。
继续参见图23～图24，在一些可能的实施方式中，靠近轮廓线P的 相邻两像素开口K中的一像素开口K与第三隔垫物930在像素界定层310上的正投影，二者具有彼此靠近且相互平行的边。为了便于下文描述，将第三隔垫物930设置的位置称第二位置W2。第二位置W2位于该相邻两像素开口K和轮廓线P之间。也就是说，在靠近第二位置W2处，相邻两像素开口K中的一个或者两个与第三隔垫物930在像素界定层310上的正投影具有彼此靠近且相互平行的边。例如，在靠近第二位置W2处第三隔垫物930在像素界定层310上的正投影具有第九边B9和第十边B10。第九边B9和第十边B10分别与靠近第二位置W2处的相邻两像素开口K在像素界定层310上的正投影的一个边平行。本实施例所取得的效果可以参照实施例，在此不再赘述。
继续参见图12A～图12B、图14～图21以及图23～图24，在一些可能的实施方式中，第三隔垫物930在像素界定层310上的正投影的形状包括三角形、长方形、正方形、平行四边形、梯形和椭圆形中的一种或多种图案类型。在相同空间内，尽可能的利用空间对第三隔垫物930进行排布。
参见图12A～图12B、图14～图21以及图23～图24，本发明的实施例提供了一种显示面板DP。在该显示面板DP包括第一隔垫物910和第三隔垫物930的情况下：第一隔垫物910和第三隔垫物930在像素界定层310上的正投影的形状不同。例如，第一隔垫物910在像素界定层310上的正投影的形状为矩形。第三隔垫物930在像素界定层310上的正投影的形状为三角形。又如，第一隔垫物910在像素界定层310上的正投影的形状为梯形。第三隔垫物930在像素界定层310上的正投影的形状为矩形。
示例性地，在该显示面板DP包括第一隔垫物910和第四隔垫物940的情况下：第一隔垫物910和第四隔垫物940在像素界定层310上的正投影的形状不同。例如，第一隔垫物910在像素界定层310上的正投影的形状为矩形。第四隔垫物940在像素界定层310上的正投影的形状为三角形。又如，第一隔垫物910在像素界定层310上的正投影的形状为梯形。第四隔垫物940在像素界定层310上的正投影的形状为三角形。
示例性地，在该显示面板DP包括第一隔垫物910、第三隔垫物930和第四隔垫物940的情况下：第一隔垫物910和第三隔垫物930在像素界定层310上的正投影的形状不同。以及，第一隔垫物910和第四隔垫物940在像素界定层310上的正投影的形状不同。例如，第一隔垫物910 在像素界定层310上的正投影的形状为矩形。第三隔垫物930和第四隔垫物940在像素界定层310上的正投影的形状为三角形。又如，第一隔垫物910在像素界定层310上的正投影的形状为梯形。第三隔垫物930和第四隔垫物940在像素界定层310上的正投影的形状为矩形。
参见图12A～图12B、图14～图21以及图23～图24，本发明的实施例提供了一种显示面板DP。在该显示面板DP包括第一隔垫物910和第三隔垫物930的情况下：第一隔垫物910和第三隔垫物930在像素界定层310上的正投影的形状和大小均一致。例如，第一隔垫物910和第三隔垫物930在像素界定层310上的正投影为大小一致的矩形。
继续参见图23～图24，本发明的实施例提供了一种显示面板DP。该显示面板DP的多个像素开口K分成沿第四方向F排布的多个开口组KI。例如，第四方向F与第三方向E垂直。
多个隔垫物900还包括至少一个第四隔垫物940。第四隔垫物940位于多个开口组KI中位于显示面板DP最边缘的一开口组与轮廓线P之间。为了便于下文描述，将位于显示面板DP最边缘的开口组KI称为第三开口组KI3。第四隔垫物940位于第三开口组KI3与轮廓线P之间。这样，第四隔垫物940被第三开口组KI3和轮廓线P包围。本实施例在第三开口组KI3与轮廓线P之间设有第四隔垫物940，从而利用该区域的空间，提高隔垫物900的密度，提高对FMM支撑的稳定性。
继续参见图23～图24，在一些可能的实施方式中，第四隔垫物940与位于显示面板最边缘的一开口组KI在像素界定层310上的正投影，两者具有彼此靠近且大致平行的边。也就是说，第四隔垫物940与第三开口组KI3在像素界定层310上的正投影均具有彼此靠近且大致平行的边。例如，第四隔垫物940在像素界定层310上的正投影具有第十一边B11。第三开口组KI3在像素界定层310上的正投影具有第十二边B12。第十一边B11和第十二边B12彼此靠近且大致平行。
继续参见图23～图24，在一些可能的实施方式中，第四隔垫物940在像素界定层310上的正投影与轮廓线P具有彼此靠近且大致平行的边。例如，第四隔垫物940在像素界定层310上的正投影具有第十三边B13。第第十三边B13与轮廓线P彼此靠近且大致平行。
图25为图12A的又一种可替换的结构图。参见图25，在一些可能的实施方式中，多个像素开口K分成沿第四方向F排布的多个开口组KI。一(例如，每一)开口组KI包括至少一个(例如，一个。又如，多 个)像素开口K。多个隔垫物900包括至少一个(例如，一个。又如，多个)第二隔垫物920。第二隔垫物920为长条状，且在相邻两开口组KI之间沿第三方向E延伸。
本实施例的，长条状的第二隔垫物920使得第二隔垫物920的排布更均匀，进一步的提高对FMM支撑的稳定性。
继续参见图25，在一些可能的实施方式中，相邻两开口组KI包括第一开口组KI1和第二开口组KI2。第一开口组KI1沿第三方向E的长度L1大于第二开口组KI2沿第三方向E的长度L2。第二隔垫物920沿第三方向E的长度L3小于等于第一开口组KI1沿第三方向E的长度L1，且大于等于第二开口组KI2沿第三方向E的长度L2。
继续参见图25，在一些可能的实施方式中，第二隔垫物920和第一开口组KI1在像素界定层310上的正投影，两者的两端齐平。也就是说，第二隔垫物920的两端和第一开口组KI1的两端在像素界定层310上的正投影平齐。这样，第二隔垫物920可以在第一开口组KI1整个长度区域对FMM进行支撑，从而的提高对FMM支撑的稳定性。并且使得第二隔垫物920的排布更均匀，进一步的提高对FMM支撑的稳定性。
图26为图25的又一种可替换的结构图。参见图26，在一些可能的实施方式中，多个隔垫物900包括第二隔垫物920、第三隔垫物930和第四隔垫物940。关于、第三隔垫物930和第四隔垫物940的相关描述可以参考前述实施例，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示面板，包括：
    衬底基板；设置在所述衬底基板上的像素界定层，所述像素界定层上包括多个像素开口，多个像素开口包括第一像素开口、第二像素开口和第三像素开口；
    设置在所述衬底基板上的多个像素，所述多个像素排列成M行N列，所述行包括沿第一方向排列的N个像素，所述列包括沿第二方向排列的M个像素，所述M≥2，所述N≥2，所述第一方向和所述第二方向交叉；其中，所述像素包括发光颜色不同的多个子像素，所述多个子像素包括：位于所述第一像素开口处的第一子像素、位于所述第二像素开口处的第二子像素和位于所述第三像素开口处的第三子像素；所述第一子像素、第二子像素和第三子像沿第三方向依次排列，所述第三方向与所述第一方向和所述第二方向均交叉；在所述第三方向上，发光颜色相同且位置相邻的两个子像素由其他发光颜色的至少两个子像素间隔开，所述至少两个子像素的发光颜色各不相同。
  2. 根据权利要求1所述的显示面板，还包括：
    多个隔垫物，位于所述像素界定层远离所述衬底基板的一侧，且位于所述像素界定层中除所述多个像素开口以外的部分所在的区域。
  3. 根据权利要求2所述的显示面板，其中，
    所述多个隔垫物包括多个第一隔垫物；
    所述第一隔垫物位于沿所述第一方向排列且彼此相邻的两个第三像素开口之间，且位于沿所述第二方向排列且彼此相邻的所述第一像素开口和所述第二像素开口之间。
  4. 根据权利要求3所述的显示面板，其中，
    与所述第一隔垫物相邻的所述第一像素开口、所述第二像素开口和所述第三像素开口中的至少一者为具有切角部分的像素开口；
    所述切角部分位于所述像素开口靠近所述第一隔垫物的位置处；所述切角部分在所述衬底基板上的正投影与所述第一隔垫物在所述衬底基板上的正投影不交叠。
  5. 根据权利要求4所述的显示面板，其中，
    具有切角部分的所述像素开口还包括与所述切角部分相邻的第一侧壁和 第二侧壁；所述切角部分与所述第一侧壁和第二侧壁分别形成第一顶角和第二顶角，所述第一顶角为所述第二顶角的0.9倍～1.1倍。
  6. 根据权利要求4～5中任一项所述的显示面板，其中，
    具有切角部分的所述像素开口还包括与沿所述第三方向与所述第二侧壁相对的第五侧壁，以及，沿第四方向与所述第一侧壁相对的第六侧壁，所述第四方向与所述第三方向交叉；
    所述第五侧壁沿所述第四方向的尺寸与所述第二侧壁沿所述第四方向的尺寸的差值为第一差值，所述第六侧壁沿所述第三方向的尺寸与所述第一侧壁沿所述第三方向的尺寸的差值为第二差值，所述第一差值等于所述第二差值。
  7. 根据权利要求4～6中任一项所述的显示面板，其中，
    在所述第一方向上，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于所述第一方向；
    和/或，
    在所述第二方向上，具有切角且对应于发光颜色相同的子像素的相邻两个像素开口，各自的几何中心的连线平行于所述第二方向。
  8. 根据权利要求4～7中任一项所述的显示面板，其中，
    在所述第一方向或所述第二方向上，具有切角部分且对应于发光颜色相同的子像素的相邻两个像素开口，各自包含的切角部分位于各自相同的角部位置处。
  9. 根据权利要求8所述的显示面板，其中，
    所述相邻两个像素开口的形状和大小均一致。
  10. 根据权利要求1～9中任一项所述的显示面板，其中，
    所述像素中的第一子像素、第二子像素和第三子像素均沿第四方向延伸，所述第四方向与所述第三方向呈80°～100°的夹角。
  11. 根据权利要求4～10中任一项所述的显示面板，其中，
    与所述第一隔垫物相邻的所述第一像素开口为具有所述切角部分的像素开口；所述第一隔垫物与具有所述切角部分的所述第一像素开口在所述像素界定层上的正投影，两者具有彼此靠近且大致平行的边；
    和/或，
    与所述第一隔垫物相邻的所述第一像素开口为具有所述切角部分的像素开口，所述第一像素开口的切角部分大致平行于所述第一方向。
  12. 根据权利要求3～11中任一项所述的显示面板，其中，
    与所述第一隔垫物相邻的所述第二像素开口为具有所述切角部分的像素开口；所述第一隔垫物与具有所述切角部分的所述第二像素开口在所述像素界定层上的正投影，两者具有彼此靠近且大致平行的边；和/或，
    与所述第一隔垫物相邻的所述第二像素开口为具有所述切角部分的像素开口，所述第二像素开口的切角部分大致平行于所述第一方向。
  13. 根据权利要求3～12中任一项所述的显示面板，其中，
    与所述第一隔垫物相邻的所述第三像素开口为具有所述切角部分的像素开口；所述第一隔垫物与具有所述切角部分的所述第三像素开口在所述像素界定层上的正投影，两者具有彼此靠近且大致平行的边；和/或，
    与所述第一隔垫物相邻的所述第三像素开口为具有切角部分的所述像素开口，所述第三像素开口的切角部分大致平行于所述第二方向。
  14. 根据权利要求3～13中任一项所述的显示面板，其中，
    所述第一隔垫物在所述像素界定层上的正投影的形状包括三角形、长方形、正方形、平行四边形、梯形、六边形、椭圆形和圆形中的一种或多种图案类型。
  15. 根据权利要求1～14中任一项所述的显示面板，其中，
    所述多个像素开口分成沿第四方向排布的多个开口组；所述第四方向与所述第三方向交叉；
    所述多个隔垫物包括至少一个第二隔垫物；所述第二隔垫物为长条状，且在相邻两开口组之间沿所述第三方向延伸。
  16. 根据权利要求15所述的显示面板，其中，
    所述相邻两开口组包括第一开口组和第二开口组，所述第一开口组沿第三方向的长度大于所述第二开口组沿第三方向的长度；
    所述第二隔垫物沿第三方向的长度小于等于第一开口组沿第三方向的长度，且大于等于所述第二开口组沿第三方向的长度。
  17. 根据权利要求16所述的显示面板，其中，
    所述第二隔垫物和所述第一开口组在所述像素界定层上的正投影，两者的两端齐平。
  18. 根据权利要求1～17中任一项所述的显示面板，其中，
    所述显示面板包括具有轮廓线的显示区，所述多个隔垫物位于所述显示区中；
    所述多个隔垫物包括多个第三隔垫物；所述第三隔垫物位于靠近所述轮廓线的相邻两像素开口之间。
  19. 根据权利要求18所述的显示面板，其中，
    所述第三隔垫物在所述像素界定层上的正投影具有靠近且大致平行于所述轮廓线的边。
  20. 根据权利要求18～19中任一项所述的显示面板，其中，
    所述靠近所述轮廓线的相邻两像素开口中的一像素开口与所述第三隔垫物在所述像素界定层上的正投影，二者具有彼此靠近且相互平行的边。
  21. 根据权利要求18～20中任一项所述的显示面板，其中，
    所述第三隔垫物在所述像素界定层上的正投影的形状包括三角形、长方形、正方形、平行四边形、梯形和椭圆形中的一种或多种图案类型。
  22. 根据权利要求18～21中任一项所述的显示面板，其中，
    所述多个像素开口分成沿第四方向排布的多个开口组；所述第四方向与所述第三方向交叉；
    所述多个隔垫物还包括至少一个第四隔垫物，所述第四隔垫物位于所述多个开口组中位于所述显示面板最边缘的一开口组与所述轮廓线之间。
  23. 根据权利要求22所述的显示面板，其中，
    所述第四隔垫物与位于所述显示面板最边缘的一开口组在所述像素界定层上的正投影，两者具有彼此靠近且大致平行的边。
  24. 根据权利要求22～23中任一项所述的显示面板，其中，
    所述第四隔垫物在所述像素界定层上的正投影与所述轮廓线具有彼此靠近且大致平行的边。
  25. 根据权利要求3～24中任一项所述的显示面板，其中，
    在所述显示面板包括所述第一隔垫物和所述第三隔垫物的情况下：
    所述第一隔垫物和所述第三隔垫物在所述像素界定层上的正投影的形状不同；和/或，
    在所述显示面板包括所述第一隔垫物和所述第四隔垫物的情况下：
    所述第一隔垫物和所述第四隔垫物在所述像素界定层上的正投影的形状不同。
  26. 根据权利要求3～25中任一项所述的显示面板，其中，
    在所述显示面板包括所述第一隔垫物和所述第三隔垫物的情况下：
    所述第一隔垫物和所述第三隔垫物在所述像素界定层上的正投影的形状和大小均一致。
  27. 一种显示装置，包括：
    权利要求1～26中任一项所述的显示面板。
PCT/CN2022/109192 2022-07-29 2022-07-29 显示面板及显示装置 WO2024021099A1 (zh)

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CN108181765A (zh) * 2018-01-30 2018-06-19 厦门天马微电子有限公司 一种显示面板和显示装置
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CN112002238A (zh) * 2020-09-07 2020-11-27 武汉天马微电子有限公司 显示面板及显示装置
CN113078191A (zh) * 2021-03-23 2021-07-06 武汉天马微电子有限公司 一种显示面板及显示装置
CN113421910A (zh) * 2021-06-25 2021-09-21 京东方科技集团股份有限公司 显示基板以及显示装置

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CN108181765A (zh) * 2018-01-30 2018-06-19 厦门天马微电子有限公司 一种显示面板和显示装置
US20200013353A1 (en) * 2018-07-05 2020-01-09 Japan Display Inc. Display device
CN112002238A (zh) * 2020-09-07 2020-11-27 武汉天马微电子有限公司 显示面板及显示装置
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