WO2023092355A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023092355A1
WO2023092355A1 PCT/CN2021/132915 CN2021132915W WO2023092355A1 WO 2023092355 A1 WO2023092355 A1 WO 2023092355A1 CN 2021132915 W CN2021132915 W CN 2021132915W WO 2023092355 A1 WO2023092355 A1 WO 2023092355A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
area
printed circuit
display panel
display
Prior art date
Application number
PCT/CN2021/132915
Other languages
English (en)
French (fr)
Inventor
张加勤
张昌
兰传艳
贾群
喻勇
王永乐
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003545.6A priority Critical patent/CN116490912A/zh
Priority to PCT/CN2021/132915 priority patent/WO2023092355A1/zh
Priority to GB2318610.9A priority patent/GB2622162A/en
Publication of WO2023092355A1 publication Critical patent/WO2023092355A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present disclosure relates to but not limited to the field of display technology, especially a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • an exemplary embodiment of the present disclosure provides a display panel including a display substrate, a first printed circuit board, and a second printed circuit board, the display substrate including a display area and a binding panel located on one side of the display area. area, the binding area is connected to the first printed circuit board through a first flexible circuit board, and the first printed circuit board is connected to the second printed circuit board through a second flexible circuit board; the first printed circuit board is connected to the second printed circuit board through a second flexible circuit board;
  • the printed circuit board is a wiring circuit board carrying signal connection lines
  • the second printed circuit board is a driving circuit board carrying a driving chip
  • the orthographic projection of the second printed circuit board on the display panel plane is consistent with the display substrate Orthographic projections on the plane of the display panel have no overlap.
  • a first connector is provided on the first printed circuit board, and the second flexible circuit board is connected to the first printed circuit board through the first connector.
  • a second connector is disposed on the second printed circuit board, and the second flexible circuit board is connected to the second printed circuit board through the second connector.
  • the first printed circuit board is a single-layer board or a multi-layer board, and the number of layers of the multi-layer board is less than or equal to three.
  • the first printed circuit board includes a first board body and a connection wire layer disposed on the first board body, the thickness of the first board body is 0.25 mm to 0.35 mm, so The thickness of the connecting wire layer is 0.15mm to 0.25mm.
  • the second printed circuit board is a multilayer board, and the number of layers of the multilayer board is 8-10.
  • the second printed circuit board includes a second board body and an electronic device layer disposed on the second board body, and the thickness of the second board body is 0.8 mm to 1.2 mm, so The thickness of the electronic device layer is 1.5 mm to 2.5 mm.
  • the electronic device layer includes at least a first chip area, a second chip area, and a third chip area arranged at intervals, the first chip area is configured to set a timing control chip and its peripheral circuits, The second chip area is configured to set a power management chip and its peripheral circuits, and the third chip area is configured to set a power supply management chip and its peripheral circuits.
  • the second printed circuit board further includes at least one silicone gasket attached to the surface of the timing control chip, the power management chip or the power supply management chip.
  • the second printed circuit board further includes at least one temperature sensor, the temperature sensor is disposed in the first chip area, adjacent to the timing control chip, and/or the temperature The sensor is disposed in the second chip area, adjacent to the power management chip, and/or the temperature sensor is disposed in the third chip area, adjacent to the power supply management chip.
  • the binding area includes a chip area and a pin area arranged in sequence along a direction away from the display area, the pin area includes a plurality of pins, and the first flexible circuit board It is arranged on the side of the pin area away from the display area, and is bound and connected with a plurality of pins in the pin area.
  • the first printed circuit board is arranged on a side of the first flexible circuit board away from the display area, and the orthographic projection of the first printed circuit board on the display panel plane is the same as the Orthographic projections of the display substrates on the plane of the display panel do not overlap.
  • the binding area includes a bending area, a chip area and a pin area arranged in sequence along a direction away from the display area, and the bending area is configured to bend the The chip area and the pin area are turned over to the back of the display area, the pin area includes a plurality of pins, the first flexible circuit board is arranged on a side of the pin area close to the display area, and Binding connection with multiple pins of the pin area.
  • the first printed circuit board is arranged on a side of the first flexible circuit board close to the display area, and the orthographic projection of the first printed circuit board on the display panel plane is the same as the Orthographic projections of the display areas on the plane of the display panel at least partially overlap.
  • an exemplary embodiment of the present disclosure also provides a display device, including the aforementioned display panel.
  • the display device further includes a host, the host is connected to the display panel through a rotating shaft, and the second flexible circuit board is disposed in the rotating shaft.
  • the host includes a main board, a keyboard and a battery, the second printed circuit board is fixed on the main board, or the second printed circuit board is arranged between the keyboard and the battery between.
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display panel
  • FIG. 3 is a schematic diagram of the side structure of another display panel
  • FIG. 4 is a schematic plan view of a display area in a display panel
  • FIG. 5 is a schematic cross-sectional structure diagram of a display area in a display panel
  • FIG. 6 is a schematic cross-sectional structure diagram of a display substrate in a display panel
  • FIG. 7 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 8 is a working timing diagram of a pixel driving circuit
  • FIG. 9 is a schematic diagram of a mounting structure of a printed circuit board in a display panel
  • FIG. 10 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure.
  • Fig. 11 is a side view of the display panel shown in Fig. 10;
  • FIG. 12 is a schematic structural diagram of a chip area according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of an equivalent circuit of a printed circuit board according to an exemplary embodiment of the present disclosure
  • FIG. 14 is a schematic plan view of another display panel according to an exemplary embodiment of the present disclosure.
  • Fig. 15 is a side view of the display panel shown in Fig. 14;
  • Fig. 16 is a schematic structural diagram of a second printed circuit board according to an exemplary embodiment of the present disclosure.
  • 93 temperature sensor
  • 100 display area
  • 101 base
  • 102 drive circuit layer
  • 104 encapsulation layer
  • 200 binding area
  • 201 bending area
  • 210 chip area
  • 220 pin area
  • 300 frame area
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively, and the data driver is connected to a plurality of data signal lines respectively.
  • the scanning drivers are respectively connected to a plurality of scanning signal lines (S1 to Sm)
  • the light emitting drivers are respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light emitting signal line and a pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver.
  • the driver can supply a clock signal, an emission stop signal, etc.
  • the data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light emitting driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic plan view of a display panel.
  • the display panel may include a display area 100 , a binding area 200 located on one side of the display area 100 in the first direction D1, and a frame area 300 located on the other side of the display area 100 .
  • the display area 100 may at least include a plurality of sub-pixels Pxij constituting a pixel array to display dynamic pictures or still images.
  • the bonding area 200 may at least include a plurality of signal leads, a Source Driver IC (SDIC for short) 20 and a plurality of pins, and the plurality of signal leads are configured to connect a plurality of data signal lines of the display area 100 to the source
  • the driver chip 20, the source driver chip 20 is configured to generate a driving signal for driving the display, which is provided to the sub-pixels in the display area 100 through a plurality of signal leads, and a plurality of pins are configured to bind and connect to a flexible circuit board (Flexible Printed Circuit, referred to as FPC) 30.
  • FPC Flexible Printed Circuit
  • the frame area 300 may at least include a gate driving circuit and a power line, the gate driving circuit is configured to generate a scan signal and an emission signal and provide it to the sub-pixels in the display area 100, and the power line is configured to supply the sub-pixels in the display area 100 Transmit voltage signal.
  • the binding area 200 and the frame area 300 may include an isolation dam in a ring structure, which is not limited in the present disclosure.
  • the bonding area 200 may at least include a chip area and a lead area sequentially arranged along the first direction D1 (a direction away from the display area), the chip area may at least include a plurality of pads, and the source driver chip 20 may be bonded and connected to multiple pads in the chip area, the pin area may at least include multiple pins, and the flexible circuit board 30 may be bonded and connected to multiple pins in the pin area.
  • the width of the source driver chip 20 and the flexible circuit board 30 in the second direction D2 may be smaller than the width of the bonding area 200 in the second direction D2, the second direction D2 crossing the first direction D1.
  • FIG. 3 is a schematic side view of another display panel.
  • the display panel may include a display area 100, a binding area 200 and a frame area, the structures of the display area 100 and the frame area are basically the same as those shown in Figure 2, and the binding area 200 may include
  • the bending area, the chip area and the pin area are set in sequence in the direction D1.
  • the bending area can be bent with a curvature in the third direction D3, and the surfaces of the chip area and the lead area can be reversed, that is, the upward facing surface of the chip area and the lead area can be converted to face-to-face through the bending of the bending area.
  • the third direction D3 intersects the first direction D1.
  • the chip area and the lead area may overlap the display area 100 in the third direction D3 (thickness direction).
  • the display panel may be deformable, such as rolled, bent, folded or rolled.
  • the first direction D1 may be the extending direction (column direction) of the data signal lines in the display area
  • the second direction D2 may be the extending direction (row direction) of the scanning signal lines in the display area
  • the third direction may be D3 may be a direction perpendicular to the plane of the display panel
  • the first direction D1 and the second direction D2 may be perpendicular to each other
  • the first direction D1 and the third direction D3 may be perpendicular to each other.
  • FIG. 4 is a schematic plan view of a display area in a display panel.
  • the display area may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include a first sub-pixel P1 that emits light of the first color, and a sub-pixel P1 that emits light of the second color.
  • each of the three sub-pixels may include a pixel driving circuit and a light emitting device, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, the pixel
  • the driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output a corresponding current to the light emitting device, and the light emitting device is connected to the pixel driving circuit of the sub-pixel respectively, and emits light.
  • the device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel that emits red (R) light
  • the second sub-pixel P2 may be a blue sub-pixel that emits blue (B) light
  • the third sub-pixel P3 It may be a green sub-pixel that emits green (G) light.
  • the shape of the sub-pixels in the pixel unit can be rectangular, rhombus, pentagonal, hexagonal, circular or elliptical, etc., and can be arranged horizontally, vertically or in the form of characters, etc. Arrangement, the disclosure is not limited here.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal arrangement, a vertical arrangement, a square or a diamond shape, which is not limited in the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of a display area in a display panel. As shown in FIG. 5, in a plane perpendicular to the display panel, along the direction from bottom to top, the display panel may include: a heat dissipation layer 22, a back film layer 21, a display substrate 10, a polarizing layer 11, an adhesive layer 12 and protective layer13.
  • the display substrate 10 is configured to display dynamic pictures or still images
  • the polarizing layer 11 is configured to reduce the reflection of ambient light
  • the protective layer 13 is configured to protect the display panel, and is bonded by the adhesive layer 12
  • the back film layer 21 is configured to protect the display substrate 10
  • the heat dissipation layer 22 is configured to improve the heat dissipation performance of the display substrate 10 .
  • FIG. 6 is a schematic cross-sectional structure diagram of a display substrate in a display panel, illustrating the structure of three sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101 , a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base 101 , and a light emitting structure layer 103 disposed on the light emitting layer.
  • the structural layer 103 is away from the encapsulation layer 104 on the side of the substrate 101 .
  • the display area may include other film layers, such as a touch structure layer, which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.
  • the pixel driving circuit includes only one transistor 102A and one storage capacitor 102B as an example.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the second electrode of the transistor 102A through a via hole, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 304.
  • the layers 303 are connected, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of a corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include an light-emitting layer (EML) and any one or more layers of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole Blocking Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL).
  • EML Electron Injection Layer
  • the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may be There is a small amount of overlap, or can be isolated.
  • FIG. 7 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit may be connected with 7 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power line VDD and the second power line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, and the initial signal line INIT extend in the horizontal direction
  • the second power line VSS, the first power line VDD, and the data signal line D extends in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 8 is a working timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 7 .
  • the pixel driving circuit in FIG. 7 includes seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C, All transistors are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 9 is a schematic diagram of an installation structure of a printed circuit board in a display panel.
  • the binding area of the display panel may at least include the source driver chip 20 and pins, the pins are connected to one end of the flexible circuit board 30, and the other end of the flexible circuit board 30 is bent to the back of the display panel, and
  • the printed circuit board (PCB for short) 40 is connected, and the electronic device is arranged on the printed circuit board 40, and the electronic device includes at least a timing control (T-con) chip, a power management chip (PMIC), and a power supply management chip (ELIC). ) and memory (Flash), etc.
  • T-con timing control
  • PMIC power management chip
  • ELIC power supply management chip
  • Flash Flash
  • the display panel may include a stacked heat dissipation layer 22, a back film layer 21, a display substrate 10, a polarizing layer 11, an adhesive layer 12, and a protective layer 13, and the printed circuit board 40 may be attached on the heat dissipation layer. 22 away from the side of the display substrate 10 , the electronic device may be disposed on the side of the printed circuit board 40 away from the display substrate 10 .
  • the thickness of the printed circuit board 40 may be about 1.0 mm, and the thickness of the electronic device may be about 1.5 mm to 2.5 mm. According to the structure shown in FIG. 9 , it can be seen that due to the large thickness of the printed circuit board 40 and the electronic devices, the overall thickness of the display panel is relatively large, about 3.2 mm to 4.4 mm.
  • the refresh rate (Frame Rate, FR for short) of display devices has gradually increased, from 60Hz to 90Hz, 120Hz, 144Hz, 240Hz, etc.
  • the improvement of the refresh rate has greatly increased the power consumption and heat generation of the driver chip (such as T-con, PMIC, etc.). Since the printed circuit board and electronic devices of the display panel structure shown in Figure 9 are arranged on the back of the display panel, when the display panel is working, the heat generated by the electronic devices is transferred to the display panel through the printed circuit board, causing the temperature of the corresponding position of the display panel to rapidly increase. The rise not only causes the characteristic deviation of the pixel driving circuit on the display panel, but also reduces the life of the light emitting device on the display panel.
  • the threshold voltage Vth characteristic of the transistor (TFT) in the pixel driving circuit is positively biased, resulting in an increase in the opening of the TFT channel when the driving voltage remains unchanged, and an increase in the driving current flowing through the light-emitting device, which directly causes Luminous intensity increased.
  • the Vth characteristic shift of the R sub-pixel, G sub-pixel and B sub-pixel is the same, due to the difference in aperture ratio and luminous efficiency of the R sub-pixel, G sub-pixel and B sub-pixel, the R sub-pixel, G sub-pixel and B sub-pixel.
  • the luminous intensity ratio of the pixel is unbalanced, deviating from the original brightness and color coordinates.
  • the lifetime of a light-emitting device is strongly related to the total luminous intensity and total luminous time. Due to the increase in luminous intensity due to temperature rise, the effect of increased luminous intensity is superimposed over time, resulting in accelerated aging of the light-emitting device and reduced lifetime.
  • An exemplary embodiment of the present disclosure provides a display panel including a display substrate, a first printed circuit board, and a second printed circuit board, the display substrate includes a display area and a binding area on one side of the display area, the The binding area is connected to the first printed circuit board through a first flexible circuit board, and the first printed circuit board is connected to the second printed circuit board through a second flexible circuit board; the first printed circuit board It is a wiring circuit board carrying signal connection lines, the second printed circuit board is a driving circuit board carrying a driving chip, and the orthographic projection of the second printed circuit board on the plane of the display panel is the same as that of the display substrate on the display panel. Orthographic projections on the plane have no overlap.
  • the binding area includes a chip area and a pin area arranged in sequence along a direction away from the display area, the pin area includes a plurality of pins, and the first flexible circuit board It is arranged on the side of the pin area away from the display area, and is bound and connected with a plurality of pins in the pin area.
  • the first printed circuit board is arranged on the side of the first flexible circuit board away from the display area, and the orthographic projection of the first printed circuit board on the display panel plane is the same as that of the display substrate on the display panel plane. The orthographic projections of do not overlap.
  • the binding area includes a bending area, a chip area and a pin area arranged in sequence along a direction away from the display area, and the bending area is configured to bend the The chip area and the pin area are turned over to the back of the display area, the pin area includes a plurality of pins, the first flexible circuit board is arranged on a side of the pin area close to the display area, and Binding connection with multiple pins of the pin area.
  • the first printed circuit board is arranged on the side of the first flexible circuit board close to the display area, and the orthographic projection of the first printed circuit board on the display panel plane is the same as that of the display substrate on the display panel plane.
  • the orthographic projections of are at least partially overlapping.
  • the first printed circuit board includes a first board body and a connection wire layer disposed on the first board body, the thickness of the first board body is 0.25 mm to 0.35 mm, so The thickness of the connecting wire layer is 0.15mm to 0.25mm.
  • the second printed circuit board includes a second board body and an electronic device layer disposed on the second board body, and the thickness of the second board body is 0.8 mm to 1.2 mm, so The thickness of the electronic device layer is 1.5 mm to 2.5 mm.
  • FIG. 10 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure
  • FIG. 11 is a side view of the display panel shown in FIG. 10
  • the display panel in a plane parallel to the display panel, the display panel may include a display area 100 , a binding area 200 located on one side of the first direction D1 of the display area 100 , and frames located on other sides of the display area 100 Area 300.
  • the bonding area 200 may include a chip area 210 and a pin area 220 arranged in sequence along the first direction D1, the chip area 210 may at least include a plurality of pads, and a plurality of SDIC chips 20 are respectively bonded and connected to multiple pads in the chip area 210.
  • the pin area 220 may at least include a plurality of pins, and the first ends of the plurality of first flexible circuit boards 31 are respectively bonded and connected to the plurality of pins of the pin area 220, and the plurality of first flexible circuit boards
  • the second end of the circuit board 31 is connected to the first end of the first printed circuit board 41
  • the second end of the first printed circuit board 41 is connected to the second printed circuit board 42 through the second flexible circuit board 32 .
  • the chip area 210 can be provided with 6 SDIC chips 20, and the 6 SDIC chips 20 can be arranged in sequence along the second direction D2, and the SDIC chips 20 can be packaged in a chip on panel (Chip On Panel, COP for short) manner.
  • the chip 20 is bonded to the chip area 210 .
  • the pin area 220 can be bonded and connected to six first flexible circuit boards 31, and the six first flexible circuit boards 31 can be respectively located on one side of the first direction D1 of the six SDIC chips 20, and the first flexible circuit board can be connected in a COP manner.
  • the first end of the board 31 is bonded to the pin area 220 .
  • the second end of the first flexible circuit board 31 may be connected to the first printed circuit board 41 in a COP manner.
  • the first printed circuit board 41 and the second flexible circuit board 32 may be connected in a COP manner, or may be connected in a connector manner.
  • the side of the first printed circuit board 41 away from the display area can be provided with a first connector 61, and the first end of the second flexible circuit board 32 can be directly inserted into the first connector 61, so that the first printed circuit board 41 and The connection of the second flexible circuit board 32 .
  • a connector is used to connect the first printed circuit board 41 and the second flexible circuit board 32 , which can facilitate the debugging and calibration of the display panel in the post-production and assembly process.
  • the second flexible circuit board 32 and the second printed circuit board 42 may be connected in a COP manner, or may be connected in a connector manner.
  • the side of the second printed circuit board 42 close to the display area can be provided with a second connector 62, and the second end of the second flexible circuit board 32 can be directly inserted into the second connector 62 to realize the connection between the second flexible circuit board 32 and the display area.
  • the connection of the second printed circuit board 42 .
  • a connector is used to connect the second flexible circuit board 32 and the second printed circuit board 42 , which can facilitate debugging and calibration of the display panel in the post-production and assembly process.
  • the connector method may be a zero insertion force (Zero Insertion Force, ZIF for short) connection method.
  • the second printed circuit board 42 may further include a connection interface 63 configured to be connected to the host of the display device through a cable TV cable (Cable line) or the third flexible circuit board 33 .
  • a connection interface 63 configured to be connected to the host of the display device through a cable TV cable (Cable line) or the third flexible circuit board 33 .
  • the display panel in a plane perpendicular to the display panel, may include a display substrate 10, a polarizing layer 11 disposed on the display substrate 10, and an adhesive layer disposed on the side of the polarizing layer 11 away from the display substrate 10. 12.
  • the protective layer 13 arranged on the side of the bonding layer 12 away from the display substrate 10 , the back film layer 21 arranged on the side of the display substrate 10 away from the protective layer 13 , and the heat dissipation device arranged on the side of the back film layer 21 away from the display substrate 10 Layer 22.
  • the polarizing layer 11 and the adhesive layer 12 may only be located in the display area 100, and the back film layer 21 and the heat dissipation layer 22 may be located in a part of the display area 100 and the binding area 200 close to the display area 100 to protect the
  • the layer 13 may be located throughout the display area 100 and the entire binding area 200 .
  • the display substrate 10 is configured to display dynamic pictures or still images, and may include a driving circuit layer, a light emitting structure layer, and a package layer stacked on a substrate, and the thickness of the display substrate 10 may be about 0.10 mm to About 0.14mm.
  • the thickness of the display substrate 10 may be about 0.12mm.
  • the polarizing layer 11 may serve as an anti-reflection layer configured to reduce reflection of external ambient light.
  • the polarizing layer 11 can be formed by a patterning process, or can be formed by attaching a polarizer.
  • the thickness of the polarizing layer 11 may be about 0.10 mm to about 0.20 mm.
  • the thickness of the polarizing layer 11 may be about 0.15 mm.
  • optical adhesive may be used for the adhesive layer 12 , and the thickness of the adhesive layer 12 may be about 0.15 mm to about 0.25 mm.
  • the thickness of the adhesive layer 12 may be about 0.2 mm.
  • the protective layer 13 may be a cover glass (Cover Glass, CG for short), or may be a plastic colorless polyimide (Colorless Polyimide, CPI for short).
  • the cover glass may have a thickness of about 0.55mm to 0.65mm, and the colorless polyimide may have a thickness of about 0.05mm to 0.07mm.
  • the thickness of the cover glass may be about 0.6 mm, and the thickness of the colorless polyimide may be about 0.06 mm.
  • the thickness of the back film layer (U-Film) 21 may be about 0.04 mm to about 0.06 mm.
  • the thickness of the back film layer 21 may be about 0.05 mm.
  • the heat sink layer (SCF) 22 may have a thickness of about 0.15 mm to about 0.25 mm.
  • the thickness of the heat dissipation layer 22 may be about 0.2 mm.
  • a plurality of pins and a plurality of pads of the bonding area 200 may be disposed on a surface of the bonding area 200 on one side in the third direction D3 (upper surface).
  • the SDIC chip 20 may be disposed on one side of the bonding area 200 in the third direction D3 (upper surface), and bonded to a plurality of pads.
  • the first end of the first flexible circuit board 31 can be arranged on one side of the pin area 220 in the third direction D3, and be connected to a plurality of pins by binding, and the second end of the first flexible circuit board 31 is along the first direction.
  • D1 After D1 is extended, it is connected to the first printed circuit board 41, that is, the first printed circuit board 41 is located on the side of the binding area 200 away from the display area 100, and the orthographic projection of the first printed circuit board 41 on the display panel plane is consistent with the display substrate.
  • the orthographic projection of 10 on the plane of the display panel has no overlap.
  • the second end of the first printed circuit board 41 is connected to the first end of the second flexible circuit board 32, and after the second end of the second flexible circuit board 32 extends away from the display panel, it is connected to the second end of the second flexible circuit board 32.
  • the second printed circuit board 42 located outside the display panel is connected.
  • the orthographic projection of the first printed circuit board 41 on the plane of the display panel may be within the range of the orthographic projection of the protective layer 13 on the plane of the display panel, and the second printed circuit board 42 on the plane of the display panel.
  • the orthographic projection of the display substrate 10 on the display panel plane does not overlap, and the orthographic projection of the second printed circuit board 42 on the display panel plane does not overlap with the orthographic projection of the protective layer 13 on the display panel plane.
  • the display panel may further include a fixing tape (Cell Tape) 50, the first end of the fixing tape 50 is attached to the side of the polarizing layer 11 away from the display area, and the second end of the fixing tape 50 is along the cell tape.
  • One direction D1 extends to one side of the first printed circuit board 41 in the first direction D1, after being bent and wound to the bottom of the first printed circuit board 41, it extends to the area where the heat dissipation layer 22 is located along the opposite direction of the first direction D1 , and pasted and fixed on the heat dissipation layer 22.
  • the fixing tape 50 can function to fix the display substrate 10 and the first printed circuit board 41 on the one hand, and can protect the bonding connection on the other hand.
  • the fixing tape 50 may have a thickness of about 0.04 mm to 0.06 mm.
  • the thickness of the fixing tape 50 may be about 0.05 mm.
  • an opening or a groove may be provided on the fixing tape 50 , and the opening or groove is configured to allow the second flexible circuit board 32 to pass through so as to be connected to the second printed circuit board 42 .
  • the first printed circuit board 41 may include a first board body and a connecting wire layer disposed on the first board body, the thickness of the first board body may be about 0.25 mm to 0.35 mm, and the connecting wire layer The thickness can be about 0.15mm to 0.25mm.
  • the overall thickness of the first printed circuit board 41 may be about 0.5 mm.
  • the first printed circuit board 41 is a wired circuit board carrying signal connection lines, only a plurality of signal connection lines are provided, and no chip-like electronic devices are provided, so the first printed circuit board 41 can A single-layer board or a multi-layer board is adopted, and the number of layers of the multi-layer board is less than or equal to 3, that is, the first printed circuit board 41 can adopt a single-layer board, two-layer board or three-layer board structure.
  • the second printed circuit board 42 may include a second board body and an electronic device layer disposed on the second board body, the thickness of the second board body may be about 0.8 mm to 1.2 mm, and the electronic device layer The thickness is 1.5mm to 2.5mm.
  • the overall thickness of the second printed circuit board 42 may be about 3 mm.
  • the second printed circuit board 42 is a driving circuit board carrying a driving chip, chip-like electronic devices need to be provided, so the second printed circuit board 42 can be a multilayer board, and the number of layers of the multilayer board It may be about 8 layers to 10 layers, that is, the second printed circuit board 42 may adopt an 8-layer board, 9-layer board or 10-layer board structure.
  • the thickness of the first flexible circuit board 31 may be about 0.05 mm to about 0.09 mm.
  • the thickness of the first flexible circuit board 31 may be about 0.07mm.
  • the display panel may include a fixing tape 50, a heat dissipation layer 22, a back film layer 21, a display substrate 10, a polarizer Layer 11, adhesive layer 12 and protective layer 13.
  • the thickness of the fixing tape 50 is about 0.05 mm
  • the thickness of the heat dissipation layer is about 0.2 mm
  • the thickness of the back film layer is about 0.05 mm
  • the thickness of the display substrate 10 is about 0.12 mm
  • the thickness of the polarizing layer is about 0.05 mm.
  • the thickness is about 0.15mm
  • the thickness of the adhesive layer is about 0.2mm.
  • cover glass is used for the protective layer
  • the overall thickness of the F1 position is about 1.37mm.
  • Colorless polyimide is used for the protective layer, and the F1 position The overall thickness is about 0.83mm.
  • the display panel may include a fixing tape 50, a first printed circuit board 41, a first flexible circuit board 31, a fixing tape 50 and a protective layer 13. .
  • cover glass is used for the protective layer, and the F2 position
  • the overall thickness of the F2 is about 1.22mm.
  • colorless polyimide is used, and the overall thickness of the F2 position is about 0.68.
  • the overall thickness of the second printed circuit board 42 may be about 3.0 mm.
  • the printed circuit board is divided into the drive separation design of the wiring circuit board and the driving circuit board, and the wiring circuit board is arranged on one side of the display substrate.
  • the overall thickness of the display panel is reduced, even at the F1 position where the display panel is the thickest, the overall thickness is only 0.83mm to 1.37mm.
  • the exemplary embodiments of the present disclosure effectively reduce the overall thickness of the display panel, which is only 20% to 30% of the overall thickness of the existing structure, maximizing achieve an ultra-thin structure.
  • FIG. 12 is a schematic structural diagram of a chip region according to an exemplary embodiment of the present disclosure. As shown in FIG. 12, along the second direction D2, the chip area 210 can be divided into a first chip sub-area 210A, a second chip sub-area 210B and a third chip sub-area 210C, and the first chip sub-area 210A and the third chip sub-area 210A.
  • Sub-section 210C can be provided with a plurality of signal leads, and the second chip sub-section 210B can be provided with a plurality of SDIC chips 20, and a plurality of SDIC chips 20 are configured to accept data such as images, videos, system UIs from the T-con chip, according to Gamma and other compensation parameters of various IPs read by Flash generate corresponding data signals.
  • the SDIC chip 20 can also generate various GOA signals, such as Gate GOA, EM GOA, Reset GOA, etc.
  • the plurality of signal leads of the first chip sub-region 210A and the third chip sub-region 210C may include FOP_Test leads, COP_Test leads, ELVSS leads, ELVDD leads, VGH leads, VGL leads, VINIT leads, EM_GOA leads , Gate_GOA leads, Reset_GOA leads, Test Point leads, etc.
  • the COP_Test lead is configured to detect the impedance after COP binding
  • the FOP_Test lead is configured to detect the impedance of the Flexible on Panel (FOP) after binding
  • the Test Point lead is configured to detect various test points.
  • the ELVDD lead, the VINIT lead and the ELVSS lead are respectively configured to provide a high-level voltage, reset voltage and low-level voltage to a plurality of pixel drive circuits in the display area
  • the VGH lead and VGL lead are respectively configured to provide a high-level voltage and a low-level voltage
  • the Gate_GOA lead, the EM_GOA lead and the Reset_GOA lead are respectively configured to provide a row scan signal, a row light emission control signal and a row reset signal to the display area.
  • the plurality of signal wires of the first chip sub-region 210A and the plurality of signal wires of the third chip sub-region 210C may be mirror-symmetrical with respect to the second chip sub-region 210B.
  • the second chip sub-region 210B may also be provided with a plurality of input signal lines and a plurality of output signal lines, and the plurality of input signal lines may include ISP1 lines to ISP4 lines, Gamma lines, VRF_H lines and VRF_L lines, etc. , the multiple output signal lines may include D1, D2, . . . , Dn.
  • the ISP1 line to the ISP4 line are configured to input image data to the SDIC chip 20
  • the Gamma line is configured to input the Gamma reference voltage to the SDIC chip 20
  • the VRF_H line is configured to input the Gamma black state to the SDIC chip 20 voltage
  • the VRF_L line is configured to input the Gamma white state voltage to the SDIC chip 20 .
  • the second chip sub-region 210B can be provided with 6 SDIC chips 20, and the output terminals of the 6 SDIC chips 20 pass through 1920 output signal lines (D1, D2, ..., D1920) and fan-out (Fan-out) lines are correspondingly connected to the data signal lines in the display area.
  • FIG. 13 is a schematic diagram of an equivalent circuit of a printed circuit board according to an exemplary embodiment of the present disclosure, illustrating the equivalent circuit structures of the first printed circuit board 41 and the second printed circuit board 42 .
  • the first printed circuit board 41 can include a plurality of signal connection lines
  • the second printed circuit board 42 can include timing control (T-con) chips, power management (PMIC) chips, power supply management (ELIC) Electronic devices such as chip, reference gamma (P-Gamma) chip, memory (Flash), level shifter (Level Shifter), temperature sensor (Temp Sensor) and connection interface.
  • T-con timing control
  • PMIC power management
  • ELIC power supply management
  • a plurality of signal connection lines on the first printed circuit board 41 are connected with a plurality of signal leads of the bonding area 200 and input signal lines of the SDIC chip on the one hand, and connected with the second printed circuit board on the other hand.
  • Multiple chips on 42 are correspondingly connected.
  • connection interface may adopt a display interface (eDP), and the eDP interface is configured to realize the connection between the driving circuit board and the host.
  • the protocol of the eDP interface can adopt eDP1.4b, which can include 4 pairs of (Lane) main channels (Main link), 1 auxiliary channel (AUX Chanel), 1 hot plug (HPD) channel, and 1 built-in self-test ( BIST) channels, etc.
  • Each pair of main channels can be a pair of differential lines to transmit high-speed, large-capacity data, and the data can include display information such as images, videos, and system UIs.
  • the auxiliary channel can transmit data with low bandwidth requirements, as well as channel management and device control signals, etc., and the hot-swap channel can be used as a hot-swap detection channel.
  • the second printed circuit board 42 can be connected with the host through the eDP interface, and the channel for transmitting data signals in the eDP interface is connected with the T-con chip and the Flash 2 respectively, such as the Main link of the 4 channels connected with the T-con chip, the main link of the 1 channel AUX, 1-channel HPD, 1-channel BIST and 1-channel I2C3, serial peripheral interface (Serial Peripheral interface, SPI for short) connected to Flash 2.
  • the channels for transmitting power signals in the eDP interface are respectively connected to the PMIC chip, P-Gamma chip, ELIC chip and Level Shifter, such as supplying 3.3V input (Vin) voltage to the PMIC chip, P-Gamma chip and Level Shifter, and input to the ELIC chip 6V to 21V power supply (Vbat) voltage, Vbat can be generated by the battery or power adapter of the host.
  • Vin 3.3V input
  • Vbat 21V power supply
  • the power management (PMIC) chip is configured to convert the low voltage input by the host into the digital voltage (VDD), analog voltage (AVDD) and high and low voltage (VGH/VGL) required by the device to supply corresponding chip.
  • the output of the PMIC chip includes at least: digital voltage (VDD) for T-con chip, Flash and Temp Sensor, generally 1.1V and 1.8V; high voltage (VGH) and low voltage (VGL) for Level Shifter; and supply
  • the analog voltage (AVDD) of P-Gamma chip and SDIC chip is generally 6.5V to 8V.
  • the power supply management (ELIC) chip is configured to convert the variable AC and DC voltage input by the host (powered by a battery or a notebook power adapter converter) into the required voltage for the pixel driving circuit and the light emitting device in the display area. Voltage.
  • the ELIC chip can output ELVDD, ELVSS, VINIT, etc. to the pixel driving circuit in the display area.
  • a reference gamma (P-Gamma) chip is configured to generate maximum gray scale voltage values in different bands (Band), and provide the SDIC chip as a Gamma reference voltage.
  • P-Gamma chip can output Gamma voltage and reference (REF) voltage.
  • the level shifter (Level Shifter) is configured to increase the signal level value to a target value without changing the time domain waveform, relative positional relationship, and duty cycle. For example, it may be configured to increase the driving level value of each GOA signal.
  • the level shifter by setting the level shifter on the second printed circuit board 42 , the number of pins of the SDIC chip can be reduced, and the bonding area and the number of signal leads and signal connection lines on the first printed circuit board 41 can be reduced.
  • Flash 1 to Flash 3 can be connected to the T-con chip through SPI, and after the system and the display panel are turned on, various data inside the Flash will be read by the T-con chip.
  • the T-con chip can integrate functional modules such as a graphics frame buffer (Frame Buffer), various types of IP, readable and writable registers, power conversion, and logic operations, and is configured to output to each SDIC chip Image, video, system UI and other data signals.
  • functional modules such as a graphics frame buffer (Frame Buffer), various types of IP, readable and writable registers, power conversion, and logic operations, and is configured to output to each SDIC chip Image, video, system UI and other data signals.
  • the image, video, system UI and other data signals output by the T-con chip are respectively transmitted to the input terminals of multiple SDIC chips through the PHI interface, and the GOA timing control signal (such as Gate GOA, EM GOA and Reset GOA) output by the T-con chip , provided to the signal connection line located on the first printed circuit board 41 after level shifting by the Level Shifter, extending along the frame of the display panel after passing through the binding area, connected with the scanning signal line and the light-emitting control line of the display area, and controlling the display Pixel drive circuits for a plurality of pixel rows.
  • the GOA timing control signal such as Gate GOA, EM GOA and Reset GOA
  • the second printed circuit board 42 may not be provided with a Level Shifter.
  • the GOA timing control signal output by the T-con chip can be directly output to the input terminals of some SDIC chips (such as SDIC1 and SDIC 6), and then control the pixel driving circuits of multiple pixel rows in the display area.
  • a display device such as a notebook
  • the second printed circuit board 42 can be arranged on the corresponding position of the host.
  • the second printed circuit board 42 can be fixed on the main board, or can be arranged between the keyboard and the battery, and the second flexible circuit board 32 connecting the first printed circuit board 41 and the second printed circuit board 42 can be hidden. Installed in the hinge of the notebook, it will neither affect the overall thickness of the display panel nor affect the overall aesthetics of the notebook.
  • the present disclosure splits the printed circuit board into a driving circuit board and a driving circuit board, and arranges the driving circuit board (the second printed circuit board) that is prone to heat at the corresponding position of the host computer other than the display panel, which is not only effective
  • the defect of display color cast caused by the heating of the driving circuit board is avoided, the display quality is improved, and the defect of the lifespan of the light-emitting device caused by the heating of the driving circuit board can be effectively avoided, and the life of the light-emitting device is improved.
  • FIG. 14 is a schematic plan view of another display panel according to an exemplary embodiment of the present disclosure.
  • FIG. 15 is a side view of the display panel shown in FIG. The folded state of the bound region after it has been bent.
  • the display panel in a plane parallel to the display panel, the display panel may include a display area 100 , a binding area 200 located on one side of the display area 100 in the first direction D1, and a frame located on the other side of the display area 100
  • the area 300, the binding area 200 may include the bending area 201, the chip area 210 and the lead area 220 arranged in sequence along the first direction D1, the bending area 201 is configured to bend in the third direction D3, so that the chip area 210 And the pin area 200 may overlap the display area 100 in the third direction D3.
  • a plurality of SDIC chips 20 are respectively bonded and connected to the chip region 210, the first ends of the plurality of first flexible circuit boards 31 are respectively bonded and connected to the pin region 220, and the second ends of the plurality of first flexible circuit boards 31 are connected to the pin region 220 respectively.
  • the first end of the first printed circuit board 41 is connected, and the second end of the first printed circuit board 41 is connected to the second printed circuit board 42 through the second flexible circuit board 32 .
  • the SDIC chip, the first flexible circuit board, the first printed circuit board, the second flexible circuit board, and the second printed circuit board may be connected in substantially the same manner and structure as the foregoing exemplary embodiments, I won't go into details here.
  • the display panel in a plane perpendicular to the display panel, may include a display substrate 10, a polarizing layer 11 disposed on the display substrate 10, and an adhesive layer 12 disposed on the side of the polarizing layer 11 away from the display substrate.
  • the protective layer 13 arranged on the side of the adhesive layer 12 away from the display substrate
  • the back film layer 21 arranged on the side of the display substrate 10 away from the protective layer 13
  • the heat dissipation layer 22 arranged on the side of the back film layer 21 away from the display substrate
  • the spacer layer 23 disposed on the side of the heat dissipation layer 22 away from the display substrate and the back glue 24 disposed on the side of the spacer layer 23 away from the display substrate.
  • the spacer (Spacer) layer 23 can be located in the display area 100 and the binding area 200 near the partial area of the display area 100, the back glue 24 can be located in the display area 100, other film layer structures and film layers thereof
  • the positional relationship of can be substantially the same as that of the foregoing exemplary embodiments.
  • a plurality of pins and a plurality of pads of the binding area 200 may be arranged on the surface of the binding area 200 on the third direction D3 (upper surface) side surface, Finally, a plurality of pins and a plurality of pads are located on the surface of the opposite direction (lower surface) side of the third direction D3 of the binding area 200, so the SDIC chip 20 can be located in the opposite direction of the third direction D3 of the binding area 200 (lower surface), and connected to a plurality of welding pads, the first end of the first flexible circuit board 31 can be located on the side of the binding area 200 in the opposite direction (lower surface) of the third direction D3, and connected to multiple bonding pads. pin connection.
  • the first flexible circuit board 31 After the second end of the first flexible circuit board 31 extends along the direction opposite to the first direction D1 (the direction close to the display area), it is connected to the first printed circuit board 41, that is, the first printed circuit board 41 is located where the display area 100 is located. area, not only the orthographic projections of the first flexible circuit board 31 and the first printed circuit board 41 on the display panel plane are within the range of the orthographic projection of the display substrate 10 on the display panel plane, but also the first flexible circuit board 31 and the second The orthographic projection of a printed circuit board 41 on the plane of the display panel is within the range of the orthographic projection of the display area 100 on the plane of the display panel.
  • the first printed circuit board 41 is connected to the first end of the second flexible circuit board 32, and the second end of the second flexible circuit board 32 extends away from the display panel and is located outside the display panel.
  • the second printed circuit board 42 of the host position of the area is connected, not only the orthographic projection of the second printed circuit board 42 on the display panel plane does not overlap with the orthographic projection of the display substrate 10 on the display panel plane, but also the second printed circuit board The orthographic projection of 42 on the plane of the display panel does not overlap with the orthographic projection of the protective layer 13 on the plane of the display panel.
  • the display panel may further include a fixing tape 50, the first end of the fixing tape 50 is pasted on the display substrate 10 outside the polarizing layer 11, and the second end of the fixing tape 50 extends along the bending direction to
  • the back side of the display substrate 10 extends to the side of the first printed circuit board 41 opposite to the first direction D1 along the opposite direction of the first direction D1, and is pasted and fixed on the spacer layer 23 by the back glue 24, and the tape is fixed 50 can play the role of fixing the display substrate 10 and the first printed circuit board 41 on the one hand, and can play the role of protecting the SDIC chip 20, the first flexible circuit board 31 and the first printed circuit board 41 on the other hand.
  • an opening or a groove may be provided on the fixing tape 50 , and the opening or groove is configured to allow the second flexible circuit board 32 to pass through so as to be connected to the second printed circuit board 42 .
  • the material of the spacer layer 23 may be polyethylene terephthalate (PET), and the thickness of the spacer layer 23 may be about 0.10 mm to 0.16 mm.
  • the thickness of the spacer layer 23 may be about 0.13 mm.
  • the SDIC chip 20 may have a thickness of about 0.15 mm to about 0.25 mm.
  • the thickness of the SDIC chip 20 may be about 0.2mm.
  • the materials and thicknesses of the display substrate 10, the polarizing layer 11, the adhesive layer 12, the protective layer 13, the heat dissipation layer 22, the back film layer 21, and the fixing tape 50 may be substantially the same as those of the foregoing exemplary embodiments.
  • the structures and thicknesses of the first printed circuit board 41 and the second printed circuit board 42 may be substantially the same as those of the foregoing exemplary embodiments.
  • the display panel may include a fixing tape 50, a first printed circuit board 41, a first flexible circuit board 31, Back glue 24, spacer layer 23, heat dissipation layer 22, back film layer 21, display substrate 10, polarizing layer 11, bonding layer 12 and protective layer 13, protective layer 13 can be cover glass (CG), or can be Colorless polyimide (CPI).
  • CG cover glass
  • CPI Colorless polyimide
  • the thickness of the adhesive layer is about 0.2 mm
  • the thickness of the polarizing layer is about 0.15 mm
  • the thickness of the display substrate 10 is about 0.12 mm
  • the thickness of the back film layer is about 0.05 mm
  • the thickness of the heat dissipation layer is about 0.15 mm.
  • the thickness can be about 0.2mm
  • the thickness of the spacer layer is about 0.13mm
  • the thickness of the fixing tape 50 is about 0.05mm
  • the total thickness of the first printed circuit board is about 0.5mm
  • the thickness of the first flexible circuit board is about 0.07mm.
  • mm as an example, if the cover glass is used for the protective layer, the overall thickness of the F1 position is about 2.07mm, and for the protective layer is colorless polyimide, the overall thickness of the F1 position is about 1.53mm.
  • the display panel may include a fixing tape 50, an SDIC chip 20, a display substrate 10, a back film layer 21, a spacer layer 23, and a heat dissipation layer 22. , a back film layer 21 , a display substrate 10 , a polarizing layer 11 , an adhesive layer 12 and a protective layer 13 .
  • the cover glass is used for the protective layer, and the overall thickness of the F2 position is about 1.87mm, and the colorless polyimide is used for the protective layer, and the overall thickness of the F2 position is about 1.33mm.
  • the overall thickness of the second printed circuit board 42 may be about 3.0mm, and the structure and installation position of the second printed circuit board 42 may be Basically the same as the previous exemplary embodiment.
  • the wiring circuit board is arranged on the back of the display substrate through the bending and driving separation design of the binding area, and the wiring circuit board is only provided with signal connection lines, which not only effectively reduces the overall thickness of the display panel, but also effectively Reduced border width. Even at the F1 position where the display panel is the thickest, the overall thickness is only 1.53 mm to 2.07 mm. Compared with the conventional structure with an overall thickness of about 3.2 mm to 4.4 mm, the exemplary embodiments of the present disclosure effectively reduce the overall thickness of the display panel. Thickness, the overall thickness is only 40% to 50% of the overall thickness of the existing structure, and the ultra-thin structure is realized to the greatest extent.
  • the frame width of the display panel is only about 3.1 mm through bending of the binding area.
  • the exemplary embodiment of the present disclosure effectively reduces the frame width of the display panel.
  • the frame width is only 30% to 40% of the frame width of the existing structure, and the screen-to-body ratio is increased by about 3%, which is conducive to realizing full-screen display.
  • Fig. 16 is a schematic structural diagram of a second printed circuit board according to an exemplary embodiment of the present disclosure.
  • the second printed circuit board may include a second board body and an electronic device layer arranged on the second board body, and the electronic device layer may include a first chip area 81, a second chip area 82, a third chip area Area 83, the first interface area 84 and the second interface area 85, the first chip area 81, the second chip area 82 and the third chip area 83 are arranged at intervals, there is a set distance between adjacent chip areas, the first interface area 84 and the second interface area 85 may be located at the edge of the second plate.
  • the first chip area 81 is configured to set a T-con chip and its peripheral circuits (such as resistors, capacitors, inductors, etc.), and the second chip area 82 is configured to set a PMIC chip and its peripheral circuits,
  • the third chip area 83 is configured to set the ELIC chip and its peripheral circuits,
  • the first interface area 84 is configured to set the second connector, so as to connect with the second flexible circuit board 32, and the second interface area 85 is configured to set the connection interface , so as to connect with the cable TV cable or the third flexible circuit board.
  • the second printed circuit board 42 may further include a plurality of fixing holes 91 to improve fixing reliability.
  • a plurality of fixing holes 91 can be arranged on the corners of the second printed circuit board 42 respectively, and the second printed circuit board 42 can be fixed on the main board of the host computer through the fixing holes 91 by screws.
  • the electronics layer faces the back cover of the motherboard.
  • the second printed circuit board 42 may be arranged at a position close to the heat dissipation fan to improve the heat dissipation capability.
  • the second printed circuit board 42 may further include a plurality of silicone pads 92 to improve heat dissipation.
  • the silica gel gasket 92 can be respectively arranged on the first chip area 81, the second chip area 82 and the third chip area 83, and one side surface of the silica gel gasket 92 can be attached to the upper surface of the chip and the surface of the peripheral components.
  • the other side surface of the silicone pad 92 can face the back cover of the host, which can effectively improve the heat dissipation in the heat-prone area, and improve the working reliability of the chip and peripheral components.
  • the second printed circuit board 42 can also be provided with a plurality of temperature sensors (Temp Sensor) 93, and the temperature sensor 93 is configured to collect temperature, convert the temperature signal into a digital signal and transmit it to the T- con chip.
  • Temperatur Sensor Temperatur Sensor
  • one temperature sensor 93 may be disposed in the second chip area 82 adjacent to the PMIC chip, and another temperature sensor 93 may be disposed in the third chip area 83 adjacent to the ELIC chip.
  • the temperature rise of the PMIC chip and the ELIC chip can be accurately measured by arranging the temperature sensor near the PMIC chip and the ELIC chip, which are prone to heat, so as to adjust the display strategy.
  • the temperature sensor 93 may be disposed in the first chip region 81 , adjacent to the T-con chip.
  • a temperature adjustment strategy may be set in the T-con chip, so as to avoid problems such as display color cast and even lifespan reduction of the light emitting device. For example, after the T-con chip receives the temperature collected by the temperature sensor, it can judge whether the temperature is greater than the preset threshold, and if the temperature is greater than the threshold, it will execute the preset temperature adjustment strategy.
  • the temperature adjustment strategy may include any one or more of the following: reducing the refresh rate, activating an energy-saving mode, limiting display grayscale, and reducing display brightness.
  • the drive circuit board of the present disclosure adopts a modular design, and a plurality of relatively dispersed chip areas are set on the drive circuit board, and T-con chips, PMIC chips and ELIC chips are respectively set in different chip areas, which can not only avoid heat generation and The rise is too concentrated, and it is good for heat dissipation.
  • T-con chips, PMIC chips and ELIC chips are respectively set in different chip areas, which can not only avoid heat generation and The rise is too concentrated, and it is good for heat dissipation.
  • the present disclosure can effectively control the temperature of the driving circuit board by setting the driving circuit board on the host computer, and through the partition design, setting the temperature sensor, setting the silicone gasket and being close to the fan, etc., and reducing the impact on the chip and its attached components due to temperature rise
  • the influence of the working efficiency of the device, improving the conversion efficiency of the power supply can further reduce the overall power consumption, can improve the overall appearance and aesthetic feeling of the display device, and significantly enhance the competitiveness of the display device.
  • the structures shown in the present disclosure are only some exemplary illustrations, and the structure and installation position of the driving circuit board can be changed according to actual needs, which is not limited in the present disclosure.
  • Exemplary embodiments of the present disclosure also provide a display device including the aforementioned display panel.
  • the display device (such as a notebook) can also include a host, the host and the display panel can be connected through a hinge, the host can at least include a main board, a keyboard, a battery and a back cover, and the second printed circuit board can be fixed on the main board , or can be arranged between the keyboard and the battery, and the second flexible circuit board can be hidden and installed in the hinge of the notebook.

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Abstract

一种显示面板和显示装置，显示面板包括显示基板(10)、第一印刷电路板(41)和第二印刷电路板(42)，显示基板(10)包括显示区域(100)和位于显示区域(100)一侧的绑定区域(200)，绑定区域(200)通过第一柔性电路板(31)与第一印刷电路板(41)连接，第一印刷电路板(41)通过第二柔性电路板(32)与第二印刷电路板(42)连接；第一印刷电路板(41)为搭载信号连接线的走线电路板，第二印刷电路板(42)为搭载驱动芯片的驱动电路板，第二印刷电路板(42)在显示面板平面上的正投影与显示基板(10)在显示面板平面上的正投影没有交叠。

Description

显示面板和显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品，已被广泛应用于手机、笔记本电脑、电视、车载显示、智能可穿戴设备等领域。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示面板，包括显示基板、第一印刷电路板和第二印刷电路板，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域通过第一柔性电路板与所述第一印刷电路板连接，所述第一印刷电路板通过第二柔性电路板与所述第二印刷电路板连接；所述第一印刷电路板为搭载信号连接线的走线电路板，所述第二印刷电路板为搭载驱动芯片的驱动电路板，所述第二印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影没有交叠。
在示例性实施方式中，所述第一印刷电路板上设置有第一连接器，所述第二柔性电路板通过所述第一连接器与所述第一印刷电路板连接。
在示例性实施方式中，所述第二印刷电路板上设置有第二连接器，所述第二柔性电路板通过所述第二连接器与所述第二印刷电路板连接。
在示例性实施方式中，所述第一印刷电路板为单层板或多层板，多层板的层数小于或等于3。
在示例性实施方式中，所述第一印刷电路板包括第一板体和设置在所述第一板体上的连接线层，所述第一板体的厚度为0.25mm至0.35mm，所述连接线层的厚度为0.15mm至0.25mm。
在示例性实施方式中，所述第二印刷电路板为多层板，多层板的层数为8至10。
在示例性实施方式中，所述第二印刷电路板包括第二板体和设置在所述第二板体上的电子器件层，所述第二板体的厚度为0.8mm至1.2mm，所述电子器件层的厚度为1.5mm至2.5mm。
在示例性实施方式中，所述电子器件层至少包括间隔设置的第一芯片区、第二芯片区和第三芯片区，所述第一芯片区被配置为设置时序控制芯片及其外围电路，所述第二芯片区被配置为设置电源管理芯片及其外围电路，所述第三芯片区被配置为设置供电电源管理芯片及其外围电路。
在示例性实施方式中，所述第二印刷电路板还包括至少一个硅胶垫片，所述硅胶垫片贴附在所述时序控制芯片、电源管理芯片或者供电电源管理芯片的表面。
在示例性实施方式中，所述第二印刷电路板还包括至少一个温度传感器，所述温度传感器设置在所述第一芯片区内，与所述时序控制芯片邻近，和/或，所述温度传感器设置在所述第二芯片区内，与所述电源管理芯片邻近，和/或，所述温度传感器设置在所述第三芯片区内，与所述供电电源管理芯片邻近。
在示例性实施方式中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的芯片区和引脚区，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区远离所述显示区域的一侧，并与所述引脚区的多个引脚绑定连接。
在示例性实施方式中，所述第一印刷电路板设置在所述第一柔性电路板远离所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影 与所述显示基板在显示面板平面上的正投影没有交叠。
在示例性实施方式中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的弯折区、芯片区和引脚区，所述弯折区被配置为通过弯折使所述芯片区和引脚区翻转到所述显示区域的背面，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区靠近所述显示区域的一侧，并与所述引脚区的多个引脚绑定连接。
在示例性实施方式中，所述第一印刷电路板设置在所述第一柔性电路板靠近所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影与所述显示区域在显示面板平面上的正投影至少部分交叠。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述的显示面板。
在示例性实施方式中，所述显示装置还包括主机，所述主机与所述显示面板通过转轴连接，所述第二柔性电路板设置在所述转轴中。
在示例性实施方式中，所述主机包括主板、键盘和电池，所述第二印刷电路板固定在所述主板上，或者，所述第二印刷电路板设置在所述键盘与所述电池之间。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示面板的平面结构示意图；
图3为另一种显示面板的侧面结构示意图；
图4为一种显示面板中显示区域的平面结构示意图；
图5为一种显示面板中显示区域的剖面结构示意图；
图6为一种显示面板中显示基板的剖面结构示意图；
图7为一种像素驱动电路的等效电路示意图；
图8为一种像素驱动电路的工作时序图；
图9为一种显示面板中印刷电路板的安装结构示意图；
图10为本公开示例性实施例一种显示面板的平面结构示意图；
图11为图10所示显示面板的侧视图；
图12为本公开示例性实施例一种芯片区的结构示意图；
图13为本公开示例性实施例一种印刷电路板的等效电路示意图；
图14为本公开示例性实施例另一种显示面板的平面结构示意图；
图15为图14所示显示面板的侧视图；
图16为本公开示例性实施例一种第二印刷电路板的结构示意图。
附图标记说明:
10—显示基板；          11—偏光层；            12—粘结层；
13—保护层；            20—源驱动芯片；        21—背膜层；
22—散热层；            23—隔垫层；            24—背胶；
30—柔性电路板；        31—第一柔性电路板；    32—第二柔性电路板；
33—第三柔性电路板；    40—印刷电路板；        41—第一印刷电路板；
42—第二印刷电路板；    50—固定胶带；          61—第一连接器；
62—第二连接器；        63—连接接口；          81—第一芯片区；
82—第二芯片区；        83—第三芯片区；        84—第一接口区；
85—第二接口区；        91—固定孔；            92—硅胶垫片；
93—温度传感器；        100—显示区域；         101—基底；
102—驱动电路层；       104—封装层；           200—绑定区域；
201—弯折区；           210—芯片区；           220—引脚区；
300—边框区域；         301—阳极；             302—像素定义层；
303—有机发光层；      304—阴极；            401—第一封装层；
402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、 “连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的 数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示面板的平面结构示意图。如图2所示，显示面板可以包 括显示区域100、位于显示区域100第一方向D1一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。显示区域100可以至少包括组成像素阵列的多个子像素Pxij，以显示动态图片或静止图像。绑定区域200可以至少包括多条信号引线、源驱动芯片(Source Driver IC，简称SDIC)20和多个引脚，多条信号引线被配置为将显示区域100的多个数据信号线连接至源驱动芯片20，源驱动芯片20被配置为产生用于驱动显示的驱动信号，通过多条信号引线提供给在显示区域100的子像素，多个引脚被配置为绑定连接柔性电路板(Flexible Printed Circuit，简称FPC)30。边框区域300可以至少包括栅极驱动电路和电源线，栅极驱动电路被配置为产生扫描信号和发射信号并提供给在显示区域100的子像素，电源线被配置为向显示区域100的子像素传输电压信号。在示例性实施方式中，绑定区域200和边框区域300可以包括环形结构的隔离坝，本公开在此不做限定。
在示例性实施方式中，绑定区域200可以至少包括沿着第一方向D1(远离显示区域的方向)依次设置的芯片区和引脚区，芯片区可以至少包括多个焊盘，源驱动芯片20可以绑定连接在芯片区的多个焊盘上，引脚区可以至少包括多个引脚，柔性电路板30可以绑定连接在引脚区的多个引脚上。在示例性实施方式中，源驱动芯片20和柔性电路板30第二方向D2上的宽度可以小于绑定区域200第二方向D2上的宽度，第二方向D2与第一方向D1交叉。
图3为另一种显示面板的侧面结构示意图。如图3所示，显示面板可以包括显示区域100、绑定区域200和边框区域，显示区域100和边框区域的结构与图2所示结构基本上相同，绑定区域200可以包括沿着第一方向D1依次设置的弯折区、芯片区和引脚区。弯折区可以在第三方向D3上以一曲率弯曲，可以将芯片区和引脚区的表面反转，即芯片区和引脚区朝向上方的表面可以通过弯折区的弯曲转换成面朝向下方，第三方向D3与第一方向D1交叉。在示例性实施方式中，当弯折区被弯曲时，芯片区和引脚区可以在第三方向D3(厚度方向)上与显示区域100重叠。
在示例性实施方式中，显示面板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，第一方向D1可以是显示区域中数据信号线的延 伸方向(列方向)，第二方向D2可以是显示区域中扫描信号线的延伸方向(行方向)，第三方向D3可以是垂直于显示面板平面的方向，第一方向D1和第二方向D2可以相互垂直，第一方向D1和第三方向D3可以相互垂直。
图4为一种显示面板中显示区域的平面结构示意图。如图4所示，显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，三个子像素均可以包括像素驱动电路和发光器件，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流，发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色(R)光线的红色子像素、第二子像素P2可以是出射蓝色(B)光线的蓝色子像素，第三子像素P3可以是出射绿色(G)光线的绿色子像素。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形、六边形、圆形或椭圆形等，可以采用水平并列、竖直并列或品字等方式等排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列、正方形或钻石形等方式排列，本公开在此不做限定。
图5为一种显示面板中显示区域的剖面结构示意图。如图5所示，在垂直于显示面板的平面内，沿着从下至上的方向，显示面板可以包括：散热层22，背膜层21，显示基板10，偏光层11，粘结层12和保护层13。
在示例性实施方式中，显示基板10被配置为显示动态图片或静止图像，偏光层11被配置为降低外界环境光的反射，保护层13被配置为保护显示面板，通过粘结层12贴合在偏光层11上，背膜层21被配置为保护显示基板10，散热层22被配置提高显示基板10的散热性能。
图6为一种显示面板中显示基板的剖面结构示意图，示意了显示区域中三个子像素的结构。如图6所示，在垂直于显示面板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示区域可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图6中仅以像素驱动电路包括一个晶体管102A和一个存储电容102B作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与晶体管102A的第二极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层和电子注入层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
图7为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。如图7所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路可以与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极 与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图8为一种像素驱动电路的工作时序图。下面通过图7示例的像素驱动电路的工作过程说明本公开示例性实施例，图7中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E 的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图9为一种显示面板中印刷电路板的安装结构示意图。如图9所示，显示面板的绑定区域可以至少包括源驱动芯片20和引脚，引脚与柔性电路板30的一端连接，柔性电路板30的另一端弯折到显示面板的背面，与印刷电路板(Printed Circuit Board，简称PCB)40连接，印刷电路板40上设置有电子器件，电子器件至少包括时序控制(T-con)芯片、电源管理芯片(PMIC)、供电电源管理芯片(ELIC)和存储器(Flash)等。
在示例性实施方式中，显示面板可以包括叠设的散热层22、背膜层21、显示基板10、偏光层11、粘结层12和保护层13，印刷电路板40可以贴设在散热层22远离显示基板10的一侧，电子器件可以设置在印刷电路板40远离显示基板10的一侧。
在示例性实施方式中，印刷电路板40的厚度可以约为1.0mm左右，电子器件的厚度可以约为1.5mm至2.5mm左右。根据图9所示结构可以看出，由于印刷电路板40和电子器件的厚度较大，使得显示面板的整体厚度较大，约为3.2mm至4.4mm左右。
随着技术革新和消费演进，显示装置刷新率(Frame Rate，简称FR)逐渐提高，已从60Hz逐步提高到90Hz、120Hz、144Hz、240Hz等。刷新率的提高使得驱动芯片(如T-con、PMIC等)的功耗和发热量大幅度增加。由于 该图9所示显示面板结构的印刷电路板和电子器件设置在显示面板的背面，显示面板工作时，电子器件产生的热量通过印刷电路板传递到显示面板，造成显示面板对应位置的温度快速上升，不仅引起显示面板上像素驱动电路的特性偏移，而且造成显示面板上发光器件的寿命降低。例如，当温度上升后，像素驱动电路中晶体管(TFT)的阈值电压Vth特性正偏，造成在驱动电压不变的情况下，TFT沟道开启增加，流过发光器件的驱动电流增加，直接造成发光强度增加。即使R子像素、G子像素和B子像素的Vth特性偏移相同，由于R子像素、G子像素和B子像素的开口率和发光效率不同，导致R子像素、G子像素和B子像素的发光强度比例失衡，偏离原来的亮度和色坐标。又如，发光器件的寿命与总发光强度和总发光时间强相关，由于温升导致发光强度增加，随着时间的推移，发光强度增加的效应叠加，因而造成发光器件老化加速，寿命降低。
本公开示例性实施例提供了一种显示面板，包括显示基板、第一印刷电路板和第二印刷电路板，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域通过第一柔性电路板与所述第一印刷电路板连接，所述第一印刷电路板通过第二柔性电路板与所述第二印刷电路板连接；所述第一印刷电路板为搭载信号连接线的走线电路板，所述第二印刷电路板为搭载驱动芯片的驱动电路板，所述第二印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影没有交叠。
在示例性实施方式中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的芯片区和引脚区，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区远离所述显示区域的一侧，并与所述引脚区的多个引脚绑定连接。所述第一印刷电路板设置在所述第一柔性电路板远离所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影没有交叠。
在示例性实施方式中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的弯折区、芯片区和引脚区，所述弯折区被配置为通过弯折使所述芯片区和引脚区翻转到所述显示区域的背面，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区靠近所述显示区域的一侧，并与所述引 脚区的多个引脚绑定连接。所述第一印刷电路板设置在所述第一柔性电路板靠近所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影至少部分交叠。
在示例性实施方式中，所述第一印刷电路板包括第一板体和设置在所述第一板体上的连接线层，所述第一板体的厚度为0.25mm至0.35mm，所述连接线层的厚度为0.15mm至0.25mm。
在示例性实施方式中，所述第二印刷电路板包括第二板体和设置在所述第二板体上的电子器件层，所述第二板体的厚度为0.8mm至1.2mm，所述电子器件层的厚度为1.5mm至2.5mm。
图10为本公开示例性实施例一种显示面板的平面结构示意图，图11为图10所示显示面板的侧视图。如图10和图11所示，在平行于显示面板的平面内，显示面板可以包括显示区域100、位于显示区域100第一方向D1一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。绑定区域200可以包括沿着第一方向D1依次设置的芯片区210和引脚区220，芯片区210可以至少包括多个焊盘，多个SDIC芯片20分别绑定连接在芯片区210的多个焊盘上，引脚区220可以至少包括多个引脚，多个第一柔性电路板31的第一端分别绑定连接在引脚区220的多个引脚上，多个第一柔性电路板31的第二端均与第一印刷电路板41的第一端连接，第一印刷电路板41的第二端通过第二柔性电路板32与第二印刷电路板42连接。
在示例性实施方式中，芯片区210可以设置6个SDIC芯片20，6个SDIC芯片20可以沿着第二方向D2依次设置，可以采用面板覆晶封装(Chip On Panel，简称COP)方式将SDIC芯片20绑定连接在芯片区210。引脚区220可以绑定连接6个第一柔性电路板31，6个第一柔性电路板31可以分别位于6个SDIC芯片20第一方向D1的一侧，可以采用COP方式将第一柔性电路板31的第一端绑定连接在引脚区220。
在示例性实施方式中，第一柔性电路板31的第二端可以采用COP方式与第一印刷电路板41连接。
在示例性实施方式中，第一印刷电路板41与第二柔性电路板32之间可 以采用COP方式连接，或者可以采用连接器方式连接。例如，第一印刷电路板41远离显示区域的一侧可以设置有第一连接器61，第二柔性电路板32的第一端可以直接插入第一连接器61，实现第一印刷电路板41与第二柔性电路板32的连接。本公开采用连接器方式连接第一印刷电路板41和第二柔性电路板32，可以在后期生产和组装过程中方便显示面板的调试和校正。
在示例性实施方式中，第二柔性电路板32与第二印刷电路板42之间可以采用COP方式连接，或者可以采用连接器方式连接。例如，第二印刷电路板42靠近显示区域的一侧可以设置有第二连接器62，第二柔性电路板32的第二端可以直接插入第二连接器62，实现第二柔性电路板32与第二印刷电路板42的连接。本公开采用连接器方式连接第二柔性电路板32和第二印刷电路板42，可以在后期生产和组装过程中方便显示面板的调试和校正。
在示例性实施方式中，连接器方式可以是零插入力(Zero Insertion Force，简称ZIF)连接方式。
在示例性实施方式中，第二印刷电路板42还可以包括连接接口63，连接接口63被配置为通过有线电视电缆(Cable线)或者第三柔性电路板33与显示装置的主机连接。
在示例性实施方式中，在垂直于显示面板的平面内，显示面板可以包括显示基板10、设置在显示基板10上的偏光层11、设置在偏光层11远离显示基板10一侧的粘结层12、设置在粘结层12远离显示基板10一侧的保护层13、设置在显示基板10远离保护层13一侧的背膜层21以及设置在背膜层21远离显示基板10一侧的散热层22。
在示例性实施方式中，偏光层11和粘结层12可以仅位于显示区域100，背膜层21和散热层22可以位于显示区域100和绑定区域200中靠近显示区域100的部分区域，保护层13以位于整个显示区域100和整个绑定区域200。
在示例性实施方式中，显示基板10被配置为显示动态图片或静止图像，可以包括在基底上叠设的驱动电路层、发光结构层和封装层，显示基板10的厚度可以约为0.10mm至0.14mm左右。例如，显示基板10的厚度可以约为0.12mm左右。
在示例性实施方式中，偏光层11可以作为防反层，被配置为降低外界环境光的反射。偏光层11可以采用图案化工艺形成，或者可以采用贴附偏光片方式形成。偏光层11的厚度可以约为0.10mm至0.20mm左右。例如，偏光层11的厚度可以约为0.15mm左右。
在示例性实施方式中，粘结层12可以采用光学胶(OCA)，粘结层12的厚度可以约为0.15mm至0.25mm左右。例如，粘结层12的厚度可以约为0.2mm左右。
在示例性实施方式中，保护层13可以是盖板玻璃(Cover Glass，简称CG)，或者可以是塑胶类无色聚酰亚胺(Colorless Polyimide，简称CPI)。
在示例性实施方式中，盖板玻璃的厚度可以约为0.55mm至0.65mm左右，无色聚酰亚胺的厚度可以约为0.05mm至0.07mm左右。例如，盖板玻璃的厚度可以约为0.6mm左右，无色聚酰亚胺的厚度可以约为0.06mm左右。
在示例性实施方式中，背膜层(U-Film)21的厚度可以约为0.04mm至0.06mm左右。例如，背膜层21的厚度可以约为0.05mm左右。
在示例性实施方式中，散热层(SCF)22的厚度可以约为0.15mm至0.25mm左右。例如，散热层22的厚度可以约为0.2mm左右。
在示例性实施方式中，绑定区域200的多个引脚和多个焊盘可以设置在绑定区域200第三方向D3(上表面)一侧的表面上。SDIC芯片20可以设置在绑定区域200第三方向D3(上表面)的一侧，并与多个焊盘绑定连接。第一柔性电路板31的第一端可以设置在引脚区220第三方向D3的一侧，并与多个引脚绑定连接，第一柔性电路板31的第二端沿着第一方向D1延伸后，与第一印刷电路板41连接，即第一印刷电路板41位于绑定区域200远离显示区域100的一侧，第一印刷电路板41在显示面板平面上的正投影与显示基板10在显示面板平面上的正投影没有交叠。
在示例性实施方式中，第一印刷电路板41的第二端与第二柔性电路板32的第一端连接，第二柔性电路板32的第二端向着远离显示面板的方向延伸后，与位于显示面板以外区域的第二印刷电路板42连接。
在示例性实施方式中，第一印刷电路板41在显示面板平面上的正投影可 以位于保护层13在显示面板平面上的正投影的范围之内，第二印刷电路板42在显示面板平面上的正投影与显示基板10在显示面板平面上的正投影没有交叠，第二印刷电路板42在显示面板平面上的正投影与保护层13在显示面板平面上的正投影没有交叠。
在示例性实施方式中，显示面板还可以包括固定胶带(Cell Tape)50，固定胶带50的第一端贴设在偏光层11远离显示区域的一侧，固定胶带50的第二端沿着第一方向D1延伸到第一印刷电路板41第一方向D1的一侧，通过弯折绕到第一印刷电路板41的下方后，沿着第一方向D1的反方向延伸到散热层22所在区域，并贴设固定在散热层22上。在示例性实施方式中，固定胶带50一方面可以起到固定显示基板10和第一印刷电路板41的作用，另一方面可以起到保护绑定连接的作用。
在示例性实施方式中，固定胶带50的厚度可以约为0.04mm至0.06mm。例如，固定胶带50的厚度可以约为0.05mm左右。
在示例性实施方式中，固定胶带50上可以设置开口或凹槽，开口或凹槽被配置为使第二柔性电路板32穿过以便与第二印刷电路板42连接。
在示例性实施方式中，第一印刷电路板41可以包括第一板体和设置在第一板体上的连接线层，第一板体的厚度可以约为0.25mm至0.35mm，连接线层的厚度可以约为0.15mm至0.25mm。例如，第一印刷电路板41的整体厚度可以约为0.5mm左右。
在示例性实施方式中，由于第一印刷电路板41为搭载信号连接线的走线电路板，仅设置多个信号连接线，而没有设置芯片类的电子器件，因而第一印刷电路板41可以采用单层板或多层板，多层板的层数小于或等于3，即第一印刷电路板41可以采用单层板、两层板或者三层板结构。
在示例性实施方式中，第二印刷电路板42可以包括第二板体和设置在第二板体上的电子器件层，第二板体的厚度可以约为0.8mm至1.2mm，电子器件层的厚度为1.5mm至2.5mm。例如，第二印刷电路板42的整体厚度可以约为3mm左右。
在示例性实施方式中，由于第二印刷电路板42为搭载驱动芯片的驱动 电路板，需要设置芯片类的电子器件，因而第二印刷电路板42可以采用多层板，多层板的层数可以约为8层至10层，即第二印刷电路板42可以采用8层板、9层板或者10层板结构。
在示例性实施方式中，第一柔性电路板31的厚度可以约为0.05mm至0.09mm左右。例如，第一柔性电路板31的厚度可以约为0.07mm左右。
在示例性实施方式中，在显示面板的F1位置，沿着第三方向D3(从下至上的方向)，显示面板可以包括固定胶带50、散热层22、背膜层21、显示基板10、偏光层11、粘结层12和保护层13。
在示例性实施方式中，以固定胶带50的厚度约为0.05mm、散热层的厚度约为0.2mm、背膜层的厚度约为0.05mm、显示基板10的厚度约为0.12mm、偏光层的厚度约为0.15mm、粘结层的厚度约为0.2mm为例，对于保护层采用盖板玻璃，F1位置的整体厚度约为1.37mm左右，对于保护层采用无色聚酰亚胺，F1位置的整体厚度约为0.83mm左右。
在示例性实施方式中，在显示面板的F2位置，沿着第三方向D3，显示面板可以包括固定胶带50、第一印刷电路板41、第一柔性电路板31、固定胶带50和保护层13。以固定胶带50的厚度约为0.05mm、第一柔性电路板31的厚度约为0.07mm、第一印刷电路板41的整体厚度约为0.5mm为例，对于保护层采用盖板玻璃，F2位置的整体厚度约为1.22mm左右，对于保护层采用无色聚酰亚胺，F2位置的整体厚度约为0.68左右。
在示例性实施方式中，在设置第二印刷电路板42所在位置的F3位置，第二印刷电路板42的整体厚度可以约为3.0mm左右。
本公开通过将印刷电路板拆分为走线电路板和驱动电路板的驱动分离设计，将走线电路板设置在显示基板的一侧，且走线电路板仅设置信号连接线，因而有效减小了显示面板的整体厚度，即使在显示面板最厚的F1位置，整体厚度仅为0.83mm至1.37mm。与整体厚度约为3.2mm至4.4mm的传统结构相比，本公开示例性实施例有效减小了显示面板的整体厚度，整体厚度仅为现有结构整体厚度的20％至30％，最大限度地实现了超薄结构。
图12为本公开示例性实施例一种芯片区的结构示意图。如图12所述， 沿着第二方向D2，芯片区210可以划分为第一芯片子区210A、第二芯片子区210B和第三芯片子区210C，第一芯片子区210A和第三芯片子区210C可以设置多条信号引线，第二芯片子区210B可以设置多个SDIC芯片20，多个SDIC芯片20被配置为接受来自T-con芯片的图像、视频、系统UI等数据，按照从Flash读取的Gamma和其它各类IP的补偿参数，产生对应的数据信号。在SDIC芯片20具有电压转换功能情况下，SDIC芯片20还可以产生各类GOA信号，比如Gate GOA、EM GOA、Reset GOA等。
在示例性实施方式中，第一芯片子区210A和第三芯片子区210C的多条信号引线可以包括FOP_Test引线、COP_Test引线、ELVSS引线、ELVDD引线、VGH引线、VGL引线、VINIT引线、EM_GOA引线、Gate_GOA引线、Reset_GOA引线、Test Point引线等。COP_Test引线被配置为检测COP绑定后的阻抗情况，FOP_Test引线被配置为检测柔性连接部(Flexibleon Panel，简称FOP)绑定后的阻抗情况，Test Point引线被配置为检测各类测试点。ELVDD引线、VINIT引线和ELVSS引线分别被配置为向显示区域中的多个像素驱动电路提供高电平电压、复位电压和低电平电压，VGH引线和VGL引线分别被配置为提供高电平电压和低电平电压，Gate_GOA引线、EM_GOA引线和Reset_GOA引线分别被配置为向显示区域提供行扫描信号、行发光控制信号和行复位信号。
在示例性实施方式中，第一芯片子区210A的多条信号引线与第三芯片子区210C的多条信号引线可以相对于第二芯片子区210B镜像对称。
在示例性实施方式中，第二芯片子区210B还可以设置多条输入信号线和多条输出信号线，多条输入信号线可以包括ISP1线至ISP4线、Gamma线、VRF_H线和VRF_L线等，多条输出信号线可以包括D1、D2、……、Dn。
在示例性实施方式中，ISP1线至ISP4线被配置为向SDIC芯片20输入图像数据，Gamma线被配置为向SDIC芯片20输入Gamma参考电压，VRF_H线被配置为向SDIC芯片20输入Gamma黑态电压，VRF_L线被配置为向SDIC芯片20输入Gamma白态电压。
在示例性实施方式中，对于分辨率3840*2400，第二芯片子区210B可以设置6个SDIC芯片20，6个SDIC芯片20的输出端通过1920条输出信号 线(D1、D2、……、D1920)和扇出(Fan-out)线与显示区域的数据信号线对应连接。
图13为本公开示例性实施例一种印刷电路板的等效电路示意图，示意了第一印刷电路板41和第二印刷电路板42的等效电路结构。如图13所示，第一印刷电路板41可以包括多条信号连接线，第二印刷电路板42可以包括时序控制(T-con)芯片、电源管理(PMIC)芯片、供电电源管理(ELIC)芯片、参考伽马(P-Gamma)芯片、存储器(Flash)、电平转换器(Level Shifter)、温度传感器(Temp Sensor)和连接接口等电子器件。
在示例性实施方式中，第一印刷电路板41上的多条信号连接线一方面与绑定区域200的多条信号引线和SDIC芯片的输入信号线连接，另一方面与第二印刷电路板42上的多个芯片对应连接。
在示例性实施方式中，连接接口可以采用显示接口(eDP)，eDP接口被配置为实现驱动电路板与主机之间的连接。eDP接口的协议可以采用eDP1.4b，可以包括4对(Lane)主通道(Main link)、1个辅助通道(AUX Chanel)、1个热拔插(HPD)通道、1个内建自测试(BIST)通道等。每对主通道可以为一对差分线，以传输高速、大容量的数据，数据可以包括图像、视频、系统UI等显示信息等。辅助通道可以传输低带宽需求的数据，以及通道管理和设备控制信号等，热拔插通道可以作为热插拔检测通道。第二印刷电路板42可以通过eDP接口与主机连接，eDP接口中传输数据信号的通道分别与T-con芯片和Flash 2连接，如与T-con芯片连接的4通道的Main link、1通道的AUX、1通道的HPD、1通道的BIST和1通道的I2C3，与Flash 2连接的串行外围设备接口(Serial Peripheral interface，简称SPI)。eDP接口中传输电源信号的通道分别与PMIC芯片、P-Gamma芯片、ELIC芯片和Level Shifter连接，如向PMIC芯片、P-Gamma芯片和Level Shifter供给3.3V输入(Vin)电压，向ELIC芯片输入6V至21V的电源(Vbat)电压，Vbat可以由主机的电池或者电源适配器产生。
在示例性实施方式中，电源管理(PMIC)芯片被配置为将主机输入的低电压转换为器件所需要的数字电压(VDD)、模拟电压(AVDD)和高低电压(VGH/VGL)等供给相应的芯片。PMIC芯片的输出至少包括：供给T-con 芯片、Flash和Temp Sensor的数字电压(VDD)，一般为1.1V和1.8V；供给Level Shifter的高电压(VGH)和低电压(VGL)；以及供给P-Gamma芯片和SDIC芯片的模拟电压(AVDD)，一般为6.5V至8V。
在示例性实施方式中，供电电源管理(ELIC)芯片被配置为将主机输入的可变交直流电压(电池或者笔记本电源适配转换器供电)转换为显示区域像素驱动电路和发光器件所需的电压。例如，ELIC芯片可以向显示区域的像素驱动电路输出ELVDD、ELVSS和VINIT等。
在示例性实施方式中，参考伽马(P-Gamma)芯片被配置为产生不同波段(Band)下的最大灰阶电压值，提供给SDIC芯片作为Gamma参考电压。P-Gamma芯片可以输出Gamma电压和参考(REF)电压。
在示例性实施方式中，电平转换器(Level Shifter)被配置为在不改变时域波形和相对位置关系、占空比的情况下，将信号电平值提升至目标值。例如，可以被配置为将各个GOA信号的驱动电平值提高。本公开通过在第二印刷电路板42上设置电平转换器，可以减少SDIC芯片的引脚数量，减少绑定区域和第一印刷电路板41上信号引线和信号连接线的数量。
在示例性实施方式中，Flash 1至Flash 3可以通过SPI与T-con芯片连接，在系统和显示面板开机后，Flash内部的各项数据就会被T-con芯片读取出来。
在示例性实施方式中，T-con芯片内部可以集成图形帧缓存器(Frame Buffer)、各类IP、可读写寄存器、电源转换、逻辑运算等功能模块，被配置为向每个SDIC芯片输出图像、视频、系统UI等数据信号。T-con芯片输出的图像、视频、系统UI等数据信号，分别通过PHI接口传输至多个SDIC芯片的输入端，T-con芯片输出的GOA时序控制信号(如Gate GOA、EM GOA和Reset GOA)，通过Level Shifter的电平转换后提供给位于第一印刷电路板41的信号连接线，经过绑定区域后沿着显示面板边框延伸，与显示区域的扫描信号线和发光控制线连接，控制显示区域多个像素行的像素驱动电路。
在示例性实施方式中，在SDIC芯片具有电压转换功能情况下，第二印刷电路板42上可以不用设置Level Shifter。T-con芯片输出的GOA时序控制信号可以直接输出至部分SDIC芯片(如SDIC1和SDIC 6)的输入端，进而 控制显示区域多个像素行的像素驱动电路。
在示例性实施方式中，显示装置(例如笔记本)可以包括主机和前述的显示面板，主机与显示面板可以通过转轴连接，主机可以至少包括主板、键盘、电池和后盖，第二柔性电路板32和第二印刷电路板42可以设置在主机的相应位置。例如，对于笔记本，第二印刷电路板42可以固定在主板上，或者可以设置在键盘与电池之间，连接第一印刷电路板41和第二印刷电路板42的第二柔性电路板32可以隐藏安装在笔记本转轴中，既不会影响显示面板的整体厚度，也不会影响到笔记本整体美观度。
本公开通过将印刷电路板拆分为走线电路板和驱动电路板的驱动分离设计，将容易发热的驱动电路板(第二印刷电路板)设置在显示面板以外的主机的相应位置，不仅有效避免了因驱动电路板发热造成显示面板显示偏色的不良，提高了显示品质，而且可以有效避免了因驱动电路板发热造成发光器件寿命下降的不良，提高了发光器件的寿命。
图14为本公开示例性实施例另一种显示面板的平面结构示意图，图15为图14所示显示面板的侧视图，图14示意了绑定区域弯折前的展开状态，图15示意了绑定区域弯折后的折叠状态。如图14和图15所示，在平行于显示面板的平面内，显示面板可以包括显示区域100、位于显示区域100第一方向D1一侧的绑定区域200以及位于显示区域100其它侧的边框区域300，绑定区域200可以包括沿着第一方向D1依次设置的弯折区201、芯片区210和引脚区220，弯折区201被配置为在第三方向D3弯曲，使得芯片区210和引脚区200可以在第三方向D3上与显示区域100重叠。多个SDIC芯片20分别绑定连接在芯片区210，多个第一柔性电路板31的第一端分别绑定连接在引脚区220，多个第一柔性电路板31的第二端均与第一印刷电路板41的第一端连接，第一印刷电路板41的第二端通过第二柔性电路板32与第二印刷电路板42连接。
在示例性实施方式中，SDIC芯片、第一柔性电路板、第一印刷电路板、第二柔性电路板和第二印刷电路板的连接方式和连接结构可以与前述示例性实施例基本上相同，这里不再赘述。
在示例性实施方式中，在垂直于显示面板的平面内，显示面板可以包括 显示基板10、设置在显示基板10上的偏光层11、设置在偏光层11远离显示基板一侧的粘结层12、设置在粘结层12远离显示基板一侧的保护层13、设置在显示基板10远离保护层13一侧的背膜层21、设置在背膜层21远离显示基板一侧的散热层22、设置在散热层22远离显示基板一侧的隔垫层23以及设置在隔垫层23远离显示基板一侧的背胶24。在示例性实施方式中，隔垫(Spacer)层23可以位于显示区域100和绑定区域200中靠近显示区域100的部分区域，背胶24可以位于显示区域100，其它膜层结构及其膜层的位置关系可以与前述示例性实施例基本上相同。
在示例性实施方式中，在弯折前，绑定区域200的多个引脚和多个焊盘可以设置在绑定区域200第三方向D3(上表面)一侧的表面上，在弯折后，多个引脚和多个焊盘位于绑定区域200第三方向D3的反方向(下表面)一侧的表面上，因而SDIC芯片20可以位于绑定区域200第三方向D3的反方向(下表面)的一侧，并与多个焊盘连接，第一柔性电路板31的第一端可以位于绑定区域200第三方向D3的反方向(下表面)的一侧，并与多个引脚连接。
第一柔性电路板31的第二端沿着第一方向D1的反方向(靠近显示区域的方向)延伸后，与第一印刷电路板41连接，即第一印刷电路板41位于显示区域100所在区域，不仅第一柔性电路板31和第一印刷电路板41在显示面板平面上的正投影位于显示基板10在显示面板平面上的正投影的范围之内，而且第一柔性电路板31和第一印刷电路板41在显示面板平面上的正投影位于显示区域100在显示面板平面上的正投影的范围之内。
在示例性实施方式中，第一印刷电路板41与第二柔性电路板32的第一端连接，第二柔性电路板32的第二端向着远离显示面板的方向延伸后，与位于显示面板以外区域的主机位置的第二印刷电路板42连接，不仅第二印刷电路板42在显示面板平面上的正投影与显示基板10在显示面板平面上的正投影没有交叠，而且第二印刷电路板42在显示面板平面上的正投影与保护层13在显示面板平面上的正投影没有交叠。
在示例性实施方式中，显示面板还可以包括固定胶带50，固定胶带50的第一端贴设在偏光层11外侧的显示基板10上，固定胶带50的第二端沿着 弯折方向延伸到显示基板10的背面，沿着第一方向D1的反方向延伸到第一印刷电路板41第一方向D1的反方向的一侧，通过背胶24贴设固定在隔垫层23上，固定胶带50一方面可以起到固定显示基板10和第一印刷电路板41的作用，另一方面可以起到保护SDIC芯片20、第一柔性电路板31和第一印刷电路板41的作用。
在示例性实施方式中，固定胶带50上可以设置开口或凹槽，开口或凹槽被配置为使第二柔性电路板32穿过以便与第二印刷电路板42连接。
在示例性实施方式中，隔垫层23的材料可以采用聚对苯二甲酸乙二酯(PET)，隔垫层23的厚度可以约为0.10mm至0.16mm。例如，隔垫层23的厚度可以约为0.13mm左右。
在示例性实施方式中，SDIC芯片20的厚度可以约为0.15mm至0.25mm左右。例如，SDIC芯片20的厚度可以约为0.2mm左右。
在示例性实施方式中，显示基板10、偏光层11、粘结层12、保护层13、散热层22、背膜层21和固定胶带50的材料和厚度可以与前述示例性实施例基本上相同，第一印刷电路板41和第二印刷电路板42的结构和厚度可以与前述示例性实施例基本上相同。
在示例性实施方式中，在显示面板的F1位置，沿着第三方向D3(从下至上的方向)，显示面板可以包括固定胶带50、第一印刷电路板41、第一柔性电路板31、背胶24、隔垫层23、散热层22、背膜层21、显示基板10、偏光层11、粘结层12和保护层13，保护层13可以是盖板玻璃(CG)，或者可以是无色聚酰亚胺(CPI)。
在示例性实施方式中，以粘结层的厚度约为0.2mm、偏光层的厚度约为0.15mm、显示基板10的厚度约为0.12mm、背膜层的厚度约为0.05mm、散热层的厚度可以约为0.2mm、隔垫层的厚度约为0.13mm、固定胶带50的厚度约为0.05mm、第一印刷电路板的总厚度约为0.5mm、第一柔性电路板的厚度约为0.07mm为例，对于保护层采用盖板玻璃，F1位置的整体厚度约为2.07mm，对于保护层采用无色聚酰亚胺，F1位置的整体厚度约为1.53mm。
在示例性实施方式中，在显示面板的F2位置，沿着第三方向D3，显示 面板可以包括固定胶带50、SDIC芯片20、显示基板10、背膜层21、隔垫层23、散热层22、背膜层21、显示基板10、偏光层11、粘结层12和保护层13。对于保护层采用盖板玻璃，F2位置的整体厚度约为1.87mm，对于保护层采用无色聚酰亚胺，F2位置的整体厚度约为1.33mm。
在示例性实施方式中，在设置第二印刷电路板42所在位置的F3位置，第二印刷电路板42的整体厚度可以约为3.0mm左右，第二印刷电路板42的结构和设置位置等可以与前述示例性实施例基本上相同。
本公开通过绑定区域弯折和驱动分离设计，将走线电路板设置在显示基板的的背面，走线电路板仅设置信号连接线，不仅有效减小了显示面板的整体厚度，而且有效减小了边框宽度。即使在显示面板最厚的F1位置，整体厚度仅为1.53mm至2.07mm，与整体厚度约为3.2mm至4.4mm的传统结构相比，本公开示例性实施例有效减小了显示面板的整体厚度，整体厚度仅为现有结构整体厚度的40％至50％，最大限度地实现了超薄结构。本公开通过绑定区域弯折，显示面板的边框宽度仅为3.1mm左右，与边框宽度约为8mm至10mm的传统结构相比，本公开示例性实施例有效减小了显示面板的边框宽度，边框宽度仅为现有结构边框宽度的30％至40％，提升屏占比约为3％左右，有利于实现全屏显示。
图16为本公开示例性实施例一种第二印刷电路板的结构示意图。如图16所示，第二印刷电路板可以包括第二板体和设置在第二板体上的电子器件层，电子器件层可以包括第一芯片区81、第二芯片区82、第三芯片区83、第一接口区84和第二接口区85，第一芯片区81、第二芯片区82和第三芯片区83间隔设置，相邻芯片区之间具有设定距离，第一接口区84和第二接口区85可以位于第二板体的边缘。
在示例性实施方式中，第一芯片区81被配置为设置T-con芯片及其外围电路(如电阻、电容、电感等)，第二芯片区82被配置为设置PMIC芯片及其外围电路，第三芯片区83被配置为设置ELIC芯片及其外围电路，第一接口区84被配置为设置第二连接器，以便与第二柔性电路板32，第二接口区85被配置为设置连接接口，以便与有线电视电缆或者第三柔性电路板连接。
在示例性实施方式中，第二印刷电路板42还可以包括多个固定孔91， 以提高固定可靠性。例如，多个固定孔91可以分别设置在第二印刷电路板42的角部，可以通过螺钉穿过固定孔91将第二印刷电路板42固定在主机的主板上，第二印刷电路板42上的电子器件层朝向主板的后盖。
在示例性实施方式中，考虑到主机的主板上通常设置有散热风扇，可以将第二印刷电路板42设置在靠近散热风扇的位置，以提高散热能力。
在示例性实施方式中，第二印刷电路板42还可以包括多个硅胶垫片92，以提高散热能力。例如，硅胶垫片92可以分别设置在第一芯片区81、第二芯片区82和第三芯片区83，硅胶垫片92的一侧表面可以贴附在芯片的上表面和外围元器件的表面上，硅胶垫片92的另一侧表面可以朝向主机的后盖，可以有效提高容易发热区域的散热量，提高芯片和外围元器件的工作可靠性。
在示例性实施方式中，第二印刷电路板42还可以设置多个温度传感器(Temp Sensor)93，温度传感器93被配置为采集温度，将温度信号转换为数字信号后通过I2C方式传输给T-con芯片。
在示例性实施方式中，一个温度传感器93可以设置在第二芯片区82内，与PMIC芯片邻近，另一个温度传感器93可以设置在第三芯片区83内，与ELIC芯片邻近。本公开通过将温度传感器设置在容易发热的PMIC芯片和ELIC芯片附近，可以准确测量PMIC芯片和ELIC芯片的温升，以便调整显示的策略。在一些可能的示例性实施方式中，温度传感器93可以设置在第一芯片区81内，与T-con芯片邻近。
在示例性实施方式中，T-con芯片中可以设置温度调整策略，以避免显示偏色甚至发光器件寿命下降等问题。例如，T-con芯片接收到温度传感器采集的温度后，可以判断温度是否大于预先设定的阈值，如果温度大于阈值，则执行预先设定的温度调整策略。在示例性实施方式中，温度调整策略可以包括如下任意一种或多种：降低刷新率，启动节能模式，限制显示灰阶，降低显示亮度。
本公开的驱动电路板采用模块化设计，在驱动电路板上设置相对分散的多个芯片区，将T-con芯片、PMIC芯片和ELIC芯片分别设置在不同的芯片区，不仅可以避免发热和温升过分集中，而且有利于散热。通过设置温度传 感器和硅胶垫片等结构，不仅可以有效控制驱动电路板的发热量，而且可以有效提高散热量。本公开通过将驱动电路板设置在主机，且通过分区设计、设置温度传感器、设置硅胶垫片以及靠近风扇等设计，可以有效控制驱动电路板的温度，降低因温升对芯片及其附属的元器件的工作效率的影响，提升电源的转换效率，可以进一步降低整体功耗，可以提升显示装置的整体外观和美感，显著提升了显示装置的竞争力。
本公开所示结构仅仅是一些示例性说明，驱动电路板的结构和设置位置可以根据实际需要进行变更，本公开在此不做限定。
本公开示例性实施例还提供了一种显示装置，显示装置包括前述的显示面板。
在示例性实施方式中，显示装置(例如笔记本)还可以包括主机，主机与显示面板可以通过转轴连接，主机可以至少包括主板、键盘、电池和后盖，第二印刷电路板可以固定在主板上，或者可以设置在键盘与电池之间，第二柔性电路板可以隐藏安装在笔记本转轴中。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (17)

  1. 一种显示面板，包括显示基板、第一印刷电路板和第二印刷电路板，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域通过第一柔性电路板与所述第一印刷电路板连接，所述第一印刷电路板通过第二柔性电路板与所述第二印刷电路板连接；所述第一印刷电路板为搭载信号连接线的走线电路板，所述第二印刷电路板为搭载驱动芯片的驱动电路板，所述第二印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影没有交叠。
  2. 根据权利要求1所述的显示面板，其中，所述第一印刷电路板上设置有第一连接器，所述第二柔性电路板通过所述第一连接器与所述第一印刷电路板连接。
  3. 根据权利要求1所述的显示面板，其中，所述第二印刷电路板上设置有第二连接器，所述第二柔性电路板通过所述第二连接器与所述第二印刷电路板连接。
  4. 根据权利要求1所述的显示面板，其中，所述第一印刷电路板为单层板或多层板，多层板的层数小于或等于3。
  5. 根据权利要求1所述的显示面板，其中，所述第一印刷电路板包括第一板体和设置在所述第一板体上的连接线层，所述第一板体的厚度为0.25mm至0.35mm，所述连接线层的厚度为0.15mm至0.25mm。
  6. 根据权利要求1所述的显示面板，其中，所述第二印刷电路板为多层板，多层板的层数为8至10。
  7. 根据权利要求1所述的显示面板，其中，所述第二印刷电路板包括第二板体和设置在所述第二板体上的电子器件层，所述第二板体的厚度为0.8mm至1.2mm，所述电子器件层的厚度为1.5mm至2.5mm。
  8. 根据权利要求7所述的显示面板，其中，所述电子器件层至少包括间隔设置的第一芯片区、第二芯片区和第三芯片区，所述第一芯片区被配置为设置时序控制芯片及其外围电路，所述第二芯片区被配置为设置电源管理芯片及其外围电路，所述第三芯片区被配置为设置供电电源管理芯片及其外 围电路。
  9. 根据权利要求8所述的显示面板，其中，所述第二印刷电路板还包括至少一个硅胶垫片，所述硅胶垫片贴附在所述时序控制芯片、电源管理芯片或者供电电源管理芯片的表面。
  10. 根据权利要求8所述的显示面板，其中，所述第二印刷电路板还包括至少一个温度传感器，所述温度传感器设置在所述第一芯片区内，与所述时序控制芯片邻近，和/或，所述温度传感器设置在所述第二芯片区内，与所述电源管理芯片邻近，和/或，所述温度传感器设置在所述第三芯片区内，与所述供电电源管理芯片邻近。
  11. 根据权利要求1至10任一项所述的显示面板，其中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的芯片区和引脚区，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区远离所述显示区域的一侧，并与所述引脚区的多个引脚绑定连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一印刷电路板设置在所述第一柔性电路板远离所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影与所述显示基板在显示面板平面上的正投影没有交叠。
  13. 根据权利要求1至10任一项所述的显示面板，其中，所述绑定区域包括沿着远离所述显示区域的方向依次设置的弯折区、芯片区和引脚区，所述弯折区被配置为通过弯折使所述芯片区和引脚区翻转到所述显示区域的背面，所述引脚区包括多个引脚，所述第一柔性电路板设置在所述引脚区靠近所述显示区域的一侧，并与所述引脚区的多个引脚绑定连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一印刷电路板设置在所述第一柔性电路板靠近所述显示区域的一侧，所述第一印刷电路板在显示面板平面上的正投影与所述显示区域在显示面板平面上的正投影至少部分交叠。
  15. 一种显示装置，包括如权利要求1至14任一项所述的显示面板。
  16. 根据权利要求15所述的显示装置，其中，所述显示装置还包括主 机，所述主机与所述显示面板通过转轴连接，所述第二柔性电路板设置在所述转轴中。
  17. 根据权利要求16所述的显示装置，其中，所述主机包括主板、键盘和电池，所述第二印刷电路板固定在所述主板上，或者，所述第二印刷电路板设置在所述键盘与所述电池之间。
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