WO2022120576A1 - 显示基板及显示面板 - Google Patents

显示基板及显示面板 Download PDF

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Publication number
WO2022120576A1
WO2022120576A1 PCT/CN2020/134554 CN2020134554W WO2022120576A1 WO 2022120576 A1 WO2022120576 A1 WO 2022120576A1 CN 2020134554 W CN2020134554 W CN 2020134554W WO 2022120576 A1 WO2022120576 A1 WO 2022120576A1
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WIPO (PCT)
Prior art keywords
sub
light
circuit
display area
pixel driving
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Application number
PCT/CN2020/134554
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English (en)
French (fr)
Inventor
黄耀
周洋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/134554 priority Critical patent/WO2022120576A1/zh
Priority to CN202080003247.2A priority patent/CN114916242A/zh
Priority to US17/615,552 priority patent/US20220366848A1/en
Publication of WO2022120576A1 publication Critical patent/WO2022120576A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a display substrate and a display panel.
  • organic electroluminescence display Organic Electroluminance Display, referred to as: OLED
  • OLED Organic Electroluminance Display
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a display panel.
  • embodiments of the present disclosure provide a display substrate having a display area and a peripheral area surrounding the display area; the display area includes a first sub-display area and a second sub-display area; wherein the display substrate includes : a substrate, a driving circuit layer and a plurality of light-emitting devices arranged on the substrate;
  • the plurality of light-emitting devices are located in the first sub-display area and the second sub-display area;
  • the driving circuit layer includes a plurality of pixel driving circuits, a gate driving circuit and a light-emitting control signal generating circuit;
  • the plurality of pixel driving circuits The circuit is located in the first sub-display area and the peripheral area;
  • the gate driving circuit and the light-emitting control circuit are located in the peripheral area;
  • the first electrode of one of the light-emitting devices is electrically connected to one of the pixel driving circuits; the gate driving circuit is configured to provide a scan signal to each of the pixel driving circuits; the light emission control circuit is configured to provide each of the pixel driving circuits The pixel drive circuit provides a light-emitting control signal;
  • the plurality of pixel driving circuits include a first pixel driving circuit for providing driving signals for light-emitting devices in the first sub-display area, and a first pixel driving circuit for providing driving signals for light-emitting devices in the second sub-display area.
  • the light-emitting control circuit includes a first sub-light-emitting control circuit and a second sub-light-emitting control circuit that are disconnected; the first sub-light-emitting control circuit is configured to provide a light-emitting control signal to each of the first pixel driving circuits; the The second sub-emission control circuit is configured to provide an emission control signal to each of the second pixel drive circuits.
  • the plurality of pixel driving circuits include redundant pixel driving circuits located in the peripheral area; the light emission control circuit includes redundant light emission control circuits; the redundant pixel driving circuits are used as the second pixel driving circuits ; The redundant lighting control circuit is used as the second sub lighting control circuit.
  • the display area has a first side and a second side oppositely arranged along the first direction, and a third side and a fourth side arranged oppositely along the second direction;
  • the second sub-display area is located in the display area the third side;
  • the second pixel driving circuit is located in the peripheral area and is close to the third side of the display area.
  • a plurality of the second pixel driving circuits form a plurality of second pixel driving circuit groups arranged side by side along the second direction; each second pixel driving circuit in each of the second pixel driving circuit groups The first directions are arranged side by side; each of the second pixel driving circuits in the same second pixel driving circuit group is connected to the same redundant scanning line and the same redundant light-emitting control line;
  • any of the redundant scan lines and any of the redundant light-emitting control lines include oppositely arranged first ends and second ends; the first and second ends of the redundant scan lines are respectively connected with the A gate driving circuit; the first end and the second end of the redundant light-emitting control line are respectively connected with the second sub-light-emitting control circuit.
  • the second light-emitting driving circuit connected to the first end of the redundant light-emitting control line is located at the connecting corner of the peripheral area close to the first side and the third side of the display area; connecting the redundant light-emitting control line
  • the second sub-light-emitting control circuit at the second end of the light-emitting control line is located at the connecting corner of the peripheral area close to the second side and the fourth side of the display area.
  • the gate driving circuit includes a first sub-gate driving circuit and a second sub-gate driving circuit which are disconnected; the first sub-gate driving circuit is configured to drive each of the first pixel driving circuits A scan signal is provided; the second sub-gate drive circuit is configured to provide a scan signal to each of the second pixel drive circuits.
  • the gate driving circuit includes a redundant gate driving circuit, and the redundant gate driving circuit is used as the second sub-gate driving circuit.
  • the plurality of pixel driving circuits are arranged side by side along the second direction to form a plurality of pixel driving circuit groups; the pixel driving circuits in the pixel driving circuit group are arranged side by side along the first direction;
  • Each pixel drive circuit located in the same pixel drive circuit group is connected to the same scan line and the same light emitting control line; any one of the scan lines and any one of the light emitting control lines includes first ends and the second end; and the scan line driving circuit is connected to the first end and the second end of each of the scan lines, and the light emission control circuit is connected to the first end and the second end of each of the light emission control lines. Control circuit.
  • the display area further includes a third sub-display area located between the second sub-display area and the second sub-display area;
  • the second sub-pixel driving circuit is located in the third sub-display area.
  • the second light-emitting control circuit is connected with the first electrode of the light-emitting device through a signal connection line; the signal connection line is a transparent wire.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned display substrate.
  • an external control circuit is also included; the external control circuit is bound and connected to the display substrate, and the external control circuit is configured to independently control the first sub-light-emitting control circuit and the second sub-light-emitting control circuit control.
  • FIG. 1 is a schematic diagram of an exemplary display substrate.
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit.
  • FIG. 3 is a schematic diagram of an exemplary lighting control circuit.
  • FIG. 4 is a schematic circuit diagram of an exemplary first shift register.
  • FIG. 5 is a schematic diagram of an exemplary gate driving circuit.
  • FIG. 6 is a schematic circuit diagram of an exemplary second shift register.
  • FIG. 7 is a schematic diagram of a display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of another display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of still another display substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the first direction and the second direction represent two different directions, for example, the first direction is the row direction, and the second direction is the column direction.
  • the first direction is the row direction and the second direction is the column direction.
  • the first direction and the second direction are two different The directions are all within the scope of the present disclosure.
  • FIG. 1 is a schematic diagram of an exemplary display substrate; as shown in FIG. 1 , the display substrate has a display area Q1 and a peripheral area Q2 surrounding the display area Q1. Wherein, the display area Q1 is divided into a first sub-display area Q11, a second sub-display area Q12 and a third sub-display area Q13; wherein, the display substrate includes a base, and a plurality of pixel units, gate driving Circuit 30 , lighting control circuit 20 .
  • a plurality of pixel units are arranged in the display area Q1 of the display substrate and are arranged in an array; wherein, each pixel unit located in the first sub-display area Q11 includes a pixel driving circuit 10 and is electrically connected to the pixel driving circuit 10 of light-emitting devices.
  • the second sub-display area Q12 is used to place hardware such as photosensitive sensors (eg, cameras), and only light-emitting devices are provided in the pixel units, and the light-emitting devices are transparent light-emitting devices to avoid affecting the operation of the photosensitive sensors.
  • Some of the pixel units in the third sub-display area Q13 include the pixel driving circuit 10 and the light-emitting device electrically connected to the pixel driving circuit 10, while the other part of the pixel units are only provided with the pixel driving circuit 10, and these pixel driving circuits 10 are connected with the first pixel driving circuit 10.
  • the light-emitting devices in the two sub-display regions Q12 are connected in a one-to-one correspondence to provide driving signals for the light-emitting devices in the second sub-display region Q12.
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit; as shown in FIG. 2, the pixel driving circuit 10 may include: a first reset sub-circuit 1, a threshold compensation sub-circuit 2, a data writing sub-circuit 4, a driver sub-circuit Circuit 3 , first lighting control sub-circuit 5 , second lighting control sub-circuit 6 , second reset sub-circuit 7 , storage sub-circuit 8 .
  • the first light-emitting control sub-circuit 5 is connected to the first voltage terminal VDD and the first terminal of the driving sub-circuit 3 respectively, and is configured to realize the connection between the driving sub-circuit 3 and the first voltage terminal VDD is turned on or disconnected
  • the second light-emitting control sub-circuit 6 is electrically connected to the second end of the driving sub-circuit and the first electrode of the light-emitting device D respectively, and is configured to realize the connection between the driving sub-circuit 3 and the light-emitting device D is turned on or disconnect.
  • the data writing sub-circuit 4 is electrically connected to the first end of the driving sub-circuit 3, and is configured to write the data signal into the storage sub-circuit 8 under the control of the scanning signal.
  • the storage sub-circuit 8 is respectively electrically connected to the control terminal of the driving sub-circuit 3 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation sub-circuit 2 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 3 respectively, and is configured to perform threshold compensation on the driving sub-circuit 3 .
  • the control terminals of the first reset sub-circuit 1 and the driving sub-circuit 3 are configured to reset the control terminal of the driving sub-circuit 3 under the control of the reset control signal.
  • the second reset sub-circuit 7 is electrically connected to the first electrode D1 of the light emitting device D, and is configured to reset the first electrode of the light emitting device D under the control of the scan signal.
  • the driving sub-circuit 3 includes a driving transistor T3
  • the data writing sub-circuit 4 includes a data writing transistor T4
  • the threshold compensation sub-circuit 2 includes a threshold compensation transistor T2
  • the first light-emitting control sub-circuit 2 includes a threshold compensation transistor T2.
  • the circuit 5 includes a first light-emitting control transistor T5, the second light-emitting control sub-circuit 6 includes a second light-emitting control transistor T6, the first reset sub-circuit 1 includes a first reset transistor T1, and the second reset sub-circuit 7 includes a second reset transistor T7 .
  • transistors can be classified into N-type transistors and P-type transistors according to their characteristics. ) as an example to illustrate the technical solution of the present disclosure in detail, that is, in the description of the present disclosure, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, the second reset transistor T7, etc. can all be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors.
  • N-type transistors eg, N-type MOS transistors
  • P-type transistors and N-type transistors e.g., P-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control electrode is used as the gate of the transistor, one of the first electrode and the second electrode is used as the source electrode of the transistor, and the other is used as the transistor.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • the first electrode is directly described as the source electrode and the second electrode as the drain electrode, so all or part of the source electrodes of the transistors in the embodiments of the present disclosure are directly described. and drain are interchangeable as required.
  • the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data line Data to receive a data signal, and the data writing transistor T4
  • the gate of the storage capacitor Cst is configured to be electrically connected to the scan line Gate to receive the scan signal; the first plate of the storage capacitor Cst is electrically connected to the first power supply voltage terminal VDD, and the second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3 Electrically connected;
  • the source of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured to be connected to the scan line
  • the gate is electrically connected to receive the compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the initialization signal terminal Vinit to receive the initialization signal, the drain of the
  • one of the first power supply voltage terminal VDD and the second power supply voltage terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply voltage terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply voltage terminal VSS can be a voltage source to output a constant voltage
  • the second voltage, the second voltage is a negative voltage, etc.
  • the second supply voltage terminal VSS may be grounded.
  • the control sub-circuit 6 and the storage sub-circuit 7 are only schematic, the reset sub-circuit 1, the threshold compensation sub-circuit 2, the data writing sub-circuit 4, the driving sub-circuit 3, the first lighting control sub-circuit 5, the second lighting control
  • the specific structures of the sub-circuits such as the sub-circuit 6 and the storage sub-circuit 7 can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • the light-emitting device D may be a micro inorganic light-emitting diode, and further, may be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED).
  • the light-emitting device D in the embodiment of the invention may also be an organic electroluminescent diode (Organic Light Emitting Diode, OLED).
  • One of the first electrode and the second electrode of the light-emitting device D is an anode, and the other is a cathode; in the embodiment of the present invention, the first electrode of the light-emitting device D is an anode and the second electrode is a cathode as an example for description .
  • the pixel driving circuits 10 in each pixel unit in the same row are provided with scan signals by the same gate line, and provided with light emission control signals by the same light emission control line. Opposing first and second ends are included for any gate line and any light emitting control line.
  • the gate drive circuit 30 and the light emission control circuit 20 in the display substrate are located in the peripheral area Q2, and the gate drive circuit 30 is connected to the first end and the second end of each gate line, and the first end of each light emission control line is connected to the gate drive circuit 30.
  • the light-emitting control circuit 20 is connected to the second end. Both the gate driving circuit 30 and the light-emitting control circuit 20 are located in the peripheral region Q2, wherein FIG.
  • FIG. 3 is a schematic diagram of an exemplary light-emitting control circuit 20; as shown in FIG. 3, the light-emitting control circuit 20 includes a plurality of cascaded The first shift register A, the first shift register A in the lighting control circuit 20 is connected to the lighting control line in a one-to-one correspondence for providing lighting control signals, and the first signal of the first shift register A of this stage The output terminal is connected to the first signal input terminal of the first shift register A of the next stage; in addition, the first signal input terminal INPUT1 of the first shift register A-1 is connected to the first frame start signal STV1.
  • FIG. 5 is a schematic diagram of an exemplary gate driving circuit 30 . As shown in FIG.
  • the gate driving circuit 30 includes a plurality of cascaded second shift registers G. As shown in FIG.
  • the second shift register G in the gate driving circuit 30 is connected to the gate lines in a one-to-one correspondence for providing scanning signals, and the second signal output end of the second shift register G of this stage is connected to the second shift register of the next stage
  • the second signal input terminal of the register G; in addition, the second signal input terminal INPUT2 of the second shift register G-1 is connected to the first frame start signal STV2.
  • FIG. 4 is a schematic circuit diagram of an exemplary first shift register A; as shown in FIG. 4 , the first shift register A includes: a signal writing circuit 101 , a first control circuit 102 , and a second control circuit 103 And the signal output circuit 104; the signal writing circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 are all connected to the first node N1, both the first control circuit 102 and the second control circuit 103 Connected to the second node N2, both the second control circuit 103 and the signal output circuit 104 are connected to the third node N3.
  • the signal writing circuit 101 is connected to the corresponding first signal input terminal INPUT and the first clock signal terminal CK, and is configured to respond to the control of the first clock signal provided by the first clock signal terminal CK, to write the corresponding first signal
  • the signal provided by the input terminal INPUT1 is written to the first node N1.
  • the first control circuit 102 is connected to the first power supply terminal VGH and the first clock signal terminal CK, and is configured to write the first operating voltage provided by the first power supply terminal VGH to the second node N2 in response to the control of the first clock signal , and the first clock signal is written to the second node N2 in response to the control of the voltage at the first node N1.
  • the second control circuit 103 is connected to the second power supply terminal VGL and the second clock signal terminal CKB, and is configured to respond to the control of the voltage at the second node N2 and the second clock signal provided by the second clock signal terminal CKB,
  • the clock signal is written to the third node N3, and in response to the control of the voltage at the first node N1, the second operating voltage provided by the second power supply terminal VGL is written to the third node N3.
  • the signal output circuit 104 is connected to the first power supply terminal VGH and the second power supply terminal VGL, and is configured to write the first operating voltage to the first signal output terminal OUT1 in response to the control of the voltage at the first node N1, and to respond to the third power supply terminal OUT1.
  • the control of the voltage at the node N3 writes the second operating voltage to the first signal output terminal OUT1.
  • the noise reduction circuit 105 is connected to the first node N1, the second node N2, the second power supply terminal VGL, and the second clock signal terminal CKB, and is configured to respond to the control of the second clock signal and the voltage at the second node N2, to the first node N2.
  • the voltage at node N1 is subjected to noise reduction processing.
  • the signal writing circuit 101 includes: a first transistor M1, the first control circuit 102 includes: a second transistor M2 and a third transistor M3, and the second control circuit 103 includes: a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6 and the first capacitor C1, the signal output circuit 104 includes a seventh transistor M7, an eighth transistor M8 and a second capacitor C2, and the noise reduction circuit 105 includes a ninth transistor M9, a tenth transistor M10 and a third capacitor C3.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor The transistors M10 are described by taking an N-type thin film transistor as an example.
  • the gate of the first transistor M1 is connected to the first clock signal terminal CK, the source of the first transistor M1 is connected to the first signal input terminal INPUT1, and the drain of the first transistor M1 is connected to the first node N1.
  • the gate of the second transistor M2 is connected to the first node N1, the source of the second transistor M2 is connected to the first clock signal terminal CK, and the drain of the second transistor M2 is connected to the second node N2.
  • the gate of the third transistor M3 is connected to the first clock signal terminal CK, the source of the third transistor M3 is connected to the first power supply terminal VGH, and the drain of the third transistor M3 is connected to the second node N2.
  • the gate of the fourth transistor M4 is connected to the second node N2, the source of the fourth transistor M4 is connected to the second clock signal terminal CKB, and the drain of the fourth transistor M4 is connected to the source of the fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the second clock signal terminal CKB, and the drain of the fifth transistor M5 is connected to the third node N3.
  • the gate of the sixth transistor M6 is connected to the first node N1, the source of the sixth transistor M6 is connected to the second power supply terminal VGL, and the drain of the sixth transistor M6 is connected to the third node N3.
  • the first plate of the first capacitor C1 is connected to the second node N2, and the second plate of the first capacitor C1 is connected to the drain of the fourth transistor M4.
  • the gate of the seventh transistor M7 is connected to the third node N3, the source of the seventh transistor M7 is connected to the second power supply terminal VGL, and the drain of the seventh transistor M7 is connected to the first signal output terminal OUT1.
  • the gate of the eighth transistor M8 is connected to the first node N1, the source of the eighth transistor M8 is connected to the first power supply terminal VGH, and the drain of the eighth transistor M8 is connected to the first signal output terminal OUT1.
  • the first plate of the second capacitor C2 is connected to the third node, and the second plate of the second capacitor C2 is connected to the first power supply terminal VGH.
  • FIG. 6 is a schematic circuit diagram of an exemplary second shift register G; as shown in FIG. 6 , the shift register includes: a first input sub-circuit 11 , a first pull-down control sub-circuit 12 , and a first output sub-circuit circuit 13 and first pull-down subcircuit 14 .
  • the first input sub-circuit 11 is connected to the second signal input terminal IPUT2, the pull-up node PU and the third clock signal terminal CLK', and the first input sub-circuit 11 is configured to respond to the control of the third clock signal terminal CLK'
  • the input signal provided by the two signal input terminals IPUT2 is written to the pull-up node PU.
  • the first pull-down control sub-circuit 12 is connected to the second power supply terminal VGL, the pull-up node PU, the pull-down node PD and the third clock signal terminal CLK', and the first pull-down control sub-circuit 12 is configured to respond to the third clock signal terminal
  • the control of CLK' writes the first working voltage provided by the second power supply terminal VGL to the pull-down node PD
  • the first clock signal provided by the third clock signal terminal CLK' is written in response to the control of the voltage at the pull-up node PU to the drop-down node PD.
  • the first output sub-circuit 13 is connected to the first power supply terminal VGH, the pull-up node PU, the pull-down node PD, the second signal output terminal OUT2, and the fourth clock signal terminal CLKB', and the first output sub-circuit 13 is configured to respond to the pull-up
  • the control of the voltage at the node PU writes the second clock signal provided by the fourth clock signal terminal CLKB' to the second signal output terminal OUT2, and responds to the control of the pull-down node PD to write the second operating voltage provided by the first power supply terminal VGH Write to the second signal output terminal OUT2.
  • the first pull-down sub-circuit 14 is connected to the first power supply terminal VGH, the pull-up node PU, the pull-down node PD, and the fourth clock signal terminal CLKB', and the first pull-down sub-circuit 14 is configured to respond to the voltage at the pull-down node PD and the fourth The control of the clock signal terminal CLKB' writes the second working voltage to the pull-up node PU.
  • the first input sub-circuit 11 includes an eleventh transistor T11
  • the first pull-down control sub-circuit 12 includes a twelfth transistor T12 and a thirteenth transistor T13
  • the first output sub-circuit 13 includes a fourteenth transistor T14
  • the first pull-down sub-circuit 14 includes a sixteenth transistor T16 and a seventeenth transistor T17.
  • the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are all Take the P-type thin film transistor as an example.
  • the gate of the eleventh transistor T11 is connected to the third clock signal terminal CLK', the source of the eleventh transistor T11 is connected to the second signal input terminal IPUT2, and the drain of the eleventh transistor T11 is connected to the pull-up node PU connect.
  • the gate of the twelfth transistor T12 is connected to the pull-up node PU, the source of the twelfth transistor T12 is connected to the third clock signal terminal CLK', and the drain of the twelfth transistor T12 is connected to the pull-down node PD.
  • the gate of the thirteenth transistor T13 is connected to the third clock signal terminal CLK', the source of the thirteenth transistor T13 is connected to the second power supply terminal VGL, and the drain of the thirteenth transistor T13 is connected to the pull-down node PD.
  • the gate of the fourteenth transistor T14 is connected to the pull-down node PD, the source of the fourteenth transistor T14 is connected to the first power supply terminal VGH, and the drain of the fourteenth transistor T14 is connected to the second signal output terminal OUT2.
  • the gate of the fifteenth transistor T15 is connected to the pull-up node PU, the source of the fifteenth transistor T15 is connected to the fourth clock signal terminal CLKB', and the drain of the fifteenth transistor T15 is connected to the second signal output terminal OUT2.
  • the gate of the sixteenth transistor T16 is connected to the pull-down node PD, the source of the sixteenth transistor T16 is connected to the first power supply terminal VGH, and the drain of the sixteenth transistor T16 is connected to the source of the seventeenth transistor T17.
  • the gate of the seventeenth transistor T17 is connected to the fourth clock signal terminal CLKB', and the drain of the seventeenth transistor T17 is connected to the pull-up node PU.
  • the gate of the eighteenth transistor T18 is connected to the second power supply terminal VGL, the source of the eighteenth transistor T18 is connected to the pull-up node PU, and the drain of the eighteenth transistor T18 is connected to the gate of the fifteenth transistor T15.
  • the first plate of the fourth capacitor C4 is connected to the gate of the fifteenth transistor T15, and the second plate of the fourth capacitor C4 is connected to the second signal output terminal OUT2.
  • the first plate of the fifth capacitor C5 is connected to the pull-down node PD, and the second plate of the fifth capacitor C5 is connected to the source of the fourteenth transistor T14.
  • a shift register is in a cascaded relationship, so that even when the photosensitive sensor in the second sub-display area needs to work, the light-emitting device in it will be lit, which will interfere with the work of the photosensitive sensor.
  • FIG. 7 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate having a display area Q1 and a peripheral area Q2 surrounding the display area Q1;
  • the display area Q1 includes a first sub-display area Q11 and a second sub-display area Q12.
  • the display substrate includes a driving circuit layer and a plurality of light-emitting devices;
  • the driving circuit layer includes a plurality of pixel driving circuits, a gate driving circuit 30 and a light-emitting control circuit.
  • a pixel driving circuit is connected to the first electrode of a light-emitting device, and is used for providing driving current for the light-emitting device.
  • the gate driving circuit 30 is used for providing scanning signals for each pixel driving circuit, and the light emission control circuit is used for providing light emission control signals for each pixel driving circuit.
  • the first sub-display area Q11 is provided with not only light emitting devices, but also a pixel driving circuit for driving the light emitting devices.
  • the second sub-display area Q12 is used to place hardware such as photosensitive sensors (eg, cameras), so only light-emitting devices are arranged in the second sub-display area Q12, and the light-emitting devices in this area are transparent light-emitting devices to prevent the photosensitive sensors from being damaged. interfere with work.
  • the pixel driving circuit for driving the light emitting devices in the second sub-display area Q12 may be provided in the first sub-display area Q11 or in the peripheral area Q2.
  • the pixel driving circuit for driving the light-emitting device in the first sub-display area Q11 will be referred to as the first pixel driving circuit 11
  • the pixel driving circuit for driving the light-emitting device in the second sub-display area Q12 will be described.
  • the circuit is referred to as the second pixel driving circuit 12 .
  • the light-emitting control circuit includes a first sub-light-emitting control circuit 21 and a second sub-light-emitting control circuit 22 that are disconnected, wherein the first sub-light-emitting control circuit 21 is configured to drive the circuit to each of the first pixels 11 provides a light emission control signal, and the second sub-light emission control sub-circuit is configured to provide the light emission control signal to each of the second sub-pixel drive circuits.
  • both the first sub-light-emitting control circuit 21 and the second sub-light-emitting control circuit 22 may include a plurality of cascaded first shift registers, and the first shift register may be the first shift register shown in FIG. 4 .
  • the circuit structure of the bit register For example, a first shift register in the first sub-light-emitting control circuit 21 provides a light-emitting control signal for the first pixel driving circuit 11 of a row; a first shift register in the second sub-light-emitting control circuit 22 is a second pixel in a row
  • the driving circuit 12 provides the lighting control signal.
  • the first sub-emission control circuit 21 and the second sub-emission control circuit 22 which are set to be disconnected include the disconnection of the light-emission control circuit, and the first sub-emission control circuit 21 sends the signal to the first pixel driving circuit 11 .
  • the second sub-light-emitting control circuit 22 provides the light-emitting control signal to the second pixel driving circuit 12; that is, the first pixel driving circuit 11 is controlled by the first sub-light-emitting control circuit 21, and the second pixel circuit is controlled by the second pixel driving circuit 12.
  • the sub-light-emitting circuit is controlled, therefore, when the photosensitive sensor in the second sub-display area Q12 needs to work, the second sub-light-emitting control circuit 22 can be controlled to output a non-operating level, so that the fifth transistor in the second pixel driving circuit 12 and the sixth transistor are turned off, and the driving current cannot be output to the light-emitting devices in the second sub-display area Q12. At this time, the light-emitting devices in the second sub-display area Q12 do not emit light, so the operation of the photosensitive sensor will not be disturbed.
  • the display substrate is not only provided with a pixel driving circuit in the display area Q1, but also can be provided with a pixel driving circuit in the peripheral area Q2, in order to distinguish whether the pixel driving circuit is located in the pixel driving circuit in the display area Q1 or in the peripheral area
  • the pixel driving circuit of Q2 in the embodiment of the present disclosure, the pixel driving circuit located in the peripheral region Q2 is called a redundant pixel driving circuit. It should be understood that the structure of the redundant pixel driving circuit may be the same as that of the pixel driving circuit located in the display area Q1, for example, the pixel driving circuit of 7T1C shown in FIG. 2 is used.
  • the light emission control driving circuit in the display substrate not only includes the cascaded first shift registers, but also includes a plurality of redundant first shift registers with the same structure as the first shift registers.
  • a plurality of redundant first shift registers are cascaded to form a redundant lighting control driving circuit.
  • the redundant pixel driving circuit is used as the second pixel driving circuit 12 to provide driving current for the light-emitting devices located in the second sub-display area Q12; at the same time, the redundant light-emitting control circuit can be used as the
  • the second sub-light-emitting control circuit 22 is used to provide a light-emitting control signal for the redundant pixel driving circuit.
  • the light-emitting devices located in the second sub-display area Q12 are driven by the redundant pixel driving circuit, so that the light-emitting devices in the display area Q1 can be uniformly arranged, especially in the second sub-display area Q12.
  • each pixel driving circuit can be connected to a light-emitting device in a one-to-one correspondence, so that the display panel using the display substrate of the embodiment of the present disclosure is more uniform in display.
  • the display area Q1 of the display substrate includes a first side (left side) and a second side (right side) oppositely arranged along the row direction, and a The third side (upper side) and the fourth side (lower side) are oppositely arranged in the column direction; the second sub-display area Q12 is located on the third side of the display area Q1, and is located at the position of the peripheral area Q2 close to the third side of the display area Q1
  • the redundant pixel driving circuit 12 is used as the second pixel circuit, so that it is convenient for the second pixel driving circuit 12 to be electrically connected with the light emitting devices in the second sub-display area Q12.
  • the second pixel driving circuit 12 is electrically connected to the light emitting device in the second display area Q1 through a signal connection line 40, and the signal connection line 40 may be a transparent wire (eg, indium tin oxide/ITO).
  • the second pixel driving circuits 12 form a plurality of second pixel driving circuit groups 12 arranged side by side in the column direction, and the second pixel driving circuits 12 in each second pixel driving circuit 12 group are arranged side by side in the row direction. Since the redundant pixel driving circuit is used as the second pixel driving circuit 12, each second pixel driving circuit 12 in the same second pixel driving circuit 12 group is connected to the same redundant scanning line and the same redundant light-emitting control line .
  • the redundant scan line and the redundant light emission control line both have oppositely arranged first ends and second ends, and both the first and second ends of the redundant scan lines are connected to the gate drive circuit 30; the redundant light emission Both the first end and the second end of the control wire are connected with a second sub-light-emitting control circuit 22 (redundant light-emitting control circuit).
  • the first end and the second end of a redundant light-emitting control line are respectively connected with a first shift register, and the first end and the second end of a redundant scan line are respectively connected with a second shift register. register.
  • the redundant lighting control circuit (second lighting driving circuit) connecting the first end of the redundant lighting control line is located in the The peripheral area Q2 is close to the connecting corner (upper left corner) of the first side and the third side of the display area Q1; the redundant lighting control circuit (second lighting driving circuit) connected to the second end of the redundant lighting control line is located in the peripheral area Q2 Near the connecting corner (upper right corner) of the second side and the fourth side of the display area Q1.
  • the reason for this arrangement is to facilitate the connection of the redundant light-emitting control circuit and the redundant pixel driving circuit.
  • FIG. 8 is a schematic diagram of another display substrate according to an embodiment of the disclosure.
  • the light-emitting control circuit in the display substrate includes the first sub-light-emitting control circuit 21 and the first sub-light-emitting control circuit 21 and the Two sub-light-emitting control circuits 22, and the gate driving circuit 30 includes a first sub-gate driving circuit 31 and a second sub-gate driving circuit 32 that are disconnected; the first sub-gate driving circuit 31 is configured to The first pixel driving circuit 11 provides scanning signals; the second sub-gate driving circuits 32 are configured to provide scanning signals to each of the second pixel driving circuits 12 .
  • the first sub-pixel driving circuit and the second pixel driving circuit 12 respectively use the first sub-gate driving circuit and the second sub-gate driving circuit 32 to provide gate driving signals. Therefore, in the second sub-display area When the photosensitive sensor in Q12 is working, the second sub-gate driving circuit 32 can be controlled to stop working, so that the power consumption of the display substrate can be reduced.
  • both the first sub-gate driving circuit 31 and the second sub-gate driving circuit 32 include cascaded second shift registers. All of the second shift registers may adopt the structure shown in FIG. 6 .
  • a second shift register in the first sub-gate driving circuit 31 provides scan signals for the first pixel driving circuit 11 in a row
  • a second shift register in the second sub-gate driving circuit 32 is a second shift register in a row
  • the pixel driving circuit 12 provides scan signals.
  • the gate driving circuit 30 in the peripheral area Q2 not only includes a second shift register for providing scan signals for the pixel driving circuit in the display area Q1, but also includes a second shift register with the same structure as the second shift register.
  • a redundant second shift register, and the redundant second shift registers are cascaded to form a redundant gate driving circuit 30.
  • the redundant gate driving circuit 30 can be used as a second sub-gate drive circuit 32 .
  • the redundant pixel driving circuit is used as the second pixel driving circuit 12, and the redundant gate driving circuit is connected to the first end and the second end of the redundant scanning line at this time.
  • the redundant gate drive circuit 30 connected to the first end of the redundant scan line may be located in the peripheral area Q2 near the upper left corner of the display area Q1, and connected to the redundant scan line
  • the redundant gate driving circuit 30 at the second end of the line may be located in the peripheral region Q2 near the upper right corner of the display region Q1, so that the connection between the redundant gate driving circuit 30 and the redundant pixel driving circuit is facilitated.
  • the first end and the second end of a redundant scan line are respectively connected to a redundant shift register.
  • the pixel driving circuits in the display substrate are arranged side by side in the column direction to form a plurality of pixel driving circuit groups; the pixel driving circuits in each pixel driving circuit group are arranged side by side in the row direction.
  • the pixel driving circuits located in the same row are connected to the same scan line and the same light-emitting control line; each scan line and light-emitting control line include oppositely arranged first and second ends, and the first end and the second end of each scan line
  • the gate driving circuit 30 is connected to the terminal and the second terminal, and the lighting control circuit is connected to the first terminal and the second terminal of each light-emitting control line. , which can improve the charging time of the pixel drive circuit and increase the brushing frequency.
  • FIG. 9 is a schematic diagram of still another display substrate according to an embodiment of the disclosure.
  • the display area Q1 not only includes the first sub-display area Q11 and the second sub-display area Q12, but also can Including a third sub-display area Q13, the third sub-display area Q13 can be arranged between the first sub-display area Q11 and the second sub-display area Q12; wherein, the arrangement density of the light-emitting devices in the third sub-display area Q13 can be It is smaller than the arrangement density of the light emitting devices in the first sub-display area Q11.
  • the pixel driving circuit for driving the light emitting devices in the second sub-display area Q12 is disposed in the third sub-display area Q13, that is, the second pixel driving circuit 12 is located in the third sub-display area Q13.
  • the second pixel driving circuit 12 in the third sub-display area Q13 may be connected to the first electrode of the light emitting device in the second sub-display area Q12 through a transparent wire.
  • the arrangement of the pixel driving circuits in the first sub-display area Q11 and the third sub-display area Q13 may be the same.
  • the first electrode of the light-emitting device is electrically connected, and another part of the pixel driving circuit is electrically connected to the light-emitting device in the second sub-display area Q12.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display panel including any one of the above-mentioned display substrates.
  • the display panel may also include an external control circuit 50 (eg, timing controller/TCON) that is bound and connected to the display substrate and provides control signals for the gate driving circuit 30 and the lighting control circuit.
  • an external control circuit 50 eg, timing controller/TCON
  • the external control circuit 50 can use two separate frame-on signal lines to be STV11 and STV12, respectively, With the first sub-light-emitting control circuit 21 and the second sub-light-emitting control circuit 22, to realize the independent control of the first sub-light-emitting control circuit 21 and the second sub-light-emitting control circuit 22.
  • the STV11 is connected to the first signal input terminal of the first register in the first sub-light-emitting control circuit 21 to control whether the first sub-light-emitting control circuit 21 works.
  • the STV12 and the second sub-light-emitting control circuit 22 The first signal input terminal of the first register is connected to control whether the second sub-light-emitting control circuit 22 works.
  • the display panel can be an electroluminescent display device, such as OLED panel, Micro LED panel, Mini LED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator and other products with display function or part. It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present invention, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present invention.

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Abstract

本发明提供一种显示基板及显示面板，属于显示技术领域。本发明的显示基板，其具有显示区和环绕显示区的周边区；所述显示区包括第一子显示区和第二子显示区；其中，所述显示基板包括：基底，设置在基底上的驱动电路层和多个发光器件；所述驱动电路层包括多个像素驱动电路、栅极驱动电路和发光控制信号生成电路；一个所述发光器件的第一电极电连接一个所述像素驱动电路；其中，所述多个像素驱动电路包括用于为所述第一子显示区中的发光器件提供驱动信号的第一像素驱动电路，以及为所述第二子显示区中的发光器件提供驱动信号的第二像素驱动电路；所述发光控制电路包括断开设置的第一子发光控制电路和第二子发光控制电路。

Description

显示基板及显示面板 技术领域
本发明属于显示技术领域，具体涉及一种显示基板及显示面板。
背景技术
随着科技的进步，近年来，异形屏以及全面屏已经逐渐走入大家的视野。不论是异形屏还是全面屏目的都是为了提升显示设备的屏占比。那么，为了实现更高的屏占比，在显示屏的一些位置上需要为一些附加部件(例如摄像头、传感器等等)预留一些开口区域(例如开孔)。
随着显示器技术发展和更新换代，有机电致发光显示器件(Organic Electroluminance Display，简称为：OLED)由于具有自发光、高亮度、高对比度、低工作电压、可制作柔性显示器等特点，已经逐渐成为显示领域的主流产品。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示面板。
第一方面，本公开实施例提供一种显示基板，其具有显示区和环绕显示区的周边区；所述显示区包括第一子显示区和第二子显示区；其中，所述显示基板包括：基底，设置在基底上的驱动电路层和多个发光器件；
所述多个发光器件位于所述第一子显示区和第二子显示区；所述驱动电路层包括多个像素驱动电路、栅极驱动电路和发光控制信号生成电路；所述多个像素驱动电路位于所述第一子显示区和所述周边区；所述栅极驱动电路和所述发光控制电路位于所述周边区；
一个所述发光器件的第一电极电连接一个所述像素驱动电路；所述栅极驱动电路被配置为向各所述像素驱动电路提供扫描信号；所述发光控制电路被配置为向各所述像素驱动电路提供发光控制信号；其中，
所述多个像素驱动电路包括用于为所述第一子显示区中的发光器件提 供驱动信号的第一像素驱动电路，以及为所述第二子显示区中的发光器件提供驱动信号的第二像素驱动电路；
所述发光控制电路包括断开设置的第一子发光控制电路和第二子发光控制电路；所述第一子发光控制电路被配置为向各所述第一像素驱动电路提供发光控制信号；所述第二子发光控制电路被配置为向各所述第二像素驱动电路提供发光控制信号。
其中，所述多个像素驱动电路包括位于所述周边区的冗余像素驱动电路；所述发光控制电路包括冗余发光控制电路；所述冗余像素驱动电路用作所述第二像素驱动电路；所述冗余发光控制电路用作所述第二子发光控制电路。
其中，所述显示区具有沿第一方向相对设置的第一侧和第二侧，以及沿第二方向相对设置的第三侧和第四侧；所述第二子显示区位于所述显示区的第三侧；所述第二像素驱动电路位于所述周边区且靠近所述显示区的第三侧。
其中，多个所述第二像素驱动电路形成沿所述第二方向并排设置的多个第二像素驱动电路组；每个所述第二像素驱动电路组中的各第二像素驱动电路沿所述第一方向并排设置；位于同一所述第二像素驱动电路组中的各所述第二像素驱动电路连接同一条冗余扫描线和同一条冗余发光控制线；
任一所述冗余扫描线和任一所述冗余发光控制线均包括相对设置的第一端和第二端；所述冗余扫描线的第一端和第二端分别连接有所述栅极驱动电路；所述冗余发光控制线的第一端和第二端分别连接有所述第二子发光控制电路。
其中，连接所述冗余发光控制线的第一端的所述第二发光驱动电路位于所述周边区靠近所述显示区的第一侧和第三侧的连接拐角处；连接所述冗余发光控制线的第二端的所述第二子发光控制电路位于所述周边区靠近所述显示区的第二侧和第四侧的连接拐角处。
其中，所述栅极驱动电路包括断开设置的第一子栅极驱动电路和第二子栅极驱动电路；所述第一子栅极驱动电路被配置为向各所述第一像素驱动电路提供扫描信号；所述第二子栅极驱动电路被配置为向各所述第二像素驱动电路提供扫描信号。
其中，所述栅极驱动电路包括冗余栅极驱动电路，所述冗余栅极驱动电路用作所述第二子栅极驱动电路。
其中，所述多个像素驱动电路沿第二方向并排设置形成多个像素驱动电路组；所述像素驱动电路组中的所述像素驱动电路沿第一方向并排设置；
位于同一所述像素驱动电路组中的各像素驱动电路连接同一条扫描线和同一条发光控制线；任一所述扫描线和任一所述发光控制线均包括沿相对设置的第一端和第二端；且在各所述扫描线的第一端和第二端均连接有所述扫描线驱动电路，在各所述发光控制线的第一端和第二端均连接有所述发光控制电路。
其中，所述显示区还包括位于所述第二子显示区第二子显示区之间的第三子显示区；
所述第二子像素驱动电路位于所述第三子显示区。
其中，所述第二发光控制电路与所述发光器件的第一电极通过信号连接线连接；所述信号连接线为透明导线。
第二方面，本公开实施例提供一种显示面板，其包括上述的显示基板。
其中，还包括外部控制电路；所述外部控制电路与所述显示基板绑定连接，且所述外部控制电路被配置为对所述第一子发光控制电路和所述第二子发光控制电路单独控制。
附图说明
图1为一种示例性的显示基板的示意图。
图2为一种示例性的像素驱动电路的示意图。
图3为一种示例性的发光控制电路的示意图。
图4为一种示例性的第一移位寄存器的电路示意图。
图5为一种示例性的栅极驱动电路的示意图。
图6为一种示例性的第二移位寄存器的电路示意图。
图7为本公开实施例的一种显示基板的示意图。
图8为本公开实施例的另一种显示基板的示意图。
图9为本公开实施例的再一种显示基板的示意图。
图10为本公开实施例的显示装置的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，现有的刘海屏或水滴屏设计均逐渐不能满足用户对显示面板高屏占比的需求，一系列能够在安装区实现显示的显示面板应运而生。该类显示面板中，可以将感光传感器(如，摄像头)等硬件设置于显示区，因无需打孔，故在确保显示面板实用性的前提下，使真全面屏成为可能。
在下述内容描述之前，对本公开内容中所提及的第一方向和第二方向进行说明。第一方向和第二方向表示两个不同的方向，例如：第一方向为行方向，第二方向为列方向。为例便于理解，在以下描述中均以第一方向为行方向，第二方向为列方向为例进行描述，当然，应当理解的是，只要是第一方向和第二方向为两个不同的方向均在本公开的保护范围内。
图1为一种示例性的显示基板的示意图；如图1所示，该显示基板具有显示区Q1和环绕显示区Q1的周边区Q2。其中，显示区Q1划分为第一子显示区Q11、第二子显示区Q12和第三子显示区Q13；其中，该显示基板包括基底，以及设置在基底上的多个像素单元、栅极驱动电路30、发光控制电路20。
其中，多个像素单元设置在显示基板的显示区Q1中，并呈阵列排布；其中，位于第一子显示区Q11中的各像素单元均包括像素驱动电路10和与像素驱动电路10电连接的发光器件。第二子显示区Q12用于放置感光传感器(如，摄像头)等硬件，其中的像素单元中仅设置有发光器件，且该发光器件选用透明发光器件，以避免影响感光传感器工作。第三子显示区Q13中的部分像素单元中包括像素驱动电路10和与像素驱动电路10电连接的发光器件，另一部分像素单元中则仅设置像素驱动电路10，这些像素驱动电路10则与第二子显示区Q12中的发光器件一一对应连接，以为第二子显示区Q12中的发光器件提供驱动信号。需要说明的是，将第二子显示区Q12中的发光器件和位于第三子显示区Q13中的像素驱动电路10电连接的信号连接线应当为透明导线(例如：氧化铟锡/ITO)，以避免信号连接线影响感光传感器工作。图2为一种示例性的像素驱动电路的示意图；如图2所示，该像素驱动电路10可以包括：第一复位子电路1、阈值补偿子电路2、数据写入子电路4、驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、第二复位子电路7、存储子电路8。参照图2，第一发光控制子电路5分别与第一电压端VDD以及驱动子电路3的第一端相连，且被配置为实现驱动子电路3和第一电压端VDD之间的连接导通或断开，第二发光控制子电路6 分别与驱动子电路的第二端和发光器件D的第一电极电连接，且被配置为实现驱动子电路3和发光器件D之间的连接导通或断开。数据写入子电路4与驱动子电路3的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储子电路8。存储子电路8分别与驱动子电路3的控制端和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿子电路2分别与驱动子电路3的控制端和第二端电连接，且被配置为对驱动子电路3进行阈值补偿。第一复位子电路1与驱动子电路3的控制端，且被配置为在复位控制信号的控制下对驱动子电路3的控制端进行复位。第二复位子电路7与发光器件D的第一电极D1电连接，且被配置为在扫描信号的控制下对发光器件D的第一电极进行复位。
继续参照图2，该像素驱动电路10中，驱动子电路3包括驱动晶体管T3，数据写入子电路4包括数据写入晶体管T4，阈值补偿子电路2包括阈值补偿晶体管T2，第一发光控制子电路5包括第一发光控制晶体管T5，第二发光控制子电路6包括第二发光控制晶体管T6，第一复位子电路1包括第一复位晶体管T1，第二复位子电路7包括第二复位晶体管T7。
像素驱动电路10在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)，或者P型晶体管和N型晶体管的组合，实现本公开的实施例中的一个或多个晶体管的功能。
另外，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第 一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
继续参照图2，数据写入晶体管T4漏极的与驱动晶体管T3的源极电连接，数据写入晶体管T4的源极被配置为与数据线Data电连接以接收数据信号，数据写入晶体管T4的栅极被配置为与扫描线Gate电连接以接收扫描信号；存储电容Cst的第一极板与第一电源电压端VDD电连接，存储电容Cst的第二极板与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的源极与驱动晶体管T3的漏极电连接，阈值补偿晶体管T2的漏极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的栅极被配置为与扫描线Gate电连接以接收补偿控制信号；第一复位晶体管T1的源极被配置为与初始化信号端Vinit电连接以接收初始化信号，第一复位晶体管T1的漏极与驱动晶体管T3的栅极电连接，第一复位晶体管T1的栅极被配置为与第一复位控制信号线Reset电连接以接收复位控制信号；第二复位晶体管T7的源极被配置为与初始化信号端Vinit电连接以接收初始化信号，第二复位晶体管T7的漏极与发光器件D的第一电极电连接，第二复位晶体管T7的栅极被配置为与扫描线Gate电连接以接收扫描信号；第一发光控制晶体管T5的源极与第一电源电压端VDD电连接，第一发光控制晶体管T5的漏极与驱动晶体管T3的源极电连接，第一发光控制晶体管T5的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号；第二发光控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第二发光控制晶体管T6的漏极与发光器件D的第一电极电连接，第二发光控制晶体管T6的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号；发光器件D的第二电极与第二电源电压端VSS电连接。
例如，第一电源电压端VDD和第二电源电压端VSS之一为高压端，另 一个为低压端。例如，如图10所示的实施例中，第一电源电压端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源电压端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源电压端VSS可以接地。
需要说明的是，图2所示的像素驱动电路1010中的复位子电路1、阈值补偿子电路2、数据写入子电路4、驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、存储子电路7仅为示意性的，复位子电路1、阈值补偿子电路2、数据写入子电路4、驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、存储子电路7等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
发光器件D可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)，当然，在发明实施例中的发光器件D还可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。发光器件D的第一电极和第二电极中的一者为阳极，另一者为阴极；在本发明实施例中以发光器件D的第一电极为阳极，第二电极为阴极为例进行说明。
在一些示例中，位于同一行的各个像素单元中的像素驱动电路10由同一条栅线提供扫描信号，以及由同一条发光控制线提供发光控制信号。对于任一栅线和任一发光控制线均包括相对的第一端和第二端。显示基板中的栅极驱动电路30和发光控制电路20位于周边区Q2，且对于各栅线的第一端和第二端均连接有栅极驱动电路30，对于各发光控制线的第一端和第二端均连接有发光控制电路20。对于栅极驱动电路30和发光控制电路20均位于周边区Q2，其中，图3为一种示例性的发光控制电路20的示意图；如图3所示，该发光控制电路20包括多个级联的第一移位寄存器A，该发光控制电路20中的第一移位寄存器A与发光控制线一一对应连接，用于提供发光控制信号，且本级第一移位寄存器A的第一信号输出端连接下一级第一移位寄 存器A的第一信号输入端；另外，第一个移位寄存器A-1的的第一信号输入端INPUT1连接第一帧开启信号STV1。图5为一种示例性的栅极驱动电路30的示意图，如图5所示，栅极驱动电路30包括多个级联的第二移位寄存器G。栅极驱动电路30中的第二移位寄存器G与栅线一一对应连接，用于提供扫描信号，且本级第二移位寄存器G的第二信号输出端连接下一级第二移位寄存器G的第二信号输入端；另外，第二个移位寄存器G-1的的第二信号输入端INPUT2连接第一帧开启信号STV2。
图4为一种示例性的第一移位寄存器A的电路示意图；如图4所示，该第一移位寄存器A包括：信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104；信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104四者连接于第一节点N1，第一控制电路102和第二控制电路103两者连接于第二节点N2，第二控制电路103和信号输出电路104两者连接于第三节点N3。其中，信号写入电路101与对应的第一信号输入端INPUT和第一时钟信号端CK连接，配置为响应于第一时钟信号端CK提供的第一时钟信号的控制，将对应的第一信号输入端INPUT1所提供的信号写入至第一节点N1。第一控制电路102与第一电源端VGH、第一时钟信号端CK连接，配置为响应于第一时钟信号的控制，将第一电源端VGH提供的第一工作电压写入至第二节点N2，以及响应于第一节点N1处电压的控制，将第一时钟信号写入至第二节点N2。第二控制电路103与第二电源端VGL、第二时钟信号端CKB连接，配置为响应于第二节点N2处电压、第二时钟信号端CKB所提供的第二时钟信号的控制，将第二时钟信号写入至第三节点N3，以及响应于第一节点N1处电压的控制，将第二电源端VGL提供的第二工作电压写入至第三节点N3。信号输出电路104与第一电源端VGH、第二电源端VGL连接，配置为响应于第一节点N1处电压的控制将第一工作电压写入至第一信号输出端OUT1，以及响应于第三节点N3处电压的控制将第二工作电压写入至第一信号输出端OUT1。降噪电路105与第一节点N1、第二节点N2、第二电源端VGL、第二时钟信号端CKB 连接，配置为响应于第二时钟信号和第二节点N2处电压的控制，对第一节点N1处的电压进行降噪处理。
信号写入电路101包括：第一晶体管M1，第一控制电路102包括：第二晶体管M2和第三晶体管M3，第二控制电路103包括：第四晶体管M4、第五晶体管M5、第六晶体管M6和第一电容C1，信号输出电路104包括：第七晶体管M7、第八晶体管M8和第二电容C2，降噪电路105包括：第九晶体管M9、第十晶体管M10和第三电容C3。其中，以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10均采用N型薄膜晶体管为例进行说明。
其中，第一晶体管M1的栅极与第一时钟信号端CK连接，第一晶体管M1的源极与第一信号输入端INPUT1连接，第一晶体管M1的漏极与第一节点N1连接。第二晶体管M2的栅极与第一节点N1连接，第二晶体管M2的源极与第一时钟信号端CK连接，第二晶体管M2的漏极与第二节点N2连接。第三晶体管M3的栅极与第一时钟信号端CK连接，第三晶体管M3的源极与第一电源端VGH连接，第三晶体管M3的漏极与第二节点N2连接。第四晶体管M4的栅极与第二节点N2连接，第四晶体管M4的源极与第二时钟信号端CKB连接，第四晶体管M4的漏极与第五晶体管M5的源极连接。第五晶体管M5的栅极与第二时钟信号端CKB连接，第五晶体管M5的漏极与第三节点N3连接。第六晶体管M6的栅极与第一节点N1连接，第六晶体管M6的源极与第二电源端VGL连接，第六晶体管M6的漏极与第三节点N3连接。第一电容C1的第一极板与第二节点N2连接，第一电容C1的第二极板与第四晶体管M4的漏极连接。第七晶体管M7的栅极与第三节点N3连接，第七晶体管M7的源极与第二电源端VGL连接，第七晶体管M7的漏极与第一信号输出端OUT1连接。第八晶体管M8的栅极与第一节点N1连接，第八晶体管M8的源极与第一电源端VGH连接，第八晶体管M8的漏极与第一信号输出端OUT1连接。第二电容C2的第一极板与第三节点连接， 第二电容C2的第二极板与第一电源端VGH连接。
图6为一种示例性的第二移位寄存器G的电路示意图；如图6所示，该移位寄存器包括：第一输入子电路11、第一下拉控制子电路12、第一输出子电路13和第一下拉子电路14。其中，第一输入子电路11与第二信号输入端IPUT2、上拉节点PU和第三时钟信号端CLK’连接，第一输入子电路11配置为响应第三时钟信号端CLK’的控制将第二信号输入端IPUT2所提供的输入信号写入至上拉节点PU。第一下拉控制子电路12与第二电源端VGL、上拉节点PU、下拉节点PD和第三时钟信号端CLK’连接，第一下拉控制子电路12配置为响应于第三时钟信号端CLK’的控制将第二电源端VGL提供的第一工作电压写入至下拉节点PD，以及响应于上拉节点PU处电压的控制将第三时钟信号端CLK’提供的第一时钟信号写入至下拉节点PD。第一输出子电路13与第一电源端VGH、上拉节点PU、下拉节点PD、第二信号输出端OUT2、第四时钟信号端CLKB’连接，第一输出子电路13配置为响应于上拉节点PU处电压的控制将第四时钟信号端CLKB’提供的第二时钟信号写入至第二信号输出端OUT2，以及响应于下拉节点PD的控制将第一电源端VGH提供的第二工作电压写入至第二信号输出端OUT2。第一下拉子电路14与第一电源端VGH、上拉节点PU、下拉节点PD、第四时钟信号端CLKB’连接，第一下拉子电路14配置为响应下拉节点PD处电压和第四时钟信号端CLKB’的控制将第二工作电压写入至上拉节点PU。
其中，该第一输入子电路11包括第十一晶体管T11，第一下拉控制子电路12包括第十二晶体管T12和第十三晶体管T13，第一输出子电路13包括第十四晶体管T14、第十五晶体管T15、第十八晶体管T18、第四电容C4和第五电容C5，第一下拉子电路14包括第十六晶体管T16和第十七晶体管T17。以下以第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18均为P型薄膜晶体管为例。
其中，第十一晶体管T11的栅极与第三时钟信号端CLK’连接，第十一 晶体管T11的源极与第二信号输入端IPUT2连接，第十一晶体管T11的漏极与上拉节点PU连接。第十二晶体管T12的栅极与上拉节点PU连接，第十二晶体管T12的源极与第三时钟信号端CLK’连接，第十二晶体管T12的漏极与下拉节点PD连接。第十三晶体管T13的栅极与第三时钟信号端CLK’连接，第十三晶体管T13的源极与第二电源端VGL连接，第十三晶体管T13的漏极与下拉节点PD连接。第十四晶体管T14的栅极与下拉节点PD连接，第十四晶体管T14的源极与第一电源端VGH连接，第十四晶体管T14的漏极与第二信号输出端OUT2连接。第十五晶体管T15的栅极与上拉节点PU连接，第十五晶体管T15的源极与第四时钟信号端CLKB’连接，第十五晶体管T15的漏极与第二信号输出端OUT2连接。第十六晶体管T16的栅极与下拉节点PD连接，第十六晶体管T16的源极与第一电源端VGH连接，第十六晶体管T16的漏极与第十七晶体管T17的源极连接。第十七晶体管T17的栅极与第四时钟信号端CLKB’连接，第十七晶体管T17的漏极与上拉节点PU连接。第十八晶体管T18的栅极与第二电源端VGL连接，第十八晶体管T18的源极与上拉节点PU连接，第十八晶体管T18的漏极与第十五晶体管T15的栅极连接。第四电容C4的第一极板与第十五晶体管T15的栅极连接，第四电容C4的第二极板与第二信号输出端OUT2连接。第五电容C5的第一极板与下拉节点PD连接，第五电容C5的第二极板与第十四晶体管T14的源极连接。
发明人发现，在相关技术中，用于驱动第二子显示区中的发光器件的像素驱动电路所连接第一移位寄存器与驱动第一子显示区中的发光器件的像素驱动电路所连接第一移位寄存器是级联关系，这样一来，即使第二子显示区中的感光传感器需要工作时，其内的发光器件也是会被点亮的，故会对感光传感器的工作造成干涉。针对该问题，在本公开实施例中提供如下技术方案。
第一方面，图7为本公开实施例的一种显示基板的示意图，如图7所示，本公开实施例提供一种显示基板，其具有显示区Q1和环绕显示区Q1的周 边区Q2；其中，显示区Q1包括第一子显示区Q11和第二子显示区Q12。该显示基板包括驱动电路层和多个发光器件；驱动电路层包括多个像素驱动电路、栅极驱动电路30和发光控制电路。一个像素驱动电路连接一个发光器件的第一电极，用以为发光器件提供驱动电流。栅极驱动电路30用于为各像素驱动电路提供扫描信号，发光控制电路用于为各像素驱动电路提供发光控制信号。第一子显示区Q11不仅设置有发光器件，而且还设置有用以驱动发光器件的像素驱动电路。第二子显示区Q12用于放置感光传感器(如，摄像头)等硬件，故在第二子显示区Q12中仅设置发光器件，且该区域内的发光器件为透明发光器件，以防止对感光传感器的工作造成干扰。用于驱动第二子显示区Q12中的发光器件的像素驱动电路可以设置在第一子显示区Q11，也可以设置在周边区Q2。以下为了便于描述，描述将用于驱动第一子显示区Q11中的发光器件的像素驱动电路称之为第一像素驱动电路11，用于驱动第二子显示区Q12中的发光器件的像素驱动电路称之为第二像素驱动电路12。在本公开实施例中，发光控制电路包括断开设置的第一子发光控制电路21和第二子发光控制电路22，其中，第一子发光控制电路21被配置为向各第一像素驱动电路11提供发光控制信号，第二子发光控制子电路被配置为向各第二子像素驱动电路提供发光控制信号。
需要说明的是，第一子发光控制电路21和第二子发光控制电路22均可以包括多个级联的第一移位寄存器，第一移位寄存器则可以为图4所示的第一移位寄存器的电路结构。例如：第一子发光控制电路21中的一个第一移位寄存器为一行第一像素驱动电路11提供发光控制信号；第二子发光控制电路22中的一个第一移位寄存器为一行第二像素驱动电路12提供发光控制信号。
在本公开实施例中，由于发光控制电路由断开包括断开设置的第一子发光控制电路21和第二子发光控制电路22，且第一子发光控制电路21向第一像素驱动电路11提供发光控制信号，第二子发光控制电路22向第二像素驱动电路12提供发光控制信号；也即，第一像素驱动电路11由第一子发光控 制电路21控制，第二像素电路由第二子发光电路控制，因此，当第二子显示区Q12中的感光传感器需要工作时，可以控制第二子发光控制电路22输出非工作电平，以使得第二像素驱动电路12中的第五晶体管和第六晶体管关断，无法向第二子显示区Q12中的发光器件输出驱动电流，此时第二子显示区Q12中的发光器件不发光，因此不会对感光传感器的工作造成干扰。
在一些实施例中，显示基板不仅在显示区Q1设置有像素驱动电路，而且在周边区Q2同样也可以设置像素驱动电路，为区分像素驱动电路是位于显示区Q1的像素驱动电路还是位于周边区Q2的像素驱动电路，在本公开实施例中，将位于周边区Q2的像素驱动电路称之为冗余像素驱动电路。应当理解的是，冗余像素驱动电路的结构与位于显示区Q1中的像素驱动电路的结构可以相同，例如采用图2所示的7T1C的像素驱动电路。与此同时，在本公开实施例中，显示基板中的发光控制驱动电路不仅包括级联的第一移位寄存器，而且还包括与第一移位寄存器结构相同的多个冗余第一移位寄存器，多个冗余第一移位寄存器级联形成冗余发光控制驱动电路。在本公开实施例中，将冗余像素驱动电路用作第二像素驱动电路12，以为位于第二子显示区Q12中的发光器件提供驱动电流；与此同时，可以将冗余发光控制电路用作第二子发光控制电路22，用于为冗余像素驱动电路提供发光控制信号。在本公开实施例中，通过冗余像素驱动电路对位于第二子显示区Q12中的发光器件进行驱动，这样一来，可以使得显示区Q1中的发光器件的均匀排布，特别是在第一子显示区Q11中，每个像素驱动电路可以与发光器件一一对应连接，从而使得应用本公开实施例显示基板的显示面板显示更加均一。
在一个示例中，继续参照图7，以矩形显示基板为例；其中，显示基板的显示区Q1包括沿行方向相对设置的第一侧(左侧)和第二侧(右侧)，以及沿列方向相对设置的第三侧(上侧)和第四侧(下侧)；第二子显示区Q12位于显示区Q1的第三侧，位于周边区Q2靠近显示区Q1的第三侧位置处的冗余像素驱动电路用作第二像素电路，这样一来，便于第二像素驱动电路12与第二子显示区Q12中的发光器件电连接。在一些实施例中，第二像素驱动 电路12与第二显示区Q1中的发光器件通过信号连接线40电连接，该信号连接线40可以采用透明导线(例如：氧化铟锡/ITO)。
例如：第二像素驱动电路12形成沿列方向并排设置的多个第二像素驱动电路12组，每个第二像素驱动电路12组中的各第二像素驱动电路12沿行方向并排设置。由于冗余像素驱动电路用作第二像素驱动电路12，此时位于同一第二像素驱动电路12组中的各第二像素驱动电路12连接同一条冗余扫描线和同一条冗余发光控制线。其中，冗余扫描线和冗余发光控制线均具有相对设置的第一端和第二端，且冗余扫描线的第一端和第二端均连接有栅极驱动电路30；冗余发光控制线的第一端和第二端均连接有第二子发光控制电路22(冗余发光控制电路)。需要说明的是，一条冗余发光控制线的第一端和第二端分别连接有一个第一移位寄存器，一条冗余扫描线的第一端和第二端分别连接有一个第二移位寄存器。
例如：继续参照图7，当冗余发光控制电路用作第二子发光控制电路22时，连接冗余发光控制线的第一端的冗余发光控制电路(第二发光驱动电路)位于所述周边区Q2靠近显示区Q1的第一侧和第三侧的连接拐角处(左上角)；连接冗余发光控制线的第二端的冗余发光控制电路(第二发光驱动电路)位于周边区Q2靠近显示区Q1的第二侧和第四侧的连接拐角处(右上角)。之所以如此设置，是为了方便冗余发光控制电路和冗余像素驱动电路的连接。
在一些实施例中，图8为本公开实施例的另一种显示基板的示意图，如图8所示，显示基板中的不仅发光控制电路包括断开设置的第一子发光控制电路21和第二子发光控制电路22，而且栅极驱动电路30包括断开设置的第一子栅极驱动电路31和第二子栅极驱动电路32；第一子栅极驱动电路31被配置为向各所述第一像素驱动电路11提供扫描信号；第二子栅极驱动电路32被配置为向各所述第二像素驱动电路12提供扫描信号。在本公开实施例中，第一子像素驱动电路和第二像素驱动电路12分别采用第一子栅极驱动和第二子栅极驱动电路32提供栅极驱动信号，因此在第二子显示区Q12中 的感光传感器工作时，可以控制第二子栅极驱动电路32停止工作，以此可以降低显示基板的功耗。
需要说明的是，第一子栅极驱动电路31和第二子栅极驱动电路32均包括级联的第二移位寄存器。第二移位寄存器均可以采用图6所示的结构。例如：第一子栅极驱动电路31中的一个第二移位寄存器为一行第一像素驱动电路11提扫描信号；第二子栅极驱动电路32中的一个第二移位寄存器为一行第二像素驱动电路12提供扫描信号。
在一些实施例中，周边区Q2的栅极驱动电路30不仅包括用于为显示区Q1中的像素驱动电路提供扫描信号的第二移位寄存器，而且还包括与第二移位寄存器结构相同的冗余第二移位寄存器，冗余第二移位寄存器级联则形成冗余栅极驱动电路30，在本公开实施例中，可以将冗余栅极驱动电路30用作第二子栅极驱动电路32。
例如：以图8所示的显示基板为例，冗余像素驱动电路用作第二像素驱动电路12，此时冗余扫描线的第一端和第二端均连接有冗余栅极驱动电路30(第二子栅极驱动电路32)，连接在冗余扫描线的第一端的冗余栅极驱动电路30可以位于周边区Q2靠近显示区Q1左上角的位置处，连接在冗余扫描线的第二端的冗余栅极驱动电路30可以位于周边区Q2靠近显示区Q1右上角的位置处，这样一来，便于冗余栅极驱动电路30与冗余像素驱动电路的连接。需要说明的是，一条冗余扫描线的第一端和第二端分别连接一个冗余移位寄存器。
在一些实施例中，显示基板中的像素驱动电路沿列方向并排设置形成多个像素驱动电路组；每个像素驱动电路组中的各像素驱动电路沿行方向并排设置。其中，位于同一行的像素驱动电路连接同一条扫描线和同一条发光控制线；每一条扫描线和发光控制线均包括相对设置的第一端和第二端，且在各扫描线的第一端和第二端均连接有栅极驱动电路30，在各发光控制线的第一端和第二端均连接有发光控制电路，也即本公开实施例的显示基板为双边驱动，这样一来，可以提高像素驱动电路的充电时间，提高刷频率。
在一些实施例中，图9为本公开实施例的再一种显示基板的示意图，如图9所示，显示区Q1不仅包括第一子显示区Q11和第二子显示区Q12，而且还可以包括第三子显示区Q13，第三子显示区Q13可以设置在第一子显示区Q11和第二子显示区Q12之间；其中，第三子显示区Q13中的发光器件的排布密度可以小于第一子显示区Q11中的发光器件的排布密度。此时，用于驱动第二子显示区Q12中的发光器件的像素驱动电路则设置在第三子显示区Q13中，也即第二像素驱动电路12位于第三子显示区Q13中。第三子显示区Q13中的第二像素驱动电路12可以通过透明导线与第二子显示区Q12中的发光器件的第一电极连接。
需要说明的是，第一子显示区Q11和第三子显示区Q13中的像素驱动电路的排布方式可以相同，此时仅需将第三子显示区Q13中部分像素驱动电路与该区域中的发光器件的第一电极电连接，另一部分像素驱动电路与第二子显示区Q12中的发光器件电连接。
第二方面，图10为本公开实施例的显示装置的示意图，如图10所示，本公开实施例提供一种显示面板，其包括上述的任意一种显示基板。当然，在该显示面板中还可以包括与显示基板绑定连接且为栅极驱动电路30和发光控制电路提供控制信号的外部控制电路50(例如：时序控制器/TCON)。由于发光控制电路包括第一子发光控制电路21和第二子发光控制电路22，且二者断开设置，此时外部控制电路50可以通过两条单独是帧开启信号线分别为STV11和STV12，与第一子发光控制电路21和第二子发光控制电路22，以实现对第一子发光控制电路21和第二子发光控制电路22单独控制。需要说明的是，STV11与第一子发光控制电路21中的第一个寄存器的第一信号输入端连接，以控制第一子发光控制电路21是否工作，STV12与第二子发光控制电路22中的第一个寄存器的第一信号输入端连接，以控制第二子发光控制电路22是否工作。其中，显示面板可以为电致发光显示装置，例如OLED面板、Micro LED面板，Mini LED面板，手机、平板电脑、电视 机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种显示基板，其具有显示区和环绕显示区的周边区；所述显示区包括第一子显示区和第二子显示区；其中，所述显示基板包括：基底，设置在基底上的驱动电路层和多个发光器件；
    所述多个发光器件位于所述第一子显示区和第二子显示区；所述驱动电路层包括多个像素驱动电路、栅极驱动电路和发光控制信号生成电路；所述多个像素驱动电路位于所述第一子显示区和所述周边区；所述栅极驱动电路和所述发光控制电路位于所述周边区；
    一个所述发光器件的第一电极电连接一个所述像素驱动电路；所述栅极驱动电路被配置为向各所述像素驱动电路提供扫描信号；所述发光控制电路被配置为向各所述像素驱动电路提供发光控制信号；其中，
    所述多个像素驱动电路包括用于为所述第一子显示区中的发光器件提供驱动信号的第一像素驱动电路，以及为所述第二子显示区中的发光器件提供驱动信号的第二像素驱动电路；
    所述发光控制电路包括断开设置的第一子发光控制电路和第二子发光控制电路；所述第一子发光控制电路被配置为向各所述第一像素驱动电路提供发光控制信号；所述第二子发光控制电路被配置为向各所述第二像素驱动电路提供发光控制信号。
  2. 根据权利要求1所述的显示基板，其中，所述多个像素驱动电路包括位于所述周边区的冗余像素驱动电路；所述发光控制电路包括冗余发光控制电路；所述冗余像素驱动电路用作所述第二像素驱动电路；所述冗余发光控制电路用作所述第二子发光控制电路。
  3. 根据权利要求2所述的显示基板，其中，所述显示区具有沿第一方向相对设置的第一侧和第二侧，以及沿第二方向相对设置的第三侧和第四侧；所述第二子显示区位于所述显示区的第三侧；所述第二像素驱动电路位于所述周边区且靠近所述显示区的第三侧。
  4. 根据权利要求3所述的显示基板，其中，多个所述第二像素驱动电路形成沿所述第二方向并排设置的多个第二像素驱动电路组；每个所述第二像素驱动电路组中的各第二像素驱动电路沿所述第一方向并排设置；位于同一所述第二像素驱动电路组中的各所述第二像素驱动电路连接同一条冗余扫描线和同一条冗余发光控制线；
    任一所述冗余扫描线和任一所述冗余发光控制线均包括相对设置的第一端和第二端；所述冗余扫描线的第一端和第二端分别连接有所述栅极驱动电路；所述冗余发光控制线的第一端和第二端分别连接有所述第二子发光控制电路。
  5. 根据权利要求4所述的显示基板，其中，连接所述冗余发光控制线的第一端的所述第二发光驱动电路位于所述周边区靠近所述显示区的第一侧和第三侧的连接拐角处；连接所述冗余发光控制线的第二端的所述第二子发光控制电路位于所述周边区靠近所述显示区的第二侧和第四侧的连接拐角处。
  6. 根据权利要求2-5中任一项所述的显示基板，其中，所述栅极驱动电路包括断开设置的第一子栅极驱动电路和第二子栅极驱动电路；所述第一子栅极驱动电路被配置为向各所述第一像素驱动电路提供扫描信号；所述第二子栅极驱动电路被配置为向各所述第二像素驱动电路提供扫描信号。
  7. 根据权利要求6所述的显示基板，其中，所述栅极驱动电路包括冗余栅极驱动电路，所述冗余栅极驱动电路用作所述第二子栅极驱动电路。
  8. 根据权利要求1所述的显示基板，其中，所述多个像素驱动电路沿第二方向并排设置形成多个像素驱动电路组；所述像素驱动电路组中的所述像素驱动电路沿第一方向并排设置；
    位于同一所述像素驱动电路组中的各像素驱动电路连接同一条扫描线和同一条发光控制线；任一所述扫描线和任一所述发光控制线均包括沿相对设置的第一端和第二端；且在各所述扫描线的第一端和第二端均连接有所述扫描线驱动电路，在各所述发光控制线的第一端和第二端均连接有所述发光 控制电路。
  9. 根据权利要求1所述的显示基板，其中，所述显示区还包括位于所述第二子显示区第二子显示区之间的第三子显示区；
    所述第二子像素驱动电路位于所述第三子显示区。
  10. 根据权利要求1所述的显示基板，其中，所述第二发光控制电路与所述发光器件的第一电极通过信号连接线连接；所述信号连接线为透明导线。
  11. 一种显示面板，其包括权利要求1-10中任一项所述的显示基板。
  12. 根据权利要求11所述的显示面板，其中，还包括外部控制电路；所述外部控制电路与所述显示基板绑定连接，且所述外部控制电路被配置为对所述第一子发光控制电路和所述第二子发光控制电路单独控制。
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