WO2022099508A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

Info

Publication number
WO2022099508A1
WO2022099508A1 PCT/CN2020/128119 CN2020128119W WO2022099508A1 WO 2022099508 A1 WO2022099508 A1 WO 2022099508A1 CN 2020128119 W CN2020128119 W CN 2020128119W WO 2022099508 A1 WO2022099508 A1 WO 2022099508A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
sub
electrode
light
Prior art date
Application number
PCT/CN2020/128119
Other languages
English (en)
French (fr)
Inventor
徐元杰
王本莲
龙跃
黄耀
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/432,574 priority Critical patent/US11763730B2/en
Priority to PCT/CN2020/128119 priority patent/WO2022099508A1/zh
Priority to CN202080002723.9A priority patent/CN115210800A/zh
Publication of WO2022099508A1 publication Critical patent/WO2022099508A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a pixel driving circuit and a display panel.
  • organic electroluminescence display Organic Electroluminance Display, referred to as: OLED
  • OLED Organic Electroluminance Display
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a pixel driving circuit and a display panel.
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes: a data writing sub-circuit, a driving sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and an auxiliary function sub-circuit and storage sub-circuits; wherein,
  • the driving sub-circuit includes a driving transistor, and is configured to generate a driving circuit according to the voltage of the first electrode and the control electrode thereof, so as to drive the light-emitting device to be driven;
  • the data writing sub-circuit is configured to write a data voltage to the first pole of the driving sub-circuit in response to the first scan signal;
  • the auxiliary function sub-circuit is configured Compensating the threshold voltage of the drive transistor;
  • the storage sub-circuit is configured to store the data voltage;
  • the auxiliary function sub-circuit is configured to short-circuit the control electrode and the second electrode of the driving transistor;
  • the reset sub-circuit is configured to respond to the reset control signal and to the to-be-driven through the initial signal
  • the first electrode of the light-emitting device is initialized, and the second light-emitting control sub-circuit transmits the initialization signal to the second electrode of the driving sub-circuit in response to the second light-emitting control signal;
  • the first light-emitting control sub-circuit is configured to write a first power supply voltage into the first electrode of the driving transistor in response to the first light-emitting control signal, so that the driving transistor generates a driving current; so
  • the second light-emitting control sub-circuit is configured to transmit the driving current to the light-emitting device to be driven in response to a second light-emitting control signal.
  • the auxiliary function sub-circuit includes: a first transistor and a second transistor;
  • the first electrode of the first transistor is connected to the second electrode of the second transistor, the second electrode is connected to the control electrode of the driving transistor, and the control electrode is connected to the first control signal line;
  • the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the control electrode is connected to the second scan line.
  • the first control signal line is configured to write any one of the following signals:
  • the auxiliary function sub-circuit includes: a first transistor and a second transistor;
  • the first electrode of the first transistor is connected to the second scan line, the second electrode is connected to the control electrode of the second transistor, and the control electrode is connected to the first control signal line;
  • the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the control electrode of the driving transistor.
  • the first control signal line is configured to write a signal opposite to the first light emission control signal or a second scanning signal.
  • the data writing sub-circuit includes a fourth transistor
  • the first electrode of the fourth transistor is connected to the data line
  • the second electrode is connected to the first electrode of the driving transistor
  • the control electrode is connected to the first scan line
  • the first light-emitting control sub-circuit includes: a fifth transistor
  • the first electrode of the fifth transistor is connected to the first power supply voltage line, the second electrode is connected to the first electrode of the driving transistor, and the control electrode is connected to the first light-emitting control line.
  • the second light-emitting control sub-circuit includes: a sixth transistor
  • the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting device with driving, and the control electrode is connected to the second light-emitting control line.
  • the reset sub-circuit includes: a seventh transistor
  • the first electrode of the seventh transistor is connected to the first electrode of the light-emitting device with driving, the second electrode is connected to the initialization signal line, and the control electrode is connected to the reset signal line.
  • the storage sub-circuit includes: a storage capacitor
  • the first plate of the storage capacitor is connected to the control electrode of the driving transistor, and the second plate is connected to the two first power supply voltage lines.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned pixel driving circuit.
  • the pixel driving circuit is arranged in an array;
  • the auxiliary sub-circuit includes a first transistor and a second transistor; the first electrode of the first transistor is connected to the second electrode of the second transistor, and the second electrode is connected to The control electrode of the driving transistor is connected to the first control signal line; the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the control electrode is connected to the second scan line;
  • each of the data writing sub-circuits is connected to the same first scan line; each of the first light-emitting control sub-circuits is connected to the same first light-emitting control line, and each of the second light-emitting control sub-circuits is connected to the same first light-emitting control line.
  • the light-emitting control sub-circuit is connected to the same second light-emitting control line, the control electrodes of the first transistors in each auxiliary function sub-circuit are connected to the same first control signal line, and the control electrodes of the second transistors are connected to the same line the second scan line; each of the reset sub-circuits is connected to the same reset signal line;
  • each of the data writing sub-circuits is connected to the same data line; each of the first light-emitting control sub-circuits and each of the storage sub-circuits is connected to the same first power supply signal line; Each of the reset sub-circuits is connected to the same initialization signal line;
  • the first scan line connected to the pixel driving circuit in the N+1th row is multiplexed into the second scan line and the reset signal line connected to the pixel driving circuit in the Nth row;
  • the first light-emitting control lines connected to the pixel driving circuits in the +1 row are multiplexed into the second light-emitting control lines connected to the pixel driving circuits in the Nth row;
  • N is an integer greater than or equal to 1.
  • the first scan line connected to the pixel driving circuit in the N+1th row is also multiplexed into the first control signal line connected to the pixel driving circuit in the Nth row.
  • the pixel driving circuit is arranged in an array;
  • the auxiliary sub-circuit includes a first transistor and a second transistor; a first electrode of the first transistor is connected to the second scan line, and a second electrode is connected to the first transistor.
  • the control electrodes of the two transistors are connected to the first control signal line; the first electrodes of the second transistors are connected to the second electrodes of the driving transistors, and the first electrodes are connected to the control electrodes of the driving transistors;
  • each of the data writing sub-circuits is connected to the same first scan line; each of the first light-emitting control sub-circuits is connected to the same first light-emitting control line, and each of the second light-emitting control sub-circuits is connected to the same first light-emitting control line.
  • the light-emitting control sub-circuit is connected to the same second light-emitting control line, the control electrodes of the first transistors in each auxiliary function sub-circuit are connected to the same first control signal line; each of the reset sub-circuits is connected to the same line the reset signal line; the first electrodes of the first transistors in each of the auxiliary function sub-circuits are connected to the same second scan line;
  • each of the data writing sub-circuits is connected to the same data line; each of the first light-emitting control sub-circuits and each of the storage sub-circuits is connected to the same first power supply signal line; Each of the reset sub-circuits is connected to the same initialization signal line;
  • the first scan line connected to the pixel driving circuit in the N+1th row is multiplexed into the second scan line and the reset signal line connected to the pixel driving circuit in the Nth row;
  • the first light-emitting control lines connected to the pixel driving circuits in the +1 row are multiplexed into the second light-emitting control lines connected to the pixel driving circuits in the Nth row;
  • N is an integer greater than or equal to 1.
  • the first scan line connected to the pixel driving circuit in the N+1th row is also multiplexed into the first control signal line connected to the pixel driving circuit in the Nth row.
  • FIG. 1 is a schematic diagram of an exemplary pixel driving circuit.
  • FIG. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 5 is an operation timing diagram of the pixel driving circuit shown in FIG. 4 .
  • FIG. 6 is a schematic diagram illustrating the conduction state of the transistor in the initialization stage of the pixel driving circuit of FIG. 4 .
  • FIG. 7 is a schematic diagram illustrating the conduction state of the transistor in the data writing and threshold compensation stages of the pixel driving circuit of FIG. 4 .
  • FIG. 8 is a schematic diagram illustrating the conduction state of the transistors in the pixel driving circuit of FIG. 4 in the continuous data writing stage.
  • FIG. 9 is a schematic diagram illustrating the conduction state of the transistor in the pre-light-emitting stage of the pixel driving circuit of FIG. 4 .
  • FIG. 10 is a schematic diagram illustrating the conduction state of the transistor in the light-emitting stage of the pixel driving circuit of FIG. 4 .
  • FIG. 11 is another operation timing diagram of the pixel driving circuit of FIG. 4 .
  • FIG. 12 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 13 is an operation timing diagram of the pixel driving circuit of FIG. 12 .
  • FIG. 14 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 15 is a schematic diagram illustrating the conduction state of the transistor in the initialization stage of the pixel driving circuit of FIG. 14 .
  • FIG. 16 is a schematic diagram illustrating the on-state of the transistor in the data writing and threshold compensation stages of the pixel driving circuit of FIG. 14 .
  • FIG. 17 is a schematic diagram illustrating the conduction state of the transistors in the pixel driving circuit of FIG. 14 in the continuous writing stage of data.
  • FIG. 18 is a schematic diagram illustrating the conduction state of the transistor in the pre-light-emitting stage of the pixel driving circuit of FIG. 14 .
  • FIG. 19 is a schematic diagram illustrating the conduction state of the transistor in the light-emitting stage of the pixel driving circuit of FIG. 14 .
  • FIG. 20 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example in detail.
  • P-type transistors for example, P-type MOS transistors
  • N-type transistors eg, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control electrode is used as the gate of the transistor, one of the first electrode and the second electrode is used as the source electrode of the transistor, and the other is used as the transistor.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • the first electrode is directly described as the source electrode and the second electrode as the drain electrode, so all or part of the source electrodes of the transistors in the embodiments of the present disclosure are directly described. and drain are interchangeable as required.
  • the transistors used in the embodiments of the present disclosure are P-type transistors
  • the working level signal corresponds to a low level signal
  • the non-working level signal corresponds to a high level signal
  • the light-emitting device in the embodiment of the present disclosure may be a micro inorganic light-emitting diode, and further, may be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED), of course, the light-emitting device in the embodiment of the invention may also be an organic electroluminescent diode (Organic Light Emitting Diode, OLED).
  • One of the first electrode and the second electrode of the light-emitting device is an anode, and the other is a cathode. In the embodiment of the present invention, the first electrode of the light-emitting device is an anode and the second electrode is a cathode for illustration.
  • FIG. 1 is a schematic diagram of an exemplary pixel driving circuit.
  • the pixel driving circuit includes a driving sub-circuit 3, a first light-emitting control sub-circuit 5, a second light-emitting control sub-circuit 6, and a data writing sub-circuit circuit 4, storage sub-circuit 8, threshold compensation sub-circuit 2, first reset sub-circuit 1 and second reset sub-circuit 7; wherein, the driving sub-circuit 3 can be a driving transistor T4, which is configured to be, according to the gate-source voltage Vgs, The driving current is output to the light-emitting device D to be driven.
  • the driving sub-circuit 3 can be a driving transistor T4, which is configured to be, according to the gate-source voltage Vgs, The driving current is output to the light-emitting device D to be driven.
  • the first light-emitting control sub-circuit 5 is respectively connected to the first power supply voltage line VDD and the source of the driving transistor T4, and is configured to turn on or off the connection between the driving transistor T4 and the first voltage terminal VDD
  • the second light-emitting control sub-circuit 6 is respectively electrically connected to the drain of the driving transistor T4 and the first electrode D1 of the light-emitting device D, and is configured to realize the connection between the driving sub-circuit 3 and the light-emitting device D to be turned on or off
  • the data writing sub-circuit 4 is electrically connected to the source of the driving transistor T4, and is configured to write a data signal into the storage sub-circuit 7 under the control of the first scan signal.
  • the storage sub-circuit 8 is electrically connected to the gate of the driving transistor T4 and the first voltage terminal VDD, respectively, and is configured to store data signals.
  • the threshold compensation sub-circuit 2 is electrically connected to the gate and the drain of the driving transistor T4, respectively, and is configured to perform threshold compensation on the driving transistor T4.
  • the first reset sub-circuit 1 is electrically connected to the gate of the driving transistor T4, and is configured to reset the gate of the driving transistor T4 under the control of the first reset signal.
  • the second reset sub-circuit 7 is electrically connected to the first electrode of the light-emitting device D, and resets the first electrode of the light-emitting device D under the control of the second reset control signal.
  • the data writing sub-circuit 4 includes a fourth transistor T4
  • the storage sub-circuit 8 includes a storage capacitor Cst
  • the threshold compensation sub-circuit 2 includes a second transistor T2
  • the first light-emitting control sub-circuit 5 includes a fifth transistor T5
  • the second lighting control sub-circuit 6 includes a sixth transistor T6, the first reset sub-circuit 1 includes a first transistor T1, and the second reset sub-circuit includes a seventh transistor T7.
  • the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor T3, the source of the fourth transistor T4 is configured to be electrically connected to the data line Data to receive the data signal, and the gate of the fourth transistor T4 It is configured to be electrically connected to the first scan signal line Gate1 to receive the first scan signal; the first plate of the storage capacitor Cst is electrically connected to the first power signal line VDD, and the second plate of the storage capacitor Cst is connected to the second plate of the drive transistor T3.
  • the gate is electrically connected; the source of the second transistor T2 is electrically connected to the drain of the driving transistor T3, the drain of the second compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the second compensation transistor T2 is configured In order to be electrically connected to the second scan signal line Gate2 to receive the compensation control signal; the source of the first transistor T1 is configured to be electrically connected to the first initialization signal line Vinit1 to receive the first initialization signal, and the drain of the first transistor T1 is connected to the first initialization signal line Vinit1.
  • the gate of the driving transistor T3 is electrically connected, the gate of the first transistor T1 is configured to be electrically connected to the first reset control signal line Reset1 to receive the first reset control signal; the source of the seventh transistor T7 is configured to be connected to the second reset control signal line
  • the initialization Vinit2 is electrically connected to receive the second initialization signal, the drain of the seventh transistor T7 is electrically connected to the first electrode of the light emitting device D, and the gate of the seventh transistor T7 is configured to be electrically connected to the second reset control signal line Reset2 to Receive the second reset control signal;
  • the source of the fifth transistor T5 is electrically connected to the first power supply voltage line VDD, the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T3, and the gates of the first and fifth transistors T5 are electrically connected to It is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the source of the sixth control transistor T6 is electrically connected to
  • one of the first power supply voltage line VDD and the second power supply voltage line VSS is connected to a high voltage terminal, and the other is connected to a low voltage terminal.
  • the first power supply voltage line VDD can be a voltage source to output a constant first voltage, and the first voltage is a positive voltage
  • the second power supply voltage line VSS can be a voltage source to output a constant second voltage, the second voltage is negative voltage, etc.
  • the second supply voltage line VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the fourth transistor T4 and the gate of the second transistor T2 may be electrically connected to the same signal line, such as the first scan signal line Gate1, to receive For the same signal (eg, scan signal), in this case, the second scan signal line Gate2 may not be provided on the display substrate, thereby reducing the number of signal lines.
  • the gate of the fourth transistor T4 and the gate of the second transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the second transistor The gate of T2 is electrically connected to the second scan signal line Gate2, and the signals transmitted by the first scan signal line Gate1 and the second scan signal line Gate2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate of the fourth transistor T4 and the second transistor T2 can be controlled separately and independently, thereby increasing the flexibility of controlling the pixel circuit.
  • the gate of the fourth transistor T4 and the gate of the second transistor T2 are electrically connected to the first scan signal line Gate1 as an example for description.
  • the first lighting control signal and the second lighting control signal may be the same, that is, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 may be electrically connected to the same signal line, for example, the first lighting control signal
  • the signal line EM1 is used to receive the same signal (eg, the first light-emitting control signal).
  • the display substrate may not be provided with the second light-emitting control signal line EM2 to reduce the number of signal lines.
  • the gate of the fifth transistor T5 and the gate of the sixth transistor T6 may also be electrically connected to different signal lines respectively, that is, the gate of the fifth transistor T5 is electrically connected to the first light-emitting control signal line EM1, and the The gates of the six transistors T6 are electrically connected to the second light emission control signal line EM2, and the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit the same signal.
  • the fifth transistor T5 and the sixth transistor T6 are different types of transistors, for example, the fifth transistor T5 is a P-type transistor and the sixth transistor T6 is an N-type transistor, the first light-emitting control signal and the The two light-emitting control signals may also be different, which is not limited in the embodiment of the present disclosure.
  • the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the first light-emitting control line as an example for description.
  • the first reset control signal and the second reset control signal may be the same, that is, the gate of the first transistor T1 and the gate of the seventh transistor T7 may be electrically connected to the same signal line, eg, the first reset control signal line Reset1 , so as to receive the same signal (for example, the first reset control signal), at this time, the display substrate may not set the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first transistor T1 and the gate of the seventh transistor T7 may also be electrically connected to different signal lines respectively, that is, the gate of the first transistor T1 is electrically connected to the first reset control signal line Reset1, the seventh The gate of the transistor T7 is electrically connected to the second reset control signal line Reset2, and the first reset control signal line Reset1 and the second reset control signal line Reset2 transmit the same signal. It should be noted that the first reset control signal and the second reset control signal may also be different.
  • the second reset control signal may be the same as the scan signal, that is, the gate of the seventh transistor T7 may be electrically connected to the scan signal line Gate to receive the scan signal as the second reset control signal.
  • the source of the first transistor T1 and the drain of the seventh transistor T7 are connected to the first initialization signal line Vinit1 and the second initialization signal line Vinit2, respectively, and the first initialization signal line Vinit1 and the second initialization signal line Vinit2 may be DC Reference voltage terminal to output a constant DC reference voltage.
  • the first initialization signal line Vinit1 and the second initialization signal line Vinit2 may be the same, for example, the source of the first transistor T1 and the source of the seventh transistor T7 are connected to the same initialization signal line.
  • the first initialization signal line Vinit1 and the second initialization signal line Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first initialization signal and the second initialization signal to control the gate of the driving transistor T3 and the first initialization signal of the light-emitting element.
  • One electrode can be reset, which is not limited in the present disclosure.
  • the source of the first transistor T1 and the source of the seventh transistor T7 may both be connected to the initialization signal line Init.
  • the driving subcircuit 3 the data writing subcircuit 4 , the storage subcircuit 8 , the threshold compensation subcircuit 2 , the first reset subcircuit 1 and the second reset subcircuit 7
  • the specific structures of the sub-circuits such as the driving sub-circuit, the data writing sub-circuit, the storage sub-circuit, the threshold compensation sub-circuit, and the reset sub-circuit can be set according to the actual application requirements, and the embodiments of the present disclosure are for this purpose. There is no specific limitation.
  • the two transistors are usually double-gate transistors, but the design of the double-gate transistors is bound to improve the resolution of the display panel.
  • FIG. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure
  • a pixel driving circuit which includes: a data writing sub-circuit 4, a driving sub-circuit 3, a reset sub-circuit 7, a first light-emitting control sub-circuit 5, a second light-emitting control sub-circuit 6, an auxiliary function sub-circuit 9 and a storage sub-circuit Circuit 8
  • the driving sub-circuit 3 includes a driving transistor T3, which is configured to generate a driving circuit according to the voltage of the first pole and the control pole, so as to drive the light-emitting device D to be driven
  • the data writing sub-circuit 4 is configured to write the data voltage into the first pole of the driving sub-circuit 3 in response to the first scanning signal
  • the auxiliary function sub-circuit 9 is configured to compensate the threshold voltage of the driving transistor T3;
  • the auxiliary function sub-circuit 9 can not only compensate the threshold voltage of the driving transistor T3 in the data access stage, but also can cooperate with the second light-emitting sub-circuit and the reset sub-circuit 7 to compensate the driving transistor T3 in the initialization stage.
  • the gate of T3 is reset, that is, the auxiliary function sub-circuit 9 in the embodiment of the present disclosure has both the threshold value compensation and reset functions, so the simplification of the pixel driving circuit is realized, which is helpful for the application of the display panel of the embodiment of the present disclosure. resolution.
  • the auxiliary function sub-circuit 9 includes a first transistor T1 and a second transistor T2; wherein the source of the first transistor T1 is connected to the drain of the second transistor T2, and the drain of the first transistor T1 is connected to the driving transistor
  • the gate of T3, the gate of the first transistor T1 is connected to the first control signal line Contor1; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the gate of the second transistor T2 is connected to the second scan line Gate1'.
  • the first control signal line Contor1 is written with a low-level signal at least in the initialization phase and the data writing and threshold compensation phase.
  • the reset sub-circuit 7 initializes the first electrode of the light-emitting device D to be driven through the initial signal under the control of the reset control signal, so that the potential of the first electrode of the light-emitting device D is the initialization potential
  • the second control signal line EM1', the second scan line Gate1' and the first control signal line Contor1 are all written with low-level signals, the first transistor T1 and the second transistor T2 are turned on, and the gate of the driving transistor T3
  • the pole potential is reset to the initialization potential by the first transistor T1 , the second transistor T2 and the second light emission control sub-circuit 6 .
  • both the second scan line Gate1' and the first control signal line Contor1 are written with low-level signals, the first transistor T1 and the second transistor T2 are turned on, and the gate and drain of the drive transistor T3 The pole is short-circuited as a diode, and the threshold voltage of the driving transistor T3 is compensated by the data voltage written on the data line Data.
  • the auxiliary function sub-circuit 9 when the auxiliary function sub-circuit 9 includes a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the drain of the second transistor T2, and the drain of the first transistor T1 is connected to the driving transistor T3 When the gate of the first transistor T1 is connected to the first control signal line Contor1; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the gate of the second transistor T2 is connected to the second scan line Gate1', During the scanning period of one frame of image, the first control signal line Contor1 is configured to write any one of a working level signal, a signal opposite to the first light emission control signal, and a second scanning signal.
  • the first transistor T1 is in an on state in one frame scanning period, which is simple in timing and easy to control. If the signal written in the first control signal line Contor1 is the opposite signal to the first light-emitting control signal, the first switch transistor will not be turned on in the light-emitting stage, but only in the data writing and threshold compensation stage and the initialization stage, so that As a result, the risk of leakage current generated by the first transistor T1 can be effectively reduced, and the service life of the first transistor T1 can be prolonged.
  • the gate of the first transistor T1 and the gate of the second transistor T2 can be connected together through a signal line to provide the second scan signal for both. In this case, it is helpful for the wiring on the display panel.
  • the auxiliary function sub-circuit 9 includes: a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the second scan line Gate1', and the drain of the first transistor T1 is connected to the second The gate of the transistor T2, the gate of the first transistor T1 is connected to the first control signal line Contor1; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the drain of the second transistor T2 is connected to the gate of the driving transistor T3 .
  • the reset sub-circuit 7 initializes the first electrode of the light-emitting device D to be driven through the initial signal under the control of the reset control signal, so that the potential of the first electrode of the light-emitting device D is the initialization potential
  • the second control signal line EM1', the second scan line Gate1' and the first control signal line Contor1 are all written with low-level signals, the first transistor T1 and the second transistor T2 are turned on, and the gate of the driving transistor T3
  • the pole potential is reset to the initialization potential by the first transistor T1 , the second transistor T2 and the second light emission control sub-circuit 6 .
  • both the second scan line Gate1' and the first control signal line Contor1 are written with low-level signals, the first transistor T1 and the second transistor T2 are turned on, and the gate and drain of the drive transistor T3 The pole is short-circuited as a diode, and the threshold voltage of the driving transistor T3 is compensated by the data voltage written on the data line Data.
  • the auxiliary function sub-circuit 9 includes: a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the second scan line Gate1', and the drain of the first transistor T1 is connected to the second scan line Gate1'.
  • the first control signal line Contor1 is configured as any one of the signal opposite to the first light emission control signal or the second scanning signal.
  • the first switch transistor will not be turned on in the light-emitting stage, and only turned on in the data writing and threshold compensation stage and the initialization stage In this way, the risk of leakage current generated by the first transistor T1 can be effectively reduced, and the service life of the first transistor T1 can be prolonged.
  • the second scan signal is written into the first control signal line Contor1
  • the gate and the source of the first transistor T1 can be connected together through a signal line to provide the second scan signal for both. In this case, Helps with wiring on the display panel.
  • the data writing sub-circuit 4 includes a fourth transistor T4; the source of the fourth transistor T4 is connected to the data line Data, the drain of the fourth transistor T4 is connected to the source of the driving transistor T3, and the drain of the fourth transistor T4 is connected to the source of the driving transistor T3.
  • the gate is connected to the first scan line Gate1.
  • the first scan line Gate1 can be written with a low level signal, the fourth transistor T4 is turned on, and the data voltage signal written on the data line Data is written into the source of the driving crystal , until the gate-source voltage Vgs of the driving transistor T3 reaches the threshold voltage.
  • the first lighting control sub-circuit 5 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first power supply voltage line Vdd, the drain of the fifth transistor T5 is connected to the source of the driving transistor T3, The gate of the fifth transistor T5 is connected to the first control signal line EM1.
  • the first control signal line EM1 writes a low-level signal
  • the fifth transistor T5 is turned on
  • the first voltage on the first power supply voltage line Vdd is transmitted to the source of the driving transistor T3, so that the driving transistor T3 outputs the driving current to the second light-emitting control sub-circuit 6,
  • the second light-emitting control sub-circuit 6 works simultaneously, outputs the driving current to the first electrode of the light-emitting device D, and causes the light-emitting device D to emit light.
  • the second light-emitting control sub-circuit 6 includes a sixth transistor T6; the source of the sixth transistor T6 is connected to the drain of the driving transistor T3, and the drain of the sixth transistor T6 is connected to the first electrode of the light-emitting device D , the gate of the sixth transistor T6 is connected to the second control signal line EM1 ′.
  • the second control signal line EM1' writes a low-level signal
  • the sixth transistor T6 is turned on
  • the driving current output by the driving transistor T3 is output to the first electrode of the light-emitting device D, so that the light-emitting device D emits light.
  • the reset sub-circuit 7 includes a seventh transistor T7; the source of the seventh transistor T7 is connected to the first electrode of the light emitting device D, the drain of the seventh transistor T7 is connected to the initialization signal line Init, and the seventh transistor T7 The gate is connected to the second scan line Gate1'.
  • the seventh transistor T7 is turned on, and the auxiliary function sub-circuit 9 and the second light-emitting control sub-circuit 6 also work, the initialization signal line Init writes the initialization signal to reset the first electrode of the light-emitting device D, and at the same time, the first electrode of the light-emitting device D is reset.
  • the gate of the drive transistor T3 is reset.
  • the storage sub-circuit 8 includes a storage capacitor Cst, the first plate of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is connected to the first power supply voltage line Vdd.
  • the data writing subcircuit 4 writes the data voltage signal into the source of the driving transistor T3, and the storage capacitor Cst stores the data voltage signal.
  • the pixel driving circuit includes: a data writing sub-circuit 4, a driving sub-circuit 3, a first light-emitting control sub-circuit 5, a second light-emitting control sub-circuit 6, an auxiliary function sub-circuit 9, a reset Sub-circuit 7, storage sub-circuit 8.
  • the data writing sub-circuit 4 includes a fourth transistor T4; the driving sub-circuit 3 includes a driving transistor T3; the first light-emitting control sub-circuit 5 includes a fifth transistor T5; the second light-emitting control sub-circuit 6 includes a sixth transistor T6; The sub-circuit 7 includes a seventh transistor T7; the auxiliary function sub-circuit 9 includes a first transistor T1 and a second transistor T2; and the storage sub-circuit 8 includes a storage capacitor Cst.
  • the source of the first transistor T1 is connected to the drain of the second transistor T2, the drain of the first transistor T1 is connected to the gate of the driving transistor T3, and the gate of the first transistor T1 is connected to the first control signal line Contorl , the first control line is configured to be input with a low level signal during a frame display period.
  • the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the gate of the second transistor T2 is connected to the second scan line Gate1'.
  • the source of the fourth transistor T4 is connected to the data line Data, the drain of the fourth transistor T4 is connected to the source of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the first scan line Gate1.
  • the source of the fifth transistor T5 is connected to the first power supply voltage line Vdd
  • the drain of the fifth transistor T5 is connected to the source of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the first control signal line EM1.
  • the source of the sixth transistor T6 is connected to the drain of the driving transistor T3, the drain of the sixth transistor T6 is connected to the first electrode of the light emitting device D, and the gate of the sixth transistor T6 is connected to the second control signal line EM1'.
  • the source of the seventh transistor T7 is connected to the first electrode of the light emitting device D
  • the drain of the seventh transistor T7 is connected to the initialization signal line Init
  • the gate of the seventh transistor T7 is connected to the reset signal line Reset.
  • the first plate of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second substrate of the storage capacitor Cst is connected to the first power supply voltage line Vdd.
  • FIG. 4 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure. As shown in FIG. 4 , when the above pixel driving circuit is applied to a display panel, each pixel driving circuit in the display panel Arranged in an array, at this time, the gates of the fourth transistors T4 of the pixel driving circuits located in the same row are connected to the same first scan line Gate1, the gates of the first transistors T1 are connected to the same first control signal line, and the second transistors are connected to the same first control signal line.
  • the gate of T2 is connected to the same second scanning line Gate1', the gate of the fifth transistor T5 is connected to the same first light-emitting control line EM1, the gate of the sixth transistor T6 is connected to the same second light-emitting control line EM1', and the gate of the sixth transistor T6 is connected to the same second light-emitting control line EM1'.
  • the gates of the seven transistors T7 are connected to the same reset signal line Reset.
  • the source of the fourth transistor T4 in the pixel driving circuit in the same column is connected to the same data line Data, and the source of the fifth transistor T5 and the second plate of the storage capacitor Cst are connected to the same first power signal line Vdd.
  • the first scan line Gate(N+1) connected to the pixel driving circuit in the N+1 row can be multiplexed into the pixel driving circuit in the Nth row.
  • the connected second scan line Gate(N)' and the reset signal line Reset(N); the first light-emitting control line EM(N+1) connected to the pixel driving circuit in the N+1 row is multiplexed for the Nth row pixel driving
  • the second light-emitting control line EM(N)' to which the circuit is connected; N is an integer greater than or equal to 1.
  • the driving process of a pixel driving circuit located in the Nth row is described as an example.
  • the gate of the second transistor T2 and the gate of the seventh transistor T7 in the pixel driving circuit are both connected to the first scanning line Gate(N-1) connected to the pixel driving circuit in the N-1th row as an example.
  • the gate of the sixth transistor T6 in the pixel driving circuit is connected to the first light-emitting control line EM(N-1) connected to the pixel units in the N-1th row.
  • FIG. 5 is a working timing diagram of the pixel driving circuit shown in FIG. 4 ; with reference to FIG. 4 and FIG. 5 , the driving method of the pixel driving circuit includes the following stages:
  • FIG. 6 is a schematic diagram of the transistor conduction state in the initialization stage of the pixel driving circuit of FIG. 4.
  • the control line EM(N-1) inputs a low-level signal
  • the first control signal line Contor1(N) inputs a low-level signal.
  • the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 is turned on, and the initialization signal line Init writes a high-level signal.
  • the first electrode (N4 node) of the light-emitting device D, the drain (N3 node) of the driving transistor T3 and the gate (N1 node) of the driving transistor T3 are all is a high-level signal, thereby completing the reset of the gate of the driving transistor T3 and the first electrode of the light-emitting device D.
  • FIG. 7 is a schematic diagram of the transistor conduction state in the data writing and threshold compensation stage of the pixel drive circuit of FIG. 4.
  • the first scan line of row N-1 is shown in FIG. Gate(N-1) continues to be input with a low-level signal
  • the first scan line Gate(N) in the Nth row is also written with a low-level signal
  • the first light-emitting control line in the N-1th row is also written.
  • Both EM(N-1) and the first light-emitting control line EM(N) of the Nth row are written with a high-level signal
  • the first control signal line Contor1(N) continues to input a low-level signal.
  • the first transistor T1, the second transistor T2, the driving transistor T3 and the fourth transistor T4 are all turned on, the driving transistor T3 is connected by the first transistor T1 and the second transistor T2 to form a diode structure, and the data voltage written on the data line Data passes through the fourth transistor T4, the first transistor T1 and the second transistor T2 write to the gate of the driving transistor T3 until the driving transistor T3 is turned off.
  • the gate (N1 node) voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3 ), and is stored in the storage capacitor Cst.
  • the voltages of the first plate and the second plate of the storage capacitor Cst are Vdata+Vth and Vdd, respectively.
  • FIG. 8 is a schematic diagram of the transistor conduction state in the data continuous writing stage of the pixel drive circuit of FIG. 4.
  • the first scan line Gate (N- 1) A high-level signal is input, the first scanning line Gate(N) of the Nth row continues to write a low-level signal, the first light-emitting control line EM(N-1) of the N-1th row and the Nth row
  • the first light-emitting control lines EM(N) are all written with high-level signals, and the first control signal line Contor1(N) continues to input low-level signals.
  • FIG. 9 is a schematic diagram of the transistor conduction state in the pre-emission stage of the pixel driving circuit of FIG. 4.
  • the first scanning lines Gate(N) of the N rows are all input with a high level signal
  • the first light emission control line EM(N-1) of the N-1th row is written with a low level signal
  • the first scan line of the Nth row The light-emitting control line EM(N) is still written with a high-level signal
  • the first control signal line Contor1(N) continues to input a low-level signal.
  • FIG. 10 is a schematic diagram of the transistor conduction state in the light-emitting stage of the pixel driving circuit of FIG. 4.
  • the first scanning line Gate (N-1) of the N-1th row and the Nth row The first scanning line Gate(N) of the 1st scan line is input with a high level signal, and the first light-emitting control line EM(N-1) of the N-1th row and the first light-emitting control line EM(N) of the Nth row are both connected to
  • the first control signal line Contor1(N) continues to input a low-level signal.
  • the fifth transistor T5, the driving transistor T3, and the sixth transistor T6 are all turned on, and the light-emitting device D is driven to emit light.
  • the light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows:
  • the current of the light-emitting device DD has nothing to do with the threshold voltage of the driving transistor T3 in the light-emitting stage, so as to avoid the influence of the threshold voltage of the driving transistor T3 on the display uniformity of the display panel.
  • the structure of the pixel driving circuit is the same as that of the pixel driving circuit shown in FIG. 4 , except that the signal input by the first control signal line during the display period of one frame of image is the same as that of the first control signal line.
  • the opposite signal of the light-emitting control line Taking driving a pixel driving circuit in the Nth row as an example, FIG. 11 is another working timing diagram of the pixel driving circuit in FIG. 4; as shown in FIG. 11, the first light-emitting control line Contor1(N) is only initialized Low level signals are written in the phase, the data writing and threshold compensation phase and the data continuous writing phase, that is, the first transistor T1 only works in these three phases, and the first transistor T1 is turned off in other phases.
  • the auxiliary function sub-circuit 9 only needs to work in the initialization stage and the data writing and threshold compensation stage, so as to realize the reset of the gate of the driving transistor T3 and the operation of the driving transistor T3 Therefore, compared with the first control signal, the low-level signal is continuously input.
  • This implementation method helps to prolong the service life of the first transistor T1, and can also avoid the leakage current generated by the first transistor T1 being turned on for a long time.
  • the respective driving methods of the pixel driving circuit are the same as the above-mentioned methods, so the description is not repeated here.
  • FIG. 12 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure; as shown in FIG. 12 , the structure of the pixel driving circuit is the same as that of the pixel driving circuit shown in FIG. 4 , The only difference is that the signal input by the first light-emitting control line Contor1(N) during the display period of one frame of image is the second scanning signal Gate(N), that is, the second scanning signal line can also be multiplexed into the first scanning signal line. Glowing control lines.
  • FIG. 13 is a working timing diagram of the pixel driving circuit of FIG. 12 ; as shown in FIG.
  • the first control signal line is only in the initialization stage, data writing and threshold value
  • the compensation stage is written with a low level signal, that is, the first transistor T1 only works in these two stages, and the first transistor T1 is in an off state in other stages.
  • the auxiliary function sub-circuit 9 only needs to work in the initialization stage and the data writing and threshold compensation stage, so as to realize the reset of the gate of the driving transistor T3 and the operation of the driving transistor T3 Therefore, compared with the first control signal, the low-level signal is continuously input.
  • This implementation method helps to prolong the service life of the first transistor T1, and can also avoid the leakage current generated by the first transistor T1 being turned on for a long time. .
  • the first control signal line Contor1(N) and the second scan line Gate(N) are multiplexed, and the wiring of the display panel to which the pixel driving circuit is applied can also be optimized.
  • the respective driving methods for the pixel driving circuit are the same as the above-mentioned methods, so the description is not repeated here.
  • FIG. 14 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure; as shown in FIG. 14 , the structure of the pixel driving circuit is substantially similar to the structure of the pixel driving circuit in FIG. 4 described above, and the difference is only In the structure of the auxiliary function sub-circuit 9, although the auxiliary function sub-circuit 9 includes the first transistor T1 and the second transistor T2 like the pixel driving circuit shown in FIG. 4, the connection relationship between the first transistor T1 and the second transistor T2 is different. Referring to FIG.
  • the source of the first transistor T1 of the auxiliary function sub-circuit 9 is connected to the second scan line, the drain of the first transistor T1 is connected to the gate of the second transistor T2, and the drain of the first transistor T1 is connected to the gate of the second transistor T2.
  • the gate is connected to the first light-emitting control line; the source of the second transistor T2 is connected to the gate of the driving transistor T3, and the drain of the second transistor T2 is connected to the drain of the driving transistor T3.
  • the signal input to the first control signal line in the scanning period of one frame of image is the opposite signal to the first light emission control signal.
  • the gates of the fourth transistors T4 of the pixel driving circuits located in the same row are connected to The same first scan line
  • the gate of the first transistor T1 is connected to the same first control signal line Contor1
  • the source of the first transistor T1 is connected to the same second scan line Gate1'
  • the gate of the fifth transistor T5 is connected to the same A first light-emitting control line EM1
  • the gate of the sixth transistor T6 is connected to the same second light-emitting control line EM1'
  • the gate of the seventh transistor T7 is connected to the same reset signal line Reset.
  • the source of the fourth transistor T4 in the pixel driving circuit in the same column is connected to the same data line Data, and the source of the fifth transistor T5 and the second plate of the storage capacitor Cst are connected to the same first power signal line Vdd.
  • the first scan line Gate(N+1) connected to the pixel driving circuit in the N+1 row can be multiplexed into the pixel driving circuit in the Nth row.
  • the driving process of a pixel driving circuit located in the Nth row is described as an example.
  • the gate of the second transistor T2 and the gate of the seventh transistor T7 in the pixel driving circuit are both connected to the first scanning line Gate(N-1) connected to the pixel driving circuit in the N-1th row as an example.
  • the gate of the sixth transistor T6 in the pixel driving circuit is connected to the first light-emitting control line EM(N-1) connected to the pixel units in the N-1th row.
  • the timing shown in FIG. 11 can also be used as the working timing diagram of the pixel driving circuit shown in FIG. 14 ; with reference to FIG. 14 and FIG. 11 , the driving method of the pixel driving circuit includes the following stages:
  • FIG. 15 is a schematic diagram of the transistor conduction state in the initialization stage of the pixel drive circuit of FIG. 14.
  • the control line EM(N-1) inputs a low-level signal
  • the first control signal line Contor1(N) inputs a low-level signal.
  • the first transistor T1, the sixth transistor T6, and the seventh transistor T7 are turned on.
  • the source of a transistor T1 is connected to the first scan line Gate(N-1) in the N-1th row, so the second transistor T2 is also turned on.
  • the initialization signal line Init writes a high-level signal.
  • the first electrode (N4 node) of the light-emitting device D, the drain (N3 node) of the driving transistor T3 and the gate (N1 node) of the driving transistor T3 are all high-level signals, so as to complete the gate of the driving transistor T3 and reset of the first electrode of the light emitting device D.
  • FIG. 16 is a schematic diagram of the transistor conduction state in the data writing and threshold compensation stage of the pixel drive circuit of FIG. 14.
  • the first scan line of the N-1th row Gate(N-1) continues to be input with a low-level signal
  • the first scan line Gate(N) in the Nth row is also written with a low-level signal
  • the first light-emitting control line in the N-1th row is also written.
  • Both EM(N-1) and the first light-emitting control line EM(N) of the Nth row are written with a high-level signal
  • the first control signal line Contor1(N) continues to input a low-level signal.
  • the first transistor T1, the second transistor T2, the driving transistor T3 and the fourth transistor T4 are all turned on, the driving transistor T3 is connected by the first transistor T1 and the second transistor T2 to form a diode structure, and the data voltage written on the data line Data passes through the fourth transistor T4, the first transistor T1 and the second transistor T2 write to the gate of the driving transistor T3 until the driving transistor T3 is turned off.
  • the gate (N1 node) voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3 ), and is stored in the storage capacitor Cst.
  • the voltages of the first plate and the second plate of the storage capacitor Cst are Vdata+Vth and Vdd, respectively.
  • FIG. 17 is a schematic diagram of the transistor conduction state in the data continuous writing stage of the pixel drive circuit of FIG. 14.
  • the first scan line Gate (N- 1) A high-level signal is input, the first scanning line Gate(N) of the Nth row continues to write a low-level signal, the first light-emitting control line EM(N-1) of the N-1th row and the Nth row
  • the first light-emitting control lines EM(N) are all written with high-level signals, and the first control signal line Contor1(N) continues to input low-level signals.
  • FIG. 18 is a schematic diagram of the transistor conduction state in the pre-emission stage of the pixel driving circuit of FIG. 14. As shown in FIG. The first scanning lines Gate(N) of the N rows are all input with a high level signal, the first light emission control line EM(N-1) of the N-1th row is written with a low level signal, and the first scan line of the Nth row The light-emitting control line EM(N) is still written with a high-level signal, and the first control signal line Contor1(N) continues to input a low-level signal.
  • FIG. 19 is a schematic diagram of the transistor conduction state in the light-emitting stage of the pixel driving circuit of FIG. 14.
  • the first scanning line Gate (N-1) of the N-1th row and the Nth row The first scanning line Gate(N) of the 1st scan line is input with a high level signal, and the first light-emitting control line EM(N-1) of the N-1th row and the first light-emitting control line EM(N) of the Nth row are both connected to
  • the first control signal line continues to input a low level signal to Contor1(N).
  • the light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows:
  • the current of the light-emitting device DD has nothing to do with the threshold voltage of the driving transistor T3 in the light-emitting stage, so as to avoid the influence of the threshold voltage of the driving transistor T3 on the display uniformity of the display panel.
  • FIG. 20 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure; as shown in FIG. 20 , the structure of the pixel driving circuit is substantially the same as that of the pixel driving circuit shown in FIG. 14 , except that,
  • the signal written in the first control signal line of the pixel driving circuit is the second scan signal, that is, the second scan signal line can be multiplexed with the first control signal line, and the gate of the first transistor T1 and the gate of the first transistor T1 can be combined with The sources are connected together.
  • the other functional modules in the pixel driving circuit may be the same as the functional modules of the pixel driving circuit described above, so they will not be described in detail here.
  • the timing diagram of FIG. 13 can also be used as the working timing diagram of the pixel driving circuit shown in FIG. 20; as shown in FIG. 13, the first control signal line is only initialized Phases, data writing and threshold compensation phases are written with low-level signals, that is, the first transistor T1 only works in these two phases, and the first transistor T1 is in an off state in other phases.
  • the auxiliary function sub-circuit 9 only needs to work in the initialization stage and the data writing and threshold compensation stage, so as to realize the reset of the gate of the driving transistor T3 and the operation of the driving transistor T3 The threshold value of the first transistor T1 is compensated.
  • This implementation manner helps to prolong the service life of the first transistor T1, and can also avoid the leakage current caused by the first transistor T1 being turned on for a long time.
  • the first control signal line and the second scan line are multiplexed, and the wiring of the display panel to which the pixel driving circuit is applied can also be optimized.
  • the respective driving methods of the pixel driving circuit are the same as the above-mentioned methods, so the description is not repeated here.
  • an embodiment of the present disclosure provides a display panel, and a pixel driving circuit in the display panel can adopt any of the above-mentioned pixel driving circuits.
  • the pixel driving circuits are arranged in an array; when the auxiliary sub-circuit includes a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the drain of the second transistor T2, and the The drain is connected to the gate of the driving transistor T3, the gate of the first transistor T1 is connected to the first control signal line; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the gate of the second transistor T2 is connected to the second scan Wire.
  • each data writing sub-circuit 4 is connected to the same first scan line; each first light-emitting control sub-circuit 5 is connected to the same first light-emitting control line, and each second light-emitting control sub-circuit 6 is connected to The same second light-emitting control line, the control electrode of the first transistor T1 in each auxiliary function sub-circuit 9 is connected to the same first control signal line, and the control electrode of the second transistor T2 is connected to the same second scanning line; Circuit 7 is connected to the same reset signal line Reset.
  • each data writing subcircuit 4 is connected to the same data line Data; each first light emission control subcircuit 5 and each storage subcircuit 8 are connected to the same first power supply signal line; each reset subcircuit 7 Connect the same initialization signal line Init.
  • the first scan line connected to the pixel driving circuit in the N+1th row is multiplexed into the second scan line and the reset signal line Reset connected to the pixel driving circuit in the Nth row;
  • the first light-emitting control line is multiplexed into the second light-emitting control line connected to the pixel driving circuit in the Nth row;
  • N is an integer greater than or equal to 1.
  • the first control signal line in the display period of one frame of image, can write a low-level signal, and also can write a signal opposite to the second light-emitting control line.
  • the auxiliary sub-circuit when the auxiliary sub-circuit includes a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the drain of the second transistor T2, and the drain of the first transistor T1 is connected to the drain of the driving transistor T3 The gate of the first transistor T1 is connected to the first control signal line; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the gate of the second transistor T2 is connected to the second scan line.
  • the first scan lines connected to the pixel driving circuits in the N+1 row are also multiplexed into the first control signal lines connected to the pixel driving circuits in the Nth row. That is, the gates of the first transistors T1 located in the same row can be connected to the gates of the second transistors T2, so that the wiring space of the display panel can be optimized.
  • the pixel driving circuits are arranged in an array; when the auxiliary sub-circuit includes a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the second scan line, and the drain of the first transistor T1 The gate of the second transistor T2 is connected to the gate of the first transistor T1, and the gate of the first transistor T1 is connected to the first control signal line; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the source of the second transistor T2 is connected to the driving transistor T3. gate.
  • each data writing sub-circuit 4 is connected to the same first scan line; each first light-emitting control sub-circuit 5 is connected to the same first light-emitting control line, and each second light-emitting control sub-circuit 6 is connected to The same second light-emitting control line, the gate of the first transistor T1 in each auxiliary function sub-circuit 9 is connected to the same first control signal line; each reset sub-circuit 7 is connected to the same reset signal line Reset; each auxiliary function sub-circuit is connected to the same reset signal line Reset; The source of the first transistor T1 in 9 is connected to the same second scan line.
  • each data writing subcircuit 4 is connected to the same data line Data; each first light emission control subcircuit 5 and each storage subcircuit 8 are connected to the same first power supply signal line; each reset subcircuit 7 Connect the same initialization signal line Init.
  • the auxiliary sub-circuit includes a first transistor T1 and a second transistor T2; the source of the first transistor T1 is connected to the second scan line, the drain of the first transistor T1 is connected to the gate of the second transistor T2, and the first transistor T1 is connected to the gate of the second transistor T2.
  • the gate of T1 is connected to the first control signal line; the source of the second transistor T2 is connected to the drain of the driving transistor T3, and the source of the second transistor T2 is connected to the gate of the driving transistor T3.
  • the first scan line connected to the pixel drive circuit in the N+1th row is multiplexed into the second scan line connected to the pixel drive circuit in the Nth row and the reset signal line Reset; the first scan line connected to the pixel drive circuit in the N+1th row
  • the light-emitting control line is multiplexed into a second light-emitting control line connected to the pixel driving circuit in the Nth row; N is an integer greater than or equal to 1.
  • the display panel of this embodiment includes the above-mentioned pixel driving circuit, the display effect is better, and high-resolution display can be realized.
  • the display panel may be a liquid crystal display device or an electroluminescent display device, such as liquid crystal panel, OLED panel, Micro LED panel, Mini LED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. Any product or part that has a display function.

Abstract

一种像素驱动电路及显示面板，属于显示技术领域。像素驱动电路包括：数据写入子电路(4)、驱动子电路(3)、复位子电路(7)、第一发光控制子电路(5)、第二发光控制子电路(6)、辅助功能子电路(9)及存储子电路(8)；数据写入子电路(4)被配置为响应于第一扫描信号，将数据电压写入驱动子电路(3)的第一极；辅助功能子电路(9)被配置对驱动晶体管(T3)的阈值电压进行补偿；复位子电路(7)被配置为响应于复位控制信号，对待驱动的发光器件(D)的第一电极进行初始化，第二发光控制子电路(6)响应于第二发光控制信号，将初始化信号传输至驱动子电路(3)的第二极；第一发光控制子电路(5)被配置为响应于第一发光控制信号，将第一电源电压写入驱动晶体管(T3)的第一极，以使驱动晶体管(T3)产生驱动电流；第二发光控制子电路(6)被配置为响应于第二发光控制信号，将驱动电流传输给待驱动的发光器件(D)。

Description

像素驱动电路及显示面板 技术领域
本发明属于显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
随着显示器技术发展和更新换代，有机电致发光显示器件(Organic Electroluminance Display，简称为：OLED)由于具有自发光、高亮度、高对比度、低工作电压、可制作柔性显示器等特点，已经逐渐成为显示领域的主流产品。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种像素驱动电路及显示面板。
第一方面，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路、驱动子电路、复位子电路、第一发光控制子电路、第二发光控制子电路、辅助功能子电路及存储子电路；其中，
所述驱动子电路包括驱动晶体管，被配置根据其第一极和控制极的电压而生成驱动电路，以对待驱动的发光器件进行驱动；
在数据写入和阈值补偿阶段，所述数据写入子电路被配置为响应于第一扫描信号，而将数据电压写入所述驱动子电路的第一极；所述辅助功能子电路被配置对驱动晶体管的阈值电压进行补偿；所述存储子电路被配置为对所述数据电压进行存储；
在初始化阶段，所述辅助功能子电路被配置将所述驱动晶体管的控制极和第二极短接；所述复位子电路被配置响应于复位控制信号，并通过初始信号对所述待驱动的发光器件的第一电极进行初始化，第二发光控制子电路响应于第二发光控制信号，将所述初始化信号传输至所述驱动子电路的第二极；
在发光阶段，所述第一发光控制子电路被配置为响应于第一发光控制信号，将第一电源电压写入所述驱动晶体管的第一极，以使所述驱动晶体管产生驱动电流；所述第二发光控制子电路被配置为响应于第二发光控制信号，而将所述驱动电流传输给所述待驱动的发光器件。
其中，所述辅助功能子电路包括：第一晶体管和第二晶体管；
所述第一晶体管的第一极连接所述第二晶体管的第二极，第二极连接所述驱动晶体管的控制极，控制极连接第一控制信号线；
所述第二晶体管的第一极连接所述驱动晶体管的第二极，控制极连接第二扫描线。
其中，在一帧图像的扫描周期内，所述第一控制信号线被配置为写入以下任一信号：
工作电平信号；
与第一发光控制信号相反的信号；
第二扫描信号。
其中，所述辅助功能子电路包括：第一晶体管和第二晶体管；
所述第一晶体管的第一极连接所述第二扫描线，第二极连接所述第二晶体管的控制极，控制极连接第一控制信号线；
所述第二晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述驱动晶体管的控制极。
其中，在一帧图像的扫描周期内，所述第一控制信号线被配置为写入与第一发光控制信号相反的信号或者第二扫描信号。
其中，所述数据写入子电路包括第四晶体管；
所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，控制极连接第一扫描线。
其中，所述第一发光控制子电路包括：第五晶体管；
所述第五晶体管的第一极连接第一电源电压线，第二极连接所述驱动晶体管的第一极，控制极连接第一发光控制线。
其中，所述第二发光控制子电路包括：第六晶体管；
所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述带驱动的发光器件的第一电极，控制极连接第二发光控制线。
其中，所述复位子电路包括：第七晶体管；
所述第七晶体管的第一极连接所述带驱动的发光器件的第一电极，第二极连接初始化信号线，控制极连接复位信号线。
其中，存储子电路包括：存储电容；
所述存储电容的第一极板连接所述驱动晶体管的控制极，第二极板连接二所述第一电源电压线。
第二方面，本公开实施例提供一种显示面板，其包括上述的像素驱动电路。
其中，所述像素驱动电路呈阵列排布；所述辅助子电路包括第一晶体管和第二晶体管；所述第一晶体管的第一极连接所述第二晶体管的第二极，第二极连接所述驱动晶体管的控制极，控制极连接第一控制信号线；所述第二晶体管的第一极连接所述驱动晶体管的第二极，控制极连接第二扫描线；
对于位于同一行的所述像素驱动电路，各所述数据写入子电路连接同一条第一扫描线；各所述第一发光控制子电路连接同一条第一发光控制线，各所述第二发光控制子电路连接同一条所述第二发光控制线，各所述辅助功能子电路中的第一晶体管的控制极连接同一条所述第一控制信号线，第二晶体管的控制极连接同一条所述第二扫描线；各所述复位子电路连接同一条所述复位信号线；
对于位于同一列的所述像素驱动电路，各所述数据写入子电路连接同一条数据线；各所述第一发光控制子电路和各所述存储子电路连接同一条第一电源信号线；各所述复位子电路连接同一条初始化信号线；
其中，第N+1行所述像素驱动电路所连接的所述第一扫描线复用为第N行所述像素驱动电路所连接的所述第二扫描线和所述复位信号线；第N+1行所述像素驱动电路所连接的第一发光控制线复用为第N行所述像素驱动电路所连接的所述第二发光控制线；N为大于或者等于1的整数。
其中，第N+1行所述像素驱动电路所连接的所述第一扫描线还复用为第N行所述像素驱动电路所连接的第一控制信号线。
其中，所述像素驱动电路呈阵列排布；所述辅助子电路包括第一晶体管和第二晶体管；所述第一晶体管的第一极连接所述第二扫描线，第二极连接所述第二晶体管的控制极，控制极连接第一控制信号线；所述第二晶体管的第一极连接所述驱动晶体管的第二极，第一极连接所述驱动晶体管的控制极；
对于位于同一行的所述像素驱动电路，各所述数据写入子电路连接同一条第一扫描线；各所述第一发光控制子电路连接同一条第一发光控制线，各所述第二发光控制子电路连接同一条所述第二发光控制线，各所述辅助功能子电路中的第一晶体管的控制极连接同一条所述第一控制信号线；各所述复位子电路连接同一条所述复位信号线；各所述辅助功能子电路中的第一晶体管的第一极连接同一条所述第二扫描线；
对于位于同一列的所述像素驱动电路，各所述数据写入子电路连接同一条数据线；各所述第一发光控制子电路和各所述存储子电路连接同一条第一电源信号线；各所述复位子电路连接同一条初始化信号线；
其中，第N+1行所述像素驱动电路所连接的所述第一扫描线复用为第N行所述像素驱动电路所连接的所述第二扫描线和所述复位信号线；第N+1行所述像素驱动电路所连接的第一发光控制线复用为第N行所述像素驱动电路所连接的所述第二发光控制线；N为大于或者等于1的整数。
其中，第N+1行所述像素驱动电路所连接的所述第一扫描线还复用为第N行所述像素驱动电路所连接的第一控制信号线。
附图说明
图1为一种示例性的像素驱动电路的示意图。
图2为本公开实施例的一种像素驱动电路的示意图。
图3为本公开实施例的另一种像素驱动电路的示意图。
图4为本公开实施例的另一种像素驱动电路的示意图。
图5为图4所示的像素驱动电路的一种工作时序图。
图6为图4的像素驱动电路初始化阶段的晶体管导通状态示意图。
图7为图4的像素驱动电路数据写入及阈值补偿阶段的晶体管导通状态示意图。
图8为图4的像素驱动电路数据持续写入阶段的晶体管导通状态示意图。
图9为图4的像素驱动电路预发光阶段的晶体管导通状态示意图。
图10为图4的像素驱动电路发光阶段的晶体管导通状态示意图。
图11为图4的像素驱动电路的另一种工作时序图。
图12为本公开实施例的另一种像素驱动电路的示意图。
图13为图12的像素驱动电路的工作时序图。
图14为本公开实施例的另一种像素驱动电路的示意图。
图15为图14的像素驱动电路初始化阶段的晶体管导通状态示意图。
图16为图14的像素驱动电路数据写入及阈值补偿阶段的晶体管导通状态示意图。
图17为图14的像素驱动电路数据持续写入阶段的晶体管导通状态示意图。
图18为图14的像素驱动电路预发光阶段的晶体管导通状态示意图。
图19为图14的像素驱动电路发光阶段的晶体管导通状态示意图。
图20为本公开实施例的另一种像素驱动电路的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描 述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
应当理解的是，由于本公开实施例中采用的晶体管为P型晶体管，因此工作电平信号则对应低电平信号，非工作电平信号则对应高电平信号。
另外，本公开实施例中的发光器件可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)，当然，在发明实施例中的发光器件还可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。发光器件的第一电极和第二电极中的一者为阳极，另一者为阴极；在本发明实施例中以发光器件的第一电极为阳极，第二电极为阴极为例进行说明。
图1为一种示例性的像素驱动电路的示意图，如图1所示，该像素驱动电路包括驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、数据写入子电路4、存储子电路8、阈值补偿子电路2、第一复位子电路1和第二复位子电路7；其中，驱动子电路3可以为驱动晶体管T4，其被配置为根据栅源电压Vgs，而将驱动电流输出给待驱动的发光器件D。
其中，第一发光控制子电路5分别与第一电源电压线VDD以及驱动驱动晶体管T4的源极相连，且被配置为实现驱动晶体管T4和第一电压端VDD之间的连接导通或断开，第二发光控制子电路6分别与驱动晶体管T4的漏极和发光器件D的第一电极D1电连接，且被配置为实现驱动子电路3和发光器件D之间的连接导通或断开。数据写入子电路4与驱动晶体管T4的源极电连接，且被配置为在第一扫描信号的控制下将数据信号写入存储子电路7。存储子电路8分别与驱动晶体管T4的栅极和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿子电路2分别与驱动晶体管T4的栅极和漏极电连接，且被配置为对驱动晶体管T4进行阈值补偿。第一复位子电路1与驱动晶体管T4的栅极电连接，被配置为在第一复位信号的控制下对驱动晶体管T4的栅极进行复位。第二复位子电路7与发光器件D的第一电 极电连接，第二复位控制信号的控制下对发光器件D的第一电极进行复位。
继续参照图1，数据写入子电路4包括第四晶体管T4，存储子电路8包括存储电容Cst，阈值补偿子电路2包括第二晶体管T2，第一发光控制子电路5包括第五晶体管T5，第二发光控制子电路6包括第六晶体管T6，第一复位子电路1包括第一晶体管T1，第二复位子电路包括第七晶体管T7。
继续参照图2，第四晶体管T4漏极的与驱动晶体管T3的源极电连接，第四晶体管T4的源极被配置为与数据线Data电连接以接收数据信号，第四晶体管T4的栅极被配置为与第一扫描信号线Gate1电连接以接收第一扫描信号；存储电容Cst的第一极板与第一电源信号线VDD电连接，存储电容Cst的第二极板与驱动晶体管T3的栅极电连接；第二晶体管T2的源极与驱动晶体管T3的漏极电连接，第二补偿晶体管T2的漏极与驱动晶体管T3的栅极电连接，第二补偿晶体管T2的栅极被配置为与第二扫描信号线Gate2电连接以接收补偿控制信号；第一晶体管T1的源极被配置为与第一初始化信号线Vinit1电连接以接收第一初始化信号，第一晶体管T1的漏极与驱动晶体管T3的栅极电连接，第一晶体管T1的栅极被配置为与第一复位控制信号线Reset1电连接以接收第一复位控制信号；第七晶体管T7的源极被配置为与第二初始化Vinit2电连接以接收第二初始化信号，第七晶体管T7的漏极与发光器件D的第一电极电连接，第七晶体管T7的栅极被配置为与第二复位控制信号线Reset2电连接以接收第二复位控制信号；第五晶体管T5的源极与第一电源电压线VDD电连接，第五晶体管T5的漏极与驱动晶体管T3的源极电连接，第一五晶体管T5的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第六控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第六控制晶体管T6的漏极与发光器件D的第一电极电连接，第六控制晶体管T6的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光器件D的第二电极与第二电源电压线VSS电连接。
例如，第一电源电压线VDD和第二电源电压线VSS之一连接高压端，另一个连接低压端。例如，，第一电源电压线VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源电压线VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源电压线VSS可以接地。
继续参照图2，扫描信号和补偿控制信号可以相同，即，第四晶体管T4的栅极和第二晶体管T2的栅极可以电连接到同一条信号线，例如第一扫描信号线Gate1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Gate2，减少信号线的数量。又例如，第四晶体管T4的栅极和第二晶体管T2的栅极也可以分别电连接至不同的信号线，即第四晶体管T4的栅极电连接到第一扫描信号线Gate1，第二晶体管T2的栅极电连接到第二扫描信号线Gate2，而第一扫描信号线Gate1和第二扫描信号线Gate2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得第四晶体管T4的栅极和第二晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。在本公开实施例中以第四晶体管T4的栅极和第二晶体管T2的栅极电连接第一扫描信号线Gate1为例进行说明。
继续参照图2，第一发光控制信号和第二发光控制信号可以相同，即，第五晶体管T5的栅极和第六晶体管T6的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第五晶体管T5的栅极和第六晶体管T6的栅极也可以分别电连接至不同的信号线，即，第五晶体管T5的栅极电连接到第一发光控制信号线EM1，第六晶体管T6的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第五晶体管T5和第六晶体管T6为不同类型的晶体管，例如，第五晶体管T5为P型晶体管，而第六晶体管T6为N型晶体管时， 第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。在本公开实施例中以第五晶体管T5和第六晶体管T6的栅极均连接第一发光控制线为例进行说明。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第一晶体管T1的栅极和第七晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Reset1，以接收相同的信号(例如，第一复位控制信号)，此时，显示基板可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一晶体管T1的栅极和第七晶体管T7的栅极也可以分别电连接至不同的信号线，即第一晶体管T1的栅极电连接到第一复位控制信号线Reset1，第七晶体管T7的栅极电连接到第二复位控制信号线Reset2，而第一复位控制信号线Reset1和第二复位控制信号线Reset2传输的信号相同。需要说明的是，第一复位控制信号和第二复位控制信号也可以不相同。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第七晶体管T7的栅极可以电连接到扫描信号线Gate以接收扫描信号作为第二复位控制信号。
例如，第一晶体管T1的源极和第七晶体管T7的漏极分别连接到第一初始化信号线Vinit1和第二初始化信号线Vinit2，第一初始化信号线Vinit1和第二初始化信号线Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一初始化信号线Vinit1和第二初始化信号线Vinit2可以相同，例如第一晶体管T1的源极和第七晶体管T7的源极连接到同一初始化信号线。第一初始化信号线Vinit1和第二初始化信号线Vinit2可以为高压端，也可以为低压端，只要其能够提供第一初始化信号和第二初始化信号以对驱动晶体管T3的栅极和发光元件的第一电极进行复位即可，本公开对此不作限制。例如，第一晶体管T1的源极和第七晶体管T7的源极可以均连接至初始化信号线Init。
需要说明的是，图2所示的像素电路中的驱动子电路3、数据写入子电路4、存储子电路8、阈值补偿子电路2和第一复位子电路1和第二复位子 电路7仅为示意性的，驱动子电路、数据写入子电路、存储子电路、阈值补偿子电路和复位子电路等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
在现有技术中，为了提高像素驱动电路中第一晶体管和第二开关晶体管的开关性能，通常这两个晶体管选用双栅型晶体管，但是双栅型晶体管的设计势必会对提高显示面板的分辨率造成影响，针对上述问题，在本公开实施例提供如下技术方案。
第一方面，图2为本公开实施例的一种像素驱动电路的示意图；图3为本公开实施例的另一种像素驱动电路的示意图；如图2和3所示，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路4、驱动子电路3、复位子电路7、第一发光控制子电路5、第二发光控制子电路6、辅助功能子电路9及存储子电路8；其中，驱动子电路3包括驱动晶体管T3，被配置根据其第一极和控制极的电压而生成驱动电路，以对待驱动的发光器件D进行驱动；在数据写入及阈值补偿阶段，数据写入子电路4被配置为响应于第一扫描信号，而将数据电压写入驱动子电路3的第一极；辅助功能子电路9被配置对驱动晶体管T3的阈值电压进行补偿；存储子电路8被配置为对数据电压进行存储；在初始化阶段，辅助功能子电路9被配置将驱动晶体管T3的栅极和源极短接；复位子电路7被配置响应于复位控制信号，并通过初始信号对待驱动的发光器件D的第一极进行初始化，第二发光控制子电路6响应于第二发光控制信号，将初始化信号传输至驱动子电路3的第二极；在发光阶段，第一发光控制子电路5被配置为响应于第一发光控制信号，将第一电源电压写入驱动晶体管T3的第一极，以使驱动晶体管T3产生驱动电流；第二发光控制子电路6被配置为响应于第二发光控制信号，而将驱动电流传输给待驱动的发光器件D。
在本公开实施例中，辅助功能子电路9不仅可以在数据接入阶段对驱动晶体管T3的阈值电压进行补偿，而且还可以在初始化阶段，配合第二发光子电路和复位子电路7对驱动晶体管T3的栅极进行复位，也即本公开实施 例中的辅助功能子电路9兼具阈值补偿和复位功能，因此实现了像素驱动电路的简化，有助于应用本公开实施例的显示面板实现高分辨率。
在一些实施例中，辅助功能子电路9包括第一晶体管T1和第二晶体管T2；其中，第一晶体管T1的源极连接第二晶体管T2的漏极，第一晶体管T1的漏极连接驱动晶体管T3的栅极，第一晶体管T1的栅极连接第一控制信号线Contorl；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的栅极连接第二扫描线Gate1'。第一控制信号线Contorl至少在初始化阶段和数据写入及阈值补偿阶段被写入低电平信号。
例如：在初始化阶段，复位子电路7在复位控制信号的控制下通过初始信号对所述待驱动的发光器件D的第一电极进行初始化，以使发光器件D的第一电极的电位为初始化电位，与此同时第二控制信号线EM1'、第二扫描线Gate1'和第一控制信号线Contorl均被写入低电平信号，第一晶体管T1和第二晶体管T2打开，驱动晶体管T3的栅极电位通过第一晶体管T1、第二晶体管T2和第二发光控制子电路6被复位为初始化电位。
在数据写入和阈值补偿阶段，第二扫描线Gate1'和第一控制信号线Contorl均被写入低电平信号，第一晶体管T1和第二晶体管T2打开，驱动晶体管T3的栅极和漏极被短接为二极管，通过数据线Data上所写入的数据电压对驱动晶体管T3的阈值电压进行补偿。
在一些实施例中，当辅助功能子电路9包括第一晶体管T1和第二晶体管T2；第一晶体管T1的源极连接第二晶体管T2的漏极，第一晶体管T1的漏极连接驱动晶体管T3的栅极，第一晶体管T1的栅极连接第一控制信号线Contorl；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的栅极连接第二扫描线Gate1'时，在一帧图像的扫描周期内，第一控制信号线Contorl被配置为写入工作电平信号、与第一发光控制信号相反的信号、第二扫描信号中的任意一种。其中，若第一控制信号线Contorl一直被写入工作电平信号，则第一晶体管T1在一帧扫描周期内均处于开启状态，该种情况时序简单，易于控制。若第一控制信号线Contorl被写入的信号为与第 一发光控制信号相反的信号，则第一开关晶体管在发光阶段不会开启，仅在数据写入及阈值补偿阶段和初始化阶段开启，这样一来，可以有效的降低第一晶体管T1产生漏电流的风险，且有助于延长第一晶体管T1的使用寿命。若第一控制信号线Contorl被写入第二扫描信号，此时可以将第一晶体管T1栅极和第二晶体管T2的栅极连接在一起通过一条信号线为二者提供第二扫描信号，该种情况下，有助于显示面板上的布线。
在一些实施例中，辅助功能子电路9包括：第一晶体管T1和第二晶体管T2；第一晶体管T1的源极连接所述第二扫描线Gate1'，第一晶体管T1的漏极连接第二晶体管T2的栅极，第一晶体管T1的栅极连接第一控制信号线Contorl；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的漏极连接驱动晶体管T3的栅极。
例如：在初始化阶段，复位子电路7在复位控制信号的控制下通过初始信号对所述待驱动的发光器件D的第一电极进行初始化，以使发光器件D的第一电极的电位为初始化电位，与此同时第二控制信号线EM1'、第二扫描线Gate1'和第一控制信号线Contorl均被写入低电平信号，第一晶体管T1和第二晶体管T2打开，驱动晶体管T3的栅极电位通过第一晶体管T1、第二晶体管T2和第二发光控制子电路6被复位为初始化电位。
在数据写入和阈值补偿阶段，第二扫描线Gate1'和第一控制信号线Contorl均被写入低电平信号，第一晶体管T1和第二晶体管T2打开，驱动晶体管T3的栅极和漏极被短接为二极管，通过数据线Data上所写入的数据电压对驱动晶体管T3的阈值电压进行补偿。
在一些实施例中，当辅助功能子电路9包括：第一晶体管T1和第二晶体管T2；第一晶体管T1的源极连接所述第二扫描线Gate1’，第一晶体管T1的漏极连接第二晶体管T2的栅极，第一晶体管T1的栅极连接第一控制信号线Contorl；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的漏极连接驱动晶体管T3的栅极时，在一帧图像的扫描周期内，第一控制信号线Contorl被配置为与第一发光控制信号相反的信号或者第二扫描信 号中的任意一种。其中，若第一控制信号线Contorl被写入的信号为与第一发光控制信号相反的信号，则第一开关晶体管在发光阶段不会开启，仅在数据写入及阈值补偿阶段和初始化阶段开启，这样一来，可以有效的降低第一晶体管T1产生漏电流的风险，且有助于延长第一晶体管T1的使用寿命。若第一控制信号线Contorl被写入第二扫描信号，此时可以将第一晶体管T1栅极和其源极连接在一起通过一条信号线为二者提供第二扫描信号，该种情况下，有助于显示面板上的布线。
在一些实施例中，数据写入子电路4包括第四晶体管T4；第四晶体管T4的源极连接数据线Data，第四晶体管T4的漏极连接驱动晶体管T3的源极，第四晶体管T4的栅极连接第一扫描线Gate1。
例如：在数据写入和阈值补偿阶段，第一扫描线Gate1可以被写入低电平信号，第四晶体管T4打开，数据线Data上所写入的数据电压信号被写入驱动晶体的源极，直至驱动晶体管T3的栅源电压Vgs为阈值电压为止。
在一些实施例中，第一发光控制子电路5包括第五晶体管T5，该第五晶体管T5的源极连接第一电源电压线Vdd，第五晶体管T5的漏极连接驱动晶体管T3的源极，第五晶体管T5的栅极连接第一控制信号线EM1。
例如：在发光阶段，第一控制信号线EM1写入低电平信号，第五晶体管T5打开，第一电源电压线Vdd上的第一电压被传输至驱动晶体管T3的源极，以使驱动晶体管T3将驱动电流输出至第二发光控制子电路6，且在发光阶段，第二发光控制子电路6同时工作，将驱动电流输出至发光器件D的第一电极，促使发光器件D发光。
在一些实施例中，第二发光控制子电路6包括第六晶体管T6；该第六晶体管T6的源极连接驱动晶体管T3的漏极，第六晶体管T6的漏极连接发光器件D的第一电极，第六晶体管T6的栅极连接第二控制信号线EM1'。
例如：在发光阶段，第二控制信号线EM1'写入低电平信号，第六晶体管T6开启，将驱动晶体管T3输出的驱动电流输出至发光器件D的第一电 极，促使发光器件D发光。
在一些实施例中，复位子电路7包括第七晶体管T7；该第七晶体管T7的源极连接发光器件D的第一电极，第七晶体管T7的漏极连接初始化信号线Init，第七晶体管T7的栅极连接第二扫描线Gate1'。
例如：在初始化阶段，第七晶体管T7打开，同时辅助功能子电路9和第二发光控制子电路6也工作，初始化信号线Init写入初始化信号对发光器件D的第一电极进行复位，同时对驱动晶体管T3的栅极进行复位。
在一些实施例中，存储子电路8包括存储电容Cst，该存储电容Cst的第一极板连接驱动晶体管T3的栅极，存储电容Cst的第二极板连接第一电源电压线Vdd。
例如：在数据写入和阈值补偿阶段，数据写入子电路4将数据电压信号写入驱动晶体管T3的源极，存储电容Cst对数据电压信号进行存储。
为清楚本公开实施例的像素驱动电路的具体结构，以下结合具体示例对本公开实施例的像素驱动电路进行说明。
在一个示例中，参照图2，该像素驱动电路包括：数据写入子电路4、驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、辅助功能子电路9、复位子电路7、存储子电路8。其中，数据写入子电路4包括第四晶体管T4；驱动子电路3包括驱动晶体管T3；第一发光控制子电路5包括第五晶体管T5；第二发光控制子电路6包括第六晶体管T6；复位子电路7包括第七晶体管T7；辅助功能子电路9包括第一晶体管T1和第二晶体管T2；存储子电路8包括存储电容Cst。
继续参照图2，第一晶体管T1的源极连接第二晶体管T2的漏极，第一晶体管T1的漏极连接驱动晶体管T3的栅极，第一晶体管T1的栅极连接第一控制信号线Contorl，该第一控制线被配置在一帧显示周期内，被输入低电平信号。第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的栅极连接第二扫描线Gate1’。第四晶体管T4的源极连接数据线Data，第 四晶体管T4的漏极连接驱动晶体管T3的源极，第四晶体管T4的栅极连接第一扫描线Gate1。第五晶体管T5的源极连接第一电源电压线Vdd，第五晶体管T5的漏极连接驱动晶体管T3的源极，第五晶体管T5的栅极连接第一控制信号线EM1。第六晶体管T6的源极连接驱动晶体管T3的漏极，第六晶体管T6的漏极连接发光器件D的第一电极，第六晶体管T6的栅极连接第二控制信号线EM1'。第七晶体管T7的源极连接发光器件D的第一电极，第七晶体管T7的漏极连接初始化信号线Init，第七晶体管T7的栅极连接复位信号线Reset。存储电容Cst的第一极板连接驱动晶体管T3的栅极，存储电容Cst的第二基板连接第一电源电压线Vdd。
需要说明的是，图4为本公开实施例的另一种像素驱动电路的示意图；如图4所示，当将上述像素驱动电路应用至显示面板中时，且显示面板中的各像素驱动电路呈阵列排布，此时位于同一行的像素驱动电路的第四晶体管T4的栅极连接同一条第一扫描线Gate1，第一晶体管T1的栅极连接同一条第一控制信号线，第二晶体管T2的栅极连接同一条第二扫描线Gate1'，第五晶体管T5的栅极连接同一条第一发光控制线EM1，第六晶体管T6的栅极连接同一条第二发光控制线EM1'，第七晶体管T7的栅极连接同一条复位信号线Reset。位于同一列的像素驱动电路中的第四晶体管T4的源极连接同一条数据线Data，第五晶体管T5的源极和存储电容Cst的第二极板连接同一条第一电源信号线Vdd。而为了简化显示面板的布线和优选显示面板的驱动时序，可以将第N+1行像素驱动电路所连接的所述第一扫描线Gate(N+1)复用为第N行像素驱动电路所连接的第二扫描线Gate(N)'和复位信号线Reset(N)；第N+1行像素驱动电路所连接的第一发光控制线EM(N+1)复用为第N行像素驱动电路所连接的第二发光控制线EM(N)'；N为大于或者等于1的整数。
在下述的该像素驱动电路的驱动方法中，以对位于第N行的一个像素驱动电路的驱动过程为例进行说明。其中，以该像素驱动电路中的第二晶体管T2的栅极和第七晶体管T7的栅极均连接第N-1行像素驱动电路所连接的第 一扫描线Gate(N-1)为例进行说明；该像素驱动电路中的第六晶体管T6的栅极连接第N-1行像素单元所连接第一发光控制线EM(N-1)。
图5为图4所示的像素驱动电路的一种工作时序图；参照图4和图5所示，该像素驱动电路的驱动方法包括如下阶段：
初始化阶段(t1)：图6为图4的像素驱动电路初始化阶段的晶体管导通状态示意图，如图6所示，第N-1行的第一扫描线Gate(N-1)和第一发光控制线EM(N-1)输入低电平信号，第一控制信号线Contorl(N)输入低电平信号，此时，第一晶体管T1、第二晶体管T2、第六晶体管T6、第七晶体管T7打开，初始化信号线Init写入高电平信号，此时发光器件D的第一电极(N4节点)、驱动晶体管T3的漏极(N3节点)以及驱动晶体管T3的栅极(N1节点)均为高电平信号，以此完成对驱动晶体管T3的栅极和发光器件D的第一电极的复位。
数据写入及阈值补偿阶段(t2)：图7为图4的像素驱动电路数据写入及阈值补偿阶段的晶体管导通状态示意图，如图7所示，第N-1行的第一扫描线Gate(N-1)继续被输入低电平信号，与此同时，第N行的第一扫描线Gate(N)也被写入低电平信号，第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4均被打开，驱动晶体管T3被第一晶体管T1和第二晶体管T2连成二极管结构，数据线Data上写入的数据电压通过第四晶体管T4、第一晶体管T1和第二晶体管T2写入驱动晶体管T3的栅极，直到驱动晶体管T3截止。驱动晶体管T3的栅极(N1节点)电压为Vdata+Vth(Vth<0，Vth为驱动晶体管T3的阈值电压)，并存储在存储电容Cst中。存储电容Cst的第一极板和第二极板的电压分别为Vdata+Vth和Vdd。
数据持续写入阶段(t3):图8为图4的像素驱动电路数据持续写入阶段的晶体管导通状态示意图，如图8所示，第N-1行的第一扫描线Gate(N-1)被输入高电平信号，第N行的第一扫描线Gate(N)持续写入低电平信号， 第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时仅第四晶体管T4、第一晶体管T1和驱动晶体管T3打开，数据线Data上写入的数据电压持续给驱动晶体管T3的源极(N2节点)充电，以使驱动晶体管T3充分打开。
预发光阶段(t4)：图9为图4的像素驱动电路预发光阶段的晶体管导通状态示意图，如图9所示，第N-1行的第一扫描线Gate(N-1)和第N行的第一扫描线Gate(N)均被输入高电平信号，第N-1行的第一发光控制线EM(N-1)被写入低电平信号，第N行的第一发光控制线EM(N)依旧被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时仅第一晶体管T1、第五晶体管T5和驱动晶体管T3打开，第一电源电压线Vdd上的第一电压被写入驱动晶体管T3的源极(N3节点)，此时N3节点的电位由Vdate变为Vdd。
发光阶段(t5)：图10为图4的像素驱动电路发光阶段的晶体管导通状态示意图，如图10所示，第N-1行的第一扫描线Gate(N-1)和第N行的第一扫描线Gate(N)均被输入高电平信号，第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入低电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时，第五晶体管T5、驱动晶体管T3、第六晶体管T6均打开，驱动发光器件D发光。
另外，在该阶段驱动晶体管T3的栅极电压为Vdata+Vth，驱动晶体管T3的源极电压为Vdd，故，驱动晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-Vdd，直到下一帧的初始化阶段。
发光器件D的发光电流等于流过驱动晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
＝β(Vdata-Vdd) 2  (1)
Figure PCTCN2020128119-appb-000001
如上述公式(1)所示，在发光阶段发光器件DD的电流与驱动晶体管T3的阈值电压无关，从而避免驱动晶体管T3的阈值电压对显示面板的显示均一性造成影响。
在另一示例中，该像素驱动电路，其结构与图4所示的像素驱动电路结构相同，区别仅在于，第一控制信号线在一帧图像的显示周期内所输入的信号为与第一发光控制线相反的信号。同样以驱动位于第N行的一个像素驱动电路为例，图11为图4的像素驱动电路的另一种工作时序图；如图11所示，第一发光控制线Contorl(N)仅在初始化阶段、数据写入及阈值补偿阶段和数据持续写入阶段被写入低电平信号，也即第一晶体管T1仅在这三个阶段工作，而在其他阶段第一晶体管T1处于关断状态。而对于本公开实施例的像素驱动电路而言，辅助功能子电路9仅需要初始化阶段和数据写入及阈值补偿阶段进行工作，以实现对驱动晶体管T3的栅极的复位，以及对驱动晶体管T3的阈值进行补偿，故相较第一控制信号持续输入低电平信号，该种实现方式，有助于延长第一晶体管T1的使用寿命，也可以避免第一晶体管T1长时间开启而产生漏电流。而对于该像素驱动电路的各个驱动方法与上述方法相同，故在此不再重复描述。
在另一示例中，图12为本公开实施例的另一种像素驱动电路的示意图；如图12所示，在该像素驱动电路中，其结构与图4所示的像素驱动电路结构相同，区别仅在于，第一发光控制线Contorl(N)在一帧图像的显示周期内所输入的信号为第二扫描信号Gate(N)，也即也可以将第二扫描信号线复用为第一发光控制线。同样以驱动位于第N行的一个像素驱动电路为例，图13为图12的像素驱动电路的工作时序图；如图13所示，第一控制信号线仅在初始化阶段、数据写入及阈值补偿阶段被写入低电平信号，也即第一晶体管T1仅在这两个阶段工作，而在其他阶段第一晶体管T1处于关断状态。而对于本公开实施例的像素驱动电路而言，辅助功能子电路9仅需要初始化阶 段和数据写入及阈值补偿阶段进行工作，以实现对驱动晶体管T3的栅极的复位，以及对驱动晶体管T3的阈值进行补偿，故相较第一控制信号持续输入低电平信号，该种实现方式，有助于延长第一晶体管T1的使用寿命，也可以避免第一晶体管T1长时间开启而产生漏电流。另外，第一控制信号线Contorl(N)和第二扫描线Gate(N)复用，还可以优化应用该像素驱动电路的显示面板的布线。而对于该像素驱动电路的各个驱动方法与上述方法相同，故在此不再重复描述。
在另一个示例中，图14为本公开实施例的另一种像素驱动电路的示意图；如图14所示，该像素驱动电路的结构与上述的图4的像素驱动电路结构大致相似，区别仅在于辅助功能子电路9的结构，虽然辅助功能子电路9与图4所示的像素驱动电路一样均包括第一晶体管T1和第二晶体管T2，但是第一晶体管T1和第二晶体管T2的连接关系不同。参照图14，该像素驱动电路中，辅助功能子电路9的第一晶体管T1的源极连接第二扫描线，第一晶体管T1的漏极连接第二晶体管T2的栅极，第一晶体管T1的栅极连接第一发光控制线；第二晶体管T2的源极连接驱动晶体管T3的栅极，第二晶体管T2的漏极连接驱动晶体管T3的漏极。其中，第一控制信号线在一帧图像的扫描周期内被输入的信号为与第一发光控制信号相反的信号。
需要说明的是，当将上述像素驱动电路应用至显示面板中时，且显示面板中的各像素驱动电路呈阵列排布，此时位于同一行的像素驱动电路的第四晶体管T4的栅极连接同一条第一扫描线，第一晶体管T1的栅极连接同一条第一控制信号线Contorl，第一晶体管T1的源极连接同一条第二扫描线Gate1'，第五晶体管T5的栅极连接同一条第一发光控制线EM1，第六晶体管T6的栅极连接同一条第二发光控制线EM1'，第七晶体管T7的栅极连接同一条复位信号线Reset。位于同一列的像素驱动电路中的第四晶体管T4的源极连接同一条数据线Data，第五晶体管T5的源极和存储电容Cst的第二极板连接同一条第一电源信号线Vdd。而为了简化显示面板的布线和优选显示面板的驱动时序，可以将第N+1行像素驱动电路所连接的所述第一扫描线 Gate(N+1)复用为第N行像素驱动电路所连接的第二扫描线Gate(N)'和复位信号线Reset(N)；第N+1行像素驱动电路所连接的第一发光控制线EM(N+1)复用为第N行像素驱动电路所连接的第二发光控制线EM(N)'；N为大于或者等于1的整数。
在下述的该像素驱动电路的驱动方法中，以对位于第N行的一个像素驱动电路的驱动过程为例进行说明。其中，以该像素驱动电路中的第二晶体管T2的栅极和第七晶体管T7的栅极均连接第N-1行像素驱动电路所连接的第一扫描线Gate(N-1)为例进行说明；该像素驱动电路中的第六晶体管T6的栅极连接第N-1行像素单元所连接第一发光控制线EM(N-1)。
图11所示的时序也可以作为图14所示的像素驱动电路的工作时序图；参照图14和图11所示，该像素驱动电路的驱动方法包括如下阶段：
初始化阶段(t1)：图15为图14的像素驱动电路初始化阶段的晶体管导通状态示意图，如图15所示，第N-1行的第一扫描线Gate(N-1)和第一发光控制线EM(N-1)输入低电平信号，第一控制信号线Contorl(N)输入低电平信号，此时，第一晶体管T1、第六晶体管T6、第七晶体管T7打开，由于第一晶体管T1的源极连接第N-1行的第一扫描线Gate(N-1)，故第二晶体管T2也被打开，与此同时，初始化信号线Init写入高电平信号，此时发光器件D的第一电极(N4节点)、驱动晶体管T3的漏极(N3节点)以及驱动晶体管T3的栅极(N1节点)均为高电平信号，以此完成对驱动晶体管T3的栅极和发光器件D的第一电极的复位。
数据写入及阈值补偿阶段(t2)：图16为图14的像素驱动电路数据写入及阈值补偿阶段的晶体管导通状态示意图，如图16所示，第N-1行的第一扫描线Gate(N-1)继续被输入低电平信号，与此同时，第N行的第一扫描线Gate(N)也被写入低电平信号，第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4均被打开，驱动晶体管T3被第一晶体管T1和 第二晶体管T2连成二极管结构，数据线Data上写入的数据电压通过第四晶体管T4、第一晶体管T1和第二晶体管T2写入驱动晶体管T3的栅极，直到驱动晶体管T3截止。驱动晶体管T3的栅极(N1节点)电压为Vdata+Vth(Vth<0，Vth为驱动晶体管T3的阈值电压)，并存储在存储电容Cst中。存储电容Cst的第一极板和第二极板的电压分别为Vdata+Vth和Vdd。
数据持续写入阶段(t3):图17为图14的像素驱动电路数据持续写入阶段的晶体管导通状态示意图，如图17所示，第N-1行的第一扫描线Gate(N-1)被输入高电平信号，第N行的第一扫描线Gate(N)持续写入低电平信号，第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时仅第四晶体管T4、第一晶体管T1和驱动晶体管T3打开，数据线Data上写入的数据电压持续给驱动晶体管T3的源极(N2节点)充电，以使驱动晶体管T3充分打开。
预发光阶段(t4)：图18为图14的像素驱动电路预发光阶段的晶体管导通状态示意图，如图18所示，第N-1行的第一扫描线Gate(N-1)和第N行的第一扫描线Gate(N)均被输入高电平信号，第N-1行的第一发光控制线EM(N-1)被写入低电平信号，第N行的第一发光控制线EM(N)依旧被写入高电平信号，第一控制信号线Contorl(N)持续输入低电平信号，此时仅第一晶体管T1、第五晶体管T5和驱动晶体管T3打开，第一电源电压线Vdd上的第一电压被写入驱动晶体管T3的源极(N3节点)，此时N3节点的电位由Vdate变为Vdd。
发光阶段(t5)：图19为图14的像素驱动电路发光阶段的晶体管导通状态示意图，如图19所示，第N-1行的第一扫描线Gate(N-1)和第N行的第一扫描线Gate(N)均被输入高电平信号，第N-1行的第一发光控制线EM(N-1)和第N行的第一发光控制线EM(N)均被写入低电平信号，第一控制信号线持续Contorl(N)输入低电平信号，此时，第五晶体管T5、驱动晶体管T3、第六晶体管T6均打开，驱动发光器件D发光。
另外，在该阶段驱动晶体管T3的栅极电压为Vdata+Vth，驱动晶体管T3的源极电压为Vdd，故，驱动晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-Vdd，直到下一帧的初始化阶段。
发光器件D的发光电流等于流过驱动晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
Figure PCTCN2020128119-appb-000002
如上述公式(1)所示，在发光阶段发光器件DD的电流与驱动晶体管T3的阈值电压无关，从而避免驱动晶体管T3的阈值电压对显示面板的显示均一性造成影响。
在另一个示例中，图20为本公开实施例的另一种像素驱动电路的示意图；如图20所示，该像素驱动电路与图14所示的像素的驱动电路结构大致相同，区别在于，在该像素驱动电路第一控制信号线被写入的信号为第二扫描信号，也即第二扫描信号线可以与第一控制信号线复用，此时可以将第一晶体管T1的栅极和源极连接在一起。而对于该像素驱动电路中的其他功能模块可以与上述的像素驱动电路的功能模块相同，故在此不再详细描述。同样以驱动位于第N行的一个像素驱动电路为例，图13的时序图也可以作为图20所示的像素驱动电路的工作时序图；如图13所示，第一控制信号线仅在初始化阶段、数据写入及阈值补偿阶段被写入低电平信号，也即第一晶体管T1仅在这两个阶段工作，而在其他阶段第一晶体管T1处于关断状态。而对于本公开实施例的像素驱动电路而言，辅助功能子电路9仅需要初始化阶段和数据写入及阈值补偿阶段进行工作，以实现对驱动晶体管T3的栅极的复位，以及对驱动晶体管T3的阈值进行补偿，该种实现方式，有助于延长第一晶体管T1的使用寿命，也可以避免第一晶体管T1长时间开启而产生漏 电流。另外，第一控制信号线和第二扫描线复用，还可以优化应用该像素驱动电路的显示面板的布线。而对于该像素驱动电路的各个驱动方法与上述方法相同，故在此不再重复描述。
第二方面，本公开实施例提供一种显示面板，该显示面板中的像素驱动电路可以采用上述的任意一种像素驱动电路。
在一个示例中，像素驱动电路呈阵列排布；当辅助子电路包括第一晶体管T1和第二晶体管T2时；第一晶体管T1的源极连接第二晶体管T2的漏极，第一晶体管T1的漏极连接驱动晶体管T3的栅极，第一晶体管T1的栅极连接第一控制信号线；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的栅极连接第二扫描线。
对于位于同一行的像素驱动电路，各数据写入子电路4连接同一条第一扫描线；各第一发光控制子电路5连接同一条第一发光控制线，各第二发光控制子电路6连接同一条第二发光控制线，各辅助功能子电路9中的第一晶体管T1的控制极连接同一条第一控制信号线，第二晶体管T2的控制极连接同一条第二扫描线；各复位子电路7连接同一条复位信号线Reset。
对于位于同一列的像素驱动电路，各数据写入子电路4连接同一条数据线Data；各第一发光控制子电路5和各存储子电路8连接同一条第一电源信号线；各复位子电路7连接同一条初始化信号线Init。
其中，第N+1行像素驱动电路所连接的第一扫描线复用为第N行像素驱动电路所连接的第二扫描线和复位信号线Reset；第N+1行像素驱动电路所连接的第一发光控制线复用为第N行像素驱动电路所连接的第二发光控制线；N为大于或者等于1的整数。
另外，对上述的连接方式，在一帧图像的显示周期内，第一控制信号线可以写入低电平信号还可以写入与第二发光控制线相反的信号。
在一些实施例中，当辅助子电路包括第一晶体管T1和第二晶体管T2时；第一晶体管T1的源极连接第二晶体管T2的漏极，第一晶体管T1的漏极连 接驱动晶体管T3的栅极，第一晶体管T1的栅极连接第一控制信号线；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的栅极连接第二扫描线。第N+1行像素驱动电路所连接的第一扫描线还复用为第N行像素驱动电路所连接的第一控制信号线。也就是说，位于同一行的第一晶体管T1的栅极可以连接第二晶体管T2的栅极连接，这样一来，可以优化显示面板的布线空间。
在另一个示例中，像素驱动电路呈阵列排布；当辅助子电路包括第一晶体管T1和第二晶体管T2时；第一晶体管T1的源极连接第二扫描线，第一晶体管T1的漏极连接第二晶体管T2的栅极，第一晶体管T1的栅极连接第一控制信号线；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的源极连接驱动晶体管T3的栅极。
对于位于同一行的像素驱动电路，各数据写入子电路4连接同一条第一扫描线；各第一发光控制子电路5连接同一条第一发光控制线，各第二发光控制子电路6连接同一条第二发光控制线，各辅助功能子电路9中的第一晶体管T1的栅极连接同一条第一控制信号线；各复位子电路7连接同一条复位信号线Reset；各辅助功能子电路9中的第一晶体管T1的源极连接同一条第二扫描线。
对于位于同一列的像素驱动电路，各数据写入子电路4连接同一条数据线Data；各第一发光控制子电路5和各存储子电路8连接同一条第一电源信号线；各复位子电路7连接同一条初始化信号线Init。
其中，当辅助子电路包括第一晶体管T1和第二晶体管T2时；第一晶体管T1的源极连接第二扫描线，第一晶体管T1的漏极连接第二晶体管T2的栅极，第一晶体管T1的栅极连接第一控制信号线；第二晶体管T2的源极连接驱动晶体管T3的漏极，第二晶体管T2的源极连接驱动晶体管T3的栅极。第N+1行像素驱动电路所连接的第一扫描线复用为第N行像素驱动电路所连接的第二扫描线和复位信号线Reset；第N+1行像素驱动电路所连接的第一发光控制线复用为第N行像素驱动电路所连接的第二发光控制线；N为大 于或者等于1的整数。
由于本实施例的显示面板包括上述的像素驱动电路，故其显示效果较佳，且可以实现高分辨率的显示。
其中，显示面板可以为液晶显示装置或者电致发光显示装置，例如液晶面板、OLED面板、Micro LED面板，Mini LED面板，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种像素驱动电路，其包括：数据写入子电路、驱动子电路、复位子电路、第一发光控制子电路、第二发光控制子电路、辅助功能子电路及存储子电路；其中，
    所述驱动子电路包括驱动晶体管，被配置根据其第一极和控制极的电压而生成驱动电路，以对待驱动的发光器件进行驱动；
    在数据写入和阈值补偿阶段，所述数据写入子电路被配置为响应于第一扫描信号，而将数据电压写入所述驱动子电路的第一极；所述辅助功能子电路被配置对驱动晶体管的阈值电压进行补偿；所述存储子电路被配置为对所述数据电压进行存储；
    在初始化阶段，所述辅助功能子电路被配置将所述驱动晶体管的控制极和第二极短接；所述复位子电路被配置响应于复位控制信号，并通过初始信号对所述待驱动的发光器件的第一电极进行初始化，第二发光控制子电路响应于第二发光控制信号，将所述初始化信号传输至所述驱动子电路的第二极；
    在发光阶段，所述第一发光控制子电路被配置为响应于第一发光控制信号，将第一电源电压写入所述驱动晶体管的第一极，以使所述驱动晶体管产生驱动电流；所述第二发光控制子电路被配置为响应于第二发光控制信号，而将所述驱动电流传输给所述待驱动的发光器件。
  2. 根据权利要求1所述的像素驱动电路，其中，所述辅助功能子电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的第一极连接所述第二晶体管的第二极，第二极连接所述驱动晶体管的控制极，控制极连接第一控制信号线；
    所述第二晶体管的第一极连接所述驱动晶体管的第二极，控制极连接第二扫描线。
  3. 根据权利要求2所述的像素驱动电路，其中，在一帧图像的扫描周 期内，所述第一控制信号线被配置为写入以下任一信号：
    工作电平信号；
    与第一发光控制信号相反的信号；
    第二扫描信号。
  4. 根据权利要求1所述的像素驱动电路，其中，所述辅助功能子电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的第一极连接所述第二扫描线，第二极连接所述第二晶体管的控制极，控制极连接第一控制信号线；
    所述第二晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述驱动晶体管的控制极。
  5. 根据权利要求2所述的像素驱动电路，其中，在一帧图像的扫描周期内，所述第一控制信号线被配置为写入与第一发光控制信号相反的信号或者第二扫描信号。
  6. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第四晶体管；
    所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，控制极连接第一扫描线。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一发光控制子电路包括：第五晶体管；
    所述第五晶体管的第一极连接第一电源电压线，第二极连接所述驱动晶体管的第一极，控制极连接第一发光控制线。
  8. 根据权利要求1所述的像素驱动电路，其中，所述第二发光控制子电路包括：第六晶体管；
    所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述带驱动的发光器件的第一电极，控制极连接第二发光控制线。
  9. 根据权利要求1所述的像素驱动电路，其中，所述复位子电路包括： 第七晶体管；
    所述第七晶体管的第一极连接所述带驱动的发光器件的第一电极，第二极连接初始化信号线，控制极连接复位信号线。
  10. 根据权利要求1所述的像素驱动电路，其中，存储子电路包括：存储电容；
    所述存储电容的第一极板连接所述驱动晶体管的控制极，第二极板连接二所述第一电源电压线。
  11. 一种显示面板，其包括权利要求1-10中任一项所述的像素驱动电路。
  12. 根据权利要求11所述的显示面板，其中，所述像素驱动电路呈阵列排布；所述辅助子电路包括第一晶体管和第二晶体管；所述第一晶体管的第一极连接所述第二晶体管的第二极，第二极连接所述驱动晶体管的控制极，控制极连接第一控制信号线；所述第二晶体管的第一极连接所述驱动晶体管的第二极，控制极连接第二扫描线；
    对于位于同一行的所述像素驱动电路，各所述数据写入子电路连接同一条第一扫描线；各所述第一发光控制子电路连接同一条第一发光控制线，各所述第二发光控制子电路连接同一条所述第二发光控制线，各所述辅助功能子电路中的第一晶体管的控制极连接同一条所述第一控制信号线，第二晶体管的控制极连接同一条所述第二扫描线；各所述复位子电路连接同一条所述复位信号线；
    对于位于同一列的所述像素驱动电路，各所述数据写入子电路连接同一条数据线；各所述第一发光控制子电路和各所述存储子电路连接同一条第一电源信号线；各所述复位子电路连接同一条初始化信号线；
    其中，第N+1行所述像素驱动电路所连接的所述第一扫描线复用为第N行所述像素驱动电路所连接的所述第二扫描线和所述复位信号线；第N+1行所述像素驱动电路所连接的第一发光控制线复用为第N行所述像素驱动电路所连接的所述第二发光控制线；N为大于或者等于1的整数。
  13. 根据权利要求12所述的显示面板，其中，第N+1行所述像素驱动电路所连接的所述第一扫描线还复用为第N行所述像素驱动电路所连接的第一控制信号线。
  14. 根据权利要求11所述的显示面板，其中，所述像素驱动电路呈阵列排布；所述辅助子电路包括第一晶体管和第二晶体管；所述第一晶体管的第一极连接所述第二扫描线，第二极连接所述第二晶体管的控制极，控制极连接第一控制信号线；所述第二晶体管的第一极连接所述驱动晶体管的第二极，第一极连接所述驱动晶体管的控制极；
    对于位于同一行的所述像素驱动电路，各所述数据写入子电路连接同一条第一扫描线；各所述第一发光控制子电路连接同一条第一发光控制线，各所述第二发光控制子电路连接同一条所述第二发光控制线，各所述辅助功能子电路中的第一晶体管的控制极连接同一条所述第一控制信号线；各所述复位子电路连接同一条所述复位信号线；各所述辅助功能子电路中的第一晶体管的第一极连接同一条所述第二扫描线；
    对于位于同一列的所述像素驱动电路，各所述数据写入子电路连接同一条数据线；各所述第一发光控制子电路和各所述存储子电路连接同一条第一电源信号线；各所述复位子电路连接同一条初始化信号线；
    其中，第N+1行所述像素驱动电路所连接的所述第一扫描线复用为第N行所述像素驱动电路所连接的所述第二扫描线和所述复位信号线；第N+1行所述像素驱动电路所连接的第一发光控制线复用为第N行所述像素驱动电路所连接的所述第二发光控制线；N为大于或者等于1的整数。
  15. 根据权利要求14所述的显示面板，其中，第N+1行所述像素驱动电路所连接的所述第一扫描线还复用为第N行所述像素驱动电路所连接的第一控制信号线。
PCT/CN2020/128119 2020-11-11 2020-11-11 像素驱动电路及显示面板 WO2022099508A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/432,574 US11763730B2 (en) 2020-11-11 2020-11-11 Pixel driving circuit having an initialization and compensation and display panel
PCT/CN2020/128119 WO2022099508A1 (zh) 2020-11-11 2020-11-11 像素驱动电路及显示面板
CN202080002723.9A CN115210800A (zh) 2020-11-11 2020-11-11 像素驱动电路及显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/128119 WO2022099508A1 (zh) 2020-11-11 2020-11-11 像素驱动电路及显示面板

Publications (1)

Publication Number Publication Date
WO2022099508A1 true WO2022099508A1 (zh) 2022-05-19

Family

ID=81601884

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/128119 WO2022099508A1 (zh) 2020-11-11 2020-11-11 像素驱动电路及显示面板

Country Status (3)

Country Link
US (1) US11763730B2 (zh)
CN (1) CN115210800A (zh)
WO (1) WO2022099508A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230067744A (ko) * 2021-11-08 2023-05-17 삼성디스플레이 주식회사 표시장치
CN115527488A (zh) * 2022-04-01 2022-12-27 武汉天马微电子有限公司上海分公司 一种显示面板及其驱动方法、显示装置
CN115311979A (zh) * 2022-08-24 2022-11-08 厦门天马显示科技有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531076A (zh) * 2017-01-12 2017-03-22 京东方科技集团股份有限公司 一种像素电路、显示面板及其驱动方法
CN107767819A (zh) * 2017-09-28 2018-03-06 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
US20180366062A1 (en) * 2015-05-28 2018-12-20 Lg Display Co., Ltd. Organic Light Emitting Diode Display
CN109087610A (zh) * 2018-08-20 2018-12-25 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路、驱动方法及显示面板
KR20190113708A (ko) * 2019-09-26 2019-10-08 아이프라임 리미티드 유기발광 표시 장치
CN111754920A (zh) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110268465B (zh) * 2019-01-14 2022-07-01 京东方科技集团股份有限公司 像素电路、显示面板及像素电路的驱动方法
KR20210021219A (ko) * 2019-08-16 2021-02-25 삼성디스플레이 주식회사 화소 회로

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180366062A1 (en) * 2015-05-28 2018-12-20 Lg Display Co., Ltd. Organic Light Emitting Diode Display
CN106531076A (zh) * 2017-01-12 2017-03-22 京东方科技集团股份有限公司 一种像素电路、显示面板及其驱动方法
CN107767819A (zh) * 2017-09-28 2018-03-06 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
CN109087610A (zh) * 2018-08-20 2018-12-25 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路、驱动方法及显示面板
KR20190113708A (ko) * 2019-09-26 2019-10-08 아이프라임 리미티드 유기발광 표시 장치
CN111754920A (zh) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板

Also Published As

Publication number Publication date
US11763730B2 (en) 2023-09-19
US20220351671A1 (en) 2022-11-03
CN115210800A (zh) 2022-10-18

Similar Documents

Publication Publication Date Title
US11631369B2 (en) Pixel circuit and driving method thereof, display panel
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
CN107358915B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
CN110268465B (zh) 像素电路、显示面板及像素电路的驱动方法
WO2021068637A1 (zh) 像素电路及其驱动方法、显示面板
WO2023005621A1 (zh) 像素电路及其驱动方法、显示面板
US10978002B2 (en) Pixel circuit and driving method thereof, and display panel
WO2020186933A1 (zh) 像素电路、其驱动方法、电致发光显示面板及显示装置
WO2020062802A1 (zh) 显示面板及像素电路的驱动方法
WO2023005694A1 (zh) 像素电路及其驱动方法、显示面板
WO2022099508A1 (zh) 像素驱动电路及显示面板
WO2019052394A1 (zh) 像素电路及其驱动方法、显示装置
JP7159182B2 (ja) 画素回路及びその駆動方法、表示パネル
WO2016011714A1 (zh) 像素电路、像素电路的驱动方法和显示装置
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
WO2022061852A1 (zh) 像素驱动电路及显示面板
US11450270B2 (en) Pixel circuit and method of driving the same, display device
TW201351378A (zh) 顯示器
WO2018184514A1 (zh) 像素补偿电路、驱动方法、有机发光显示面板及显示装置
WO2023016138A1 (zh) 像素驱动电路及显示面板
WO2018219066A1 (zh) 像素电路、驱动方法、显示面板及显示装置
US11355060B2 (en) Pixel circuit, method of driving pixel circuit, display panel and display device
WO2022022146A1 (zh) 像素电路及其驱动方法、显示基板和显示装置
WO2019047701A1 (zh) 像素电路及其驱动方法、显示装置
US10235943B2 (en) Display panel, method for controlling display panel and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20961067

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM1205A DATED 12.09.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20961067

Country of ref document: EP

Kind code of ref document: A1