WO2018219066A1 - 像素电路、驱动方法、显示面板及显示装置 - Google Patents

像素电路、驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2018219066A1
WO2018219066A1 PCT/CN2018/084194 CN2018084194W WO2018219066A1 WO 2018219066 A1 WO2018219066 A1 WO 2018219066A1 CN 2018084194 W CN2018084194 W CN 2018084194W WO 2018219066 A1 WO2018219066 A1 WO 2018219066A1
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Prior art keywords
circuit
sub
node
pixel
control
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PCT/CN2018/084194
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English (en)
French (fr)
Inventor
杨盛际
董学
吕敬
陈小川
玄明花
王磊
刘冬妮
肖丽
付杰
卢鹏程
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京东方科技集团股份有限公司
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Priority to US16/096,138 priority Critical patent/US10770000B2/en
Publication of WO2018219066A1 publication Critical patent/WO2018219066A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method, a display panel, and a display device.
  • OLED Organic Light Emitting Diode
  • LCDs liquid crystal displays
  • OLEDs have the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response.
  • OLED displays have begun to replace traditional LCD displays.
  • Pixel circuit design is the core technology content of OLED display, which has important research significance.
  • OLEDs are current driven and require a constant current to control illumination. Due to process process and device aging, etc., the threshold voltage Vth of the driving transistor of the pixel circuit may be non-uniform, which causes a change in current flowing through different OLED pixels, thereby causing uneven display brightness, thereby affecting the entire The display of the image.
  • the circuit is composed of one driving transistor M2, one switching transistor M1, and one storage capacitor Cs.
  • the scan line Scan selects a certain row, the scan line Scan inputs a low level signal, the P-type switch transistor M1 is turned on, and the voltage of the data line Data is written to the storage capacitor Cs; when the line scan is finished, the scan line Scan is input.
  • the signal goes high, the P-type switching transistor M1 is turned off, and the voltage stored in the storage capacitor Cs controls the driving transistor M2 to generate a current to drive the OLED pixel, ensuring that the OLED pixel continues to emit light within one frame.
  • the threshold voltage Vth of the driving transistor T2 may drift due to process process and device aging, etc., which causes the current flowing through different OLED pixels to change due to the change of the threshold voltage Vth of the driving transistor, resulting in an image. The brightness is uneven.
  • An embodiment of the present disclosure provides a pixel circuit including at least two pixel sub-circuits, and a data line, a first scan line, a second scan line, a third scan line, and a light corresponding to the pixel circuit.
  • a control line wherein each of the pixel sub-circuits comprises: an illumination control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit, and a light-emitting device.
  • the illumination control sub-circuit is respectively connected to the first voltage signal end, the illumination control end and the first node; the illumination control sub-circuit is configured to provide the signal of the first voltage signal end under the control of the illumination control end Giving the first node;
  • the node reset sub-circuit is respectively connected to the first scan signal end, the first node and the second node; the node reset sub-circuit is configured to enable the first control under the control of the first scan signal end a node is electrically connected to the second node;
  • the write sub-circuit is respectively connected to the second scan signal end, the data signal end and the second node; the write sub-circuit is configured to send the data signal end under the control of the second scan signal end Data signal and threshold voltage are written to the second node;
  • the driving control sub-circuit is respectively connected to the first node, the second node, and the light emitting device; the driving control sub-circuit is configured to drive the light emitting device to emit light under the control of the second node ;as well as
  • the light emitting device is connected between the driving control subcircuit and the second voltage signal terminal.
  • each of the pixel sub-circuits further includes a voltage regulator sub-circuit.
  • the voltage regulator circuit is connected between the second node and the second voltage signal terminal, and the voltage regulator circuit is configured to maintain a potential of the second node;
  • each of the pixel sub-circuits are connected to the data line
  • the first scan signal end of each of the pixel sub-circuits is connected to the first scan signal line
  • each of the The light emission control ends of the pixel sub-circuits are all connected to the light emission control line
  • the illumination control sub-circuit includes: a first switching transistor
  • the first switching transistor has a gate connected to the light emission control end, a source connected to the first voltage signal end, and a drain connected to the first node.
  • the node reset sub-circuit includes: a second switching transistor
  • the second switching transistor has a gate connected to the first scan signal end, a source connected to the first node, and a drain connected to the second node.
  • the write sub-circuit includes: a third switching transistor and a fourth switching transistor;
  • a gate of the third switching transistor is connected to the second scan signal end, a source is connected to the data signal end, and a drain is connected to a source of the fourth switching transistor;
  • the fourth switching transistor has a gate connected to the second node, a source connected to a drain of the third switching transistor, and a drain connected to the second node.
  • the driving control sub-circuit includes: a driving transistor
  • the driving transistor has a gate connected to the second node, a source connected to the first node, and a drain connected to the light emitting device.
  • the voltage regulator sub-circuit includes: a first capacitor;
  • the first capacitor is connected between the second node and the second voltage signal terminal.
  • all switching transistors are N-type transistors.
  • the embodiment of the present disclosure further provides a driving method of any one of the foregoing pixel circuits, including:
  • the illumination control sub-circuit provides a signal of the first voltage signal end to the first node under control of the illumination control terminal; the node resets The sub-circuit turns on the first node and the second node under the control of the first scanning signal end;
  • the write sub-circuit in the pixel sub-circuit connected to the second scan line sends the data signal end under the control of a signal sent by the second scan line
  • the first data signal and the threshold voltage are written to the second node of the pixel sub-circuit connected to the second scan line;
  • the write sub-circuit in the pixel sub-circuit connected to the third scan line sends the data signal end under the control of a signal sent by the third scan line
  • the second data signal and the threshold voltage are written to the second node of the pixel sub-circuit connected to the second scan line;
  • the illuminating control sub-circuit provides a signal of the first voltage signal end to the first node under the control of the illuminating control end; the voltage regulator sub-circuit Maintaining a voltage of the second node; the drive control sub-circuit driving the light emitting device to emit light under the control of the second node.
  • an embodiment of the present disclosure further provides an organic light emitting display panel, including any one of the above pixel circuits provided by the embodiments of the present disclosure arranged in a matrix;
  • Each of the columns of the pixel circuits shares a data line, and each row of the pixel circuits shares a first scan line, a second scan line, a third scan line, and an illumination control line.
  • the embodiment of the present disclosure further provides a display device, including any of the above display panels provided by the embodiments of the present disclosure.
  • 1 is a schematic structural view of a conventional 2T1C pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit timing diagram of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a schematic flowchart diagram of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a specific structure of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a second schematic structural diagram of a pixel circuit arrangement manner according to an embodiment of the present disclosure.
  • the pixel circuit includes: two pixel sub-circuits, a data line corresponding to the pixel circuit, a first scan line, a second scan line, a third scan line, and an illumination control line; wherein each pixel sub-circuit includes: An illumination control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit, a voltage regulator sub-circuit, and a light-emitting device; sharing one data line through two pixel sub-circuits, thereby implementing two pixel circuits to complete two
  • the driving of the pixel greatly reduces the distance between the pixels, increases the aperture ratio, and realizes high pixel display to improve the display quality.
  • the pixel circuit can be driven by the cooperation of the above sub-circuits.
  • the driving current of the control sub-circuit driving the light-emitting device to emit light is independent of the threshold voltage of the driving control sub-circuit and the first voltage signal, and the influence of the threshold voltage of the driving control sub-circuit on the light-emitting device can be avoided, that is, the same data signal is used to load differently.
  • the pixel unit is used, an image with the same brightness can be obtained, and the display area of the display device is improved. Uniformity of the image brightness.
  • a data line Data corresponding to the pixel circuit a first scan line Scan1, a second scan line Scan2, a third scan line Scan3, and a light emission control line EM;
  • the pixel sub-circuit 10 includes an emission control sub-circuit 1, a node reset sub-circuit 2, a drive control sub-circuit 4, a write sub-circuit 3, a voltage regulator sub-circuit 5, and a light-emitting device 6.
  • the illumination control sub-circuit 1 is respectively connected to the first voltage signal terminal Vdd, the illumination control terminal and the first node a; the illumination control sub-circuit is configured to provide the signal of the first voltage signal terminal Vdd to the first under the control of the illumination control terminal Node a;
  • the node reset sub-circuit 2 is respectively connected to the first scan signal end, the first node a and the second node b; the node reset sub-circuit is configured to make the first node a and the second node under the control of the first scan signal end b conducting;
  • the write sub-circuit 3 is respectively connected to the second scan signal end, the data signal end and the second node b; the write sub-circuit 3 is configured to transmit the data signal and the threshold value of the data signal end under the control of the second scan signal end The voltage is written to the second node b;
  • the driving control sub-circuit 4 is respectively connected to the first node a, the second node b and the light-emitting device 6; the driving control sub-circuit 4 is configured to drive the light-emitting device 6 to emit light under the control of the second node b;
  • the light emitting device 6 is connected between the driving control sub-circuit 4 and the second voltage signal terminal Vss;
  • the voltage regulator sub-circuit 5 is connected between the second node and the second voltage signal terminal Vss, and the voltage regulator circuit 5 is configured to maintain the potential of the second node b.
  • the data signal ends of the two pixel sub-circuits 10 are all connected to the data line Data, the first scanning signal ends of the two pixel sub-circuits 10 are connected to the first scanning signal line Scan1, and the light-emitting control ends of the two pixel sub-circuits 10 are both Connected to the light emission control line EM; wherein the second scan signal end of one pixel sub-circuit 10 is connected to the second scan signal line Scan2 (for example, see the sub-pixel 10 on the left side of FIG. 2), and the other pixel sub-circuit 10
  • the two scanning signal terminals are connected to the third scanning signal line Scan3 (for example, see the sub-pixel 10 on the right side of FIG. 2).
  • each of the pixel sub-circuits 10 of the embodiment of the present disclosure a port connected to the data line Data is referred to as a data signal terminal, and a port connected to the scanning signal line Scan is referred to as a scanning signal terminal, and a port connected to the light emission control line EM. It is called the light control terminal.
  • Each of the pixel sub-circuits 10 includes a first scan signal terminal connected to the first scan line Scan1 and a second scan signal terminal connected to the second scan line Scan2 or the third scan line Scan3.
  • the pixel circuit includes: at least two pixel sub-circuits, a data line corresponding to the pixel circuit, a first scan line, a second scan line, a third scan line, and an emission control line; wherein each pixel
  • the sub-circuit includes: an illumination control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit, a voltage regulator sub-circuit, and a light-emitting device.
  • the two pixel sub-circuits share one data line, thereby realizing the driving of two pixels by using one pixel circuit, greatly reducing the distance between pixels, increasing the aperture ratio, and thereby achieving high pixel display to improve display quality;
  • the pixel circuit can make the driving current of the driving control sub-circuit driving the illuminating device to be independent of the threshold voltage of the driving control sub-circuit and the first voltage signal, thereby avoiding the driving control.
  • the influence of the threshold voltage of the sub-circuit on the light-emitting device that is, when the same data signal is loaded to different pixel units, an image with the same brightness can be obtained, and the uniformity of the brightness of the image in the display area of the display device is improved.
  • the light-emitting control sub-circuit 1 specifically includes: a first switching transistor T1;
  • the first switching transistor T1 has a gate connected to the light emission control terminal, a source connected to the first voltage signal terminal Vdd, and a drain connected to the first node a.
  • the first switching transistor T1 may be an N-type transistor. At this time, when the light-emission control signal VEM from the light-emitting control terminal is at a high level, the first switching transistor T1 is turned on.
  • the first switching transistor T1 is in an off state when the illumination control signal VEM from the illumination control terminal is low; the first switching transistor T1 may also be a P-type transistor (not shown in the figure), at this time, when the illumination When the light-emitting control signal VEM from the control terminal is at a low level, the first switching transistor T1 is in an on state, and when the light-emission control signal VEM from the light-emitting control terminal is at a high level, the first switching transistor T1 is in an off state;
  • the pixel circuit provided by the embodiment of the present disclosure, when the first switching transistor is in an on state under the control of the illumination control signal, the first voltage signal sent by the first voltage signal end passes through the first switch that is turned on. The transistor is transmitted to the first node.
  • the specific structure of the illuminating control sub-circuit in the pixel circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. , not limited here.
  • the node reset sub-circuit 2 specifically includes: a second switching transistor T2;
  • the second switching transistor T2 has a gate connected to the first scan signal terminal, a source connected to the first node a, and a drain connected to the second node b.
  • the second switching transistor T2 may be an N-type transistor.
  • the second switching transistor T2 when the first scan signal VScan1 emitted by the first scan signal terminal is at a high level, the second switching transistor T2 In the on state, the second switching transistor T2 is in an off state when the first scan signal VScan1 from the first scan signal terminal is at a low level; the second switching transistor T2 may also be a P-type transistor (not shown in the figure)
  • the second switch transistor T2 is in an on state, and when the first scan signal VScan1 from the first scan signal terminal is at a high level, the second The switching transistor T2 is in an off state; it is not limited herein.
  • the pixel circuit provided by the embodiment of the present disclosure, when the second switching transistor is in an on state under the control of the first scan signal, the first voltage signal at the first node passes through the second switching transistor that is turned on. Transfer to the second node.
  • the above is only a specific structure of the node reset sub-circuit in the pixel circuit.
  • the specific structure of the node reset sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be known to those skilled in the art. Other structures are not limited herein.
  • the write sub-circuit 3 specifically includes: a third switching transistor T3 and a fourth switching transistor T4;
  • a gate of the third switching transistor T3 is connected to the second scan signal end, a source is connected to the data signal end, and a drain is connected to a source of the fourth switching transistor T4;
  • the fourth switching transistor T4 has a gate connected to the second node b, a source connected to the drain of the third switching transistor T3, and a drain connected to the second node b.
  • the third switching transistor T3 may be an N-type transistor. At this time, when the signal sent from the second scanning signal terminal is at a high level, the third switching transistor T3 is in an on state. The third switching transistor T3 is in an off state when the signal sent from the second scanning signal terminal is a low level; the third switching transistor T3 may also be a P-type transistor (not shown in the figure), and at this time, when the second scanning When the signal sent from the signal terminal is low, the third switching transistor T3 is in an on state, and when the signal from the second scanning signal terminal is at a high level, the third switching transistor T3 is in an off state; it is not limited herein.
  • the fourth switching transistor T4 may be an N-type transistor. At this time, when the voltage at the second node b is a high level, the fourth switching transistor T4 is in an on state. The fourth switching transistor T4 is in an off state when the voltage at the second node b is low.
  • the data signal is transmitted to the fourth switching transistor through the turned-on third switching transistor. a source electrode; when the fourth switching transistor is in an on state under the control of the voltage at the second node, writing the threshold voltage of the data signal and the fourth switching transistor to the second node.
  • the second scan signal end of the pixel sub-circuit 10 on the left side is connected to the second scan signal line Scan2, so that the gate of the third switch transistor T3 on the left side and the second scan signal are connected.
  • the line Scan2 is connected;
  • the second scanning signal terminal of the pixel sub-circuit 10 on the right side is connected to the third scanning signal line Scan3, so that the gate of the third switching transistor T3 on the right side is connected to the third scanning signal line Scan3.
  • the above is only a specific structure of the write sub-circuit in the pixel circuit.
  • the specific structure of the write sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. , not limited here.
  • the drive control sub-circuit 4 specifically includes: a drive transistor DT1;
  • the driving transistor DT1 has a gate connected to the second node b, a source connected to the first node a, and a drain connected to the light emitting device 6.
  • the driving transistor DT1 is an N-type transistor.
  • the voltage of the corresponding first voltage signal is generally a positive voltage
  • the voltage of the second voltage signal is generally grounded or a negative value.
  • the driving transistor DT1 can also be a P-type transistor, and the disclosure is not limited herein.
  • the voltage regulator circuit 5 specifically includes: a first capacitor C1; the first capacitor C1 is connected to the second node b and the second voltage signal terminal Vss between.
  • the first capacitor C1 is used to stabilize the voltage at the second node b.
  • all of the switching transistors may be N-type transistors, which are not limited herein.
  • the driving transistor and the switching transistor mentioned in the above pixel circuit provided by the embodiment of the present disclosure may all adopt an N-type transistor design, so that the hysteresis effect of the pixel can be reduced, and the fabrication process of the pixel circuit can be simplified.
  • the driving transistor is an N-type transistor
  • the driving transistor is a P-type transistor and the same design principle is adopted is also within the scope of the present disclosure.
  • the driving transistor and the switching transistor may be a thin film transistor (TFT), or may be a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the sources and drains of these transistors may be interchanged depending on the type of transistor and the input signal, and no specific distinction is made here.
  • the driving transistor DT1 and all the switching transistors are N-type transistors, and each N-type transistor is turned off under the action of a low level, and is turned on under a high level;
  • the corresponding input timing diagram is as Figure 4 shows. Specifically, four stages of t1, t2, t3, and t4 in the input timing chart shown in FIG. 4 are selected, VScan1 represents a first scan signal sent by the first scan signal line, and VScan2 represents a second scan signal line. The second scan signal, VScan3 represents the third scan signal from the third scan signal line.
  • the first switching transistor T1 and the second switching transistor T2 are in an on state, and the driving transistor DT1, the third switching transistor T3, and the fourth switching transistor T4 are in an off state.
  • the first voltage signal sent by the first voltage signal terminal Vdd is supplied to the first node a through the turned-on first switching transistor T1. Therefore, at this stage, the voltage of the first node a is the first voltage signal; at the first node a The voltage is supplied to the second node b through the turned-on second switching transistor T2, and the voltage at the second node b is reset. At this stage, the voltage of the second node b is the first voltage signal.
  • the third switching transistor T3 is in an on state under the control of the second scanning signal VScan2, and at the same time, the fourth switching transistor is under the control of the voltage of the second node b.
  • T4 is also in an on state, and the first switching transistor T1 and the second switching transistor T2 are in an off state.
  • the first data signal Vdata1 sent by the data signal terminal Data is supplied to the source of the fourth switching transistor T4 through the turned-on third switching transistor T3. Since the fourth switching transistor T4 is a diode connection structure, the first data signal Vdata1 is connected through a diode.
  • the fourth switching transistor T4 of the structure is transmitted to the second node b.
  • the voltage of the second node b is changed by the first voltage signal to Vdata1+Vth1, that is, the first data signal Vdata1 and the threshold voltage Vth1 are written to the second node b.
  • Vth1 is the threshold voltage of the fourth switching transistor T4.
  • the switching transistors T1, T2, and T3 are not turned on for the pixel sub-circuit 10 connected to the third scanning signal line Scan3. Since the switching transistor T3 is not turned on, the data Vdata1 is not written to the second node b of the pixel sub-circuit 10 connected to the third scanning signal line Scan3 (ie, the second node of the pixel sub-circuit 10 on the right side in FIG. 3) b).
  • the third switching transistor T3 is in an on state under the control of the third scanning signal VScan3, and at the same time, the fourth switching transistor is under the control of the voltage of the second node b.
  • T4 is also in an on state, and the first switching transistor T1 and the second switching transistor T2 are in an off state.
  • the second data signal Vdata2 sent by the data signal terminal Data is supplied to the source of the fourth switching transistor T4 through the turned-on third switching transistor T3. Since the fourth switching transistor T4 is a diode connection structure, the second data signal Vdata2 is connected through a diode.
  • the fourth switching transistor T4 of the structure is transmitted to the second node b.
  • the voltage of the second node b is changed by the first voltage signal to Vdata2+Vth1, that is, the second data signal Vdata2 and the threshold voltage Vth1 are written to the second node b.
  • Vth1 is the threshold voltage of the fourth switching transistor T4.
  • the switching transistors T1, T2, and T3 are not turned on for the pixel sub-circuit 10 connected to the second scanning signal line Scan2. Since the switching transistor T3 is not turned on, the data Vdata2 is not written to the second node b of the pixel sub-circuit 10 connected to the second scanning signal line Scan2 (ie, the second node of the pixel sub-circuit 10 on the left side in FIG. 3) b) At this time, the voltage of the second node b of the pixel sub-circuit 10 connected to the second scanning signal line Scan2 is still Vdata1 + Vth1.
  • the first switching transistor T1 and the driving transistor DT1 are in an on state, and the second switching transistor T2 and the third switching transistor T3 are in an off state.
  • the first voltage signal from the first voltage signal terminal Vdd is supplied to the first node a through the turned-on first switching transistor T1 under the control of the light-emitting control terminal to drive the light-emitting device 6 through the driving transistor DT1.
  • Light-emitting wherein the light-emitting device 6 is an organic light-emitting diode OLED.
  • the voltage difference between the gate and the drain of the driving transistor DT1 is Vdata+Vth1-Voled, and the current flowing through the driving transistor DT1 is:
  • I OLED K(VGS–Vth2) 2
  • I OLED is the current flowing through the driving transistor DT1
  • K is the operation coefficient
  • VGS is the voltage difference between the gate and the drain of the driving transistor DT1
  • Vth2 is the threshold voltage of the driving transistor DT1
  • Vdata is at the stage of t2 or t3
  • the data signal Vth1 is the threshold voltage of the fourth switching transistor T4, and Voled is the partial voltage of the light emitting device.
  • the data signal sent by the signal terminal Data is:
  • the driving current of the driving control sub-circuit driving the light-emitting device to emit light is only related to the voltage of the data signal and the voltage of the light-emitting device, and is independent of the threshold voltage in the driving control sub-circuit, and can avoid the threshold voltage of the driving control sub-circuit to the light-emitting device.
  • the voltage of the second node changes in the t2 phase and the t3 phase, the voltage is in an unstable state, and the light-emitting device does not emit light, and all the light-emitting devices perform uniform illumination in the t4 phase to improve the service life of the OLED.
  • an embodiment of the present disclosure further provides a driving method for any of the above pixel circuits. As shown in FIG. 5, the method includes:
  • the illumination control sub-circuit provides the signal of the first voltage signal end to the first node under the control of the illumination control end; the node reset sub-circuit is controlled by the first scan signal end Making the first node and the second node conductive;
  • the write sub-circuit in the pixel sub-circuit connected to the second scan line controls the first data signal and the threshold voltage sent by the data signal end under the control of the signal sent by the second scan line.
  • the write sub-circuit in the pixel sub-circuit connected to the third scan line controls the second data signal and the threshold voltage sent by the data signal end under the control of the signal sent by the third scan line.
  • the illuminating control sub-circuit provides the signal of the first voltage signal end to the first node under the control of the illuminating control end; the voltage regulator sub-circuit maintains the voltage of the second node; the driving control The sub-circuit drives the illumination device to emit light under the control of the second node.
  • the timing of the driving method of the pixel circuit is as shown in FIG. 4, the t1 phase is the reset phase, the t2 phase is the first writing phase, the t3 phase is the second writing phase, and the t4 phase is the lighting phase.
  • the t1 phase is the reset phase
  • the t2 phase is the first writing phase
  • the t3 phase is the second writing phase
  • the t4 phase is the lighting phase.
  • an embodiment of the present disclosure further provides a display panel including any one of the above-mentioned pixel circuits provided by a plurality of embodiments of the present disclosure arranged in a matrix. Since the principle of solving the problem in the display panel is similar to that of the foregoing pixel circuit, the implementation of the pixel circuit in the display panel can be referred to the implementation of the pixel circuit in the foregoing example, and the repeated description is omitted.
  • each column of pixel circuits shares one data line
  • each row of pixel circuits shares a first scan line, a second scan line, a third scan line, and an illumination control line.
  • the data line Data may be disposed between the two pixel sub-circuits 10 of the same pixel circuit, as shown in FIG. 7, the data line Data is further The same side of the two pixel sub-circuits 10 in the same pixel circuit can be disposed, which is not limited herein.
  • the three scan lines can be shared with each other.
  • the pixel circuits of the nth row and the n+1th row are taken as an example.
  • Gate n is the first scan line of the pixel circuit of the nth row, Gate.
  • n+1 is the second scan line of the pixel circuit of the nth row
  • Gate n+2 is the third scan line of the pixel circuit of the nth row
  • Gate n+1 is the first scan line of the pixel circuit of the n+1th row
  • Gate N+2 is the second scan line of the n+1th row pixel circuit
  • Gate n+3 is the third scan line of the n+1th row pixel circuit, and so on, and will not be described in detail.
  • an embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure.
  • the display device may be a display, a mobile phone, a television, a notebook computer, an electronic paper, a digital photo frame, a navigator, an all-in-one, etc., and other essential components for the display device are understood by those skilled in the art. It is not intended to be exhaustive or to limit the disclosure.

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Abstract

一种像素电路、驱动方法及显示装置，像素电路包括：至少两个像素子电路(10)、数据线(Data)、第一扫描线(Scan1)、第二扫描线(Scan2)、第三扫描线(Scan3)和发光控制线(EM)。各像素子电路(10)包括：发光控制子电路(1)、节点重置子电路(2)、驱动控制子电路(4)、写入子电路(3)和发光器件(6)。对于各像素子电路(10)：发光控制子电路(1)被配置为在发光控制端的控制下将第一电压信号端的信号提供给第一节点(a)；节点重置子电路(2)被配置为在第一扫描信号端的控制下使第一节点(a)与第二节点(b)导通；写入子电路(3)被配置为在第二扫描信号端的控制下，将数据信号端发出的数据信号和阈值电压写入第二节点(b)；驱动控制子电路(4)被配置为在第二节点(b)的控制下驱动发光器件(6)发光。

Description

像素电路、驱动方法、显示面板及显示装置
本公开要求于2017年5月31日递交的中国专利申请第201710398726.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。
技术领域
本公开实施例涉及一种像素电路、驱动方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是当今显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，LCD)相比，OLED具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、PDA、数码相机等显示领域，OLED显示屏已经开始取代传统的LCD显示屏。像素电路设计是OLED显示器核心技术内容，具有重要的研究意义。
与LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制发光。由于工艺制程和器件老化等原因，会使像素电路的驱动晶体管的阈值电压V th存在不均匀性，这样就导致了流过不同OLED像素的电流发生变化，因而使得显示亮度不均，从而影响整个图像的显示效果。
例如现有的2M1C的像素电路中，如图1所示，该电路由1个驱动晶体管M2，一个开关晶体管M1和一个存储电容Cs组成。当扫描线Scan选择某一行时，扫描线Scan输入低电平信号，P型的开关晶体管M1导通，数据线Data的电压写入存储电容Cs；当该行扫描结束后，扫描线Scan输入的信号变为高电平，P型的开关晶体管M1关断，存储电容Cs存储的电压控制驱动晶体管M2产生电流来驱动OLED像素，保证OLED像素在一帧内持续发光。例如，驱动晶体管M2的饱和电流公式为I OLED＝K(V SG-V th) 2，其中，V SG是驱动晶体管M2源极和栅极之间的电压差，K是结构系数，V th是驱动晶体管M2的阈值电压。正如前述，由于工艺制程和器件老化等原因，驱动晶体 管T2的阈值电压V th会漂移，这样就导致了流过不同OLED像素的电流因驱动晶体管的阈值电压V th的变化而变化，从而导致图像亮度不均匀。
例如，可以通过在像素电路中增加晶体管数量来改善图像亮度显示不均匀的现象，但是在像素电路中增加晶体管就会使开口率降低，不利于高像素显示。
发明内容
本公开实施例提供了一种像素电路，所述像素电路包括至少两个像素子电路，以及与所述像素电路对应的数据线、第一扫描线、第二扫描线、第三扫描线和发光控制线；其中，各所述像素子电路包括：发光控制子电路、节点重置子电路、驱动控制子电路、写入子电路和发光器件。对于各所述像素子电路：
所述发光控制子电路分别与第一电压信号端、发光控制端和第一节点连接；所述发光控制子电路被配置为在所述发光控制端的控制下将所述第一电压信号端的信号提供给所述第一节点；
所述节点重置子电路分别与第一扫描信号端、所述第一节点和第二节点连接；所述节点重置子电路被配置为在所述第一扫描信号端的控制下使所述第一节点与所述第二节点导通；
所述写入子电路分别与第二扫描信号端、数据信号端和第二节点连接；所述写入子电路被配置为在所述第二扫描信号端的控制下，将所述数据信号端发出的数据信号和阈值电压写入所述第二节点；
所述驱动控制子电路分别与所述第一节点、所述第二节点和所述发光器件连接；所述驱动控制子电路被配置为在所述第二节点的控制下驱动所述发光器件发光；以及
所述发光器件连接于所述驱动控制子电路与第二电压信号端之间。
例如，各所述像素子电路还包括稳压子电路。对于各所述像素子电路，所述稳压子电路连接于所述第二节点与第二电压信号端之间，所述稳压子电路被配置为保持所述第二节点的电位；
例如，各所述像素子电路的所述数据信号端均与所述数据线相连，各所述像素子电路的所述第一扫描信号端均与所述第一扫描信号线相连，各所述 像素子电路的所述发光控制端均与所述发光控制线相连，所述至少两个像素子电路中的第一个像素子电路的所述第二扫描信号端与所述第二扫描信号线相连，所述至少两个像素子电路中的第二个像素子电路的所述第二扫描信号端与所述第三扫描信号线相连。
例如，对于各所述像素子电路，所述发光控制子电路包括：第一开关晶体管；
所述第一开关晶体管，其栅极与所述发光控制端连接，源极与所述第一电压信号端连接，漏极与所述第一节点连接。
例如，对于各所述像素子电路，所述节点重置子电路包括：第二开关晶体管；
所述第二开关晶体管，其栅极与所述第一扫描信号端连接，源极与所述第一节点连接，漏极与所述第二节点连接。
例如，对于各所述像素子电路，所述写入子电路包括：第三开关晶体管和第四开关晶体管；
所述第三开关晶体管的栅极与所述第二扫描信号端连接，源极与所述数据信号端连接，漏极与所述第四开关晶体管的源极连接；
所述第四开关晶体管，其栅极与所述第二节点连接，源极与所述第三开关晶体管的漏极连接，漏极与所述第二节点连接。
例如，对于各所述像素子电路，所述驱动控制子电路包括：驱动晶体管；
所述驱动晶体管，其栅极与所述第二节点连接，源极与所述第一节点连接，漏极与所述发光器件连接。
例如，对于各所述像素子电路，所述稳压子电路包括：第一电容；
所述第一电容连接于所述第二节点与第二电压信号端之间。
例如，所有的开关晶体管均为N型晶体管。
相应地，本公开实施例还提供了一种上述任一种像素电路的驱动方法，包括：
在重置阶段，针对各所述像素子电路：所述发光控制子电路在所述发光控制端的控制下，将所述第一电压信号端的信号提供给所述第一节点；所述节点重置子电路在所述第一扫描信号端的控制下使所述第一节点与所述第二节点导通；
在第一写入阶段，与所述第二扫描线连接的所述像素子电路中的所述写入子电路在所述第二扫描线发出的信号的控制下，将所述数据信号端发出的第一数据信号和阈值电压写入与所述第二扫描线连接的像素子电路的所述第二节点；
在第二写入阶段，与所述第三扫描线连接的所述像素子电路中的所述写入子电路在所述第三扫描线发出的信号的控制下，将所述数据信号端发出的第二数据信号和阈值电压写入与所述第二扫描线连接的像素子电路的所述第二节点；
在发光阶段，针对各所述像素子电路：所述发光控制子电路在所述发光控制端的控制下，将所述第一电压信号端的信号提供给所述第一节点；所述稳压子电路保持所述第二节点的电压；所述驱动控制子电路在所述第二节点的控制下驱动所述发光器件发光。
相应地，本公开实施例还提供了一种有机发光显示面板，包括呈矩阵排列的多个本公开实施例提供的上述任一种像素电路；
其中，每一列所述像素电路共用一条数据线，每一行所述像素电路共用一条第一扫描线、一条第二扫描线、一条第三扫描线和一条发光控制线。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种显示面板。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有的2T1C的像素电路的结构示意图；
图2为本公开实施例提供的一种像素电路的结构示意图；
图3为本公开实施例提供的一种像素电路的具体结构示意图；
图4为图3所示的像素电路的电路时序示意图；
图5为本公开实施例提供的一种像素电路的驱动方法的流程示意图；
图6为本公开实施例提供的一种像素电路的排布方式的具体结构示意图 之一；以及
图7为本公开实施例提供的一种像素电路的排布方式的具体结构示意图之二。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
下面结合附图，对本公开实施例提供的像素电路、驱动方法、显示面板及显示装置的具体实施方式进行详细地说明。
本公开实施例提供的像素电路、驱动方法、显示面板及显示装置，用以在保证图像亮度均匀的基础上，增大开口率以及提高显示质量。例如，该像素电路包括：两个像素子电路，与该像素电路对应的数据线、第一扫描线、第二扫描线、第三扫描线和发光控制线；其中，每个像素子电路包括：发光控制子电路、节点重置子电路、驱动控制子电路、写入子电路、稳压子电路和发光器件；通过两个像素子电路共用一条数据线，从而实现利用一个像素电路来完成两个像素的驱动，大大缩减了像素之间的距离，增加了开口率，进而实现高像素显示，以提高显示质量；同时针对各像素子电路，通过上述各子电路的配合工作该像素电路可以使驱动控制子电路驱动发光器件发光的驱动电流与驱动控制子电路的阈值电压以及第一电压信号无关，能避免驱动控制子电路的阈值电压对发光器件的影响，即在使用相同的数据信号加载到不同的像素单元时，能够得到亮度相同的图像，提高了显示装置显示区域图像亮度的均匀性。
本公开实施例提供的一种像素电路，如图2所示，像素电路包括：
至少两个像素子电路10；以及
与该像素电路对应的数据线Data、第一扫描线Scan1、第二扫描线Scan2、第三扫描线Scan3和发光控制线EM；
其中，各像素子电路10包括：发光控制子电路1、节点重置子电路2、驱动控制子电路4、写入子电路3、稳压子电路5和发光器件6。
对于各像素子电路10：
发光控制子电路1分别与第一电压信号端Vdd、发光控制端和第一节点a连接；发光控制子电路被配置为在发光控制端的控制下将第一电压信号端Vdd的信号提供给第一节点a；
节点重置子电路2分别与第一扫描信号端、第一节点a和第二节点b连接；节点重置子电路被配置为在第一扫描信号端的控制下使第一节点a与第二节点b导通；
写入子电路3分别与第二扫描信号端、数据信号端和第二节点b连接；写入子电路3被配置为在第二扫描信号端的控制下，将数据信号端发出的数据信号和阈值电压写入第二节点b；
驱动控制子电路4分别与第一节点a、第二节点b和发光器件6连接；驱动控制子电路4被配置为在第二节点b的控制下驱动发光器件6发光；
发光器件6连接于驱动控制子电路4与第二电压信号端Vss之间；以及
稳压子电路5连接于第二节点与第二电压信号端Vss之间，稳压子电路5被配置为保持第二节点b的电位。
两个像素子电路10的数据信号端均与数据线Data相连，两个像素子电路10的第一扫描信号端均与第一扫描信号线Scan1相连，两个像素子电路10的发光控制端均与发光控制线EM相连；其中，一个像素子电路10的第二扫描信号端与第二扫描信号线Scan2相连(例如，参见图2左侧的子像素10)，另一个像素子电路10的第二扫描信号端与第三扫描信号线Scan3相连(例如，参见图2右侧的子像素10)。
在本公开实施例的各像素子电路10中，与数据线Data连接的端口被称作数据信号端、与扫描信号线Scan连接的端口被称作扫描信号端，与发光控制线EM连接的端口被称作发光控制端。每个像素子电路10均包括与第一扫描线Scan1连接的第一扫描信号端、以及与第二扫描线Scan2或第三扫描线Scan3连接的第二扫描信号端。
本公开实施例提供的上述像素电路中包括：至少两个像素子电路，与像素电路对应的数据线、第一扫描线、第二扫描线、第三扫描线和发光控制线；其中，各像素子电路包括：发光控制子电路、节点重置子电路、驱动控制子电路、写入子电路、稳压子电路和发光器件。通过两个像素子电路共用一条 数据线，从而实现利用一个像素电路来完成两个像素的驱动，大大缩减了像素之间的距离，增加了开口率，进而实现高像素显示，以提高显示质量；同时针对各像素子电路，通过上述各子电路的配合工作该像素电路可以使驱动控制子电路驱动发光器件发光的驱动电流与驱动控制子电路的阈值电压以及第一电压信号无关，能避免驱动控制子电路的阈值电压对发光器件的影响，即在使用相同的数据信号加载到不同的像素单元时，能够得到亮度相同的图像，提高了显示装置显示区域图像亮度的均匀性。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例中是为了更好的解释本公开，但不限制本公开。
例如，在本公开实施例提供的上述像素电路中，如图3所示，对于各子像素电路10，发光控制子电路1具体包括：第一开关晶体管T1；
第一开关晶体管T1，其栅极与发光控制端连接，源极与第一电压信号端Vdd连接，漏极与第一节点a连接。
进一步地，在具体实施时，如图3所示，第一开关晶体管T1可以为N型晶体管，此时，当发光控制端发出的发光控制信号VEM为高电平时第一开关晶体管T1处于导通状态，当发光控制端发出的发光控制信号VEM为低电平时第一开关晶体管T1处于截止状态；第一开关晶体管T1也可以为P型晶体管(在图中未示出)，此时，当发光控制端发出的发光控制信号VEM为低电平时第一开关晶体管T1处于导通状态，当发光控制端发出的发光控制信号VEM为高电平时第一开关晶体管T1处于截止状态；在此不作限定。
具体地，本公开实施例提供的上述像素电路，当第一开关晶体管在发光控制信号的控制下处于导通状态时，第一电压信号端发出的第一电压信号就通过导通的第一开关晶体管传输给第一节点。
以上仅是举例说明像素电路中发光控制子电路的具体结构，在具体实施时，发光控制子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，在本公开实施例提供的上述像素电路中，如图3所示，对于各子像素电路10，节点重置子电路2具体包括：第二开关晶体管T2；
第二开关晶体管T2，其栅极与第一扫描信号端连接，源极与第一节点a连接，漏极与第二节点b连接。
进一步地，在具体实施时，如图3所示，第二开关晶体管T2可以为N型晶体管，此时，当第一扫描信号端发出的第一扫描信号VScan1为高电平时第二开关晶体管T2处于导通状态，当第一扫描信号端发出的第一扫描信号VScan1为低电平时第二开关晶体管T2处于截止状态；第二开关晶体管T2也可以为P型晶体管(在图中未示出)，此时，当第一扫描信号端发出的第一扫描信号VScan1为低电平时第二开关晶体管T2处于导通状态，当第一扫描信号端发出的第一扫描信号VScan1为高电平时第二开关晶体管T2处于截止状态；在此不作限定。
具体地，本公开实施例提供的上述像素电路，当第二开关晶体管在第一扫描信号的控制下处于导通状态时，第一节点处的第一电压信号就通过导通的第二开关晶体管传输给第二节点。
以上仅是举例说明像素电路中节点重置子电路的具体结构，在具体实施时，节点重置子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，在本公开实施例提供的上述像素电路中，如图3所示，对于各子像素电路10，写入子电路3具体包括：第三开关晶体管T3和第四开关晶体管T4；
第三开关晶体管T3的栅极与第二扫描信号端连接，源极与数据信号端连接，漏极与第四开关晶体管T4的源极连接；
第四开关晶体管T4，其栅极与第二节点b连接，源极与第三开关晶体管T3的漏极连接，漏极与第二节点b连接。
进一步地，在具体实施时，如图3所示，第三开关晶体管T3可以为N型晶体管，此时，当第二扫描信号端发出的信号为高电平时第三开关晶体管T3处于导通状态，当第二扫描信号端发出的信号为低电平时第三开关晶体管T3处于截止状态；第三开关晶体管T3也可以为P型晶体管(在图中未示出)，此时，当第二扫描信号端发出的信号为低电平时第三开关晶体管T3处于导通状态，当第二扫描信号端发出的信号为高电平时第三开关晶体管T3处于截止状态；在此不作限定。
进一步地，在具体实施时，如图3所示，第四开关晶体管T4可以为N型晶体管，此时，当第二节点b处的电压为高电平时第四开关晶体管T4处 于导通状态，当第二节点b处的电压为低电平时第四开关晶体管T4处于截止状态。
具体地，本公开实施例提供的上述像素电路，当第三开关晶体管在第一扫描信号的控制下处于导通状态时，数据信号就通过导通的第三开关晶体管传输给第四开关晶体管的源极；当第四开关晶体管在第二节点处的电压的控制下处于导通状态时，将数据信号和第四开关晶体管的阈值电压写入第二节点。
值得注意的是，如图3所示，左侧的像素子电路10的第二扫描信号端与第二扫描信号线Scan2相连，使得左侧的第三开关晶体管T3的栅极与第二扫描信号线Scan2相连；右侧的像素子电路10的第二扫描信号端与第三扫描信号线Scan3相连，使得右侧的第三开关晶体管T3的栅极与第三扫描信号线Scan3相连。
以上仅是举例说明像素电路中写入子电路的具体结构，在具体实施时，写入子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，在本公开实施例提供的上述像素电路中，如图3所示，对于各像素子电路10，驱动控制子电路4具体包括：驱动晶体管DT1；
驱动晶体管DT1，其栅极与第二节点b连接，源极与第一节点a连接，漏极与发光器件6连接。
在具体实施时，本公开实施例提供的上述像素电路中，驱动晶体管DT1为N型晶体管。为了保证驱动晶体管DT1能正常工作，对应的第一电压信号的电压一般为正电压，第二电压信号的电压一般接地或为负值。当然，驱动晶体管DT1也可以为P型晶体管，本公开在此不作限定。
例如，在本公开实施例提供的上述像素电路中，如图3所示，稳压子电路5具体包括：第一电容C1；第一电容C1连接于第二节点b与第二电压信号端Vss之间。在具体实施时，第一电容C1用于稳定第二节点b处的电压。
例如，在本公开实施例提供的上述像素电路中，所有的开关晶体管可以均为N型晶体管，在此不作限定。
例如，本公开实施例提供的上述像素电路中提到的驱动晶体管和开关晶体管可以全部采用N型晶体管设计，这样既可以减少像素的迟滞效应，还可 以简化像素电路的制作工艺流程。
需要说明的是本公开上述实施例中是以驱动晶体管为N型晶体管为例进行说明的，对于驱动晶体管为P型晶体管且采用相同设计原理的情况也属于本公开保护的范围。
在具体实施时，驱动晶体管和开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
下面分别以图3所示的像素电路为例对本公开实施例提供的像素电路的工作过程作以描述。且下述描述中以1表示高电平信号，0表示低电平信号。
在图3所示的像素电路中，驱动晶体管DT1和所有开关晶体管均为N型晶体管，各N型晶体管在低电平作用下截止，在高电平作用下导通；对应的输入时序图如图4所示。具体地，选取如图4所示的输入时序图中的t1、t2、t3和t4四个阶段，VScan1表示第一扫描信号线发出的第一扫描信号，VScan2表示第二扫描信号线发出的第二扫描信号，VScan3表示第三扫描信号线发出的第三扫描信号。
在t1阶段，VEM＝1，VScan1＝1，VScan2＝0，VScan3＝0，Vdata＝0。
针对像素电路中的每一像素子电路10，第一开关晶体管T1和第二开关晶体管T2处于导通状态，驱动晶体管DT1、第三开关晶体管T3和第四开关晶体管T4处于截止状态。第一电压信号端Vdd发出的第一电压信号通过导通的第一开关晶体管T1提供给第一节点a，因此，此阶段，第一节点a的电压为第一电压信号；第一节点a处的电压通过导通的第二开关晶体管T2提供给第二节点b，对第二节点b处的电压进行重置，此阶段，第二节点b的电压为第一电压信号。
在t2阶段，VEM＝0，VScan1＝0，VScan2＝1，VScan3＝0，Vdata＝Vdata1。
针对与第二扫描信号线Scan2连接的像素子电路10，在第二扫描信号VScan2的控制下第三开关晶体管T3处于导通状态，同时，在第二节点b的电压的控制下第四开关晶体管T4也处于导通状态，第一开关晶体管T1、第二开关晶体管T2处于截止状态。数据信号端Data发出的第一数据信号Vdata1通过导通的第三开关晶体管T3提供给第四开关晶体管T4的源极，由 于第四开关晶体管T4为二极管连接结构，第一数据信号Vdata1通过二极管连接结构的第四开关晶体管T4传输至第二节点b，此阶段第二节点b的电压由第一电压信号变化到Vdata1+Vth1，即将第一数据信号Vdata1和阈值电压Vth1写入到第二节点b，其中Vth1为第四开关晶体管T4的阈值电压。在此阶段，即使驱动晶体管DT1在第二节点b的电压的作用下导通，由于晶体管T1截止，因此，OLED不会发光。
在t2阶段，针对与第三扫描信号线Scan3连接的像素子电路10，开关晶体管T1、T2、T3均未导通。由于开关晶体管T3未导通，因此不会将数据Vdata1写到与第三扫描信号线Scan3连接的像素子电路10的第二节点b(即图3中右侧的像素子电路10的第二节点b)。
在t3阶段，VEM＝0，VScan1＝0，VScan2＝0，VScan3＝1，Vdata＝Vdata2。
针对与第三扫描信号线Scan3连接的像素子电路10，在第三扫描信号VScan3的控制下第三开关晶体管T3处于导通状态，同时，在第二节点b的电压的控制下第四开关晶体管T4也处于导通状态，第一开关晶体管T1、第二开关晶体管T2处于截止状态。数据信号端Data发出的第二数据信号Vdata2通过导通的第三开关晶体管T3提供给第四开关晶体管T4的源极，由于第四开关晶体管T4为二极管连接结构，第二数据信号Vdata2通过二极管连接结构的第四开关晶体管T4传输至第二节点b，此阶段第二节点b的电压由第一电压信号变化到Vdata2+Vth1，即将第二数据信号Vdata2和阈值电压Vth1写入到第二节点b，其中Vth1为第四开关晶体管T4的阈值电压。在此阶段，即使驱动晶体管DT1在第二节点b的电压的作用下导通，由于晶体管T1截止，因此，OLED不会发光。
在t3阶段，针对与第二扫描信号线Scan2连接的像素子电路10，开关晶体管T1、T2、T3均未导通。由于开关晶体管T3未导通，因此不会将数据Vdata2写到与第二扫描信号线Scan2连接的像素子电路10的第二节点b(即图3中左侧的像素子电路10的第二节点b)，此时，与第二扫描信号线Scan2连接的像素子电路10的第二节点b的电压仍为Vdata1+Vth1。
在t4阶段，VEM＝1，VScan1＝0，VScan2＝0，VScan3＝0，Vdata＝0。
针对像素电路中的每一像素子电路，第一开关晶体管T1和驱动晶体管DT1处于导通状态，第二开关晶体管T2、第三开关晶体管T3处于截止状态。 在发光控制端的控制下，第一电压信号端Vdd发出的第一电压信号通过导通的第一开关晶体管T1将第一电压信号提供给第一节点a，以通过驱动晶体管DT1驱动发光器件6进行发光，其中，发光器件6为有机发光二极管OLED。此时，驱动晶体管DT1栅极和漏极之间的电压差为Vdata+Vth1-Voled，流过驱动晶体管DT1的电流为：
I OLED＝K(VGS–Vth2) 2
＝K[Vdata+Vth1–Voled–Vth2] 2
其中，I OLED为流过驱动晶体管DT1的电流，K为运算系数，VGS为驱动晶体管DT1栅极和漏极之间的电压差，Vth2为驱动晶体管DT1的阈值电压，Vdata为在t2或t3阶段的数据信号，Vth1为第四开关晶体管T4的阈值电压，Voled为发光器件的分压。
由于Vth1和Vth2分别是第四开关晶体管T4的阈值电压和驱动晶体管DT1的阈值电压，由于第四开关晶体管T4和驱动晶体管DT1距离比较近，在制备过程中应用同一工艺进行制备，因此认为Vth1与Vth2近似相等，即Vth1＝Vth2，因此，I OLED＝K(Vdata–Voled) 2。
因此，对于图3左侧的像素子电路，由于在t2阶段Vdata＝Vdata1，因此，流过驱动晶体管DT1的电流为：I OLED＝K(Vdata1–Voled) 2，其中，Vdata1为在t2阶段数据信号端Data发出的数据信号。同理，流过图3右侧的像素子电路中驱动晶体管DT1的电流为：I OLED＝K(Vdata2–Voled) 2，其中，Vdata2为在t3阶段数据信号端Data发出的数据信号。
此时，驱动控制子电路驱动发光器件发光的驱动电流仅与数据信号的电压和发光器件的电压有关，与驱动控制子电路中的阈值电压无关，能避免驱动控制子电路的阈值电压对发光器件的影响，即在使用相同的数据信号加载到不同的像素单元时，能够得到亮度相同的图像，提高了显示装置显示区域图像亮度的均匀性。并且，本公开实施例提供的像素电路中，每个像素子电路中仅需要5个晶体管和1个电容就可以实现，结构简单，有利于实现高像素的显示面板。
需要说明的是，在t2阶段和t3阶段第二节点电压发生变化时，电压处于不稳定状态，发光器件不进行发光，所有发光器件均在t4阶段进行统一的发光，以提高OLED的使用寿命。
基于同一发明构思，本公开实施例还提供了一种上述任一种像素电路的驱动方法，如图5所示，包括：
S501、在重置阶段，针对各像素子电路：发光控制子电路在发光控制端的控制下，将第一电压信号端的信号提供给第一节点；节点重置子电路在第一扫描信号端的控制下使第一节点与第二节点导通；
S502、在第一写入阶段，与第二扫描线连接的像素子电路中的写入子电路在第二扫描线发出的信号的控制下，将数据信号端发出的第一数据信号和阈值电压写入与第二扫描线连接的像素子电路的第二节点；
S503、在第二写入阶段，与第三扫描线连接的像素子电路中的写入子电路在第三扫描线发出的信号的控制下，将数据信号端发出的第二数据信号和阈值电压写入与第三扫描线连接的像素子电路的第二节点；
S504、在发光阶段，针对每一像素子电路：发光控制子电路在发光控制端的控制下，将第一电压信号端的信号提供给第一节点；稳压子电路保持第二节点的电压；驱动控制子电路在第二节点的控制下驱动发光器件发光。
像素电路的驱动方法的时序如图4所示，t1阶段为重置阶段、t2阶段为第一写入阶段、t3阶段为第二写入阶段和t4阶段为发光阶段，具体工作原理参见对上述描述像素电路结构时对图4进行的说明，在此不再详述。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括呈矩阵排列的多个本公开实施例提供的上述任一种像素电路。由于该显示面板解决问题的原理与前述一种像素电路相似，因此该显示面板中的像素电路的实施可以参见前述实例中像素电路的实施，重复之处不再赘述。
在具体实施时，每一列像素电路共用一条数据线，每一行像素电路共用一条第一扫描线、一条第二扫描线、一条第三扫描线和一条发光控制线。
在具体实施时，在本公开实施例提供的显示面板中，如图6所示，数据线Data可以设置在同一像素电路的两像素子电路10之间，如图7所示，数据线Data还可以设置在同一像素电路中的两个像素子电路10的同一侧，在此不作限定。
由于每一个像素电路中的第一扫描线、第二扫描线和第三扫描线是根据时序依次进行扫描的，因此，不同行中的像素电路中的第一扫描线、第二扫描线和第三扫描线之间可以相互共用，以第n行和第n+1行像素电路为例进 行说明，如图6和图7所示，Gate n为第n行像素电路的第一扫描线，Gate n+1为第n行像素电路的第二扫描线，Gate n+2为第n行像素电路的第三扫描线；Gate n+1为第n+1行像素电路的第一扫描线，Gate n+2为第n+1行像素电路的第二扫描线，Gate n+3为第n+1行像素电路的第三扫描线，以此类推，不再详述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以是显示器、手机、电视、笔记本电脑、电子纸、数码相框、导航仪、一体机等，对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种像素电路，包括至少两个像素子电路，以及与所述像素电路对应的数据线、第一扫描线、第二扫描线、第三扫描线和发光控制线；其中，
    各所述像素子电路包括：发光控制子电路、节点重置子电路、驱动控制子电路、写入子电路和发光器件；以及
    对于各所述像素子电路：
    所述发光控制子电路分别与第一电压信号端、发光控制端和第一节点连接；所述发光控制子电路被配置为在所述发光控制端的控制下将所述第一电压信号端的信号提供给所述第一节点；
    所述节点重置子电路分别与第一扫描信号端、所述第一节点和第二节点连接；所述节点重置子电路被配置为在所述第一扫描信号端的控制下使所述第一节点与所述第二节点导通；
    所述写入子电路分别与第二扫描信号端、数据信号端和第二节点连接；所述写入子电路被配置为在所述第二扫描信号端的控制下，将所述数据信号端发出的数据信号和阈值电压写入所述第二节点；
    所述驱动控制子电路分别与所述第一节点、所述第二节点和所述发光器件连接；所述驱动控制子电路被配置为在所述第二节点的控制下驱动所述发光器件发光；以及
    所述发光器件连接于所述驱动控制子电路与第二电压信号端之间。
  2. 如权利要求1所述的像素电路，其中，各所述像素子电路还包括稳压子电路，
    对于各所述像素子电路，所述稳压子电路连接于所述第二节点与第二电压信号端之间，所述稳压子电路被配置为保持所述第二节点的电位。
  3. 如权利要求1或2所述的像素电路，其中，各所述像素子电路的所述数据信号端均与所述数据线相连，各所述像素子电路的所述第一扫描信号端均与所述第一扫描信号线相连，各所述像素子电路的所述发光控制端均与所述发光控制线相连，所述至少两个像素子电路中的第一个像素子电路的所述第二扫描信号端与所述第二扫描信号线相连，所述至少两个像素子电路中的第二个像素子电路的所述第二扫描信号端与所述第三扫描信号线相连。
  4. 如权利要求1-3任一项所述的像素电路，其中，对于各所述像素子电 路，所述发光控制子电路包括：第一开关晶体管；
    所述第一开关晶体管，其栅极与所述发光控制端连接，源极与所述第一电压信号端连接，漏极与所述第一节点连接。
  5. 如权利要求1-4任一项所述的像素电路，其中，对于各所述像素子电路，所述节点重置子电路包括：第二开关晶体管；
    所述第二开关晶体管，其栅极与所述第一扫描信号端连接，源极与所述第一节点连接，漏极与所述第二节点连接。
  6. 如权利要求1-5任一项所述的像素电路，其中，对于各所述像素子电路，所述写入子电路包括：第三开关晶体管和第四开关晶体管；
    所述第三开关晶体管的栅极与所述第二扫描信号端连接，源极与所述数据信号端连接，漏极与所述第四开关晶体管的源极连接；
    所述第四开关晶体管，其栅极与所述第二节点连接，源极与所述第三开关晶体管的漏极连接，漏极与所述第二节点连接。
  7. 如权利要求1-6任一项所述的像素电路，其中，对于各所述像素子电路，所述驱动控制子电路包括：驱动晶体管；
    所述驱动晶体管，其栅极与所述第二节点连接，源极与所述第一节点连接，漏极与所述发光器件连接。
  8. 如权利要求2所述的像素电路，其中，对于各所述像素子电路，所述稳压子电路包括：第一电容；
    所述第一电容连接于所述第二节点与第二电压信号端之间。
  9. 如权利要求4-6任一项所述的像素电路，其中，所有的开关晶体管均为N型晶体管。
  10. 一种如权利要求1-9任一项所述的像素电路的驱动方法，包括：
    在重置阶段，针对各所述像素子电路：所述发光控制子电路在所述发光控制端的控制下，将所述第一电压信号端的信号提供给所述第一节点；所述节点重置子电路在所述第一扫描信号端的控制下使所述第一节点与所述第二节点导通；
    在第一写入阶段，与所述第二扫描线连接的像素子电路中的所述写入子电路在所述第二扫描线发出的信号的控制下，将所述数据信号端发出的第一数据信号和阈值电压写入与所述第二扫描线连接的像素子电路的所述第二节 点；
    在第二写入阶段，与所述第三扫描线连接的像素子电路中的所述写入子电路在所述第三扫描线发出的信号的控制下，将所述数据信号端发出的第二数据信号和所述阈值电压写入与所述第三扫描线连接的像素子电路的所述第二节点；以及
    在发光阶段，针对各所述像素子电路：所述发光控制子电路在所述发光控制端的控制下，将所述第一电压信号端的信号提供给所述第一节点；所述稳压子电路保持所述第二节点的电压；所述驱动控制子电路在所述第二节点的控制下驱动所述发光器件发光。
  11. 一种显示面板，包括呈矩阵排列的如权利要求1-9任一项所述的像素电路；
    其中，每一列所述像素电路共用一条数据线，每一行所述像素电路共用一条第一扫描线、一条第二扫描线、一条第三扫描线和一条发光控制线。
  12. 一种显示装置，包括权利要求11所述的显示面板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114093300A (zh) * 2020-07-30 2022-02-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN115909943A (zh) * 2022-12-27 2023-04-04 惠科股份有限公司 显示面板及电子设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106971691A (zh) 2017-05-31 2017-07-21 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN107230455A (zh) * 2017-07-21 2017-10-03 京东方科技集团股份有限公司 一种像素驱动电路、像素驱动方法和显示基板
CN109559679B (zh) * 2017-09-26 2024-07-09 京东方科技集团股份有限公司 触控显示面板及其驱动方法、像素电路、电子装置
CN108597446B (zh) * 2018-05-09 2020-03-24 京东方科技集团股份有限公司 一种像素结构及其驱动方法、显示面板及显示装置
CN111627386A (zh) * 2020-06-10 2020-09-04 武汉华星光电半导体显示技术有限公司 一种oled显示面板及显示装置
US11997892B2 (en) 2020-06-18 2024-05-28 Boe Technology Group Co., Ltd. Display panel and manufacturing method thereof, and display device
CN111899684B (zh) * 2020-08-07 2024-08-23 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078004A (zh) * 2014-06-18 2014-10-01 京东方科技集团股份有限公司 像素电路和显示装置
CN203982748U (zh) * 2014-06-18 2014-12-03 京东方科技集团股份有限公司 像素电路和显示装置
CN104252845A (zh) * 2014-09-25 2014-12-31 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
US20150364085A1 (en) * 2014-06-12 2015-12-17 Samsung Display Co., Ltd. Display circuit and display apparatus
CN105448234A (zh) * 2014-09-01 2016-03-30 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN106128362A (zh) * 2016-06-24 2016-11-16 北京大学深圳研究生院 一种像素电路及显示装置
CN106971691A (zh) * 2017-05-31 2017-07-21 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100739318B1 (ko) * 2004-11-22 2007-07-12 삼성에스디아이 주식회사 화소회로 및 발광 표시장치
TWI417843B (zh) * 2011-06-02 2013-12-01 Univ Nat Chiao Tung 對偶畫素單元及對偶驅動電路
KR101473844B1 (ko) * 2012-09-28 2014-12-17 엘지디스플레이 주식회사 유기발광 표시장치
CN103474024B (zh) 2013-09-06 2015-09-16 京东方科技集团股份有限公司 一种像素电路及显示器
CN104134426B (zh) * 2014-07-07 2017-02-15 京东方科技集团股份有限公司 像素结构及其驱动方法、显示装置
CN104112427B (zh) * 2014-07-21 2017-10-13 京东方科技集团股份有限公司 像素电路及其驱动方法和显示装置
KR102367483B1 (ko) 2014-09-23 2022-02-25 엘지디스플레이 주식회사 유기발광 다이오드 표시장치
CN104318898B (zh) 2014-11-11 2017-12-08 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN105825813B (zh) * 2016-05-25 2018-12-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
CN106531084B (zh) * 2017-01-05 2019-02-05 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150364085A1 (en) * 2014-06-12 2015-12-17 Samsung Display Co., Ltd. Display circuit and display apparatus
CN104078004A (zh) * 2014-06-18 2014-10-01 京东方科技集团股份有限公司 像素电路和显示装置
CN203982748U (zh) * 2014-06-18 2014-12-03 京东方科技集团股份有限公司 像素电路和显示装置
CN105448234A (zh) * 2014-09-01 2016-03-30 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN104252845A (zh) * 2014-09-25 2014-12-31 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN106128362A (zh) * 2016-06-24 2016-11-16 北京大学深圳研究生院 一种像素电路及显示装置
CN106971691A (zh) * 2017-05-31 2017-07-21 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114093300A (zh) * 2020-07-30 2022-02-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN115909943A (zh) * 2022-12-27 2023-04-04 惠科股份有限公司 显示面板及电子设备
CN115909943B (zh) * 2022-12-27 2023-11-17 惠科股份有限公司 显示面板及电子设备

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