WO2023016138A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2023016138A1
WO2023016138A1 PCT/CN2022/103403 CN2022103403W WO2023016138A1 WO 2023016138 A1 WO2023016138 A1 WO 2023016138A1 CN 2022103403 W CN2022103403 W CN 2022103403W WO 2023016138 A1 WO2023016138 A1 WO 2023016138A1
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Prior art keywords
transistor
node
pole
circuit
sub
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PCT/CN2022/103403
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English (en)
French (fr)
Inventor
卢江楠
刘利宾
单真真
史世明
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京东方科技集团股份有限公司
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Priority to US18/274,958 priority Critical patent/US20240144884A1/en
Publication of WO2023016138A1 publication Critical patent/WO2023016138A1/zh

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Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a pixel driving circuit and a display panel.
  • AMOLED Active matrix organic electrode light emitting diode display panel
  • OLED Organic Light-Emitting Diode
  • AMOLED can emit light by driving a thin-film transistor to generate a driving current in a saturated state, and the driving current drives the light-emitting device to emit light.
  • the present invention aims to solve at least one of the technical problems in the prior art, and provides a pixel driving circuit and a display panel.
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes: a data writing subcircuit, a threshold compensation subcircuit, a driving subcircuit, a storage subcircuit, a first reset subcircuit and a second reset subcircuit; wherein , the connection node between the driving sub-circuit and the second end of the storage sub-circuit is the first node; the connection node between the data writing sub-circuit and the second end of the storage sub-circuit is the second node Two nodes; the connection node between the driving subcircuit and the threshold compensation subcircuit is a third node;
  • the first reset subcircuit includes a first transistor, the control pole of the first transistor is connected to the first reset signal line, the first pole is connected to the first initialization signal line, and the second pole is connected to the first node;
  • the second reset subcircuit is configured to reset the potential of the second node through a reference voltage under the control of a second reset signal
  • the data writing sub-circuit is configured to transmit a data voltage signal to the second node in response to a first scan signal, and store it through the storage sub-circuit;
  • the threshold compensation sub-circuit includes a second transistor, the first pole of the second transistor is connected to the first node, the second pole is connected to the second node, and the control pole is connected to the second scanning line;
  • the driving sub-circuit is configured to provide a driving current for the light emitting device to be driven according to the potentials of the first node and the third node;
  • the storage sub-circuit is configured to store the data voltage; wherein,
  • the first transistor and/or the second transistor includes an oxide thin film transistor.
  • the pixel driving circuit further includes: a first light emission control subcircuit and a second light emission control subcircuit;
  • the first light emission control subcircuit is configured to transmit the driving current generated by the driving subcircuit to the light emitting device to be driven under the control of the first light emission control signal;
  • the second light emission control subcircuit is configured to transmit the reference voltage to the second node under the control of a second light emission control signal.
  • the first light emission control subcircuit includes a sixth transistor; the second light emission control subcircuit includes a seventh transistor;
  • the first pole of the sixth transistor is connected to the third node, the second pole is connected to the light-emitting device to be driven, and the control pole is connected to the first light-emitting control line;
  • the first electrode of the seventh transistor is connected to the reference voltage line, the second electrode is connected to the second node, and the control electrode is connected to the second light emission control line.
  • the switching characteristics of the sixth transistor and the seventh transistor are the same and opposite to those of the first transistor.
  • the pixel driving circuit further includes: a third reset subcircuit
  • the third reset sub-circuit is configured to initialize the light-emitting device to be driven through the second initialization signal on the control line of the third reset signal.
  • the third reset subcircuit includes an eighth transistor
  • the first pole of the eighth transistor is connected to the first pole of the light-emitting device to be driven, the second pole is connected to the second initialization signal line, and the control pole is connected to the third reset signal line.
  • the switching characteristics of the eighth transistor and the sixth transistor are opposite, and the first lighting control line is multiplexed with the second reset signal line.
  • the eighth transistor includes an oxide thin film transistor.
  • the driving sub-circuit includes: a third transistor
  • the first pole of the third transistor is connected to the first power supply voltage line, the second pole is connected to the third node, and the control pole is connected to the first node.
  • the switching characteristic of the third transistor is opposite to that of the first transistor.
  • the data writing sub-circuit includes: a fourth transistor
  • the first pole of the fourth transistor is connected to the data line, the second pole is connected to the second node, and the control pole is connected to the first scan line.
  • the switching characteristic of the fourth transistor is opposite to that of the first transistor.
  • the second reset subcircuit includes: a fifth transistor
  • the first pole of the fifth transistor is connected to the reference voltage line, the second pole is connected to the second node, and the control pole is connected to the second reset signal line.
  • the switching characteristic of the fifth transistor is opposite to that of the first transistor.
  • the storage sub-circuit includes a storage capacitor, and a first end of the storage capacitor is connected to the second node. The second end is connected to the first node.
  • An embodiment of the present disclosure also provides a pixel driving circuit, which includes: a data writing sub-circuit, a threshold compensation sub-circuit, a driving sub-circuit, a storage sub-circuit, a first reset sub-circuit, a second reset sub-circuit, a third reset sub-circuit circuit, the first light emission control subcircuit, and the second light emission control subcircuit; wherein, the connection node between the driving subcircuit and the second end of the storage subcircuit is the first node; the data writing The connection node between the subcircuit and the first end of the storage subcircuit is a second node; the connection node between the driving subcircuit and the threshold compensation subcircuit is a third node;
  • the first reset subcircuit includes a first transistor, the first pole of the first transistor is connected to the first initialization signal line, the second pole is connected to the first node, and the control pole is connected to the first reset signal line;
  • the second reset subcircuit includes a fifth transistor, the first pole of the fifth transistor is connected to the reference voltage line, the second pole is connected to the second node, and the control pole is connected to the second reset signal line;
  • the driving sub-circuit includes a third transistor, the first pole of the third transistor is connected to the first power supply voltage line, the second pole is connected to the third node, and the control pole is connected to the first node;
  • the data writing sub-circuit includes: a fourth transistor, the first pole of the fourth transistor is connected to the data line, the second pole is connected to the second node, and the control pole is connected to the first scanning line;
  • the threshold compensation sub-circuit includes a second transistor, the first pole of the second transistor is connected to the first node, the second pole is connected to the second node, and the control pole is connected to the second scanning line;
  • the first light emission control sub-circuit includes a sixth transistor, the first electrode of the sixth transistor is connected to the third node, the second electrode is connected to the light emitting device to be driven, and the control electrode is connected to the first light emission control line;
  • the second light emission control sub-circuit includes a seventh transistor, the first electrode of the seventh transistor is connected to the reference voltage line, the second electrode is connected to the second node, and the control electrode is connected to the second light emission control line;
  • the third reset sub-circuit includes an eighth transistor, the first pole of the eighth transistor is connected to the first pole of the light emitting device to be driven, the second pole is connected to the second initialization signal line, and the control pole is connected to the third Reset signal line;
  • the storage sub-circuit includes a storage capacitor, the first end of the storage capacitor is connected to the second node, and the second end is connected to the first node;
  • the first transistor and/or the second transistor includes an oxide thin film transistor.
  • the switching characteristics of the first transistor, the second transistor and the eighth transistor are the same;
  • the switching characteristics of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the same; and the switching characteristics of the first transistor and the third transistor are opposite .
  • an embodiment of the present disclosure provides a display panel, which includes any one of the pixel driving circuits described above.
  • FIG. 1 is a schematic diagram of an exemplary display substrate structure.
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit.
  • FIG. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 4 is a working timing diagram of the pixel driving circuit shown in FIG. 3 .
  • FIG. 5 is a working timing diagram of the pixel driving circuit shown in FIG. 3 .
  • Fig. 1 is a schematic structural diagram of an exemplary display substrate
  • Fig. 2 is a schematic diagram of an exemplary pixel driving circuit
  • the display substrate includes a plurality of pixel units arranged in an array, each Each pixel unit 100 includes a pixel driving circuit and a light emitting device D.
  • the pixel driving circuit in each pixel unit 100 may include: a first reset subcircuit 11, a threshold compensation subcircuit 121, a driving subcircuit 13, a data writing subcircuit 14, a first light emission control subcircuit 15, a second light emission control subcircuit Circuit 16 , second reset subcircuit 17 and storage subcircuit 18 .
  • the first reset subcircuit 11 is connected to the control terminal of the driving subcircuit 13 and is configured to reset the control terminal of the driving subcircuit 13 under the control of the first reset signal.
  • the threshold compensation sub-circuit 12 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 13 , and is configured to perform threshold compensation on the driving sub-circuit 13 .
  • the data writing sub-circuit 14 is electrically connected to the first end of the driving sub-circuit 13 and is configured to write data signals into the storage sub-circuit under the control of the scan signal.
  • the storage sub-circuit 8 is electrically connected to the control terminal of the driving sub-circuit 13 and the first power supply voltage line VDD11 respectively, and is configured to store data signals.
  • the first light emission control sub-circuit 15 is respectively connected to the first power supply voltage line VDD11 and the first end of the driving sub-circuit 13, and is configured to realize the connection between the driving sub-circuit 13 and the first power supply voltage line VDD11.
  • the second light emission control subcircuit 16 is electrically connected to the second terminal of the driving subcircuit 13 and the first electrode of the light emitting device D, and is configured to realize the connection between the driving subcircuit 13 and the light emitting device D to be turned on or off open.
  • the second reset subcircuit 17 is electrically connected to the first electrode of the light emitting device D, and is configured to reset the control terminal of the driving subcircuit 13 and the first electrode of the light emitting device D under the control of the second reset control signal.
  • the first reset subcircuit includes a first reset transistor T11
  • the threshold compensation subcircuit 12 includes a threshold compensation transistor T12
  • the driving subcircuit 13 includes a driving transistor T13
  • the control terminal of the driving subcircuit 13 includes a control terminal of the driving transistor T13. pole, the first end of the driving sub-circuit 13 includes the first pole of the driving transistor T13, and the second end of the driving sub-circuit 13 includes the second pole of the driving transistor T13.
  • the data writing subcircuit 14 includes a data writing transistor T14, the storage subcircuit 18 includes a storage capacitor Cst11, the first light emission control subcircuit 15 includes a first light emission control transistor T15, and the second light emission control subcircuit 16 includes a second light emission control transistor. T16, the second reset subcircuit 17 includes a second reset transistor T17.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the pixel driving circuit in FIG. The example elaborates the technical solution of the present disclosure in detail, that is to say, in the description of the present disclosure, the driving transistor T13, the data writing transistor T14, the threshold compensation transistor T12, the first light emission control transistor T15, the second light emission control transistor T16, Both the first reset transistor T11 and the second reset transistor T17 can be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can use N-type transistors (for example, N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control pole is used as the gate of the transistor, one of the first pole and the second pole is used as the source of the transistor, and the other is used as the transistor
  • the drain of the transistor; and the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the first pole is the source and the second pole is the drain, so the sources of all or part of the transistors in the embodiments of the present disclosure and drain are interchangeable as required.
  • the drain of the data writing transistor T14 is electrically connected to the source of the driving transistor T13, the source of the data writing transistor T14 is configured to be electrically connected to the data line Data11 to receive a data signal, and the data writing transistor T14
  • the gate is configured to be electrically connected to the first scanning signal line Ga11 to receive the scanning signal;
  • the second plate of the storage capacitor Cst11 is electrically connected to the first power supply voltage line VDD11, and the first plate of the storage capacitor Cst11 is connected to the drive transistor T13
  • the gate of the threshold compensation transistor T12 is electrically connected to the gate of the driving transistor T13, the drain of the threshold compensation transistor T12 is electrically connected to the drain of the driving transistor T13, and the gate of the threshold compensation transistor T12 is configured as It is electrically connected to the second scanning signal line Ga12 to receive the compensation control signal;
  • the source of the first reset transistor T11 is configured to be electrically connected to the first initialization signal line VInit11 to receive the first reset signal, and the drain of the
  • the gate of the first light emission control transistor T15 is configured to be electrically connected to the first light emission control signal line EM11 to receive the first light emission control signal;
  • the source of the second light emission control transistor T16 is electrically connected to the drain of the driving transistor T13 , the drain of the second light emission control transistor T16 is electrically connected to the first pole of the light emitting device D, and the gate of the second light emission control transistor T16 is configured to be electrically connected to the second light emission control signal line EM12 to receive the second light emission control signal ;
  • the second electrode of the light emitting device D is electrically connected to the second power supply terminal VSS11.
  • one of the first power supply voltage line VDD11 and the second power supply terminal VSS11 is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power supply voltage line VDD11 is a voltage source to output a constant first voltage, and the first voltage is a positive voltage
  • the second power supply terminal VSS11 can be a voltage source to output a constant second voltage
  • the second voltage is a negative voltage or the like.
  • the second power supply terminal VSS11 may be grounded.
  • the scan signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T14 and the gate of the threshold compensation transistor T12 can be electrically connected to the same signal line, such as the first scan signal line Ga11, to To receive the same signal (for example, a scan signal), at this time, the display substrate may not be provided with the second scan signal line Ga12 to reduce the number of signal lines.
  • the gate of the data writing transistor T14 and the gate of the threshold compensation transistor T12 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T14 is electrically connected to the first scanning signal line Ga11, and the threshold The gate of the compensation transistor T12 is electrically connected to the second scanning signal line Ga12, and the signals transmitted by the first scanning signal line Ga11 and the second scanning signal line Ga12 are the same.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T14 and the threshold compensation transistor T12 can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the gate of the data writing transistor T14 and the gate of the threshold compensation transistor T12 are electrically connected to the first scanning signal line Ga(A) as an example for illustration.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T15 and the gate of the second light emission control transistor T16 may be electrically connected to the same signal line, for example
  • the first light emission control signal line EM11 is used to receive the same signal (for example, the first light emission control signal).
  • the display substrate may not be provided with the second light emission control signal line EM12 to reduce the number of signal lines.
  • the gate of the first light emission control transistor T15 and the gate of the second light emission control transistor T16 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T15 is electrically connected to the first light emission control transistor T15.
  • the control signal line EM11 and the gate of the second light emission control transistor T16 are electrically connected to the second light emission control signal line EM12 , and the signals transmitted by the first light emission control signal line EM11 and the second light emission control signal line EM12 are the same.
  • first light emission control transistor T15 and the second light emission control transistor T16 are transistors of different types, for example, the first light emission control transistor T15 is a P-type transistor, and the second light emission control transistor T16 is an N-type transistor.
  • the first light emission control signal and the second light emission control signal may also be different, which is not limited in this embodiment of the present disclosure.
  • the gates of the first light emission control transistor T15 and the second light emission control transistor T16 are both connected to the light emission control line EM as an example for illustration.
  • the first reset control signal and the second reset control signal can be the same, that is, the gate of the first reset transistor T11 and the gate of the second reset transistor T17 can be electrically connected to the same signal line, such as the first reset signal line Rst11 to receive the same signal (for example, the first sub-reset control signal), at this time, the display substrate may not be provided with the second reset signal line Rst12 to reduce the number of signal lines.
  • the gate of the first reset transistor T11 and the gate of the second reset transistor T17 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T11 is electrically connected to the first reset signal line Rst11, The gate of the second reset transistor T17 is electrically connected to the second reset signal line Rst12 , and the signals transmitted by the first reset control signal line Rst11 and the second reset signal line Rst12 are the same. It should be noted that the first reset signal and the second reset signal may also be different. In the embodiment of the present disclosure, it is taken as an example that both the gate of the first reset transistor T11 and the gate of the second reset transistor T17 are electrically connected to the reset control signal line Rst.
  • the second reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T17 may be electrically connected to the scan signal line Ga(A) to receive the scan signal as the second sub-reset control signal.
  • the source of the first reset transistor T11 and the drain of the second reset transistor T17 are respectively connected to the first initialization signal line VInit11 and the second initialization signal line VInit12, and the first initialization signal line VInit11 and the second initialization signal line initialization signal
  • the line VInit12 can be a DC reference voltage terminal to output a constant DC reference voltage.
  • the first initialization signal line VInit11 and the second initialization signal line VInit12 may be the same, for example, the source of the first reset transistor T11 and the drain of the second reset transistor T17 are connected to the same initialization signal line.
  • the first initialization signal line VInit11 and the second initialization signal line VInit12 can be high-voltage signal lines or low-voltage signal lines, as long as they can provide the first reset signal and the first reset signal to drive the gate of the transistor T13 and the first pole of the light emitting element can be reset, and the present disclosure is not limited thereto.
  • the source of the first reset transistor T11 and the drain of the second reset transistor T17 may both be connected to the reset power signal line Init.
  • both the gate of the first reset transistor T11 and the gate of the second reset transistor T17 are electrically connected to Rst11; the source of the first reset transistor T11 and the gate of the second reset transistor
  • the drain of T17 is electrically connected to the reset power signal line Init as an example for illustration.
  • the second reset subcircuit 17 and the storage subcircuit 8 are only schematic, the first reset subcircuit 11, the threshold compensation subcircuit 12, the driving subcircuit 13, the data writing subcircuit 14, and the first light emission control subcircuit 15.
  • the specific structures of the second lighting control sub-circuit 16 , the second reset sub-circuit 17 , and the storage sub-circuit 8 can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • circuit structure such as a 7T12C structure, a 6T1C structure, a 6T12C structure or a 9T12C structure, is not limited in this embodiment of the present disclosure.
  • the light emitting device D in the embodiment of the invention may be an organic light emitting diode (Organic Light Emitting Diode, OLED).
  • OLED Organic Light Emitting Diode
  • the light-emitting device D can also be a miniature inorganic light-emitting diode, further, it can be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED).
  • One of the first electrode and the second electrode of the light-emitting device D is an anode, and the other is a cathode; in the embodiment of the present invention, the first electrode and the second electrode of the light-emitting device D are taken as an example for illustration.
  • each transistor in the pixel driving circuit is a low-temperature polysilicon transistor, and the drain of the first reset transistor and the source of the threshold compensation transistor are both connected to the gate of the driving transistor. Therefore, the first reset transistor and the When the threshold compensation transistor leaks, it will affect the gate voltage of the drive transistor, causing abnormal display problems.
  • FIG. 3 is a schematic diagram of a pixel driving circuit of an embodiment of the present disclosure
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes: a data writing sub-circuit 24, a threshold compensation Circuit 22, drive subcircuit 23, storage subcircuit 29, first reset subcircuit 21 and second reset subcircuit 25; wherein, the connection node between the second end of drive subcircuit 23 and storage subcircuit 29 is the first Node N1; the connection node between the data writing sub-circuit 24 and the second end of the storage sub-circuit 29 is the second node N2; the connection node between the driving sub-circuit 23 and the threshold compensation sub-circuit 22 is the third node N3.
  • the first reset subcircuit 21 is configured to initialize (that is, reset) the potential of the first node N1 through the first initialization signal under the control of the first reset signal.
  • the second reset sub-circuit 25 is configured to write the reference voltage into the second node N2 under the control of the second reset signal, so as to reset the second node N2.
  • the data write sub-circuit 24 is configured to transmit the data voltage signal to the second node N2 in response to the first scan signal, and store it through the storage sub-circuit 29;
  • the threshold compensation sub-circuit 22 is configured to respond to the second scan signal , write the threshold voltage into the first node N1.
  • the driving sub-circuit 23 is configured to provide a driving current for the light emitting device D to be driven according to the potentials of the first node N1 and the third node N3.
  • the storage sub-circuit 29 is configured to store the data voltage.
  • the first reset subcircuit 21 may include a first transistor T21
  • the threshold compensation subcircuit 22 may include a second transistor T22.
  • the source of the first transistor T21 is connected to the first initialization signal line Init21
  • the drain of the first transistor T21 is connected to the first node N1
  • the gate of the first transistor T21 is connected to the first reset signal line Rst21 .
  • the source of the second transistor T22 is connected to the first node N1, the drain of the second transistor T22 is connected to the third node N3, and the gate of the second transistor T22 is connected to the second scanning line Ga2.
  • at least one of the first transistor T21 and the second transistor T22 is an oxide thin film transistor.
  • the first transistor T21 Since the drain of the first transistor T21 and the source of the second transistor T22 are both connected to the first node N1, at this time, if the first transistor T21 is an oxide thin film transistor, it can effectively prevent the leakage of the first transistor T21 from affecting the first node N1.
  • the potential of the node N1 is the same, if the second transistor T22 is an oxide thin film transistor, it can effectively prevent the leakage of the second transistor T22 from affecting the potential of the first node N1.
  • the preferred first transistor T21 and the second transistor T22 in the embodiment of the present disclosure are oxide thin film transistors. In the following description, both the first transistor T21 and the second transistor T22 use oxide thin film transistors as an example for description.
  • the first transistor T21 and the second transistor T22 are not only oxide thin film transistors, but also have the same switching characteristics.
  • the second transistor T22 can be formed while the first transistor T21 is formed, Therefore, the process steps and costs will not be increased.
  • both the first transistor T21 and the second transistor T22 are N-type transistors.
  • the pixel driving circuit in the embodiment of the present disclosure not only includes the above structure, but also includes a first light emission control sub-circuit 26 and a second light emission control sub-circuit 27 .
  • the first light emission control subcircuit 26 is configured to transmit the drive current generated by the drive subcircuit 23 to the light emitting device D to be driven under the control of the first light emission control signal;
  • the second light emission control subcircuit 27 is configured to Under the control of the second lighting control signal, the reference voltage is transmitted to the second node N2.
  • the first light emission control subcircuit 26 includes a sixth transistor T26
  • the second light emission control subcircuit 27 includes a seventh transistor T27.
  • the source of the sixth transistor T26 is connected to the third node N3, the drain of the sixth transistor T26 is connected to the anode of the light emitting device D to be driven, and the gate of the sixth transistor T26 is connected to the light emission control line EM and the first light emission control line EM21.
  • the source of the seventh transistor T27 is connected to the reference voltage line, the drain of the seventh transistor T27 is connected to the second node N2, and the gate of the seventh transistor T27 is connected to the light emission control line EM and the second light emission control line EM22.
  • the light emission control line EM for controlling the first light emission control subcircuit 26 and the light emission control line EM21 for controlling the second light emission control subcircuit 27 may be the same light emission control line EM.
  • the light emission control line EM, the first light emission control line EM21 and the light emission control line EM, the second light emission control line EM22 are the same light emission control line EM as an example, that is, the light emission control line EM, the first light emission control line EM21 and the light emission control line EM21
  • the control line EM and the second light emission control line EM22 are both called light emission control lines EM.
  • the switching characteristics of the sixth transistor T26 and the seventh transistor T27 may be the same, and may be the same as the switching characteristics of the first transistor T21, that is, the first transistor T21 adopts an N-type transistor. All seven transistors T27 are P-type transistors, otherwise, vice versa.
  • the sixth transistor T26 and the seventh transistor T27 may be low temperature polysilicon thin film transistors or oxide thin film transistors. In the embodiment of the present disclosure, it is taken as an example that both the sixth transistor T26 and the seventh transistor T27 are low-temperature polysilicon thin film transistors.
  • the first reset signal line Rst21 writes a high-level signal
  • the first transistor T21 is turned on
  • the potential of the first node N1 is controlled by the first initialization signal written on the first initialization signal line Init21. initialization.
  • the second reset signal is a working level signal
  • the second reset sub-circuit 25 works, and writes the reference voltage into the second node N2 to initialize the potential of the second node N2.
  • the first scanning signal is an operating level signal
  • the data writing sub-circuit 24 is working
  • the data voltage signal is written into the second node N2 through the data writing sub-circuit 24, that is, the second node N2
  • the second scan line Ga2 is written with a high-level signal
  • the second transistor T22 is turned on
  • the threshold voltage Vth is written into the first node N1 through the second transistor T22.
  • the first node N1 The sum of the first power supply voltage VDD21 and the threshold voltage Vth, that is, the potential of the first node N1 is VDD21+Vth.
  • a low-level signal is written to the light-emitting control line EM, the sixth transistor T26 and the seventh transistor T27 are turned on at the same time, and the potential of the second node N2 jumps from Vdata21 to the reference voltage Vref.
  • the jump voltage of the second node N2 is written into the first node N1, and the potential of the first node N1 at this time is VDD21+Vth+Vref ⁇ Vdata21.
  • the driving sub-circuit 23 drives the light-emitting device D to emit light according to the driving current generated by the first node N1 and the third node N3.
  • the pixel driving circuit in the embodiment of the present disclosure not only includes the above structure, but also includes a third reset sub-circuit 28 .
  • the third reset sub-circuit 28 is configured to reset the potential of the anode of the light emitting device D through the second initialization signal on the control line of the third reset signal.
  • the first reset subcircuit 21 is used to reset the first node N1
  • the second reset subcircuit 25 is used to reset the anode of the light emitting device D; that is, the reset circuit of the first node N1 and
  • the reset circuits for the anode of the light emitting device D are two different reset circuits.
  • the reset of the anode of the light-emitting device D can be independently controlled.
  • different initialization voltages can be used for reset, and not only The anode of the light-emitting device D is initialized through the third reset sub-circuit 28 in the initialization phase when refreshing each frame, and can also be initialized through the third reset sub-circuit 28 when the frame is maintained.
  • the holding frame refers to a time period between refreshing two frames of images. In this way, the brightness difference between the refresh frame and the maintain frame can be effectively improved, and the probability of flicker (Flicker) on the display panel can be reduced.
  • the third reset sub-circuit 28 may include an eighth transistor T28, the source of the eighth transistor T28 is connected to the anode of the light-emitting device D to be driven, the drain of the eighth transistor T28 is connected to the second initialization signal line Init22, and the eighth transistor T28 The gate of T28 is connected to the third reset signal line Rst23.
  • the switching characteristic of the eighth transistor T28 may be the same as that of the first transistor T21, that is, the switching characteristic of the sixth transistor T26 in the first light emission control circuit is opposite.
  • the light emission control line EM can be multiplexed as the third reset signal line Rst23.
  • a PWM modulation signal is used as the light-emitting control signal, and four pulse signals are inserted into the light-emitting control line EM in one cycle (the time for refreshing one frame+the time for maintaining the frame) as an example.
  • the light emission control signal written into the light emission control line EM is a high level signal
  • the eighth transistor T28 is turned on
  • the anode of the light emitting device D is reset through the second initialization signal written in the second initialization line.
  • the light-emitting control signal written to the light-emitting control line EM is a low-level signal
  • the sixth transistor T26 is turned on, and the driving current generated by the driving sub-circuit 23 is transmitted to the light-emitting device D through the sixth transistor T26 to drive the light-emitting device D shines.
  • the emission control line EM and the third reset signal line Rst23 are multiplexed, the number of control signal lines can be effectively reduced, which helps to improve the pixel aperture ratio of the display substrate to which the pixel driving circuit is applied.
  • the eighth transistor T28 may not have the same switching characteristics as the first transistor T21, and the switching characteristics of the sixth transistor T26 may be used. thin film transistors with the same characteristics.
  • the eighth transistor T28 in the third reset subcircuit 28 in the embodiment of the present disclosure adopts a thin film transistor with the same switching characteristics as the first transistor T21 in the first reset subcircuit 21, the eighth transistor T28 preferably The oxide thin film transistor is used, so that the eighth transistor T28 can be formed while the first transistor T21 is formed, without increasing process steps and costs.
  • the eighth transistor T28 it is also feasible to use other types of thin film transistors for the eighth transistor T28, for example, use low temperature polysilicon thin film transistors.
  • the driving sub-circuit 23 includes a third transistor T23, the source of the third transistor T23 is connected to the first power supply voltage line VDD21, and the third The drain of the transistor T23 is connected to the third node N3, and the gate of the third transistor T23 is connected to the first node N1.
  • the third transistor T23 can generate a corresponding driving current according to the potentials of its gate (first node N1 ) and source (VDD), so as to drive the light-emitting device D to emit light.
  • the switching characteristics of the third transistor T23 are opposite to those of the first switching transistor, that is, the third transistor T23 is a P-type transistor.
  • the data writing sub-circuit 24 may include a fourth transistor T24, and the source of the fourth transistor T24 is connected to the data line Data21, the drain of the fourth transistor T24 is connected to the second node N2, and the gate of the fourth transistor T24 is connected to the first scanning line Ga1.
  • the switching characteristic of the fourth transistor T24 is opposite to that of the first transistor T21 in the first reset sub-circuit 21 , that is, the fourth transistor T24 is a P-type transistor.
  • the first scan line Ga1 writes a low-level signal
  • the fourth transistor T24 is turned on
  • the data voltage signal written on the data line Data21 is written into the second transistor T24 through the fourth transistor T24. node N2, and store it through the storage sub-circuit 29.
  • the switching characteristics of the fourth transistor T24 can also be the same as that of the first transistor T21 in the first reset sub-circuit 21, that is, the fourth transistor T24 can also be an N-type transistor.
  • Line Ga1 works when a high level signal is written.
  • the fourth transistor T24 in the embodiment of the present disclosure may be an oxide thin film transistor or a low temperature polysilicon thin film transistor, or other types of thin film transistors.
  • the fourth transistor T24 adopts a low temperature polysilicon thin film transistor as example.
  • the second reset sub-circuit 25 therein may include a fifth transistor T25, the source of which is connected to the reference The drain of the fifth transistor T25 is connected to the second stage, and the gate of the fifth transistor T25 is connected to the second reset signal line Rst22.
  • the fifth transistor T25 when the switching characteristics of the fifth transistor T25 and the first transistor T21 in the first reset sub-circuit 21 are opposite, that is, the fifth transistor T25 is a P-type transistor.
  • the fifth transistor T25 in the initialization phase, can be turned on by writing a low-level signal to the second reset signal line Rst22, and at this time, the potential of the second node N2 can be initialized by the reference voltage written on the reference voltage line , that is, the reset of the second node N2 is completed.
  • the fifth transistor T25 can also have the same switching characteristics as the first transistor T21 in the first reset sub-circuit 21, that is, the fifth transistor T25 can also be an N-type transistor, and at this time, the fifth transistor T25 is in the first scanning mode.
  • Line Ga1 works when a high level signal is written.
  • the fifth transistor T25 in the embodiment of the present disclosure may be an oxide thin film transistor or a low temperature polysilicon thin film transistor, or other types of thin film transistors.
  • the fifth transistor T25 adopts a low temperature polysilicon thin film transistor as example.
  • the storage subcircuit 29 may include a storage capacitor Cst21, the first end of the storage capacitor Cst21 is connected to the second node N2, The second end of the storage capacitor Cst21 is connected to the first node N1.
  • the specific function of the storage capacitor Cst21 in the pixel driving circuit will be described in detail in the following driving method of the pixel driving circuit.
  • an embodiment of the present disclosure provides a pixel driving circuit, a data writing subcircuit 24, a threshold compensation subcircuit 22, a driving subcircuit 23, a storage subcircuit 29, a first reset subcircuit 21, a second reset subcircuit Subcircuit 25, the third reset subcircuit 28, the first light emission control subcircuit 26 and the second light emission control subcircuit 27; wherein, the connection node between the second end of the driving subcircuit 23 and the storage subcircuit 29 is The first node N1; the connection node between the data writing sub-circuit 24 and the first end of the storage sub-circuit 29 is the second node N2; the connection node between the driving sub-circuit 23 and the threshold compensation sub-circuit 22 is the third node N3; the first reset subcircuit 21 includes a first transistor T21; the second reset subcircuit 25 includes a fifth transistor T25; the driving subcircuit 23 includes a third transistor T23; the data writing subcircuit 24 includes a fourth transistor T24; the threshold compensation
  • the first transistor T21 and the second transistor T22 is an oxide thin film transistor, and in the following description, it is taken that both the first transistor T21 and the second transistor T22 are oxide thin film transistors as an example.
  • the eighth transistor T28 may also be an oxide thin film transistor, and in order to reduce process steps, the switching characteristics of the first transistor T21, the second transistor T22, and the eighth transistor T28 are the same.
  • the first transistor T21 , The second transistor T22 and the eighth transistor T28 take N-type transistors as an example.
  • the switching characteristics of the third transistor T23, the fourth transistor T24, the fifth transistor T25, the sixth transistor T26, and the seventh transistor T27 are opposite to those of the first transistor T21, that is, the third transistor T23, the fourth transistor T24, the seventh transistor T27
  • the fifth transistor T25, the sixth transistor T26 and the seventh transistor T27 are P-type transistors.
  • the third transistor T23, the fourth transistor T24, the fifth transistor T25, the sixth transistor T26 and the seventh transistor T27 Low-temperature polysilicon thin film transistors can be used.
  • the third transistor T23, the fourth transistor T24, the fifth transistor T25, the sixth transistor T26 and the seventh transistor T27 can also use oxide thin film transistors or other types of thin film transistors.
  • the third transistor T23 , the fourth transistor T24 , the fifth transistor T25 , the sixth transistor T26 and the seventh transistor T27 adopt low-temperature polysilicon thin film transistors as an example.
  • the source of the first transistor T21 is connected to the first initialization signal line Init21
  • the drain of the first transistor T21 is connected to the first node N1
  • the gate of the first transistor T21 is connected to the first reset signal line Rst21 .
  • the source of the fifth transistor T25 is connected to the reference voltage line, the drain of the fifth transistor T25 is connected to the second node N2, and the gate of the fifth transistor T25 is connected to the second reset signal line Rst22.
  • the source of the third transistor T23 is connected to the first power supply voltage line VDD21 , the drain of the third transistor T23 is connected to the third node N3 , and the gate of the third transistor T23 is connected to the first node N1 .
  • the source of the fourth transistor T24 is connected to the data line Data21, the drain of the fourth transistor T24 is connected to the second node N2, and the gate of the fourth transistor T24 is connected to the first scan line Ga1.
  • the source of the second transistor T22 is connected to the first node N1, the drain of the second transistor T22 is connected to the second node N2, and the gate of the second transistor T22 is connected to the second scanning line Ga2.
  • the source of the sixth transistor T26 is connected to the third node N3, the drain of the sixth transistor T26 is connected to the light emitting device D to be driven, and the gate of the sixth transistor T26 is connected to the light emission control line EM.
  • the source of the seventh transistor T27 is connected to the reference voltage line, the drain of the seventh transistor T27 is connected to the second node N2, and the gate of the seventh transistor T27 is connected to the light emission control line EM.
  • the source of the eighth transistor T28 is connected to the anode of the light-emitting device D to be driven, the drain of the eighth transistor T28 is connected to the second initialization signal line Init22, and the gate of the eighth transistor T28 is connected to the third reset signal line Rst23.
  • the switching characteristics of the transistor T28 and the sixth transistor T26 are different, so the control electrode of the eighth transistor T28 can also be connected to the light emission control line EM.
  • a first end of the storage capacitor Cst21 is connected to the second node N2, and a second end of the storage capacitor Cst21 is connected to the first node N1.
  • FIG. 4 is a working timing diagram of the pixel driving circuit shown in FIG. 3
  • FIG. 5 is a working timing diagram of the pixel driving circuit shown in FIG. 3 .
  • the difference between FIG. 4 and FIG. 5 is only that the eighth transistor T28 is controlled by the third reset control line or by the light emission control line EM, and the working principles of both the timing sequence in FIG. 4 and the timing sequence in FIG. 5 are roughly the same.
  • the timing control of FIG. 5 will be described as an example.
  • the light emission control signal written in the light emission control line EM is a PWM modulation signal, with a period of ( Refresh one frame time + hold frame time) light control line EM inserts four pulse signals as an example.
  • the first node N1, that is, the potential of the first node N1 is Vint1;
  • the reference voltage written on the reference voltage line is written into the second node N2 through the fifth transistor T25, that is, the potential of the second node N2 is Vref;
  • the second initialization signal written on the initialization signal line Init22 is written into the anode of the light emitting device D to be driven through the eighth transistor T28, that is, the potential of the anode of the light emitting device
  • Vint21 is the reset voltage of the gate of the third transistor T23, and generally takes a value between -1V and -5V, and the specific setting value can be set in combination with the compensation effect and the brightness of the black screen.
  • Vint2 can set the cathode voltage VSS21 of the light-emitting device D to be driven, or it can be a pulse signal. Generally, Vint2 is set close to VSS21, or just a voltage that can ensure that the light-emitting device D is not turned on (for example, between -2V and -6V) .
  • Data writing and threshold compensation stage (T2) the first scanning signal line writes a low-level signal, and the second scanning signal writes a high-level signal.
  • the second transistor T22 and the fourth transistor T24 are turned on, and the data line Data21
  • the data voltage signal written above is written into the second node N2 through the fourth transistor T24, that is, the potential of the second node N2 is Vdata21; at the same time, since the second transistor T22 is turned on, the threshold voltage Vth is written through the second transistor T22 Input the first node N1, at this time, the potential of the first node N1 is the sum of the first power supply voltage VDD21 and the threshold voltage Vth, that is, the potential of the first node N1 is VDD21+Vth.
  • Light-emitting stage (T3) the light-emitting control line EM writes a low-level signal, the sixth transistor T26 and the seventh transistor T27 are turned on at the same time, the potential of the second node N2 jumps from Vdata to the reference voltage Vref, and the role of the storage capacitor Cst21 Next, the jump voltage of the second node N2 is written into the first node N1, and the potential of the first node N1 at this time is VDD21+Vth+Vref ⁇ Vdata21. At this moment, the driving current generated by the third transistor T23 drives the light emitting device D to emit light.
  • the light-emitting control signal is a high-level signal
  • the eighth transistor T28 is turned on
  • the second initialization signal written on the second initialization signal line Init22 is used to emit light
  • the anode voltage of the device D is reset to ensure that the anode voltage of each light emitting device D in the display substrate is constant at the beginning of the next frame refresh, thereby effectively improving the consistency of the response time of the light emitting device D, which is beneficial to Improved low grayscale Mura and Flicker.
  • an embodiment of the present invention further provides a display panel, which includes any one of the above-mentioned pixel driving circuits. Therefore, the display effect of the display panel of this embodiment is better.
  • the display panel can be a liquid crystal display device or an electroluminescent display device, such as: OLED panel, Micro LED panel, Mini LED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. A product or part showing a function.

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Abstract

一种像素驱动电路及显示面板。像素驱动电路包括：数据写入子电路（24）、阈值补偿子电路（22）、驱动子电路（23）、存储子电路（29）、第一复位子电路（21）和第二复位子电路（25）；驱动子电路（23）和存储子电路（29）的第二端之间的连接节点为第一节点；数据写入子电路（24）和存储子电路（29）的第一端之间的连接节点为第二节点；驱动子电路（23）和阈值补偿子电路（22）之间的连接节点为第三节点；第一复位子电路（21）包括第一晶体管，其控制极连接第一复位信号线，第一极连接第一初始化信号线，第二极连接第一节点；阈值补偿子电路（22），包括第二晶体管，第二晶体管的第一极连接第一节点，第二极连接第三节点，控制极连接第二扫描线；第一晶体管和/或第二晶体管包括氧化物薄膜晶体管。

Description

像素驱动电路及显示面板 技术领域
本公开属于显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
有源矩阵有机电极发光二极管显示面板(Active Matrix Organic Light EmittingDiode，简称：AMOLED)的应用越来越广泛。AMOLED的像素显示器件为有机发光二极管(Organic Light-Emitting Diode,简称OLED)，AMOLED能够发光是通过驱动薄膜晶体管在饱和状态下产生驱动电流，该驱动电流驱动发光器件发光。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种像素驱动电路及显示面板。
第一方面，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一复位子电路和第二复位子电路；其中，所述驱动子电路和所述存储子电路的第二端之间的连接节点为第一节点；所述数据写入子电路和所述存储子电路的第二端之间的连接节点为第二节点；所述驱动子电路和所述阈值补偿子电路之间的连接节点为第三节点；
所述第一复位子电路，包括第一晶体管，所述第一晶体管的控制极连接第一复位信号线，第一极连接第一初始化信号线，第二极连接所述第一节点；
所述第二复位子电路，被配置为在第二复位信号的控制下，通过参考电压对所述第二节点的电位进行复位；
所述数据写入子电路，被配置为响应于第一扫描信号，将数据电压信号传输至所述第二节点，并通过所述存储子电路进行存储；
所述阈值补偿子电路，包括第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接所述第二节点，控制极连接第二扫描线；
所述驱动子电路，被配置为根据所述第一节点和所述第三节点的电位为待驱动的发光器件提供驱动电流；
所述存储子电路，被配置为对数据电压进行存储；其中，
所述第一晶体管和/或所述第二晶体管包括氧化薄膜晶体管。
其中，所述像素驱动电路还包括：第一发光控制子电路和第二发光控制子电路；
所述第一发光控制子电路，被配置为在第一发光控制信号的控制下，将所述驱动子电路生成的驱动电流传输给所述待驱动的发光器件；
所述第二发光控制子电路，被配置为在第二发光控制信号的控制下，将所述参考电压传输至所述第二节点。
其中，所述第一发光控制子电路包括第六晶体管；所述第二发光控制子电路包括第七晶体管；
所述第六晶体管的第一极连接所述第三节点，第二极连接所述待驱动的发光器件，控制极连接第一发光控制线；
所述第七晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二发光控制线。
其中，所述第六晶体管和所述第七晶体管的开关特性相同，且均与所述第一晶体管的开关特性相反。
其中，所述的像素驱动电路还包括：第三复位子电路；
所述第三复位子电路，被配置为在第三复位信号的控制线，通过第二初始化信号对所述待驱动的发光器件进行初始化。
其中，所述第三复位子电路包括第八晶体管；
所述第八晶体管的第一极连接所述待驱动的发光器件的第一极，第二极连接第二初始化信号线，控制极连接第三复位信号线。
其中，所述第八晶体管与所述第六晶体管的开关特性相反，所述第一发光控制线与所述第但复位信号线复用。
其中，所述第八晶体管包括氧化物薄膜晶体管。
其中，所述驱动子电路包括：第三晶体管；
所述第三晶体管的第一极连接所述第一电源电压线，第二极连接所述第三节点，控制极连接所述第一节点。
其中，所述第三晶体管与所述第一晶体管的开关特性相反。
其中，所述数据写入子电路包括：第四晶体管；
所述第四晶体管的第一极连接数据线，第二极连接所述第二节点，控制极连接第一扫描线。
其中，所述第四晶体管与所述第一晶体管的开关特性相反。
其中，所述第二复位子电路包括：第五晶体管；
所述第五晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二复位信号线。
其中，所述第五晶体管与所述第一晶体管的开关特性相反。
其中，所述存储子电路包括存储电容，所述存储电容的第一端连接所述第二节点。第二端连接所述第一节点。
本公开实施例还提供一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一复位子电路、第二复位子电路、第三复位子电路、第一发光控制子电路和所述第二发光控制子电路；其中，所述驱动子电路和所述存储子电路的第二端之间的连接节点为第一节点；所述数据写入子电路和所述存储子电路的第一端之间的连接节点为第二节点；所述驱动子电路和所述阈值补偿子电路之间的连接节点为第三节点；
所述第一复位子电路，包括第一晶体管，所述第一晶体管的第一极连接第一初始化信号线，第二极连接所述第一节点，控制极连接第一复位信号线；
所述第二复位子电路包括，第五晶体管，所述第五晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二复位信号线；
所述驱动子电路包括，第三晶体管，所述第三晶体管的第一极连接第一 电源电压线，第二极连接所述第三节点，控制极连接所述第一节点；
所述数据写入子电路包括：第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述第二节点，控制极连接第一扫描线；
所述阈值补偿子电路，包括第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接所述第二节点，控制极连接第二扫描线；
所述第一发光控制子电路包括第六晶体管，所述第六晶体管的第一极连接所述第三节点，第二极连接所述待驱动的发光器件，控制极连接第一发光控制线；
所述第二发光控制子电路，包括第七晶体管，所述第七晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二发光控制线；
所述第三复位子电路，包括第八晶体管，所述第八晶体管的第一极连接所述待驱动的发光器件的第一极，第二极连接第二初始化信号线，控制极连接第三复位信号线；
所述存储子电路，包括存储电容，所述存储电容的第一端连接所述第二节点，第二端连接所述第一节点；
所述第一晶体管和/或所述第二晶体管包括氧化薄膜晶体管。
其中，所述第一晶体管、所述第二晶体管和所述第八晶体管的开关特性相同；
所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管的开关特性相同；且所述第一晶体管与所述第三晶体管的开关特性相反。
第二方面，本公开实施例提供一种显示面板，其包括上述任一所述的像素驱动电路。
附图说明
图1为一种示例性的显示基板结构示意图。
图2为一种示例性的像素驱动电路的示意图。
图3为本公开实施例的一种像素驱动电路的示意图。
图4为图3所示的像素驱动电路的一种工作时序图。
图5为图3所示的像素驱动电路的一种工作时序图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种示例性的显示基板结构示意图；图2为一种示例性的像素驱动电路的示意图；如图1和2所示，该显示基板包括呈阵列排布的多个像素单元，每个像素单元100中均包括像素驱动电路和发光器件D。各像素单元100中的像素驱动电路可以包括：第一复位子电路11、阈值补偿子电路121、驱动子电路13、数据写入子电路14、第一发光控制子电路15、第二发光控制子电路16、第二复位子电路17及存储子电路18。
其中，第一复位子电路11与驱动子电路13的控制端连接，且被配置为在第一复位信号的控制下对驱动子电路13的控制端进行复位。阈值补偿子电路12分别与驱动子电路13的控制端和第二端电连接，且被配置为对驱动子电路13进行阈值补偿。数据写入子电路14与驱动子电路13的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储子电路。存储子 电路8分别与驱动子电路13的控制端和第一电源电压线VDD11电连接，且被配置为存储数据信号。第一发光控制子电路15分别与第一电源电压线VDD11以及驱动子电路13的第一端相连，且被配置为实现驱动子电路13和第一电源电压线VDD11间的连接导通或断开，第二发光控制子电路16分别与驱动子电路13的第二端和发光器件D的第一电极电连接，且被配置为实现驱动子电路13和发光器件D之间的连接导通或断开。第二复位子电路17与发光器件D的第一电极电连接，且被配置为在第二复位控制信号的控制下对驱动子电路13的控制端和发光器件D的第一电极进行复位。
继续参照图2，第一复位子电路包括第一复位晶体管T11，阈值补偿子电路12包括阈值补偿晶体管T12，驱动子电路13包括驱动晶体管T13，驱动子电路13的控制端包括驱动晶体管T13的控制极，驱动子电路13的第一端包括驱动晶体管T13的第一极，驱动子电路13的第二端包括驱动晶体管T13的第二极。数据写入子电路14包括数据写入晶体管T14，存储子电路18包括存储电容Cst11，第一发光控制子电路15包括第一发光控制晶体管T15，第二发光控制子电路16包括第二发光控制晶体管T16，第二复位子电路17包括第二复位晶体管T17。
在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，图2中的像素驱动电路以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T13、数据写入晶体管T14、阈值补偿晶体管T12、第一发光控制晶体管T15、第二发光控制晶体管T16、第一复位晶体管T11和第二复位晶体管T17等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
另外，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第 一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
继续参照图2，数据写入晶体管T14漏极的与驱动晶体管T13的源极电连接，数据写入晶体管T14的源极被配置为与数据线Data11电连接以接收数据信号，数据写入晶体管T14的栅极被配置为与第一扫描信号线Ga11电连接以接收扫描信号；存储电容Cst11的第二极板与第一电源电压线VDD11电连接，存储电容Cst11的第一极板与驱动晶体管T13的栅极电连接；阈值补偿晶体管T12的源极与驱动晶体管T13的栅极电连接，阈值补偿晶体管T12的漏极与驱动晶体管T13的漏极电连接，阈值补偿晶体管T12的栅极被配置为与第二扫描信号线Ga12电连接以接收补偿控制信号；第一复位晶体管T11的源极被配置为与第一初始化信号线VInit11电连接以接收第一复位信号，第一复位晶体管T11的漏极与驱动晶体管T13的栅极电连接，第一复位晶体管T11的栅极被配置为与第一复位控制信号线Rst11电连接以接收第一复位控制信号；第二复位晶体管T17的漏极被配置为与第一初始化信号线VInit11电连接以接收第一复位信号，第二复位晶体管T17的源极与发光器件D的第一电极电连接，第二复位晶体管T17的栅极被配置为与第二复位控制信号线Rst12电连接以接收第二复位控制信号；第一发光控制晶体管T15的源极与第一电源电压线VDD11电连接，第一发光控制晶体管T15的漏极与驱动晶体管T13的源极电连接，第一发光控制晶体管T15的栅极被配置为与第一发光控制信号线EM11电连接以接收第一发光控制信号；第二发光控制晶体管T16的源极与驱动晶体管T13的漏极电连接，第二发光控制晶体管T16的漏极与发光器件D的第一极电连接，第二发光控制晶体管T16的栅极被配置为与第二发光控制信号线EM12电连接以接收第二发光控制信号；发光器件D的第二电极与第二电源端VSS11电连接。
例如，第一电源电压线VDD11和第二电源端VSS11之一为高压端，另一个为低压端。例如，如图2所示，第一电源电压线VDD11为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS11可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS11可以接地。
继续参照图2，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T14的栅极和阈值补偿晶体管T12的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga11，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Ga12，减少信号线的数量。又例如，数据写入晶体管T14的栅极和阈值补偿晶体管T12的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T14的栅极电连接到第一扫描信号线Ga11，阈值补偿晶体管T12的栅极电连接到第二扫描信号线Ga12，而第一扫描信号线Ga11和第二扫描信号线Ga12传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T14的栅极和阈值补偿晶体管T12可以被分开单独控制，增加控制像素电路的灵活性。在本公开实施例中以数据写入晶体管T14的栅极和阈值补偿晶体管T12的栅极电连接第一扫描信号线Ga(A)为例进行说明。
继续参照图2，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T15的栅极和第二发光控制晶体管T16的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM11，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM12，减少信号线的数量。又例如，第一发光控制晶体管T15的栅极和第二发光控制晶体管T16的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T15的栅极电连接到第一发光控制信号线EM11，第二发光控制晶体管T16的栅极电连接到第二发光控制信号线EM12，而第一发光控制信号线EM11和第二发光控制信号线EM12传输的信号相同。
需要说明的是，当第一发光控制晶体管T15和第二发光控制晶体管T16为不同类型的晶体管，例如，第一发光控制晶体管T15为P型晶体管，而第 二发光控制晶体管T16为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。在本公开实施例中以第一发光控制晶体管T15和第二发光控制晶体管T16的栅极均连接发光控制线EM为例进行说明。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第一复位晶体管T11的栅极和第二复位晶体管T17的栅极可以电连接到同一条信号线，例如第一复位信号线Rst11，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位信号线Rst12，减少信号线的数量。又例如，第一复位晶体管T11的栅极和第二复位晶体管T17的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T11的栅极电连接到第一复位信号线Rst11，第二复位晶体管T17的栅极电连接到第二复位信号线Rst12，而第一复位控制信号线Rst11和第二复位信号线Rst12传输的信号相同。需要说明的是，第一复位信号和第二复位信号也可以不相同。在本公开实施例中以第一复位晶体管T11的栅极和第二复位晶体管T17的栅极均电连接到复位控制信号线Rst为例。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第二复位晶体管T17的栅极可以电连接到扫描信号线Ga(A)以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T11的源极和第二复位晶体管T17的漏极分别连接到第一初始化信号线VInit11和第二初始化信号线VInit12，第一初始化信号线VInit11和第二初始化信号线初始化信号线VInit12可以为直流参考电压端，以输出恒定的直流参考电压。第一初始化信号线VInit11和第二初始化信号线初始化信号线VInit12可以相同，例如第一复位晶体管T11的源极和第二复位晶体管T17的漏极连接到同一初始化信号线。第一初始化信号线VInit11和第二初始化信号线初始化信号线VInit12可以为高压信号线，也可以为低压信号线，只要其能够提供第一复位信号和第一复位信号以对驱动晶体管T13的栅极和发光元件的第一极进行复位即可，本公开对此不作限制。例如，第一复位晶体管T11的源极和第二复位晶体管T17的漏极可以均连接 至复位电源信号线Init。
需要说明的是，在本公开实施例中，以第一复位晶体管T11的栅极和第二复位晶体管的T17的栅极均电连接Rst11；第一复位晶体管T11的源极和第二复位晶体管的T17的漏极均电连接复位电源信号线Init为例进行说明。另外，图2所示的像素电路中的第一复位子电路11、阈值补偿子电路12、驱动子电路13、数据写入子电路14、第一发光控制子电路15、第二发光控制子电路16、第二复位子电路17及存储子电路8仅为示意性的，第一复位子电路11、阈值补偿子电路12、驱动子电路13、数据写入子电路14、第一发光控制子电路15、第二发光控制子电路16、第二复位子电路17及存储子电路8等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图2所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管和电容的电路结构，如7T12C结构、6T1C结构、6T12C结构或者9T12C结构，本公开实施例对此不作限定。
在发明实施例中的发光器件D可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。当然，发光器件D还可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)。发光器件D的第一电极和第二极中的一者为阳极，另一者为阴极；在本发明实施例中以发光器件D的第一极为阳极，第二极为阴极为例进行说明。
发明人发现，通常像素驱动电路中的各晶体管均采用低温多晶硅晶体管，且其中的第一复位晶体管的漏极和阈值补偿晶体管的源极均连接驱动晶体管的栅极，因此，第一复位晶体管和阈值补偿晶体管漏电时，会影响驱动晶体管的栅极电压，造成显示异常的问题。
针对上述问题，在本公开实施例中提供如下技术方案。
第一方面，图3为本公开实施例的一种像素驱动电路的示意图；如图3所示，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路24、阈值补偿子电路22、驱动子电路23、存储子电路29、第一复位子电路21和第二复位子电路25；其中，驱动子电路23和存储子电路29的第二端之间的连接节点为第一节点N1；数据写入子电路24和存储子电路29的第二端之间的连接节点为第二节点N2；驱动子电路23和阈值补偿子电路22之间的连接节点为第三节点N3。在本公开实施例中，第一复位子电路21，被配置为在所述第一复位信号的控制下，通过第一初始化信号对第一节点N1的电位进行初始化(也即复位)。第二复位子电路25被配置为在第二复位信号的控制下，将参考电压写入第二节点N2，以对第二节点N2进行复位。数据写入子电路24被配置为响应于第一扫描信号，将数据电压信号传输至第二节点N2，并通过存储子电路29进行存储；阈值补偿子电路22被配置为响应于第二扫描信号，将阈值电压写入第一节点N1。驱动子电路23被配置为根据第一节点N1和第三节点N3的电位为待驱动的发光器件D提供驱动电流。存储子电路29被配置为数据电压进行存储。
其中，在本公开实施例中第一复位子电路21可以包括第一晶体管T21，阈值补偿子电路22可以包括第二晶体管T22。第一晶体管T21的源极连接第一初始化信号线Init21，第一晶体管T21的漏极连接第一节点N1，第一晶体管T21的栅极连接第一复位信号线Rst21。第二晶体管T22的源极连接第一节点N1，第二晶体管T22的漏极连接第三节点N3，第二晶体管T22的栅极连接第二扫描线Ga2。特别的是，第一晶体管T21和第二晶体管T22中至少一者为氧化物薄膜晶体管。由于第一晶体管T21的漏极和第二晶体管T22的源极均连接第一节点N1，此时，若第一晶体管T21采用氧化物薄膜晶体管，可以有效的避免第一晶体管T21漏电而影响第一节点N1的电位，同理，若第二晶体管T22采用氧化物薄膜晶体管，可以有效的避免第二晶体管T22漏电而影响第一节点N1的电位。需要说明的是，为尽可能的保证像素驱动电路的性能，在本公开实施例中优选的第一晶体管T21和第二晶体管T22均采用氧化物薄膜晶体管。在以下描述中也均以第一晶体管T21和第二晶体 管T22均采用氧化物薄膜晶体管为例进行描述。
在一些示例中，第一晶体管T21和第二晶体管T22不仅均采用氧化物薄膜晶体管，而且二者开关特性相同，在该种情况下，可以在形成第一晶体管T21的同时形成第二晶体管T22，故不会增加工艺步骤和成本。在本公开实施例中，以第一晶体管T21和第二晶体管T22均采用N型晶体管为例。
在一些示例中，继续参照图3，本公开实施例中像素驱动电路不仅包括上述结构，而且还可以包括第一发光控制子电路26和第二发光控制子电路27。第一发光控制子电路26被配置为在第一发光控制信号的控制下，将驱动子电路23生成的驱动电流传输给待驱动的发光器件D；第二发光控制子电路27被配置为在第二发光控制信号的控制下，将参考电压传输至所述第二节点N2。
例如：第一发光控制子电路26包括第六晶体管T26，第二发光控制子电路27包括第七晶体管T27。第六晶体管T26的源极连接第三节点N3，第六晶体管T26的漏极连接待驱动的发光器件D的阳极，第六晶体管T26的栅极连接发光控制线EM第一发光控制线EM21。第七晶体管T27的源极连接参考电压线，第七晶体管T27的漏极连接第二节点N2，第七晶体管T27的栅极连接发光控制线EM第二发光控制线EM22。在一些示例中，由于第一发光控制子电路26(第六晶体管T26)和第二发光控制子电路27(第七晶体管T27)均发光阶段工作，也即二者的工作时序相同，故用以控制第一发光控制子电路26的发光控制线EM第一发光控制线EM21和用以控制第二发光控制子电路27的发光控制线EM第二发光控制线EM22可以为同一发光控制线EM。在下述描述中，以发光控制线EM第一发光控制线EM21和发光控制线EM第二发光控制线EM22为同一发光控制线EM为例，也即发光控制线EM第一发光控制线EM21和发光控制线EM第二发光控制线EM22均称之为发光控制线EM。在一些示例中，第六晶体管T26和第七晶体管T27的开关特性可以相同，且可以与第一晶体管T21的开关特性，也即第一晶体管T21采用N型晶体管，此时第六晶体管T26和第七晶体管T27均采用P型晶体管，否则反之。在一些示例中，第六晶体管T26和第七晶体 管T27可以为低温多晶硅薄膜晶体管也可以为氧化物薄膜晶体管。在本公开实施例中以第六晶体管T26和第七晶体管T27均采用低温多晶硅薄膜晶体管为例。
具体的，在初始化阶段，第一复位信号线Rst21写入高电平信号，第一晶体管T21打开，通过第一初始化信号线Init21上所写入的第一初始化信号对第一节点N1的电位进行初始化。与此同时，第二复位信号为工作电平信号，第二复位子电路25工作，并将参考电压写入第二节点N2，以对第二节点N2的电位进行初始化。数据电压写入及阈值补偿阶段，第一扫描信号为工作电平信号，数据写入子电路24工作，数据电压信号经由数据写入子电路24写入第二节点N2，也即第二节点N2的电位为Vdata21；与此同时，第二扫描线Ga2被写入高电平信号，第二晶体管T22开启，阈值电压Vth经由第二晶体管T22写入第一节点N1，此时第一节点N1的电位第一电源电压VDD21和阈值电压Vth之和，也即第一节点N1的电位为VDD21+Vth。在发光阶段，给发光控制线EM写入低电平信号，第六晶体管T26和第七晶体管T27同时打开，第二节点N2的电位由Vdata21跳变为参考电压Vref，在存储子电路29的作用下，将第二节点N2的跳变电压写入第一节点N1，此时第一节点N1的电位为VDD21+Vth+Vref-Vdata21。此时，驱动子电路23根据第一节点N1和第三节点N3的产生的驱动电流，驱动发光器件D发光。
在一些示例中，继续参照图3，本公开实施例中像素驱动电路不仅包括上述结构，而且还可以包括第三复位子电路28。该第三复位子电路28被配置为在第三复位信号的控制线，通过第二初始化信号对发光器件D的阳极的电位进行复位。在本公开实施例中，对第一节点N1采用第一复位子电路21进行复位，对发光器件D的阳极采用第二复位子电路25进行复位；也即，对第一节点N1的复位电路和对发光器件D的阳极的复位电路是两个不同复位电路。在该种情况下，相较于现有产品对于发光器件D的阳极的复位可以单独控制，此时，对于发光器件D在显示不同灰阶时，可以采用不同的初始化电压进行复位，而且不仅可以在刷新每一帧画面时的初始化阶段通过 第三复位子电路28对发光器件D的阳极进行初始化，而且还可以在保持帧时通过第三复位子电路28进行初始化。其中，保持帧是指刷新两帧画面之间的时段。这样一来，可以有效的改善刷新帧和保持帧的亮度差异，降低显示面板出现闪烁(Flicker)的概率。
例如：第三复位子电路28可以包括第八晶体管T28，该第八晶体管T28的源极连接待驱动的发光器件D阳极，第八晶体管T28的漏极连接第二初始化信号线Init22，第八晶体管T28的栅极连接第三复位信号线Rst23。
在一些示例中，第八晶体管T28的开关特性可以与第一晶体管T21的开关特性相同，也即第一发光控制电路中的第六晶体管T26的开关特性相反。此时，发光控制线EM可以复用为第三复位信号线Rst23。例如：采用PWM调制信号作为发光控制信号，以一个周期(刷新一帧的时间+保持帧的时间)发光控制线EM插入四个脉冲信号为例。在初始化阶段，给发光控制线EM写入的发光控制信号为高电平信号，第八晶体管T28打开，通过第二初始化线所写入的第二初始化信号对发光器件D的阳极进行复位。在发光阶段，给发光控制线EM写入的发光控制信号为低电平信号，第六晶体管T26打开，驱动子电路23产生的驱动电流经由第六晶体管T26传输给发光器件D，以驱动发光器件D发光。当发光控制线EM和第三复位信号线Rst23复用时，可以有效的减少控制信号线条数，有助于提高应用该像素驱动电路的显示基板的像素开口率。当然，采用单独的第三复位信号线Rst23对第八晶体管T28进行控制也是可行的，此时第八晶体管T28也可以不与第一晶体管T21的开关特性相同，可以采用与第六晶体管T26的开关特性相同的薄膜晶体管。
进一步的，当本公开实施例中的第三复位子电路28中的第八晶体管T28采用与第一复位子电路21中的第一晶体管T21开关特性相同的薄膜晶体管时，第八晶体管T28优选的采用氧化物薄膜晶体管，这样一来，在形成第一晶体管T21的同时可以形成第八晶体管T28，不会增加工艺步骤和成本。当然，第八晶体管T28采用其他类型的薄膜晶体管也是可行的，例如采用低温多晶硅薄膜晶体管。在一些示例中，在本公开实施例中，无论上述任一像素驱动电路，其中的驱动子电路23包括第三晶体管T23，该第三晶体管T23 的源极连接第一电源电压线VDD21，第三晶体管T23的漏极连接第三节点N3，第三晶体管T23的栅极连接第一节点N1。
例如：在发光阶段，该第三晶体管T23则可以根据其栅极(第一节点N1)和源极(VDD)的电位产生相应的驱动电流，以驱动发光器件D发光。在一些示例中，第三晶体管T23的开关特性与第一开关晶体管的开关特性相反，也即第三晶体管T23采用P型晶体管。
在一些示例中，继续参照图3，在本公开实施例中，无论上述任一像素驱动电路，其中的数据写入子电路24可以包括第四晶体管T24，该第四晶体管T24的源极连接数据线Data21，第四晶体管T24的漏极连接第二节点N2，第四晶体管T24的栅极连接第一扫描线Ga1。
例如：第四晶体管T24的开关特性与第一复位子电路21中的第一晶体管T21的开关特性相反，也即第四晶体管T24采用P型晶体管。具体的，在数据写入及阈值补偿阶段，第一扫描线Ga1写入低电平信号，第四晶体管T24打开，数据线Data21上写入的数据电压信号通过第四晶体管T24被写入第二节点N2，并通过存储子电路29进行存储。当然，第四晶体管T24也可以与第一复位子电路21中的第一晶体管T21的开关特性相同，也即第四晶体管T24也可以采用N型晶体管，此时第四晶体管T24则在第一扫描线Ga1写入高电平信号时工作。另外，本公开实施例中的第四晶体管T24可以为氧化物薄膜晶体管也可以低温多晶体硅薄膜晶体管，或者其他类型的薄膜晶体管，本公开实施例中以第四晶体管T24采用低温多晶硅薄膜晶体管为例。
在一些示例中，继续参照图3，在本公开实施例中，无论上述任一像素驱动电路，其中的第二复位子电路25可以包括第五晶体管T25，该第五晶体管T25的源极连接参考电压线，第五晶体管T25的漏极连接第二阶段，第五晶体管T25的栅极连接第二复位信号线Rst22。
例如：第五晶体管T25与第一复位子电路21中的第一晶体管T21的开关特性相反时，也即，第五晶体管T25采用P型晶体管。具体的，在初始化 阶段，可以通过给第二复位信号线Rst22写入低电平信号，第五晶体管T25打开，此时通过参考电压线上写入的参考电压对第二节点N2的电位进行初始化，也即完成第二节点N2的复位。当然，第五晶体管T25也可以与第一复位子电路21中的第一晶体管T21的开关特性相同，也即第五晶体管T25也可以采用N型晶体管，此时第五晶体管T25则在第一扫描线Ga1写入高电平信号时工作。另外，本公开实施例中的第五晶体管T25可以为氧化物薄膜晶体管也可以低温多晶体硅薄膜晶体管，或者其他类型的薄膜晶体管，本公开实施例中以第五晶体管T25采用低温多晶硅薄膜晶体管为例。
在一些示例中，继续参照图3在本公开实施例中，无论上述任一像素驱动电路，其中的存储子电路29可以包括存储电容Cst21，该存储电容Cst21的第一端连接第二节点N2，存储电容Cst21的第二端连接第一节点N1。对于存储电容Cst21在像素驱动电路中的具体功能，在下述像素驱动电路的驱动方法中进行详细描述。
如图3所示，本公开实施例提供一种像素驱动电路，数据写入子电路24、阈值补偿子电路22、驱动子电路23、存储子电路29、第一复位子电路21、第二复位子电路25、第三复位子电路28、第一发光控制子电路26和所述第二发光控制子电路27；其中，驱动子电路23和存储子电路29的第二端之间的连接节点为第一节点N1；数据写入子电路24和所述存储子电路29的第一端之间的连接节点为第二节点N2；驱动子电路23和所述阈值补偿子电路22之间的连接节点为第三节点N3；第一复位子电路21包括第一晶体管T21；第二复位子电路25包括第五晶体管T25；驱动子电路23包括第三晶体管T23；数据写入子电路24包括第四晶体管T24；阈值补偿子电路22包括第二晶体管T22；第一发光控制子电路26包括第六晶体管T26；第二发光控制子电路27包括第七晶体管T27；第三复位子电路28包括第八晶体管T28；存储子电路29包括存储电容Cst21。其中，第一晶体管T21和第二晶体管T22中的至少一者采用氧化薄膜晶体管，在下述描述中以第一晶体管T21和第二晶体管T22均采用氧化物薄膜晶体管为例。另外，第八晶体管T28也可以采用氧化物薄膜晶体管，且为了减少工艺步骤，第一晶体管T21、 第二晶体管T22和第八晶体管T28的开关特性相同，在本公开实施例中以第一晶体管T21、第二晶体管T22和第八晶体管T28采用N型晶体管为例。第三晶体管T23、第四晶体管T24、第五晶体管T25、第六晶体管T26和第七晶体管T27的开关特性与第一晶体管T21的开关特性相反，也即第三晶体管T23、第四晶体管T24、第五晶体管T25、第六晶体管T26和第七晶体管T27为P型晶体管，另外，在本公开实施例中第三晶体管T23、第四晶体管T24、第五晶体管T25、第六晶体管T26和第七晶体管T27均可以采用低温多晶硅薄膜晶体管，当然第三晶体管T23、第四晶体管T24、第五晶体管T25、第六晶体管T26和第七晶体管T27也可以采用氧化物薄膜晶体管或者其他类型的薄膜晶体管，在本公开实施例中以第三晶体管T23、第四晶体管T24、第五晶体管T25、第六晶体管T26和第七晶体管T27采用低温多晶硅薄膜晶体管为例。具体的，第一晶体管T21的源极连接第一初始化信号线Init21，第一晶体管T21的漏极连接第一节点N1，第一晶体管T21的栅极连接第一复位信号线Rst21。第五晶体管T25的源极连接参考电压线，第五晶体管T25的漏极连接第二节点N2，第五晶体管T25的栅极连接第二复位信号线Rst22。第三晶体管T23的源极连接第一电源电压线VDD21，第三晶体管T23的漏极连接第三节点N3，第三晶体管T23的栅极连接所述第一节点N1。第四晶体管T24的源极连接数据线Data21，第四晶体管T24的漏极连接所述第二节点N2，第四晶体管T24的栅极连接第一扫描线Ga1。第二晶体管T22的源极连接第一节点N1，第二晶体管T22的漏极连接所述第二节点N2，第二晶体管T22的栅极连接第二扫描线Ga2。第六晶体管T26的源极连接第三节点N3，第六晶体管T26的漏极连接所述待驱动的发光器件D，第六晶体管T26的栅极连接发光控制线EM。第七晶体管T27的源极连接参考电压线，第七晶体管T27的漏极连接第二节点N2，第七晶体管T27的栅极连接发光控制线EM。第八晶体管T28的源极连接待驱动的发光器件D的阳极，第八晶体管T28的漏极连接第二初始化信号线Init22，第八晶体管T28的栅极连接第三复位信号线Rst23，由于第八晶体管T28和第六晶体管T26的开关特性不同，故第八晶体管T28的控制极还可以连接发光控制线EM。存储电容 Cst21的第一端连接第二节点N2，存储电容Cst21的第二端连接第一节点N1。
为了更清楚理解本公开实施例中的像素驱动电路，以下结合该像素驱动电路驱动方法进行说明。其中，图4为图3所示的像素驱动电路的一种工作时序图，图5为图3所示的像素驱动电路的一种工作时序图。其中，图4和图5的区别仅在于第八晶体管T28由第三复位控制线控制还是由发光控制线EM控制，无论是图4的时序还是图5的时序工作原理大致形同，以下以在图5的时序的控制下为例进行说明。需要说明的是，由于第八晶体管T28的栅极和第六晶体管T26的栅极句连接发光控制线EM，此时发光控制线EM所写入的发光控制信号为PWM调制信号，以一个周期(刷新一帧的时间+保持帧的时间)发光控制线EM插入四个脉冲信号为例。
初始化阶段(T1)：第一复位信号线Rst21写入的第一复位信号为高电平信号，第二复位信号线Rst22写入的第二复位信号为低电平信号，发光控制线EM写入的发光控制信号为高电平信号，此时第一晶体管T21、第五晶体管T25和第八晶体管T28均打开，第一初始化信号线Init21上写入的第一初始化信号通过第一晶体管T21写入第一节点N1，也即第一节点N1的电位为Vint1；参考电压线上写入的参考电压通过第五晶体管T25写入第二节点N2，也即第二节点N2的电位为Vref；第二初始化信号线Init22上写入的第二初始化信号通过第八晶体管T28写入待驱动的发光器件D的阳极，也即待驱动的发光器件D的阳极的电位为Vint22。需要说明的是，Vint21为第三晶体管T23的栅极的复位电压，一般取值在-1V～-5V之间，具体设定值可以结合补偿效果和黑画面下的亮度情况设定。Vint2可以对随待驱动的发光器件D的阴极电压VSS21进行设置，也可为脉冲信号，一般Vint2设置接近VSS21，或者恰好可以保证发光器件D不开启的电压(例如-2V～-6V之间)。
数据写入及阈值补偿阶段(T2)：第一扫描信号线写入低电平信号，第二扫描信号写入高电平信号，此时第二晶体管T22和第四晶体管T24打开，数据线Data21上写入的数据电压信号经由第四晶体管T24写入第二节点N2，也即第二节点N2的电位为Vdata21；与此同时，由于第二晶体管T22 开启，阈值电压Vth经由第二晶体管T22写入第一节点N1，此时第一节点N1的电位第一电源电压VDD21和阈值电压Vth之和，也即第一节点N1的电位为VDD21+Vth。
发光阶段(T3)：发光控制线EM写入低电平信号，第六晶体管T26和第七晶体管T27同时打开，第二节点N2的电位由Vdata跳变为参考电压Vref，在存储电容Cst21的作用下，将第二节点N2的跳变电压写入第一节点N1，此时第一节点N1的电位为VDD21+Vth+Vref-Vdata21。此时，第三晶体管T23产生的驱动电流驱动发光器件D发光。
另外，在每一帧画面刷新完成之后进入帧保持阶段，此时，发光控制信号为高电平信号，第八晶体管T28打开，通过第二初始化信号线Init22上写入的第二初始化信号对发光器件D的阳极电压进行复位，以保证在显示基板中的各发光器件D阳极电压在下一帧画面刷新的起始时刻的电压一直，从而有效的提升发光器件D的响应时间的一致性，有利于改善低灰阶Mura和Flicker。
第二方面，本发明实施例还提供一种显示面板，其包括上述的任意一种像素驱动电路，因此，本实施例的显示面板的显示效果较佳。
其中，显示面板可以为液晶显示装置或者电致发光显示装置，例如：OLED面板、Micro LED面板，Mini LED面板，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (18)

  1. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一复位子电路和第二复位子电路；其中，所述驱动子电路和所述存储子电路的第二端之间的连接节点为第一节点；所述数据写入子电路和所述存储子电路的第二端之间的连接节点为第二节点；所述驱动子电路和所述阈值补偿子电路之间的连接节点为第三节点；
    所述第一复位子电路，包括第一晶体管，所述第一晶体管的控制极连接第一复位信号线，第一极连接第一初始化信号线，第二极连接所述第一节点；
    所述第二复位子电路，被配置为在第二复位信号的控制下，通过参考电压对所述第二节点的电位进行复位；
    所述数据写入子电路，被配置为响应于第一扫描信号，将数据电压信号传输至所述第二节点，并通过所述存储子电路进行存储；
    所述阈值补偿子电路，包括第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接所述第二节点，控制极连接第二扫描线；
    所述驱动子电路，被配置为根据所述第一节点和所述第三节点的电位为待驱动的发光器件提供驱动电流；
    所述存储子电路，被配置为对数据电压进行存储；其中，
    所述第一晶体管和/或所述第二晶体管包括氧化薄膜晶体管。
  2. 根据权利要求1所述的像素驱动电路，其中，还包括：第一发光控制子电路和第二发光控制子电路；
    所述第一发光控制子电路，被配置为在第一发光控制信号的控制下，将所述驱动子电路生成的驱动电流传输给所述待驱动的发光器件；
    所述第二发光控制子电路，被配置为在第二发光控制信号的控制下，将所述参考电压传输至所述第二节点。
  3. 根据权利要求2所述像素驱动电路，其中，所述第一发光控制子电路包括第六晶体管；所述第二发光控制子电路包括第七晶体管；
    所述第六晶体管的第一极连接所述第三节点，第二极连接所述待驱动的发光器件，控制极连接第一发光控制线；
    所述第七晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二发光控制线。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第六晶体管和所述第七晶体管的开关特性相同，且均与所述第一晶体管的开关特性相反。
  5. 根据权利要求4所述的像素驱动电路，其中，还包括：第三复位子电路；
    所述第三复位子电路，被配置为在第三复位信号的控制线，通过第二初始化信号对所述待驱动的发光器件进行初始化。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第三复位子电路包括第八晶体管；
    所述第八晶体管的第一极连接所述待驱动的发光器件的第一极，第二极连接第二初始化信号线，控制极连接第三复位信号线。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第八晶体管与所述第六晶体管的开关特性相反，所述第一发光控制线与所述第但复位信号线复用。
  8. 根据权利要求6所述的像素驱动电路，其中，所述第八晶体管包括氧化物薄膜晶体管。
  9. 根据权利要求1-8中任一项所述的像素驱动电路，其中，所述驱动子电路包括：第三晶体管；
    所述第三晶体管的第一极连接所述第一电源电压线，第二极连接所述第三节点，控制极连接所述第一节点。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第三晶体管与所述第一晶体管的开关特性相反。
  11. 根据权利要求1-8中任一项所述的像素驱动电路，其中，所述数据 写入子电路包括：第四晶体管；
    所述第四晶体管的第一极连接数据线，第二极连接所述第二节点，控制极连接第一扫描线。
  12. 根据权利要求11所述的像素驱动电路，其中，所述第四晶体管与所述第一晶体管的开关特性相反。
  13. 根据权利要求1-8中任一项所述的像素驱动电路，其中，所述第二复位子电路包括：第五晶体管；
    所述第五晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二复位信号线。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第五晶体管与所述第一晶体管的开关特性相反。
  15. 根据权利要求1-8中任一项所述的像素驱动电路，其中，所述存储子电路包括存储电容，所述存储电容的第一端连接所述第二节点。第二端连接所述第一节点。
  16. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一复位子电路、第二复位子电路、第三复位子电路、第一发光控制子电路和所述第二发光控制子电路；其中，所述驱动子电路和所述存储子电路的第二端之间的连接节点为第一节点；所述数据写入子电路和所述存储子电路的第一端之间的连接节点为第二节点；所述驱动子电路和所述阈值补偿子电路之间的连接节点为第三节点；
    所述第一复位子电路，包括第一晶体管，所述第一晶体管的第一极连接第一初始化信号线，第二极连接所述第一节点，控制极连接第一复位信号线；
    所述第二复位子电路包括，第五晶体管，所述第五晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二复位信号线；
    所述驱动子电路包括，第三晶体管，所述第三晶体管的第一极连接第一电源电压线，第二极连接所述第三节点，控制极连接所述第一节点；
    所述数据写入子电路包括：第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述第二节点，控制极连接第一扫描线；
    所述阈值补偿子电路，包括第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接所述第二节点，控制极连接第二扫描线；
    所述第一发光控制子电路包括第六晶体管，所述第六晶体管的第一极连接所述第三节点，第二极连接所述待驱动的发光器件，控制极连接第一发光控制线；
    所述第二发光控制子电路，包括第七晶体管，所述第七晶体管的第一极连接参考电压线，第二极连接所述第二节点，控制极连接第二发光控制线；
    所述第三复位子电路，包括第八晶体管，所述第八晶体管的第一极连接所述待驱动的发光器件的第一极，第二极连接第二初始化信号线，控制极连接第三复位信号线；
    所述存储子电路，包括存储电容，所述存储电容的第一端连接所述第二节点，第二端连接所述第一节点；
    所述第一晶体管和/或所述第二晶体管包括氧化薄膜晶体管。
  17. 根据权利要求16所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管和所述第八晶体管的开关特性相同；
    所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管的开关特性相同；且所述第一晶体管与所述第三晶体管的开关特性相反。
  18. 一种显示面板，其包括权利要求1-17中任一项所述的像素驱动电路。
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EP4300474A4 (en) 2024-02-28
WO2023004812A1 (zh) 2023-02-02
EP4300474A1 (en) 2024-01-03
CN114424280B (zh) 2022-09-23
US20240144884A1 (en) 2024-05-02

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