WO2019109673A1 - 像素电路及其驱动方法、显示面板和显示设备 - Google Patents

像素电路及其驱动方法、显示面板和显示设备 Download PDF

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Publication number
WO2019109673A1
WO2019109673A1 PCT/CN2018/102261 CN2018102261W WO2019109673A1 WO 2019109673 A1 WO2019109673 A1 WO 2019109673A1 CN 2018102261 W CN2018102261 W CN 2018102261W WO 2019109673 A1 WO2019109673 A1 WO 2019109673A1
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Prior art keywords
transistor
circuit
bias
control
driving
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PCT/CN2018/102261
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English (en)
French (fr)
Inventor
董甜
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18847206.2A priority Critical patent/EP3723075A4/en
Priority to US16/327,653 priority patent/US11341908B2/en
Publication of WO2019109673A1 publication Critical patent/WO2019109673A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • OLED display panel has the characteristics of self-luminous, high contrast, low energy consumption, wide viewing angle, fast response, flexible panel, wide temperature range, simple manufacturing, etc. Development prospects. As a new generation of display methods, OLED display panels can be widely used in mobile phones, displays, notebook computers, digital cameras, instrumentation and other devices with display functions.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a light emitting element, a driving circuit, a first reset bias circuit, and a second reset bias circuit.
  • a control end of the driving circuit is electrically connected to the data signal end and the second end of the first reset bias circuit, and the first end of the driving circuit is electrically connected to the second end of the second reset bias circuit
  • the second end of the driving circuit is electrically connected to the light emitting element;
  • the control end of the first reset bias circuit is electrically connected to the first control end, and the first end of the first reset bias circuit is a bias voltage terminal is electrically connected;
  • a control end of the second reset bias circuit is electrically connected to the bias control terminal, and a first end of the second reset bias circuit is electrically connected to the second bias voltage terminal;
  • the first reset bias circuit and the second reset bias circuit are configured to reset the drive circuit during a reset phase and control the drive circuit to be in a biased state.
  • the driving circuit includes a driving transistor, the first reset bias circuit includes a first bias transistor, and the second reset bias circuit includes a second bias a transistor, a control terminal of the driving circuit is a gate of the driving transistor, a first end of the driving circuit is a first pole of the driving transistor, and a second end of the driving circuit is a driving transistor a second pole, a first end of the first reset bias circuit is a first pole of the first bias transistor, and a second end of the first reset bias circuit is a first bias transistor a second pole, a control end of the first reset bias circuit is a gate of the first bias transistor, and a first end of the second reset bias circuit is a first end of the second bias transistor
  • the second end of the second reset bias circuit is a second pole of the second bias transistor, and the control end of the second reset bias circuit is a gate of the second bias transistor.
  • a pixel circuit provided by an embodiment of the present disclosure further includes: a data writing circuit and a storage circuit.
  • the data write circuit is configured to write a data signal to a gate of the drive transistor during a data write phase; the memory circuit configured to store the data signal and maintain it at a gate of the drive transistor pole.
  • a pixel circuit provided by an embodiment of the present disclosure further includes a threshold compensation circuit.
  • the threshold compensation circuit is configured to write a threshold compensation signal to a gate of the drive transistor during the data write phase.
  • the threshold compensation circuit includes a threshold compensation transistor
  • the data write circuit includes a data write transistor
  • the storage circuit includes a storage capacitor
  • the threshold compensation transistor a first pole is electrically connected to a second pole of the data write transistor, a second pole and a gate of the threshold compensation transistor are electrically connected to each other, and are electrically connected to a gate of the drive transistor;
  • the data is written a first pole of the transistor is electrically connected to the data signal end, a gate of the data write transistor is electrically connected to a second control end;
  • a first end of the storage capacitor is electrically connected to a first pole of the drive transistor The second end of the storage capacitor is electrically connected to a gate of the driving transistor.
  • a pixel circuit provided by an embodiment of the present disclosure further includes a voltage drop compensation circuit.
  • the voltage drop compensation circuit is configured to write a reference voltage signal to the first pole of the drive transistor during the data write phase.
  • the voltage drop compensation circuit includes a voltage drop compensation transistor
  • the memory circuit includes a storage capacitor
  • the first pole of the voltage drop compensation transistor is electrically connected to a reference power terminal.
  • a second pole of the voltage drop compensating transistor is electrically connected to a first pole of the driving transistor, a gate of the voltage drop compensating transistor is electrically connected to a second control end; and a first end of the storage capacitor is electrically connected To a first pole of the drive transistor, a second end of the storage capacitor is electrically coupled to a gate of the drive transistor.
  • a pixel circuit provided by an embodiment of the present disclosure further includes an illumination control circuit.
  • the illumination control circuit is configured to control the drive circuit to drive the illumination element to emit light.
  • the light emission control circuit includes a first control transistor and a second control transistor, and a first electrode of the first control transistor is electrically connected to a second of the driving transistor a second pole of the first control transistor is electrically connected to the light emitting element, a gate of the first control transistor is electrically connected to a third control terminal; and a first pole of the second control transistor is electrically connected to At a first supply voltage terminal, a second electrode of the second control transistor is electrically coupled to a first pole of the drive transistor, and a gate of the second control transistor is configured to receive an illumination control signal.
  • a gate of the second control transistor is electrically connected to the third control terminal to receive the light emission control signal, and a gate of the second bias transistor
  • the first control terminal is electrically connected to the first control terminal
  • the first terminal of the second bias transistor is electrically connected to the reset voltage terminal
  • the reset voltage terminal is the second bias voltage terminal
  • the first control terminal is The bias control terminal.
  • a signal output by the first bias voltage terminal is the same as a signal output by the second bias voltage terminal.
  • the second bias transistor is multiplexed into the second control transistor.
  • the second bias transistor is an N-type transistor, and a gate of the second bias transistor is electrically connected to the second control terminal, the first The power voltage terminal is the second bias voltage terminal, and the second control terminal is the bias control terminal.
  • At least one embodiment of the present disclosure also provides a display panel comprising the pixel circuit according to any of the above.
  • At least one embodiment of the present disclosure further provides a display device comprising the display panel of any of the above.
  • At least one embodiment of the present disclosure provides a method for driving a pixel circuit according to any one of the preceding claims, comprising: resetting the driving circuit and controlling the driving circuit to be in a bias state during the reset phase; In the data writing phase, a data signal is written to the driving circuit; in the light emitting phase, the light emitting element is driven to emit light.
  • the driving circuit includes a driving transistor
  • the first reset bias circuit includes a first bias transistor
  • the second reset bias circuit includes a second bias
  • Transducing the drive circuit and controlling the drive circuit to be in a biased state includes: writing a first bias voltage signal to a gate of the drive transistor through the first bias transistor; A second bias transistor writes a second bias voltage signal to the first pole of the drive transistor. The difference between the first bias voltage signal and the second bias voltage signal controls the drive transistor to be in a biased state.
  • the first bias voltage signal and the second bias voltage signal are the same.
  • a first pole of the second bias transistor is electrically connected to a first power voltage terminal to receive a first power voltage signal, and the first power voltage signal is The second bias voltage signal is described.
  • the driving method provided by an embodiment of the present disclosure further includes: writing, in the data writing phase, a threshold compensation signal to a gate of the driving transistor by a threshold compensation circuit.
  • the driving method provided by an embodiment of the present disclosure further includes: writing, by the voltage drop compensation circuit, a reference voltage signal to the first electrode of the driving transistor during the data writing phase.
  • FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8A is a schematic diagram of a reset phase of the pixel circuit shown in FIG. 2;
  • FIG. 8B is a schematic diagram of a data writing phase of the pixel circuit shown in FIG. 2;
  • 8C is a schematic diagram of a light emitting phase of the pixel circuit shown in FIG. 2;
  • FIG. 9A is a schematic diagram of a reset phase of the pixel circuit shown in FIG. 3;
  • 9B is a schematic diagram of a data writing phase of the pixel circuit shown in FIG. 3;
  • 9C is a schematic diagram of an illumination phase of the pixel circuit shown in FIG.
  • OLED Organic Light Emitting Diode
  • Each pixel on the OLED display panel is driven by a plurality of thin film transistors (TFTs), and TFT driving technology can improve display speed, contrast and brightness, and improve resolution.
  • TFTs thin film transistors
  • the hysteresis effect of the TFT is an uncertainty in the electrical characteristics of the TFT under a certain bias voltage, that is, the current flowing through the TFT is not only related to the current bias voltage, but also The state of the TFT at the last moment.
  • the hysteresis effect of TFT is related to the gate dielectric of the TFT, the semiconductor material and the interface state trap between the two.
  • the hysteresis effect of the TFT causes short-term afterimage, and the image of the previous frame tends to remain in the image of the next frame. Thereby affecting the display quality of the OLED display panel, and even causing display errors.
  • At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device, wherein a driving circuit is in an offset state during a reset phase, so that when a screen is displayed, the driving circuit is changed from an offset state to According to the corresponding display state, the data voltage of the display frame of the latter frame is not affected by the data voltage of the display picture of the previous frame, thereby improving the short-term afterimage problem caused by the hysteresis effect and improving the display quality of the display panel.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure may further perform a threshold compensation operation and a voltage drop compensation operation, thereby compensating for threshold voltage drift of the driving transistor and a power drop (IR drop) of the display panel, thereby improving display uniformity. , effectively improve the display effect of the display panel.
  • FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 100 may include a light emitting element EL, a driving circuit 10, a first reset bias circuit 21, and a second reset bias circuit 22.
  • the control end of the driving circuit 10 is electrically connected to the data signal terminal VD and the second end of the first reset bias circuit 21, respectively, and the first end of the driving circuit 10 is electrically connected to the second end of the second reset bias circuit 22, and is driven.
  • the second end of the circuit 10 is electrically connected to the light emitting element EL.
  • the control end of the first reset bias circuit 21 is electrically connected to the first control terminal SC1, the first end of the first reset bias circuit 21 is electrically connected to the first bias voltage terminal VB1, and the second reset bias circuit 22 is controlled.
  • the terminal is electrically connected to the bias control terminal BS, and the first terminal of the second reset bias circuit 22 is electrically connected to the second bias voltage terminal VB2; the first reset bias circuit 21 and the second reset bias circuit 22 are configured as
  • the drive circuit 10 is reset during the reset phase and the drive circuit 10 is controlled to be in an offset state.
  • the pixel circuit 100 provided by the embodiment of the present disclosure may be applied to a display panel such as an active matrix organic light emitting diode (AMOLED) display panel or the like.
  • a display panel such as an active matrix organic light emitting diode (AMOLED) display panel or the like.
  • AMOLED active matrix organic light emitting diode
  • the light emitting element EL is configured to emit light with application of a voltage or current.
  • the light emitting element EL may be an organic light emitting element, and the organic light emitting element may be, for example, an organic light emitting diode, but embodiments of the present disclosure are not limited thereto.
  • the light-emitting elements EL may, for example, use different luminescent materials to emit light of different colors to perform color illuminating.
  • the specific structure of the driving circuit 10, the first reset bias circuit 21, and the second reset bias circuit 22 may be set according to actual application requirements, which is not specifically limited in the embodiment of the present disclosure.
  • a pixel circuit 100 provided by an embodiment of the present disclosure may be implemented as a circuit structure as shown in FIG. 2.
  • the driver circuit 10 includes a drive transistor T1.
  • the control terminal a3 of the driving circuit 10 is the gate of the driving transistor T1
  • the first end a1 of the driving circuit 10 is the first pole of the driving transistor T1
  • the second end a2 of the driving circuit 10 is the second pole of the driving transistor T1.
  • the drive circuit 10 is in a biased state may indicate that the drive transistor T1 is in a biased state, that is, the first reset bias circuit 21 and the second reset bias circuit 22 may control the drive transistor T1 to be in a bias state during the reset phase. .
  • the driving transistor T1 is a P-type transistor.
  • the first pole of the driving transistor T1 may be a source, and the second pole of the driving transistor T1 may be a drain.
  • “the driving transistor T1 is in a bias state” may mean that the voltage difference between the gate and the source of the driving transistor T1 is not greater than the gate and source corresponding to the maximum gray scale (ie, 255 gray scale).
  • the voltage difference between Vgs255 that is, the Vgs of the driving transistor T1 (i.e., the voltage difference between the gate and the source of the driving transistor T1) is equal to or less than Vgs255.
  • the first reset bias circuit 21 is configured to write a first bias voltage signal to the gate of the driving transistor T1 in the reset phase; the second reset bias circuit 22 is configured to be in the reset phase to the driving transistor T1 One pole writes a second bias voltage signal.
  • the difference between the first bias voltage signal and the second bias voltage signal controls the driving transistor T1 to be in a biased state.
  • the first bias voltage signal and the second bias voltage signal are the gate voltage and the source voltage of the driving transistor T1, respectively, such that the voltage difference between the first bias voltage signal and the second bias voltage signal (For example, the voltage difference represents a difference obtained by subtracting the second bias voltage signal from the first bias voltage signal) is greater than or equal to V th1 ; or, is less than or equal to Vgs255.
  • the first reset bias circuit 21 includes a first bias transistor T4.
  • the first end b1 of the first reset bias circuit 21 is the first pole of the first bias transistor T4, and the second end b2 of the first reset bias circuit 21 is the second pole of the first bias transistor T4, first
  • the control terminal b3 of the reset bias circuit 21 is the gate of the first bias transistor T4.
  • the second reset bias circuit 22 includes a second bias transistor T8.
  • the first end c1 of the second reset bias circuit 22 is the first pole of the second bias transistor T8, the second end c2 of the second reset bias circuit 22 is the second pole of the second bias transistor T8, and the second The control terminal c3 of the reset bias circuit 22 is the gate of the second bias transistor T8.
  • the first bias voltage terminal VB1 is configured to output a first bias voltage signal V init1
  • the second bias voltage terminal VB2 is configured to output a second bias voltage signal V init2 .
  • the gate of the first bias transistor T4 is electrically connected to the first control terminal SC1 to receive the first control signal S 1
  • the first pole of the first bias transistor T4 is electrically connected to the first bias voltage terminal VB1 to receive The first bias voltage signal V init1
  • the second pole of the first biasing transistor T4 is electrically coupled to the gate of the driving transistor T1 to transmit a first bias voltage signal V init1 to the gate of the driving transistor T1 when the first biasing transistor T4 is turned on.
  • the gate of the second bias transistor T8 is electrically connected to the first control terminal SC1
  • the first electrode of the second bias transistor T8 is electrically connected to the reset voltage terminal VR
  • the second bias transistor T8 The second pole is electrically connected to the first pole of the driving transistor T1.
  • the first control terminal SC1 is the bias control terminal BS
  • the reset voltage terminal VR is the second bias voltage terminal VB2.
  • the first control terminal SC1 may output a first control signal S 1
  • the first control signal S 1 is a bias control signal.
  • the reset voltage terminal VR can output a second bias voltage signal V init2 , and the first pole of the second bias transistor T8 can receive the second bias voltage signal V init2 , so that the second bias voltage signal V init2 can be in the second bias When the transistor T8 is turned on, it is transmitted to the first electrode of the driving transistor T1.
  • the first bias transistor T4 and the second bias transistor T8 are of the same type.
  • the first bias transistor T4 and the second bias transistor T8 are both P-type transistors, and the gates of the first bias transistor T4 and the gate of the second bias transistor T8 are both electrically connected to the first control terminal SC1 and The same first control signal S 1 is controlled so that the number of signal control terminals can be saved.
  • the first bias transistor T4 and the second bias transistor T8 operate simultaneously under the control of the first control signal S1.
  • the gate of the first bias transistor T4 and the gate of the second bias transistor T8 may also be electrically connected to different signal control terminals respectively to receive different control signals, as long as the first bias transistor is ensured.
  • the gate of T4 and the second bias transistor T8 can operate simultaneously in the reset phase.
  • first biasing transistor T4 and the second biasing transistor T8 may also be different, which is not limited in the disclosure.
  • the first bias voltage signal V init1 and the second bias voltage signal V init2 may be equal, whereby the first pole of the first bias transistor T4 and the first pole of the second bias transistor T8 may be electrically connected to The same bias voltage terminal (for example, the first bias voltage terminal VB1 or the second bias voltage terminal VB2), that is, the pixel circuit 100 may include only one bias voltage terminal, thereby saving the number of bias voltage terminals. Save production costs.
  • the first bias voltage signal V init1 and the second bias voltage signal V init2 may not be equal, as long as the difference between the first bias voltage signal V init1 and the second bias voltage signal V init2 is greater than or equal to V th1 .
  • V init1 -V init2 ⁇ Vgs255 V init1 -V init2 ⁇ V th1
  • the disclosure does not specifically limit this.
  • the pixel circuit 100 may further include a data writing circuit 11 and a memory circuit 12.
  • the data write circuit 11 is configured to write a data signal to the gate of the drive transistor T1 during the data write phase;
  • the memory circuit 12 is configured to store the data signal and hold it at the gate of the drive transistor T1.
  • the memory circuit 12 includes a storage capacitor Cst.
  • the first end of the storage capacitor Cst is electrically connected to the first pole of the driving transistor T1, and the second end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1. That is, the second pole of the first bias transistor T4 is electrically coupled to the second terminal of the storage capacitor Cst, and the second pole of the second bias transistor T8 is electrically coupled to the first terminal of the storage capacitor Cst.
  • the first terminal of the storage capacitor Cst can store the second bias voltage signal V init2 and be held at the first pole of the driving transistor T1
  • the second terminal of the storage capacitor Cst can store the first bias voltage
  • the signal V init1 is held at the gate of the driving transistor T1.
  • the pixel circuit 100 may also have an electrical compensation function according to actual application requirements.
  • the electrical compensation function can be implemented by voltage compensation, current compensation or hybrid compensation.
  • the pixel circuit 100 may further include a threshold compensation circuit 13.
  • the threshold compensation circuit 13 is configured to write a threshold compensation signal to the gate of the driving transistor T1 during the data writing phase to compensate for the threshold voltage Vth1 drift of the driving transistor T1.
  • the pixel circuit 100 of the embodiment of the present disclosure can compensate for the threshold voltage drift of the driving transistor T1, improving display uniformity and display effect.
  • the threshold compensation circuit 13 may include a threshold compensation transistor T3, and the data write circuit 11 may include a data write transistor T2.
  • the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the data writing transistor T2, and the second electrode and the gate of the threshold compensation transistor T3 are electrically connected to each other and electrically connected to the driving transistor T1.
  • the first electrode of the data writing transistor T2 is electrically connected to the data signal terminal VD, and the gate of the data writing transistor T2 is electrically connected to the second control terminal SC2.
  • the threshold compensation transistor T3 and the driving transistor T1 are the same, that is, the types, preparation processes, and the like of the threshold compensation transistor T3 and the driving transistor T1 are the same, thereby ensuring the threshold voltage Vth2 of the threshold compensation transistor T3 and the threshold of the driving transistor T1.
  • the voltage V th1 is the same.
  • the threshold compensation transistor T3 is also, for example, a P-type transistor.
  • the first bias voltage signal V init1 needs to be smaller than the sum of the threshold voltage V th2 of the threshold compensation transistor T3 and the data signal V data . That is, the first bias voltage signal V init1 needs to satisfy the following formula: V init1 ⁇ V th2 +V data . Because the same threshold voltage V th2 of the transistor T1 and the driving transistor T3 threshold compensation threshold voltage V th1, i.e., V init1 ⁇ V th1 + V data.
  • the second control terminal SC2 may provide a second control signal S 2 to the gate of the data writing transistor T2 to turn on the data writing transistor T2.
  • VD data signal terminal of the transistor T2 can be written to the data electrode to provide a first data signal V data. Since the second electrode and the gate of the threshold compensation transistor T3 are electrically connected to each other, the threshold compensation transistor T3 is turned on.
  • the data signal V data provided by the data signal terminal VD can charge the second end of the storage capacitor Cst via the data writing transistor T2 and the threshold compensation transistor T3, and the voltage of the second terminal of the storage capacitor Cst reaches the data signal V data and
  • the threshold compensation transistor T3 is turned off, that is, the charging is ended, and the data signal V data and the threshold voltage V th1 of the driving transistor T1 can be stored at the second end of the storage capacitor Cst, and the storage is performed.
  • the data signal V data and the threshold voltage V th1 of the driving transistor T1 can control the conduction degree of the driving transistor T1, thereby controlling the magnitude of the illuminating current flowing through the driving transistor T1, and the illuminating current flowing through the driving transistor T1 can determine the illuminating element EL
  • the illuminating gray scale ie the luminous intensity
  • the threshold compensation circuit 13 is an internal compensation circuit, but is not limited thereto.
  • the threshold compensation circuit 13 may also be an external compensation circuit, and the external compensation circuit may include, for example, a sensing circuit portion to sense
  • the electrical characteristics of the driving transistor T1 or the electrical characteristics of the light-emitting element EL can be referred to a conventional design, and will not be described herein.
  • the pixel circuit 100 may further include a voltage drop compensation circuit 14.
  • the voltage drop compensation circuit 14 is configured to write a reference voltage signal V ref to the first electrode of the driving transistor T1 in the data writing phase to compensate for the display voltage difference of the light emitting element EL due to the power supply voltage drop (IR drop) of the display panel. Improve display quality and improve display.
  • the voltage drop compensation circuit 14 can include a voltage drop compensation transistor T6.
  • the first pole of the voltage drop compensation transistor T6 is electrically coupled to the reference power supply terminal REF.
  • the second pole of the voltage drop compensation transistor T6 is electrically connected to the first pole of the driving transistor T1, that is, the second pole of the voltage drop compensating transistor T6 is also electrically connected to the first end of the storage capacitor Cst.
  • the gate of the voltage drop compensation transistor T6 is electrically connected to the second control terminal SC2.
  • the second control terminal SC2 may provide a second control signal S2 to the gate of the voltage drop compensation transistor T6 to turn on the voltage drop compensation transistor T6.
  • the reference power supply terminal REF can supply the reference voltage signal V ref to the first pole of the voltage drop compensation transistor T6 such that the reference voltage signal V ref charges the first end of the storage capacitor Cst via the voltage drop compensation transistor T6, thereby storing the capacitance Cst
  • the voltage at the first terminal can be the reference voltage signal V ref .
  • the pixel circuit 100 may further include a light emission control circuit 15.
  • the light emission control circuit 15 is configured to control the drive circuit 10 to drive the light emitting element EL to emit light.
  • the illumination control circuit 15 may include a first illumination control sub-circuit 151 and a second illumination control sub-circuit 152.
  • the first light emission control sub-circuit 151 is disposed between the drive circuit 10 and the light emitting element EL, and is configured to control to turn on or off the electrical connection between the drive circuit 10 and the light emitting element EL.
  • the second lighting control sub-circuit 152 is disposed between the first power voltage terminal V1 and the driving circuit 10, and is configured to control to turn on or off the electrical connection between the first power voltage terminal V1 and the driving circuit 10.
  • the first lighting control sub-circuit 151 may include a first control transistor T7
  • the second lighting control sub-circuit 152 may include a second control transistor T5.
  • the first pole of the first control transistor T7 is electrically connected to the second pole of the driving transistor T1
  • the second pole of the first control transistor T7 is electrically connected to the first end of the light emitting element EL (for example, the positive terminal of the light emitting element EL)
  • the gate of the first control transistor T7 is electrically connected to the third control terminal SC3
  • the first electrode of the second control transistor T5 is electrically connected to the first power supply voltage terminal V1
  • the second electrode of the second control transistor T5 is electrically connected to the driving transistor
  • the first pole of T1, the gate of the second control transistor T5 is configured to receive an illumination control signal.
  • the second end of the light emitting element EL (for example, the negative end of the light emitting element EL) is electrically connected to the second power supply voltage terminal V2.
  • the control terminal of the third stage SC3 may output a third light emitting control signal S 3, the third control signal S 3 is the light emission control signal, a second control gate of the transistor T5 can be Electrically connected to the third control terminal SC3 to receive the illumination control signal, that is, the gate of the first control transistor T7 and the gate of the second control transistor T5 can be electrically connected to the third control terminal SC3, and the third The control terminal SC3 can simultaneously transmit the same illumination control signal to the gate of the first control transistor T7 and the gate of the second control transistor T5.
  • first control transistor T7 and the second control transistor T5 may also be electrically connected to different control terminals, and the illumination control signals applied by different control terminals are synchronized.
  • the embodiments of the present disclosure do not limit this.
  • the light emission control signal is simultaneously applied to the gates of the first control transistor T7 and the second control transistor T5 such that the first control transistor T7 and the second control transistor T5 are simultaneously turned on, thereby the first power supply voltage
  • the terminal V1, the second control transistor T5, the driving transistor T1, the first control transistor T7, the light emitting element EL and the second power supply voltage terminal V2 may form a loop, and the illuminating current is passed through the second control transistor T5, the driving transistor T1 and the first A control transistor T7 is transmitted to the light emitting element EL to drive its light emission.
  • the first power voltage terminal V1 is a high voltage terminal, and the first power voltage signal V dd can be output, the second power voltage terminal V2 is a low voltage terminal, and the second power voltage signal V ss can be output.
  • the voltage signal outputted by the high voltage terminal is greater than the voltage signal output by the low voltage terminal, that is, the first power voltage signal V dd may be greater than the second power voltage signal V ss .
  • the present invention is not limited thereto.
  • the first power voltage terminal V1 may also be a low voltage terminal, and the second power voltage terminal V2 may be a high voltage terminal.
  • the high voltage terminal can be electrically connected to the positive pole of the power supply.
  • the low voltage side can be electrically connected to the negative pole of the power supply.
  • the low voltage side can also be electrically connected to the ground (GND).
  • the specific structures of the data writing circuit 11, the storage circuit 12, the threshold compensation circuit 13, the voltage drop compensation circuit 14, and the illumination control circuit 15 can be set according to actual application requirements, and the embodiments of the present disclosure are This is not specifically limited.
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the second bias transistor shown in FIG. 2 can be multiplexed into a second control transistor, whereby the pixel circuit can save one transistor (the transistor T5 of FIG. 2 is omitted), saving production costs.
  • the second bias transistor T8 may be an N-type transistor and configured to write a second bias voltage signal V init2 to the first electrode of the driving transistor T1 during the reset phase.
  • the gate of the second bias transistor T8 is electrically connected to the second control terminal SC2
  • the first pole of the second bias transistor T8 is electrically connected to the first power supply voltage terminal V1
  • the second bias transistor T8 is second.
  • the pole is electrically connected to the first pole of the drive transistor T1.
  • the first power voltage terminal V1 is configured to transmit a first power voltage signal V dd to the first pole of the second bias transistor T8 during the reset phase.
  • the second bias voltage signal V init2 is the first power voltage signal. V dd .
  • the first control terminal SC1 may output a first control signal S 1 to control the first bias transistor T4 to be turned on, and the second control terminal SC2 may output a second control signal S 2 to control the second bias transistor.
  • T8 is turned on; the first bias voltage terminal VB1 is configured to output a first bias voltage signal V init1 , and the first bias voltage signal V init1 can be transmitted to the gate of the driving transistor T1 via the first bias transistor T4,
  • a power supply voltage terminal V1 can output a first power voltage signal V dd , the first power voltage signal V dd is a second bias voltage signal V init2 , and the first power voltage signal V dd can be transmitted to the second bias transistor T8 to The first pole of the transistor T1 is driven.
  • the second control terminal SC2 is the bias control terminal BS
  • the first power supply voltage terminal V1 is the second bias voltage terminal VB2
  • the first control signal S 1 and the second control signal S 2 Both are bias control signals.
  • the second control terminal SC2 outputs a second control signal S 2
  • the third control terminal outputs a third control signal S 3
  • the second control signal S 2 and the third control signal S 3 are used to control the second bias
  • the transistor T8 and the first control transistor T7 are simultaneously turned on, thereby controlling the transfer of the light-emission current to the light-emitting element EL to drive its light emission.
  • the second control signal S 2 and the third control signal S 3 are both light emission control signals.
  • the remaining circuits in the embodiment shown in FIG. 3 may be The structure and connection mode of the corresponding circuit in the embodiment shown in FIG. 2 are the same, and details are not described herein again.
  • the gate of the second bias transistor T8 and the gate of the data write transistor T2 and the gate of the voltage drop compensation transistor T6 are both controlled by the same second control signal S 2 .
  • the type of the second bias transistor T8 and the data write transistor T2 and the voltage drop compensation transistor T6 may be different. That is, if the second bias transistor T8 is an N-type transistor, the data write transistor T2 and the voltage drop compensation transistor T6 are both P-type transistors.
  • the gate of the second bias transistor T8 and the gate of the data write transistor T2 and the gate of the voltage drop compensation transistor T6 can also be controlled by different control signals.
  • the second bias transistor T8 and the data write transistor T2 and the voltage drop compensation transistor T6 can be of the same type (for example, both are P-type). Transistors) can also be different. The disclosure does not limit this.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the embodiment of the present disclosure elaborates the technical solution of the present disclosure by taking a transistor as a P-type transistor as an example.
  • the transistor of the embodiment of the present disclosure is not limited to a P-type transistor.
  • the driving transistor T1 and the threshold compensation transistor T3 those skilled in the art may implement one or more of the embodiments in the present disclosure by using an N-type transistor according to actual needs. The function of a transistor.
  • the first pole of the transistor may be a source or a drain, and correspondingly, a second drain or source of the transistor. Therefore, the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure are interchangeable as needed.
  • the control signals for their gates are also different. For example, for an N-type transistor, the N-type transistor is in an on state when the control signal is a high level signal, and the N-type transistor is in an off state when the control signal is a low level signal. For a P-type transistor, the P-type transistor is in an on state when the control signal is a low level signal, and the P-type transistor is in an off state when the control signal is a high level signal.
  • the control signals in the embodiments of the present disclosure may vary correspondingly depending on the type of transistor.
  • FIG. 4 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 70 includes a plurality of pixel units 110 , and the plurality of pixel units 110 may be arranged in an array.
  • the display panel 70 may include, for example, 1440 rows and 900 columns of pixel units 110 according to actual application requirements.
  • Each of the pixel units 110 may include the pixel circuit 100 described in any of the above embodiments.
  • the pixel circuit 100 improves the display quality of the display panel by improving the short-term afterimage phenomenon caused by the hysteresis effect by biasing the driving circuit in the reset phase.
  • the display panel 70 may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel.
  • the display panel 70 may be not only a flat panel but also a curved panel or even a spherical panel.
  • the display panel 70 can also be provided with a touch function, that is, the display panel 70 can be a touch display panel.
  • FIG. 5 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 80 includes the display panel 70 of any of the above, and the display panel 70 is for displaying an image.
  • Each of the pixel units of the display panel 70 includes the pixel circuit described in any of the above embodiments.
  • the pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, a light emitting element, a first reset bias circuit, a second reset bias circuit, and the like.
  • the first reset bias circuit and the second reset bias circuit are configured to control the driving circuit to be in a bias state during the reset phase, thereby improving a short-term afterimage phenomenon due to a hysteresis effect and improving display quality of the display device.
  • display device 80 may also include a gate driver 82.
  • the gate driver 82 is also configured to be electrically coupled to the data write circuit through a plurality of gate lines for providing a second control signal to the data write circuit.
  • display device 80 may also include a data driver 84.
  • Data driver 84 is configured to provide a data signal to display panel 70.
  • the data signal can be a voltage signal for controlling the intensity of illumination of the light-emitting elements of the respective pixel unit. The higher the voltage of the data signal, the larger the gray scale, thereby making the luminous intensity of the light-emitting element larger.
  • gate driver 82 and data driver 84 can each be implemented by a respective application specific integrated circuit chip or can be directly fabricated on display panel 70 by a semiconductor fabrication process.
  • the display device 80 can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure further provides a driving method of a pixel circuit, which can be applied to the pixel circuit described in any of the above.
  • FIG. 6 is a schematic flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 6, the driving method of the pixel circuit includes the following steps:
  • Step S101 in the reset phase, resetting the driving circuit and controlling the driving circuit to be in a bias state;
  • Step S102 writing a data signal to the driving circuit during the data writing phase
  • Step S103 In the light emitting phase, the light emitting element is driven to emit light.
  • the pixel circuit 100 may include a light emitting element EL, a driving circuit 10, a first reset bias circuit 21, and a second reset bias circuit 22.
  • the drive circuit 10 includes a drive transistor T1
  • the first reset bias circuit 21 includes a first bias transistor T4
  • the second reset bias circuit 22 includes a second bias transistor T8.
  • resetting the driving circuit and controlling the driving circuit to be in a bias state may include: writing a first bias voltage signal to a gate of the driving transistor through the first bias transistor; and passing the second bias The transistor writes a second bias voltage signal to the first pole of the drive transistor. The difference between the first bias voltage signal and the second bias voltage signal controls the drive transistor to be in a biased state.
  • the first bias voltage signal and the second bias voltage signal can be the same.
  • the first bias voltage signal is less than the second bias voltage signal.
  • the second bias transistor T8 can be time-multiplexed into a second control transistor, and the second bias voltage signal can be a first power voltage signal.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure may include a threshold compensation operation.
  • the driving method may further include: writing a threshold compensation signal to the gate of the driving transistor through the threshold compensation circuit in the data writing phase. Thereby the pixel circuit can compensate for the threshold voltage of the drive transistor.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure may include an IR drop compensation operation.
  • the driving method may further include: writing a reference voltage signal to the first electrode of the driving transistor through the voltage drop compensation circuit in the data writing phase. Thereby the pixel circuit can compensate for the IR drop of the first supply voltage terminal.
  • the timing chart of the pixel circuit can be set according to actual requirements, which is not specifically limited in the embodiment of the present disclosure.
  • FIG. 7 is an exemplary timing diagram of a driving method of the pixel circuit illustrated in FIGS. 2 and 3.
  • FIGS. 8A through 8C are schematic views of the pixel circuit shown in FIG. 2 at various stages of operation.
  • the operation flow of a driving method of a pixel circuit according to an embodiment of the present disclosure is described in detail below with reference to FIG. 2, FIG. 7 and FIG. 8A to FIG.
  • a dotted line at the position of the transistor indicates that the transistor is in an off state, and a no symbol at a position of the transistor indicates that the transistor is in an on state.
  • the solid line with an arrow indicates the direction of signal flow.
  • FIGS. 7 and 8A in the reset RT stage, a first control terminal of the first control signal S 1 supplied SC1 low level signal, thereby biasing the first and second biasing transistor T4 Transistor T8 is turned on.
  • the second control signal S 2 provided by the second control terminal SC2 is a high level signal
  • the third control signal S 3 (ie, the illumination control signal) provided by the third control terminal SC3 is a high level signal, so that the data is written into the transistor T2.
  • the voltage drop compensation transistor T6, the first control transistor T7, and the second control transistor T5 are all in an off state.
  • the first bias voltage terminal VB1 outputs a first bias voltage signal V init1 , and the first bias voltage signal V init1 is smaller than a sum of the threshold voltage V th2 of the threshold compensation transistor T3 and the data signal V data , so that the threshold compensation transistor T3 is at On state.
  • the first bias voltage signal V init1 is transmitted to the gate of the driving transistor T1 via the first biasing transistor T4, so that the voltage of the gate of the driving transistor T1 is reset to the first bias voltage signal V init1 .
  • the second bias voltage terminal VB2 (ie, the reset voltage terminal VR) may output a second bias voltage signal V init2 , and the second bias voltage signal V init2 is transmitted to the first pole of the driving transistor T1 via the second bias transistor T8 Thus, the voltage of the first pole of the driving transistor T1 is reset to the second bias voltage signal V init2 . At this time, the driving transistor T1 may be in an on state.
  • the driving transistor T1 in the reset phase RT, is in an on state. However, it is not limited thereto, and in the reset phase RT, the driving transistor T1 may also be in an off state.
  • the first bias voltage signal V init1 and the second bias voltage signal V init2 may be the same, for example, in which case the driving transistor T1 is in an off state.
  • the data writing stage at DT the first control signals S 1 becomes a high level signal
  • the second control signal S 2 becomes a low level signal
  • the third control Signal S 3 remains at a high level signal.
  • the first bias transistor T4, the second bias transistor T8, the first control transistor T7, and the second control transistor T5 are all in an off state, the driving transistor T1, the data writing transistor T2, the voltage drop compensation transistor T6, and the threshold.
  • the compensation transistor T3 is turned on.
  • the data signal V data charges the second end of the storage capacitor Cst via the data write transistor T2 and the threshold compensation transistor T3 until the voltage at the second end of the storage capacitor Cst is V data + V th2 , and V th2 is threshold compensation transistor T3 threshold voltage V th2, the same threshold voltage V th2 of the drive transistor T1, a threshold compensation transistor T3, the threshold voltage V th1, i.e., the voltage of the second terminal of the storage capacitor Cst may be V data + V th1. At this time, the voltage of the gate of the driving transistor T1 becomes V data + V th1 .
  • the reference voltage signal V ref charges the first end of the storage capacitor Cst via the voltage drop compensation transistor T6, that is, the voltage of the first end of the storage capacitor Cst may be the reference voltage signal V ref , and at this time, the first pole of the driving transistor T1 The voltage becomes V ref .
  • the first control signal S 1 maintains a high level signal
  • the second control signal S 2 becomes a high level signal
  • the third control signal S 3 Becomes a low level signal.
  • the first bias transistor T4, the second bias transistor T8, the data write transistor T2, the voltage drop compensation transistor T6, and the threshold compensation transistor T3 are all in an off state
  • the driving transistor T1, the first control transistor T7, and the The two control transistors T5 are all turned on.
  • the first power voltage signal V dd outputted by the first power voltage terminal V1 can be transmitted to the first pole of the driving transistor T1 via the second control transistor T5, and the voltage of the first pole of the driving transistor T1 becomes the first power voltage.
  • the signal V dd due to the bootstrap effect of the storage capacitor Cst, causes the voltage of the gate of the driving transistor T1 to become V data + V th1 + V dd - V ref .
  • the correspondence between the voltage of the gate of the driving transistor T1 and the voltage of the first electrode can be as shown in Table 1 below.
  • FIGS. 9A through 9C are schematic views of the pixel circuits shown in FIG. 3 at various stages of operation.
  • the operation flow of another driving method of the pixel circuit provided by the embodiment of the present disclosure is described in detail below with reference to FIG. 3, FIG. 7 and FIG. 9A to FIG. 9C.
  • a dotted line at the position of the transistor indicates that the transistor is in an off state, and a no symbol at a position of the transistor indicates that the transistor is in an on state.
  • the solid line with an arrow indicates the direction of signal flow.
  • FIGS. 3, 7 and 9A in the reset RT stage, a first control terminal of the first control signal S 1 supplied SC1 low level signal, so that the first bias transistor T4 is turned on.
  • the second control signal S 2 provided by the second control terminal SC2 is a high level signal, so that the second bias transistor T8 is turned on, and the data writing transistor T2 and the voltage drop compensating transistor T6 are in an off state.
  • the third control signal S 3 (ie, the light emission control signal) provided by the third control terminal SC3 is a high level signal, so that the first control transistor T7 is in an off state.
  • the first bias voltage terminal VB1 outputs a first bias voltage signal V init1 , and the first bias voltage signal V init1 is smaller than a sum of the threshold voltage V th2 of the threshold compensation transistor T3 and the data signal V data , so that the threshold compensation transistor T3 is at On state.
  • the first bias voltage signal V init1 is transmitted to the gate of the driving transistor T1 via the first biasing transistor T4, so that the voltage of the gate of the driving transistor T1 is reset to the first bias voltage signal V init1 .
  • the first power voltage terminal V1 ie, the second bias voltage terminal VB2 may output the first power voltage signal V dd , and the first power voltage signal V dd is transmitted to the first pole of the driving transistor T1 via the second bias transistor T8.
  • the voltage of the first pole of the driving transistor T1 is set to the first power supply voltage signal V dd .
  • the driving transistor T1 may be in an on state.
  • the first power voltage signal V dd may be greater than the first bias voltage signal V init1 , and the difference between the first bias voltage signal V init1 and the first power voltage signal V dd is not greater than Vgs255 (the maximum gray scale corresponding driving transistor)
  • the gate-to-source voltage difference of T1), that is, V init1 - V dd is less than or equal to Vgs255.
  • the driving transistor T1 in the reset phase RT, is in an on state. However, it is not limited thereto, and in the reset phase RT, the driving transistor T1 may also be in an off state. For example, if in the reset phase RT, V init1 - V dd is greater than the threshold voltage V th1 of the driving transistor T1, at this time, the driving transistor T1 is in an off state.
  • a first control signals S 1 becomes a high level signal
  • the second control signal S 2 becomes a low level signal
  • the third control Signal S 3 remains at a high level signal.
  • the first bias transistor T4, the second bias transistor T8, and the first control transistor T7 are all in an off state, and the driving transistor T1, the data writing transistor T2, the voltage drop compensation transistor T6, and the threshold compensation transistor T3 are both turned on. .
  • the data signal V data charges the second end of the storage capacitor Cst via the data write transistor T2 and the threshold compensation transistor T3 until the voltage at the second end of the storage capacitor Cst is V data + V th2 , and V th2 is threshold compensation transistor T3 threshold voltage V th2, the same threshold voltage V th2 of the drive transistor T1, a threshold compensation transistor T3, the threshold voltage V th1, i.e., the voltage of the second terminal of the storage capacitor Cst may be V data + V th1. At this time, the voltage of the gate of the driving transistor T1 becomes V data + V th1 .
  • the reference voltage signal V ref charges the first end of the storage capacitor Cst via the voltage drop compensation transistor T6, that is, the voltage of the first end of the storage capacitor Cst may be the reference voltage signal V ref , and at this time, the first pole of the driving transistor T1 The voltage becomes V ref .
  • the first control signal S 1 maintains a high level signal
  • the second control signal S 2 becomes a high level signal
  • the third control signal S 3 Becomes a low level signal.
  • the first bias transistor T4, the data write transistor T2, the voltage drop compensation transistor T6, and the threshold compensation transistor T3 are all in an off state, and the driving transistor T1, the first control transistor T7, and the second bias transistor T8 are both guided. through. Therefore, the first power voltage signal V dd outputted by the first power voltage terminal V1 can be transmitted to the first pole of the driving transistor T1 via the second bias transistor T8, and the voltage of the first pole of the driving transistor T1 becomes the first power source.
  • the voltage signal V dd due to the bootstrap effect of the storage capacitor Cst, causes the voltage of the gate of the driving transistor T1 to become V data + V th1 + V dd - V ref .
  • the correspondence between the voltage of the gate of the driving transistor T1 and the voltage of the first electrode can be as shown in Table 2 below.
  • the light emitting current I OLED flowing through the driving transistor T1 can be expressed as:
  • I OLED K(V GS –V th1 ) 2
  • V GS is the voltage difference between the gate and the source of the driving transistor T1
  • V dd is the first power supply voltage signal outputted from the first power supply voltage terminal V1
  • V th1 is the threshold voltage of the driving transistor T1. It can be seen from the above formula that the illuminating current I OLED has not been affected by the threshold voltage V th1 of the driving transistor T1 and the first power voltage signal of the first power supply voltage terminal V1, but only the reference voltage outputted from the reference power terminal REF.
  • the signal V ref is related to the data signal V data .
  • the data signal V data is directly transmitted by the data signal terminal VD, which is independent of the threshold voltage Vth of the driving transistor T1, so that the problem of the threshold voltage drift of the driving transistor T1 due to the process process and long-time operation can be solved.
  • the reference voltage signal V ref is provided by the reference power supply terminal REF, which is independent of the IR drop of the first power supply voltage terminal V1, so that the problem of the IR drop of the display panel can be solved.
  • the pixel circuit can ensure the accuracy of the illuminating current I OLED , eliminate the threshold voltage of the driving transistor T1 and the influence of the IR drop on the illuminating current I OLED , ensure the normal operation of the illuminating element EL, improve the uniformity of the display picture, and improve display effect.
  • K is a constant, and K can be expressed as:
  • ⁇ n is the electron mobility of the driving transistor T1
  • C ox is the gate unit capacitance of the driving transistor T1
  • W is the channel width of the driving transistor T1
  • L is the channel length of the driving transistor T1.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure improves the display uniformity and display quality by improving the short-term afterimage problem caused by the hysteresis effect by causing the driving transistor to be in a bias state in the reset phase.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure can also perform the threshold compensation operation and the voltage drop compensation operation, thereby compensating the threshold voltage drift of the driving transistor and the IR drop of the display panel, effectively improving the display effect of the display panel, and improving the display. quality.

Abstract

一种像素电路及其驱动方法、显示面板和显示设备。像素电路（100）包括：发光元件（EL）、驱动电路（10）、第一复位偏置电路（21）和第二复位偏置电路（22）。驱动电路（10）的控制端与数据信号端（VD）和第一复位偏置电路（21）的第二端电连接，驱动电路（10）的第一端与第二复位偏置电路（22）的第二端电连接，驱动电路（10）的第二端与发光元件（EL）电连接；第一复位偏置电路（21）的控制端与第一控制端（SC1）电连接，第一复位偏置电路（21）的第一端与第一偏置电压端（VB1）电连接；第二复位偏置电路（22）的控制端与偏置控制端（BS）电连接，第二复位偏置电路（22）的第一端与第二偏置电压端（VB2）电连接；第一复位偏置电路（21）和第二复位偏置电路（22）被配置为在复位阶段控制驱动电路（10）处于偏置状态。

Description

像素电路及其驱动方法、显示面板和显示设备
本申请要求于2017年12月06日递交的中国专利申请第201711278159.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板和显示设备。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。作为新一代的显示方式，OLED显示面板可以被广泛应用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开至少一实施例提供一种像素电路，包括：发光元件、驱动电路、第一复位偏置电路和第二复位偏置电路。所述驱动电路的控制端与数据信号端以及所述第一复位偏置电路的第二端电连接，所述驱动电路的第一端与所述第二复位偏置电路的第二端电连接，所述驱动电路的第二端与所述发光元件电连接；所述第一复位偏置电路的控制端与第一控制端电连接，所述第一复位偏置电路的第一端与第一偏置电压端电连接；所述第二复位偏置电路的控制端与偏置控制端电连接，所述第二复位偏置电路的第一端与第二偏置电压端电连接；所述第一复位偏置电路和所述第二复位偏置电路被配置为在复位阶段对所述驱动电路进行复位并控制所述驱动电路处于偏置状态。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括驱动晶体管，所述第一复位偏置电路包括第一偏置晶体管，所述第二复位偏置电路包括第二偏置晶体管，所述驱动电路的控制端为所述驱动晶体管的栅极，所述驱动电路的第一端为所述驱动晶体管的第一极，所述驱动电路的第二端为所述驱动晶体管的第二极，所述第一复位偏置电路的第一端为所述第一偏置晶体管的第 一极，所述第一复位偏置电路的第二端为所述第一偏置晶体管的第二极，所述第一复位偏置电路的控制端为所述第一偏置晶体管的栅极，所述第二复位偏置电路的第一端为所述第二偏置晶体管的第一极，所述第二复位偏置电路的第二端为所述第二偏置晶体管的第二极，所述第二复位偏置电路的控制端为所述第二偏置晶体管的栅极。
例如，本公开一实施例提供的像素电路还包括：数据写入电路和存储电路。所述数据写入电路被配置为在数据写入阶段向所述驱动晶体管的栅极写入数据信号；所述存储电路被配置为存储所述数据信号并将其保持在所述驱动晶体管的栅极。
例如，本公开一实施例提供的像素电路还包括阈值补偿电路。所述阈值补偿电路被配置为在所述数据写入阶段向所述驱动晶体管的栅极写入阈值补偿信号。
例如，在本公开一实施例提供的像素电路中，所述阈值补偿电路包括阈值补偿晶体管，所述数据写入电路包括数据写入晶体管，所述存储电路包括存储电容，所述阈值补偿晶体管的第一极与所述数据写入晶体管的第二极电连接，所述阈值补偿晶体管的第二极和栅极彼此电连接，并电连接至所述驱动晶体管的栅极；所述数据写入晶体管的第一极与所述数据信号端电连接，所述数据写入晶体管的栅极与第二控制端电连接；所述存储电容的第一端电连接至所述驱动晶体管的第一极，所述存储电容的第二端电连接至所述驱动晶体管的栅极。
例如，本公开一实施例提供的像素电路还包括压降补偿电路。所述压降补偿电路被配置在所述数据写入阶段向所述驱动晶体管的第一极写入参考电压信号。
例如，在本公开一实施例提供的像素电路中，所述压降补偿电路包括压降补偿晶体管，所述存储电路包括存储电容，所述压降补偿晶体管的第一极与参考电源端电连接，所述压降补偿晶体管的第二极电连接至所述驱动晶体管的第一极，所述压降补偿晶体管的栅极与第二控制端电连接；所述存储电容的第一端电连接至所述驱动晶体管的第一极，所述存储电容的第二端电连接至所述驱动晶体管的栅极。
例如，本公开一实施例提供的像素电路还包括发光控制电路。所述发光控制电路被配置为控制所述驱动电路驱动所述发光元件发光。
例如，在本公开一实施例提供的像素电路中，所述发光控制电路包括第一 控制晶体管和第二控制晶体管，所述第一控制晶体管的第一极电连接至所述驱动晶体管的第二极，所述第一控制晶体管的第二极电连接至所述发光元件，所述第一控制晶体管的栅极与第三控制端电连接；所述第二控制晶体管的第一极电连接至第一电源电压端，所述第二控制晶体管的第二极电连接至所述驱动晶体管的第一极，所述第二控制晶体管的栅极被配置接收发光控制信号。
例如，在本公开一实施例提供的像素电路中，所述第二控制晶体管的栅极电连接至所述第三控制端以接收所述发光控制信号，所述第二偏置晶体管的栅极与所述第一控制端电连接，所述第二偏置晶体管的第一极与复位电压端电连接，所述复位电压端为所述第二偏置电压端，所述第一控制端为所述偏置控制端。
例如，在本公开一实施例提供的像素电路中，所述第一偏置电压端输出的信号与所述第二偏置电压端输出的信号相同。
例如，在本公开一实施例提供的像素电路中，所述第二偏置晶体管复用为所述第二控制晶体管。
例如，在本公开一实施例提供的像素电路中，所述第二偏置晶体管为N型晶体管，所述第二偏置晶体管的栅极与所述第二控制端电连接，所述第一电源电压端为所述第二偏置电压端，所述第二控制端为所述偏置控制端。
本公开至少一实施例还提供一种显示面板，包括根据上述任一项所述的像素电路。
本公开至少一实施例还提供一种显示设备，包括上述任一项所述的显示面板。
本公开至少一实施例还提供一种上述任一项所述的像素电路的驱动方法，包括：在所述复位阶段，对所述驱动电路进行复位并控制所述驱动电路处于偏置状态；在数据写入阶段，向所述驱动电路写入数据信号；在发光阶段，驱动所述发光元件发光。
例如，在本公开一实施例提供的驱动方法中，所述驱动电路包括驱动晶体管，所述第一复位偏置电路包括第一偏置晶体管，所述第二复位偏置电路包括第二偏置晶体管；对所述驱动电路进行复位并控制所述驱动电路处于偏置状态包括：通过所述第一偏置晶体管向所述驱动晶体管的栅极写入第一偏置电压信号；以及通过所述第二偏置晶体管向所述驱动晶体管的第一极写入第二偏置电压信号。所述第一偏置电压信号和所述第二偏置电压信号之差控制所述驱动晶 体管处于偏置状态。
例如，在本公开一实施例提供的驱动方法中，所述第一偏置电压信号和所述第二偏置电压信号相同。
例如，在本公开一实施例提供的驱动方法中，所述第二偏置晶体管的第一极电连接至第一电源电压端以接收第一电源电压信号，所述第一电源电压信号为所述第二偏置电压信号。
例如，本公开一实施例提供的驱动方法还包括：在所述数据写入阶段，通过阈值补偿电路向所述驱动晶体管的栅极写入阈值补偿信号。
例如，本公开一实施例提供的驱动方法还包括：在所述数据写入阶段，通过压降补偿电路向所述驱动晶体管的第一极写入参考电压信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种像素电路的示意性框图；
图2为本公开一实施例提供的一种像素电路的结构示意图；
图3为本公开另一实施例提供的一种像素电路的结构示意图；
图4为本公开一实施例提供的一种显示面板的示意性框图；
图5为本公开一实施例提供的一种显示设备的示意性框图；
图6为本公开一实施例提供的一种像素电路的驱动方法的示意性流程图；
图7为本公开一实施例提供的一种像素电路的示意性时序图；
图8A为图2所示的像素电路的复位阶段的示意图；
图8B为图2所示的像素电路的数据写入阶段的示意图；
图8C为图2所示的像素电路的发光阶段的示意图；
图9A为图3所示的像素电路的复位阶段的示意图；
图9B为图3所示的像素电路的数据写入阶段的示意图；以及
图9C为图3所示的像素电路的发光阶段的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本 公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
随着有机发光二极管(Organic Light Emitting Diode，OLED)显示面板的尺寸增大，OLED显示面板的电源电压降(IR drop)的问题越来越严重，从而导致OLED显示面板的显示亮度不均匀，影响OLED显示面板的显示效果。
OLED显示面板上的每个像素点由多个薄膜晶体管(TFT)驱动发光，采用TFT驱动技术可以提升显示速度、对比度和亮度、提高分辨率。但是，TFT存在磁滞效应现象，TFT的磁滞效应是在一定的偏压下，TFT电特性表现出来的一种不确定性，即流过TFT的电流不仅与当前的偏压有关，还与上一时刻TFT所处的状态。TFT的磁滞效应与TFT的栅介质、半导体材料以及两者之间的界面态陷阱有关，TFT的磁滞效应会造成短期残像，前一帧的图像往往会保留在后一帧的图像中，从而影响OLED显示面板的显示品质，甚至导致显示错误。
本公开至少一实施例提供一种像素电路及其驱动方法、显示面板和显示设备，其通过在复位阶段使驱动电路处于偏置状态，从而在显示画面时，驱动电路均由偏置状态改变为相应的显示状态，后一帧显示画面的数据电压不受前一帧显示画面的数据电压的影响，从而改善因磁滞效应产生的短期残像问题，提高显示面板的显示质量。另外，本公开实施例提供的像素电路的驱动方法还可 以进行阈值补偿操作和压降补偿操作，从而补偿驱动晶体管的阈值电压漂移和显示面板的电源电压降(IR drop)，从而提高显示均匀性，有效改善显示面板的显示效果。
下面对本公开的一些实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一实施例提供的一种像素电路的示意性框图。图2为本公开一实施例提供的一种像素电路的结构示意图。
例如，如图1所示，本公开实施例提供的像素电路100可以包括发光元件EL、驱动电路10、第一复位偏置电路21和第二复位偏置电路22。驱动电路10的控制端与数据信号端VD以及第一复位偏置电路21的第二端分别电连接，驱动电路10的第一端与第二复位偏置电路22的第二端电连接，驱动电路10的第二端与发光元件EL电连接。第一复位偏置电路21的控制端与第一控制端SC1电连接，第一复位偏置电路21的第一端与第一偏置电压端VB1电连接；第二复位偏置电路22的控制端与偏置控制端BS电连接，第二复位偏置电路22的第一端与第二偏置电压端VB2电连接；第一复位偏置电路21和第二复位偏置电路22被配置为在复位阶段对驱动电路10进行复位并控制驱动电路10处于偏置状态。
例如，本公开实施例提供的像素电路100可应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。
例如，发光元件EL被配置为在施加电压或电流的情况下发光。发光元件EL可以为有机发光元件，有机发光元件例如可以为有机发光二极管，但本公开的实施例不限于此。发光元件EL例如可以采用不同的发光材料，以发出不同颜色的光，从而进行彩色发光。
例如，驱动电路10、第一复位偏置电路21和第二复位偏置电路22的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。例如，本公开实施例提供的一种像素电路100可以实现为如图2所示的电路结构。
例如，如图2所示，在一个实施例中，驱动电路10包括驱动晶体管T1。驱动电路10的控制端a3为驱动晶体管T1的栅极，驱动电路10的第一端a1为驱动晶体管T1的第一极，驱动电路10的第二端a2为驱动晶体管T1的第二极。“驱动电路10处于偏置状态”可以表示驱动晶体管T1处于偏置状态，也就是说，第一复位偏置电路21和第二复位偏置电路22可以在复位阶段控制驱 动晶体管T1处于偏置状态。
例如，驱动晶体管T1为P型晶体管。驱动晶体管T1的第一极可以为源极，驱动晶体管T1的第二极可以为漏极。在本公开的描述中，“驱动晶体管T1处于偏置状态”可以表示驱动晶体管T1的栅极和源极之间的电压差不大于最大灰阶(即255灰阶)对应的栅极和源极之间的电压差Vgs255，即驱动晶体管T1的Vgs(即驱动晶体管T1的栅极和源极之间的电压差)小于等于Vgs255。“驱动晶体管T1处于偏置状态”还可以表示驱动晶体管T1的栅极和源极之间的电压差不小于驱动晶体管T1的阈值电压V th1，即驱动晶体管T1的Vgs大于等于V th1。
例如，第一复位偏置电路21被配置为在复位阶段向驱动晶体管T1的栅极写入第一偏置电压信号；第二复位偏置电路22被配置为在复位阶段向驱动晶体管T1的第一极写入第二偏置电压信号。第一偏置电压信号和第二偏置电压信号之差控制驱动晶体管T1处于偏置状态。在复位阶段，第一偏置电压信号和第二偏置电压信号分别为驱动晶体管T1的栅极电压和源极电压，从而第一偏置电压信号和第二偏置电压信号之间的电压差(例如，该电压差表示第一偏置电压信号减去第二偏置电压信号得到的差值)大于等于V th1；或者，小于等于Vgs255。
例如，如图2所示，第一复位偏置电路21包括第一偏置晶体管T4。第一复位偏置电路21的第一端b1为第一偏置晶体管T4的第一极，第一复位偏置电路21的第二端b2为第一偏置晶体管T4的第二极，第一复位偏置电路21的控制端b3为第一偏置晶体管T4的栅极。第二复位偏置电路22包括第二偏置晶体管T8。第二复位偏置电路22的第一端c1为第二偏置晶体管T8的第一极，第二复位偏置电路22的第二端c2为第二偏置晶体管T8的第二极，第二复位偏置电路22的控制端c3为第二偏置晶体管T8的栅极。
例如，第一偏置电压端VB1被配置为输出第一偏置电压信号V init1，第二偏置电压端VB2被配置为输出第二偏置电压信号V init2。
例如，第一偏置晶体管T4的栅极与第一控制端SC1电连接以接收第一控制信号S 1，第一偏置晶体管T4的第一极与第一偏置电压端VB1电连接以接收第一偏置电压信号V init1。第一偏置晶体管T4的第二极与驱动晶体管T1的栅极电连接，以在第一偏置晶体管T4导通时向驱动晶体管T1的栅极传输第一偏置电压信号V init1。
例如，如图2所示，第二偏置晶体管T8的栅极与第一控制端SC1电连接，第二偏置晶体管T8的第一极与复位电压端VR电连接，第二偏置晶体管T8的第二极与驱动晶体管T1的第一极电连接。第一控制端SC1即为偏置控制端BS，复位电压端VR为第二偏置电压端VB2。在复位阶段，第一控制端SC1可以输出第一控制信号S 1，第一控制信号S 1为偏置控制信号。复位电压端VR可以输出第二偏置电压信号V init2，第二偏置晶体管T8的第一极可以接收第二偏置电压信号V init2，从而第二偏置电压信号V init2可以在第二偏置晶体管T8导通时被传输至驱动晶体管T1的第一极。
例如，在图2所示的实施例中，第一偏置晶体管T4和第二偏置晶体管T8的类型相同。第一偏置晶体管T4和第二偏置晶体管T8例如均为P型晶体管，第一偏置晶体管T4的栅极和第二偏置晶体管T8的栅极均电连接到第一控制端SC1且由相同的第一控制信号S 1控制，从而可以节省信号控制端的数量。第一偏置晶体管T4和第二偏置晶体管T8在第一控制信号S1的控制下同时工作。需要说明的是，第一偏置晶体管T4的栅极和第二偏置晶体管T8的栅极也可以分别电连接到不同的信号控制端，以接收不同的控制信号，只要保证第一偏置晶体管T4的栅极和第二偏置晶体管T8能在复位阶段同时工作即可。
需要说明的是，第一偏置晶体管T4和第二偏置晶体管T8的类型也可以不相同，本公开对此不作限制。
例如，第一偏置电压信号V init1与第二偏置电压信号V init2可以相等，由此第一偏置晶体管T4的第一极和第二偏置晶体管T8的第一极可以均电连接到同一个偏置电压端(例如，第一偏置电压端VB1或第二偏置电压端VB2)，也就是说，像素电路100可以仅包括一个偏置电压端，从而节省偏置电压端的数量，节省生产成本。但不限于此，第一偏置电压信号V init1与第二偏置电压信号V init2可以不相等，只要第一偏置电压信号V init1与第二偏置电压信号V init2之差大于等于V th1；或者，第一偏置电压信号V init1与第二偏置电压信号V init2之差小于等于Vgs255即可(即，V init1-V init2≤Vgs255，或V init1-V init2≥V th1)。本公开对此不作具体限制。
例如，如图2所示，像素电路100还可以包括数据写入电路11和存储电路12。数据写入电路11被配置为在数据写入阶段向驱动晶体管T1的栅极写入数据信号；存储电路12被配置为存储数据信号并将其保持在驱动晶体管T1的栅极。
例如，存储电路12包括存储电容Cst。存储电容Cst的第一端电连接至驱动晶体管T1的第一极，存储电容Cst的第二端电连接至驱动晶体管T1的栅极。也就是说，第一偏置晶体管T4的第二极与存储电容Cst的第二端电连接，第二偏置晶体管T8的第二极与存储电容Cst的第一端电连接。从而，在复位阶段，存储电容Cst的第一端可以存储第二偏置电压信号V init2并将其保持在驱动晶体管T1的第一极，存储电容Cst的第二端可以存储第一偏置电压信号V init1并将其保持在驱动晶体管T1的栅极。
例如，根据实际应用需求，像素电路100还可以具备电学补偿功能。电学补偿功能可以通过电压补偿、电流补偿或混合补偿来实现。
例如，如图2所示，像素电路100还可以包括阈值补偿电路13。阈值补偿电路13被配置为在数据写入阶段向驱动晶体管T1的栅极写入阈值补偿信号，以补偿驱动晶体管T1的阈值电压V th1漂移。从而，本公开实施例的像素电路100可以补偿驱动晶体管T1的阈值电压漂移，提高显示均匀性和显示效果。
例如，阈值补偿电路13可以包括阈值补偿晶体管T3，数据写入电路11可以包括数据写入晶体管T2。如图2所示，阈值补偿晶体管T3的第一极与数据写入晶体管T2的第二极电连接，阈值补偿晶体管T3的第二极和栅极彼此电连接，并电连接至驱动晶体管T1的栅极。数据写入晶体管T2的第一极与数据信号端VD电连接，数据写入晶体管T2的栅极与第二控制端SC2电连接。
例如，阈值补偿晶体管T3和驱动晶体管T1相同，也就是说，阈值补偿晶体管T3和驱动晶体管T1的类型、制备工艺等均相同，从而保证阈值补偿晶体管T3的阈值电压V th2和驱动晶体管T1的阈值电压V th1相同。阈值补偿晶体管T3例如也为P型晶体管。
例如，第一偏置电压信号V init1需要小于阈值补偿晶体管T3的阈值电压V th2和数据信号V data之和。也就是说，第一偏置电压信号V init1需要满足以下公式：V init1<V th2+V data。由于阈值补偿晶体管T3的阈值电压V th2和驱动晶体管T1的阈值电压V th1相同，即，V init1<V th1+V data。
例如，在数据写入阶段，第二控制端SC2可以向数据写入晶体管T2的栅极提供第二控制信号S 2，以使数据写入晶体管T2导通。数据信号端VD可以向数据写入晶体管T2的第一极提供数据信号V data。由于阈值补偿晶体管T3的第二极和栅极彼此电连接，阈值补偿晶体管T3导通。由此，数据信号端VD提供的数据信号V data可以经由数据写入晶体管T2和阈值补偿晶体管T3对存 储电容Cst的第二端充电，当存储电容Cst的第二端的电压达到数据信号V data和驱动晶体管T1的阈值电压V th1时，阈值补偿晶体管T3截止，即充电结束，此时数据信号V data和驱动晶体管T1的阈值电压V th1可以被存储在存储电容Cst的第二端，且该存储的数据信号V data和驱动晶体管T1的阈值电压V th1可以控制驱动晶体管T1的导通程度，从而控制流过驱动晶体管T1的发光电流大小，该流过驱动晶体管T1的发光电流可以决定发光元件EL的发光的灰阶(即发光强度)。
例如，在图2所示的实施例中，阈值补偿电路13为内部补偿电路，但不限于此，阈值补偿电路13也可以为外部补偿电路，外部补偿电路例如可以包括感测电路部分以感测驱动晶体管T1的电学特性或发光元件EL的电学特性，具体构造可以参见常规设计，这里不再赘述。
例如，如图2所示，像素电路100还可以包括压降补偿电路14。压降补偿电路14被配置在数据写入阶段向驱动晶体管T1的第一极写入参考电压信号V ref，以补偿由于显示面板的电源电压降(IR drop)引起的发光元件EL的显示电压差异，提高显示画质、改善显示效果。
例如，压降补偿电路14可以包括压降补偿晶体管T6。压降补偿晶体管T6的第一极与参考电源端REF电连接。压降补偿晶体管T6的第二极电连接至驱动晶体管T1的第一极，即压降补偿晶体管T6的第二极也与存储电容Cst的第一端电连接。压降补偿晶体管T6的栅极与第二控制端SC2电连接。
例如，在数据写入阶段，第二控制端SC2可以向压降补偿晶体管T6的栅极提供第二控制信号S2，以使压降补偿晶体管T6导通。参考电源端REF可以向压降补偿晶体管T6的第一极提供参考电压信号V ref，从而参考电压信号V ref经由压降补偿晶体管T6对存储电容Cst的第一端充电，由此存储电容Cst的第一端的电压可以为参考电压信号V ref。
例如，如图2所示，像素电路100还可以包括发光控制电路15。发光控制电路15被配置为控制驱动电路10驱动发光元件EL发光。发光控制电路15可以包括第一发光控制子电路151和第二发光控制子电路152。第一发光控制子电路151设置在驱动电路10与发光元件EL之间，且被配置为控制将驱动电路10与发光元件EL之间的电连接导通或断开。第二发光控制子电路152设置在第一电源电压端V1和驱动电路10之间，且被配置为控制将第一电源电压端V1和驱动电路10之间的电连接导通或断开。
例如，第一发光控制子电路151可以包括第一控制晶体管T7，第二发光控制子电路152可以包括第二控制晶体管T5。第一控制晶体管T7的第一极电连接至驱动晶体管T1的第二极，第一控制晶体管T7的第二极电连接至发光元件EL的第一端(例如，发光元件EL的正极端)，第一控制晶体管T7的栅极与第三控制端SC3电连接；第二控制晶体管T5的第一极电连接至第一电源电压端V1，第二控制晶体管T5的第二极电连接至驱动晶体管T1的第一极，第二控制晶体管T5的栅极被配置接收发光控制信号。发光元件EL的第二端(例如，发光元件EL的负极端)电连接至第二电源电压端V2。
例如，在图2所示的实施例中，第三控制端SC3可以在发光阶段输出第三控制信号S 3，第三控制信号S 3即为发光控制信号，第二控制晶体管T5的栅极可以电连接至第三控制端SC3以接收该发光控制信号，也就是说，第一控制晶体管T7的栅极和第二控制晶体管T5的栅极可以均电连接到第三控制端SC3，且第三控制端SC3可以同时向第一控制晶体管T7的栅极和第二控制晶体管T5的栅极传输相同的发光控制信号。
需要说明的是，第一控制晶体管T7和第二控制晶体管T5也可以电连接至不同的控制端，而不同的控制端施加的发光控制信号同步。本公开实施例对此不作限制。
例如，在发光阶段，发光控制信号被同时施加到第一控制晶体管T7和第二控制晶体管T5的栅极，以使得第一控制晶体管T7和第二控制晶体管T5同时导通，从而第一电源电压端V1、第二控制晶体管T5、驱动晶体管T1、第一控制晶体管T7、发光元件EL和第二电源电压端V2可以形成回路，发光电流经由导通的第二控制晶体管T5、驱动晶体管T1和第一控制晶体管T7被传输至发光元件EL以驱动其发光。
例如，第一电源电压端V1为高压端，且可以输出第一电源电压信号V dd，第二电源电压端V2为低压端，且可以输出第二电源电压信号V ss。高压端输出的电压信号大于低压端输出的电压信号，即第一电源电压信号V dd可以大于第二电源电压信号V ss。但不限于此，在一些实施例中，第一电源电压端V1也可以为低压端，而第二电源电压端V2为高压端。例如，高压端可以电连接电源的正极。低压端可以电连接电源的负极。低压端还可以电连接至地端(GND)。
需要说明的是，数据写入电路11、存储电路12、阈值补偿电路13、压降补偿电路14和发光控制电路15等电路的具体结构可以根据实际应用需求进行 设定，本公开的实施例对此不作具体限定。
图3为本公开另一实施例提供的一种像素电路的结构示意图。
例如，在另一个实施例中，图2所示的第二偏置晶体管可以复用为第二控制晶体管，由此该像素电路可以节省一个晶体管(省去图2的晶体管T5)，节约生产成本。如图3所示，第二偏置晶体管T8可以为N型晶体管，且被配置为在复位阶段向驱动晶体管T1的第一极写入第二偏置电压信号V init2。此处，第二偏置晶体管T8的栅极与第二控制端SC2电连接，第二偏置晶体管T8的第一极与第一电源电压端V1电连接，第二偏置晶体管T8的第二极与驱动晶体管T1的第一极电连接。第一电源电压端V1被配置为在复位阶段向第二偏置晶体管T8的第一极传输第一电源电压信号V dd，此时，第二偏置电压信号V init2即为第一电源电压信号V dd。
例如，在复位阶段，第一控制端SC1可以输出第一控制信号S 1以控制第一偏置晶体管T4导通，第二控制端SC2可以输出第二控制信号S 2以控制第二偏置晶体管T8导通；第一偏置电压端VB1被配置为输出第一偏置电压信号V init1，第一偏置电压信号V init1可以经由第一偏置晶体管T4传输至驱动晶体管T1的栅极，第一电源电压端V1可以输出第一电源电压信号V dd，第一电源电压信号V dd即为第二偏置电压信号V init2，第一电源电压信号V dd可以经由第二偏置晶体管T8传输至驱动晶体管T1的第一极。在这种情形下，在复位阶段，第二控制端SC2为偏置控制端BS，第一电源电压端V1为第二偏置电压端VB2，第一控制信号S 1和第二控制信号S 2均为偏置控制信号。
例如，在发光阶段，第二控制端SC2输出第二控制信号S 2，第三控制端输出第三控制信号S 3，第二控制信号S 2和第三控制信号S 3用于控制第二偏置晶体管T8和第一控制晶体管T7同时导通，从而控制将发光电流传输至发光元件EL以驱动其发光。在这种情形下，在发光阶段，第二控制信号S 2和第三控制信号S 3均为发光控制信号。
需要说明的是，图3所示的实施例中其余电路(例如，第一复位偏置电路21、数据写入电路11、存储电路12、阈值补偿电路13和压降补偿电路14等)可以与图2所示的实施例中相应电路的结构和连接方式均相同，在此不再赘述。
例如，在图3所示的实施例中，第二偏置晶体管T8的栅极与数据写入晶体管T2的栅极、压降补偿晶体管T6的栅极均通过相同的第二控制信号S 2控制，第二偏置晶体管T8与数据写入晶体管T2、压降补偿晶体管T6的类型可 以不同。也就是说，若第二偏置晶体管T8为N型晶体管，则数据写入晶体管T2和压降补偿晶体管T6均为P型晶体管。但不限于此，第二偏置晶体管T8的栅极与数据写入晶体管T2的栅极、压降补偿晶体管T6的栅极也可以通过不同的控制信号控制，在此种情形下，第二偏置晶体管T8与数据写入晶体管T2、压降补偿晶体管T6的类型则没有限制，即第二偏置晶体管T8与数据写入晶体管T2、压降补偿晶体管T6的类型可以相同(例如均为P型晶体管)，也可以不相同。本公开对此不作限制。
值得注意的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管为例详细阐述了本公开的技术方案。然而本公开的实施例的晶体管不限于P型晶体管，除了驱动晶体管T1和阈值补偿晶体管T3以外，本领域技术人员还可以根据实际需要利用N型晶体管实现本公开中的实施例中的一个或多个晶体管的功能。
在本公开的实施例中，晶体管的第一极可以为源极或漏极，相应地，晶体管的第二极为漏极或源极。所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。对于不同类型的晶体管，其栅极的控制信号也不相同。例如，对于N型晶体管，在控制信号为高电平信号时，该N型晶体管处于开启状态；而在控制信号为低电平信号时，N型晶体管处于截止状态。对于P型晶体管时，在控制信号为低电平信号时，该P型晶体管处于开启状态；而在控制信号为高电平信号时，P型晶体管处于截止状态。本公开实施例中的控制信号可以根据晶体管的类型而相应变化。
本公开实施例还提供一种显示面板。图4为本公开一实施例提供的一种显示面板的示意性框图。如图4所示，显示面板70包括多个像素单元110，多个像素单元110可以阵列排布，根据实际应用需求，显示面板70例如可以包括1440行、900列的像素单元110。每个像素单元110可以包括上述任一实施例所述的像素电路100。该像素电路100通过在复位阶段使驱动电路处于偏置状态，从而改善因磁滞效应产生的短期残像现象，提高显示面板的显示质量。
例如，显示面板70可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板70不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板70还可以具备触控功能，即显示面板70可以为触控显示面板。
本公开实施例还提供一种显示设备。图5为本公开一实施例提供的一种显示设备的示意性框图。如图5所示，显示设备80包括上述任一所述的显示面板70，显示面板70用于显示图像。显示面板70的每个像素单元包括上述任一实施例所述的像素电路。像素电路包括驱动电路、数据写入电路、存储电路、发光元件、第一复位偏置电路和第二复位偏置电路等。第一复位偏置电路和第二复位偏置电路被配置为在复位阶段控制驱动电路处于偏置状态，从而改善因磁滞效应产生的短期残像现象，提高显示设备的显示质量。
例如，显示设备80还可以包括栅极驱动器82。栅极驱动器82还被配置为通过多条栅线与数据写入电路电连接，以用于为数据写入电路提供第二控制信号。
例如，显示设备80还可以包括数据驱动器84。数据驱动器84被配置为向显示面板70提供数据信号。该数据信号可以为电压信号，用于控制相应像素单元的发光元件的发光强度。数据信号的电压越高则代表灰阶越大，由此使得发光元件的发光强度越大。
例如，栅极驱动器82和数据驱动器84可以分别由各自的专用集成电路芯片或者可以通过半导体制备工艺直接制备在显示面板70上来实现。
例如，显示设备80可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，对于显示设备80的其它组成部分(例如控制装置、图像数据编码/解码装置、时钟电路等)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例还提供一种像素电路的驱动方法，该驱动方法可以应用于上述任一项所述的像素电路。
图6为本公开一实施例提供的一种像素电路的驱动方法的示意性流程图。如图6所示，像素电路的驱动方法包括以下步骤：
步骤S101：在复位阶段，对驱动电路进行复位并控制驱动电路处于偏置状态；
步骤S102：在数据写入阶段，向驱动电路写入数据信号；
步骤S103：在发光阶段，驱动发光元件发光。
例如，以图2所示的像素电路为例，像素电路100可以包括发光元件EL、驱动电路10、第一复位偏置电路21和第二复位偏置电路22。驱动电路10包 括驱动晶体管T1，第一复位偏置电路21包括第一偏置晶体管T4，第二复位偏置电路22包括第二偏置晶体管T8。由此，在步骤S101中，对驱动电路进行复位并控制驱动电路处于偏置状态可以包括：通过第一偏置晶体管向驱动晶体管的栅极写入第一偏置电压信号；以及通过第二偏置晶体管向驱动晶体管的第一极写入第二偏置电压信号。第一偏置电压信号和第二偏置电压信号之差控制驱动晶体管处于偏置状态。
例如，第一偏置电压信号和第二偏置电压信号可以相同。或者，第一偏置电压信号小于第二偏置电压信号。
例如，在图3所示的实施例中，第二偏置晶体管T8可以被分时复用为第二控制晶体管，第二偏置电压信号可以为第一电源电压信号。
例如，在一个示例中，本公开实施例提供的像素电路的驱动方法可以包括阈值补偿操作。在步骤S102中，驱动方法还可以包括：在数据写入阶段，通过阈值补偿电路向驱动晶体管的栅极写入阈值补偿信号。从而该像素电路可以补偿驱动晶体管的阈值电压。
例如，在一个示例中，本公开实施例提供的像素电路的驱动方法可以包括压降(IR drop)补偿操作。在步骤S102中，驱动方法还可以包括：在数据写入阶段，通过压降补偿电路向驱动晶体管的第一极写入参考电压信号。从而该像素电路可以补偿第一电源电压端的IR drop。
例如，像素电路的时序图可以根据实际需求进行设定，本公开的实施例对此不作具体限定。
例如，在一个示例中，图7是图2和图3所示的像素电路的驱动方法的示例性时序图。
例如，图8A至图8C是图2所示的像素电路的在各个工作阶段的示意图。下面结合图2、图7和图8A至图8C详细说明本公开实施例提供的一种像素电路的驱动方法的操作流程。
需要说明的是，在图8A至图8C中，在晶体管的位置处设置虚线方框表示该晶体管处于截止状态，在晶体管的位置处不设置符号则表示该晶体管处于开启状态。带箭头的实线表示信号流向。
例如，如图2、图7和图8A所示，在复位阶段RT，第一控制端SC1提供的第一控制信号S 1为低电平信号，从而第一偏置晶体管T4和第二偏置晶体管T8导通。第二控制端SC2提供的第二控制信号S 2为高电平信号，第三控制端 SC3提供的第三控制信号S 3(即发光控制信号)为高电平信号，从而数据写入晶体管T2、压降补偿晶体管T6、第一控制晶体管T7和第二控制晶体管T5均处于截止状态。第一偏置电压端VB1输出第一偏置电压信号V init1，且第一偏置电压信号V init1小于阈值补偿晶体管T3的阈值电压V th2和数据信号V data之和，从而阈值补偿晶体管T3处于导通状态。第一偏置电压信号V init1经由第一偏置晶体管T4传输至驱动晶体管T1的栅极，从而驱动晶体管T1的栅极的电压被重置为第一偏置电压信号V init1。第二偏置电压端VB2(即复位电压端VR)可以输出第二偏置电压信号V init2，且第二偏置电压信号V init2经由第二偏置晶体管T8传输至驱动晶体管T1的第一极，从而驱动晶体管T1的第一极的电压被重置为第二偏置电压信号V init2。此时，驱动晶体管T1可以处于导通状态。
例如，在图8A所示的示例中，在复位阶段RT，驱动晶体管T1处于导通状态。但不限于此，在复位阶段RT，驱动晶体管T1也可以处于截止状态。第一偏置电压信号V init1和第二偏置电压信号V init2例如可以相同，在这种情况下，驱动晶体管T1处于截止状态。
例如，如图2、图7和图8B所示，在数据写入阶段DT，第一控制信号S 1变为高电平信号，第二控制信号S 2变为低电平信号，第三控制信号S 3保持为高电平信号。此时，第一偏置晶体管T4、第二偏置晶体管T8、第一控制晶体管T7和第二控制晶体管T5均处于截止状态，驱动晶体管T1、数据写入晶体管T2、压降补偿晶体管T6和阈值补偿晶体管T3均导通。由此，数据信号V data经由数据写入晶体管T2和阈值补偿晶体管T3对存储电容Cst的第二端充电，一直充电至存储电容Cst的第二端的电压为V data+V th2为止，V th2为阈值补偿晶体管T3的阈值电压V th2，阈值补偿晶体管T3的阈值电压V th2与驱动晶体管T1的阈值电压V th1相同，即存储电容Cst的第二端的电压可以为V data+V th1。此时，驱动晶体管T1的栅极的电压变为V data+V th1。参考电压信号V ref经由压降补偿晶体管T6对存储电容Cst的第一端进行充电，即存储电容Cst的第一端的电压可以为参考电压信号V ref，此时，驱动晶体管T1的第一极的电压变为V ref。
例如，如图2、图7和图8C所示，在发光阶段LT，第一控制信号S 1保持高电平信号，第二控制信号S 2变为高电平信号，第三控制信号S 3变为低电平信号。此时，第一偏置晶体管T4、第二偏置晶体管T8、数据写入晶体管T2、压降补偿晶体管T6和阈值补偿晶体管T3均处于截止状态，而驱动晶体管T1、第一控制晶体管T7和第二控制晶体管T5均导通。由此，第一电源电压端V1 输出的第一电源电压信号V dd可以经由第二控制晶体管T5传输至驱动晶体管T1的第一极，驱动晶体管T1的第一极的电压变为第一电源电压信号V dd，由于存储电容Cst的自举效应，从而驱动晶体管T1的栅极的电压变为V data+V th1+V dd-V ref。
由上分析可知，在三个阶段(复位阶段、数据写入阶段和发光阶段)中，驱动晶体管T1的栅极和第一极的电压的对应关系可以如下表格1所示。
表格1
工作阶段 驱动晶体管T1的栅极 驱动晶体管T1的第一极
RT V init1 V init2
DT V data+V th1 V ref
LT V data+V th1+V dd-V ref V dd
例如，图9A至图9C是图3所示的像素电路的在各个工作阶段的示意图。下面结合图3、图7和图9A至图9C详细说明本公开实施例提供的另一种像素电路的驱动方法的操作流程。
需要说明的是，在图9A至图9C中，在晶体管的位置处设置虚线方框表示该晶体管处于截止状态，在晶体管的位置处不设置符号则表示该晶体管处于开启状态。带箭头的实线表示信号流向。
例如，如图3、图7和图9A所示，在复位阶段RT，第一控制端SC1提供的第一控制信号S 1为低电平信号，从而第一偏置晶体管T4导通。第二控制端SC2提供的第二控制信号S 2为高电平信号，从而第二偏置晶体管T8导通，而数据写入晶体管T2和压降补偿晶体管T6处于截止状态。第三控制端SC3提供的第三控制信号S 3(即发光控制信号)为高电平信号，从而第一控制晶体管T7处于截止状态。第一偏置电压端VB1输出第一偏置电压信号V init1，且第一偏置电压信号V init1小于阈值补偿晶体管T3的阈值电压V th2和数据信号V data之和，从而阈值补偿晶体管T3处于导通状态。第一偏置电压信号V init1经由第一偏置晶体管T4传输至驱动晶体管T1的栅极，从而驱动晶体管T1的栅极的电压被重置为第一偏置电压信号V init1。第一电源电压端V1(即第二偏置电压端VB2)可以输出第一电源电压信号V dd，且第一电源电压信号V dd经由第二偏置晶体管T8传输至驱动晶体管T1的第一极，从而驱动晶体管T1的第一极 的电压被置为第一电源电压信号V dd。此时，驱动晶体管T1可以处于导通状态。
例如，第一电源电压信号V dd可以大于第一偏置电压信号V init1，且第一偏置电压信号V init1与第一电源电压信号V dd之差不大于Vgs255(最大灰阶对应的驱动晶体管T1的栅源电压差)，即V init1-V dd小于等于Vgs255。
例如，在图9A所示的示例中，在复位阶段RT，驱动晶体管T1处于导通状态。但不限于此，在复位阶段RT，驱动晶体管T1也可以处于截止状态。例如，若在复位阶段RT，V init1-V dd大于驱动晶体管T1的阈值电压V th1，此时，驱动晶体管T1处于截止状态。
例如，如图3、图7和图9B所示，在数据写入阶段DT，第一控制信号S 1变为高电平信号，第二控制信号S 2变为低电平信号，第三控制信号S 3保持为高电平信号。此时，第一偏置晶体管T4、第二偏置晶体管T8和第一控制晶体管T7均处于截止状态，驱动晶体管T1、数据写入晶体管T2、压降补偿晶体管T6和阈值补偿晶体管T3均导通。由此，数据信号V data经由数据写入晶体管T2和阈值补偿晶体管T3对存储电容Cst的第二端充电，一直充电至存储电容Cst的第二端的电压为V data+V th2为止，V th2为阈值补偿晶体管T3的阈值电压V th2，阈值补偿晶体管T3的阈值电压V th2与驱动晶体管T1的阈值电压V th1相同，即存储电容Cst的第二端的电压可以为V data+V th1。此时，驱动晶体管T1的栅极的电压变为V data+V th1。参考电压信号V ref经由压降补偿晶体管T6对存储电容Cst的第一端进行充电，即存储电容Cst的第一端的电压可以为参考电压信号V ref，此时，驱动晶体管T1的第一极的电压变为V ref。
例如，如图3、图7和图9C所示，在发光阶段LT，第一控制信号S 1保持高电平信号，第二控制信号S 2变为高电平信号，第三控制信号S 3变为低电平信号。此时，第一偏置晶体管T4、数据写入晶体管T2、压降补偿晶体管T6和阈值补偿晶体管T3均处于截止状态，而驱动晶体管T1、第一控制晶体管T7和第二偏置晶体管T8均导通。由此，第一电源电压端V1输出的第一电源电压信号V dd可以经由第二偏置晶体管T8传输至驱动晶体管T1的第一极，驱动晶体管T1的第一极的电压变为第一电源电压信号V dd，由于存储电容Cst的自举效应，从而驱动晶体管T1的栅极的电压变为V data+V th1+V dd-V ref。
由上分析可知，在三个阶段(复位阶段、数据写入阶段和发光阶段)中，驱动晶体管T1的栅极和第一极的电压的对应关系可以如下表格2所示。
表格2
工作阶段 驱动晶体管T1的栅极 驱动晶体管T1的第一极
RT V init1 V dd
DT V data+V th1 V ref
LT V data+V th1+V dd-V ref V dd
参考表格1和表格2，基于驱动晶体管T1的饱和电流公式，在发光阶段LT，流经驱动晶体管T1的发光电流I OLED可以表示为：
I OLED＝K(V GS–V th1) 2
＝K[(V data+V th1+V dd-V ref)–V dd–V th1] 2
＝K(V data-V ref) 2
上述公式中V GS为驱动晶体管T1的栅极和源极之间的电压差，V dd为第一电源电压端V1输出的第一电源电压信号，V th1是驱动晶体管T1的阈值电压。由上式中可以看到，发光电流I OLED已经不受驱动晶体管T1的阈值电压V th1和第一电源电压端V1的第一电源电压信号的影响，而只与参考电源端REF输出的参考电压信号V ref和数据信号V data有关。数据信号V data由数据信号端VD直接传输，其与驱动晶体管T1的阈值电压V th无关，这样就可以解决驱动晶体管T1由于工艺制程及长时间的操作造成阈值电压漂移的问题。参考电压信号V ref由参考电源端REF提供，其与第一电源电压端V1的IR drop无关，从而可以解决显示面板的IR drop的问题。综上所述，像素电路可以保证发光电流I OLED的准确性，消除驱动晶体管T1的阈值电压和IR drop对发光电流I OLED的影响，保证发光元件EL正常工作，提高显示画面的均匀性，提升显示效果。
例如，上述公式中K为常数，且K可以表示为：
K＝0.5μ nC ox(W/L)
其中，μ n为驱动晶体管T1的电子迁移率，C ox为驱动晶体管T1的栅极单位电容量，W为驱动晶体管T1的沟道宽，L为驱动晶体管T1的沟道长。
需要说明的是，复位阶段、数据写入阶段和发光阶段的设置方式可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
由此，本公开实施例提供的像素电路的驱动方法通过在复位阶段使驱动晶体管处于偏置状态，从而改善因磁滞效应产生的短期残像问题，提高显示均匀性和显示质量。另外，本公开实施例提供的像素电路的驱动方法还可以进行阈 值补偿操作和压降补偿操作，从而补偿驱动晶体管的阈值电压漂移和显示面板的IR drop，有效改善显示面板的显示效果，提高显示质量。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素电路，包括：发光元件、驱动电路、第一复位偏置电路和第二复位偏置电路，其中，
    所述驱动电路的控制端与数据信号端以及所述第一复位偏置电路的第二端电连接，所述驱动电路的第一端与所述第二复位偏置电路的第二端电连接，所述驱动电路的第二端与所述发光元件电连接；
    所述第一复位偏置电路的控制端与第一控制端电连接，所述第一复位偏置电路的第一端与第一偏置电压端电连接；
    所述第二复位偏置电路的控制端与偏置控制端电连接，所述第二复位偏置电路的第一端与第二偏置电压端电连接；
    所述第一复位偏置电路和所述第二复位偏置电路被配置为在复位阶段对所述驱动电路进行复位并控制所述驱动电路处于偏置状态。
  2. 根据权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述第一复位偏置电路包括第一偏置晶体管，所述第二复位偏置电路包括第二偏置晶体管，
    所述驱动电路的控制端为所述驱动晶体管的栅极，所述驱动电路的第一端为所述驱动晶体管的第一极，所述驱动电路的第二端为所述驱动晶体管的第二极，
    所述第一复位偏置电路的第一端为所述第一偏置晶体管的第一极，所述第一复位偏置电路的第二端为所述第一偏置晶体管的第二极，所述第一复位偏置电路的控制端为所述第一偏置晶体管的栅极，
    所述第二复位偏置电路的第一端为所述第二偏置晶体管的第一极，所述第二复位偏置电路的第二端为所述第二偏置晶体管的第二极，所述第二复位偏置电路的控制端为所述第二偏置晶体管的栅极。
  3. 根据权利要求2所述的像素电路，还包括：数据写入电路和存储电路，
    其中，所述数据写入电路被配置为在数据写入阶段向所述驱动晶体管的栅极写入数据信号；
    所述存储电路被配置为存储所述数据信号并将其保持在所述驱动晶体管的栅极。
  4. 根据权利要求3所述的像素电路，还包括阈值补偿电路，
    其中，所述阈值补偿电路被配置为在所述数据写入阶段向所述驱动晶体管的栅极写入阈值补偿信号。
  5. 根据权利要求4所述的像素电路，其中，所述阈值补偿电路包括阈值补偿晶体管，所述数据写入电路包括数据写入晶体管，所述存储电路包括存储电容，
    所述阈值补偿晶体管的第一极与所述数据写入晶体管的第二极电连接，所述阈值补偿晶体管的第二极和栅极彼此电连接，并电连接至所述驱动晶体管的栅极；
    所述数据写入晶体管的第一极与所述数据信号端电连接，所述数据写入晶体管的栅极与第二控制端电连接；
    所述存储电容的第一端电连接至所述驱动晶体管的第一极，所述存储电容的第二端电连接至所述驱动晶体管的栅极。
  6. 根据权利要求3或4所述的像素电路，还包括压降补偿电路，
    其中，所述压降补偿电路被配置在所述数据写入阶段向所述驱动晶体管的第一极写入参考电压信号。
  7. 根据权利要求6所述的像素电路，其中，所述压降补偿电路包括压降补偿晶体管，所述存储电路包括存储电容，
    所述压降补偿晶体管的第一极与参考电源端电连接，所述压降补偿晶体管的第二极电连接至所述驱动晶体管的第一极，所述压降补偿晶体管的栅极与第二控制端电连接；
    所述存储电容的第一端电连接至所述驱动晶体管的第一极，所述存储电容的第二端电连接至所述驱动晶体管的栅极。
  8. 根据权利要求2-7任一项所述的像素电路，还包括发光控制电路，
    其中，所述发光控制电路被配置为控制所述驱动电路驱动所述发光元件发光。
  9. 根据权利要求8所述的像素电路，其中，所述发光控制电路包括第一控制晶体管和第二控制晶体管，
    所述第一控制晶体管的第一极电连接至所述驱动晶体管的第二极，所述第一控制晶体管的第二极电连接至所述发光元件，所述第一控制晶体管的栅极与第三控制端电连接；
    所述第二控制晶体管的第一极电连接至第一电源电压端，所述第二控制晶 体管的第二极电连接至所述驱动晶体管的第一极，所述第二控制晶体管的栅极被配置接收发光控制信号。
  10. 根据权利要求9所述的像素电路，其中，所述第二控制晶体管的栅极电连接至所述第三控制端以接收所述发光控制信号，
    所述第二偏置晶体管的栅极与所述第一控制端电连接，所述第二偏置晶体管的第一极与复位电压端电连接，所述复位电压端为所述第二偏置电压端，所述第一控制端为所述偏置控制端。
  11. 根据权利要求10所述的像素电路，其中，所述第一偏置电压端输出的信号与所述第二偏置电压端输出的信号相同。
  12. 根据权利要求9所述的像素电路，其中，所述第二偏置晶体管复用为所述第二控制晶体管。
  13. 根据权利要求12所述的像素电路，其中，所述第二偏置晶体管为N型晶体管，所述第二偏置晶体管的栅极与所述第二控制端电连接，所述第一电源电压端为所述第二偏置电压端，所述第二控制端为所述偏置控制端。
  14. 一种显示面板，包括根据权利要求1-13任一所述的像素电路。
  15. 一种显示设备，包括如权利要求14所述的显示面板。
  16. 一种如权利要求1-13任一项所述的像素电路的驱动方法，包括：
    在所述复位阶段，对所述驱动电路进行复位并控制所述驱动电路处于偏置状态；
    在数据写入阶段，向所述驱动电路写入数据信号；
    在发光阶段，驱动所述发光元件发光。
  17. 根据权利要求16所述的驱动方法，其中，所述驱动电路包括驱动晶体管，所述第一复位偏置电路包括第一偏置晶体管，所述第二复位偏置电路包括第二偏置晶体管；
    对所述驱动电路进行复位并控制所述驱动电路处于偏置状态包括：
    通过所述第一偏置晶体管向所述驱动晶体管的栅极写入第一偏置电压信号；以及
    通过所述第二偏置晶体管向所述驱动晶体管的第一极写入第二偏置电压信号，
    其中，所述第一偏置电压信号和所述第二偏置电压信号之差控制所述驱动晶体管处于偏置状态。
  18. 根据权利要求17所述的驱动方法，其中，所述第一偏置电压信号和所述第二偏置电压信号相同。
  19. 根据权利要求17所述的驱动方法，其中，所述第二偏置晶体管的第一极电连接至第一电源电压端以接收第一电源电压信号，所述第一电源电压信号为所述第二偏置电压信号。
  20. 根据权利要求16-19任一项所述的驱动方法，还包括：
    在所述数据写入阶段，通过阈值补偿电路向所述驱动晶体管的栅极写入阈值补偿信号；以及
    在所述数据写入阶段，通过压降补偿电路向所述驱动晶体管的第一极写入参考电压信号。
PCT/CN2018/102261 2017-12-06 2018-08-24 像素电路及其驱动方法、显示面板和显示设备 WO2019109673A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110675829A (zh) * 2019-11-08 2020-01-10 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN115188309A (zh) * 2022-06-29 2022-10-14 武汉天马微电子有限公司 显示面板及显示装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110197638A (zh) * 2019-06-28 2019-09-03 上海天马有机发光显示技术有限公司 一种显示面板、显示装置和显示面板的驱动方法
TWI697884B (zh) * 2019-08-20 2020-07-01 友達光電股份有限公司 畫素電路
CN111883064B (zh) * 2020-08-12 2022-04-22 合肥京东方显示技术有限公司 像素驱动电路及其驱动方法、显示面板与显示装置
CN113421511B (zh) * 2021-06-17 2022-05-03 昆山国显光电有限公司 显示面板的驱动方法、驱动装置及显示装置
CN113327555B (zh) * 2021-06-25 2023-04-18 合肥京东方卓印科技有限公司 像素电路、显示面板和控制方法
EP4300474A4 (en) * 2021-07-30 2024-02-28 Boe Technology Group Co Ltd PIXEL CIRCUIT, CONTROL METHOD AND DISPLAY DEVICE
CN114582289B (zh) * 2022-04-21 2023-07-28 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779385A (zh) * 2012-10-19 2014-05-07 株式会社日本显示器 显示装置
US20160180775A1 (en) * 2014-12-18 2016-06-23 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN107331345A (zh) * 2017-07-25 2017-11-07 武汉华星光电半导体显示技术有限公司 一种像素补偿电路及显示装置
CN107863072A (zh) * 2017-12-14 2018-03-30 京东方科技集团股份有限公司 显示装置、阵列基板、像素电路及其驱动方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160038150A (ko) * 2014-09-29 2016-04-07 삼성디스플레이 주식회사 표시장치
CN105096831B (zh) 2015-08-21 2018-03-27 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN106940983A (zh) 2017-05-11 2017-07-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN116030764A (zh) 2017-08-25 2023-04-28 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779385A (zh) * 2012-10-19 2014-05-07 株式会社日本显示器 显示装置
US20160180775A1 (en) * 2014-12-18 2016-06-23 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN107331345A (zh) * 2017-07-25 2017-11-07 武汉华星光电半导体显示技术有限公司 一种像素补偿电路及显示装置
CN107863072A (zh) * 2017-12-14 2018-03-30 京东方科技集团股份有限公司 显示装置、阵列基板、像素电路及其驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3723075A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110675829A (zh) * 2019-11-08 2020-01-10 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN110675829B (zh) * 2019-11-08 2021-03-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN115188309A (zh) * 2022-06-29 2022-10-14 武汉天马微电子有限公司 显示面板及显示装置

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