WO2020052287A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020052287A1
WO2020052287A1 PCT/CN2019/090148 CN2019090148W WO2020052287A1 WO 2020052287 A1 WO2020052287 A1 WO 2020052287A1 CN 2019090148 W CN2019090148 W CN 2019090148W WO 2020052287 A1 WO2020052287 A1 WO 2020052287A1
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Prior art keywords
transistor
control
compensation
pole
terminal
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PCT/CN2019/090148
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English (en)
French (fr)
Inventor
李全虎
刁永富
王文康
杨中流
杨明警
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/630,305 priority Critical patent/US11189228B2/en
Priority to JP2020560968A priority patent/JP2021536026A/ja
Priority to EP19831582.2A priority patent/EP3852095B1/en
Publication of WO2020052287A1 publication Critical patent/WO2020052287A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display device.
  • OLED display panels have the characteristics of self-luminous, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide temperature range, simple manufacturing, etc. Development prospects. With the rapid development of OLED display panels, OLED display panels need to have the characteristics of high resolution and high refresh rate.
  • a pixel circuit including a storage circuit, a data writing circuit, a light emitting driving circuit, and a compensation circuit.
  • the data writing circuit is connected to the storage circuit and is configured to scan a control signal. Writes a data voltage to the storage circuit under the control of; the storage circuit is configured to store the data voltage and make the stored data voltage available to the compensation circuit for a compensation operation; the compensation circuit and the light emitting driver It is connected to a circuit, and is configured to maintain a compensation voltage based on the stored data voltage at a control end of the light-emitting driving circuit under the control of a compensation control signal; the light-emitting driving circuit is also connected to a light-emitting element and is configured In order to drive the light emitting element to emit light under the control of the compensation voltage.
  • the storage circuit includes a first capacitor, a first terminal of the first capacitor is connected to a first power source terminal, and a second terminal of the first capacitor is connected to The data writing circuit.
  • the light-emitting driving circuit includes a driving transistor, a control terminal of the light-emitting driving circuit includes a control electrode of the driving transistor, and a first electrode of the driving transistor is connected to The data writing circuit and the second terminal of the first capacitor, the second pole and the control pole of the driving transistor are both connected to the compensation circuit.
  • the data writing circuit includes a data writing transistor, a first pole of the data writing transistor is configured to receive the data voltage, and the data writing The second pole of the transistor is connected to the second terminal of the first capacitor and the first pole of the driving transistor, and the control pole of the data writing transistor is configured to receive the scan control signal.
  • the compensation circuit includes a compensation transistor and a second capacitor, a first pole of the compensation transistor is connected to a second pole of the driving transistor, and A second electrode is connected to a control electrode of the driving transistor, and a control electrode of the compensation transistor is configured to receive the compensation control signal; a first terminal of the second capacitor is connected to a second power source terminal, and the second The second end of the capacitor is connected to the control electrode of the driving transistor; the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.
  • the pixel circuit provided by some embodiments of the present disclosure further includes a light emission control circuit, which is respectively connected to the light emission driving circuit and the light emitting element, and is configured to control the light emission control signal under the control of the light emission control signal.
  • a light emitting driving circuit drives the light emitting element to emit light.
  • the light emission control circuit includes a first light emission control transistor, the light emission control signal includes a first light emission control sub-signal, and a first pole of the first light emission control transistor.
  • the second pole of the first light emitting control transistor Connected to the second power terminal, the second pole of the first light emitting control transistor is connected to the first pole of the driving transistor, and the control pole of the first light emitting control transistor is configured to receive the first light emitting Control subsignal.
  • a first voltage signal output from the first power supply terminal is the same as a second voltage signal output from the second power supply terminal.
  • the light emission control circuit further includes a second light emission control transistor, the light emission control signal includes a second light emission control sub-signal, and the first of the second light emission control transistors is A second pole of the second light-emitting control transistor is connected to a first end of the light-emitting element, and a second pole of the second light-emitting control transistor is configured to receive the second pole of the driving transistor
  • the second light-emitting control sub-signal, the second terminal of the light-emitting element is connected to a third power terminal.
  • the first voltage signal output by the first power source terminal and the third voltage signal output by the third power source terminal are the same.
  • the pixel circuit provided by some embodiments of the present disclosure further includes a first reset circuit, the first reset circuit is connected to a control terminal and a reset signal terminal of the light-emitting driving circuit, and is configured to The control terminal of the light-emitting driving circuit is reset under control.
  • the pixel circuit provided by some embodiments of the present disclosure further includes a second reset circuit, the second reset circuit is connected to the first terminal and the reset signal terminal of the light emitting element, and is configured to The first end of the light emitting element is reset under control.
  • the compensation control signal and the second reset control signal are the same signal.
  • the first voltage signal output from the first power terminal and the reset signal output from the reset signal terminal are the same.
  • At least some embodiments of the present disclosure also provide a pixel circuit including: a first capacitor, a second capacitor, a driving transistor, a data writing transistor, a compensation transistor, a first light emitting control transistor, a second light emitting control transistor, and a first reset transistor.
  • a first pole of the data writing transistor is configured to receive a data voltage
  • a second pole of the data writing transistor is connected to a second terminal of the first capacitor
  • the data writing A control electrode of the transistor is configured to receive a scanning control signal
  • a first terminal of the first capacitor is connected to a first power source terminal, and the first capacitor is configured to store the data voltage written by the data writing transistor ;
  • a first pole of the driving transistor is connected to a second pole of the data writing transistor and a second terminal of the first capacitor, and a second pole of the driving transistor is connected to a first pole of the compensation transistor
  • a control electrode of the driving transistor is connected to a second electrode of the compensation transistor;
  • the control electrode of the compensation transistor is configured to receive a compensation control signal;
  • a first terminal of two capacitors is connected to the first power source terminal, a second terminal of the second capacitor is connected to a control electrode of the driving transistor;
  • a first electrode of the first light-emitting control transistor is connected to the first A power terminal, the second
  • At least some embodiments of the present disclosure also provide a driving method applied to a pixel circuit according to any one of the above, including: writing the data voltage to the storage circuit in a data writing phase; in a compensation phase, Write the compensation voltage to the compensation circuit according to the stored data voltage; and in a light emitting stage, drive the light emitting element to emit light based on the compensation voltage.
  • a duration of the data writing phase is shorter than a duration of the compensation phase.
  • At least some embodiments of the present disclosure also provide a display device including the pixel circuit according to any one of the above.
  • the light emitting element according to any one of the above is included, and the pixel circuit is configured to drive the light emitting element to emit light.
  • FIG. 1 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 2A is a structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • 2B is a schematic structural diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic flowchart of a driving method of a pixel circuit provided by some embodiments of the present disclosure
  • 4A is a schematic structural diagram of a pixel circuit
  • 4B is a timing diagram of a driving method of the pixel circuit shown in FIG. 4A;
  • FIG. 5 is an exemplary timing diagram of a driving method of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 6 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device, which temporarily store a data voltage through a storage circuit, so that a compensation operation can be performed after the data writing stage, and a compensation time is extended to achieve a purpose of full compensation.
  • To achieve compensation time has nothing to do with the refresh rate and resolution of the display panel, improve the uniformity of display brightness of the display panel, and improve the display effect.
  • the transistor may be divided into an N-type transistor and a P-type transistor.
  • the embodiments of the present disclosure take the transistor as a P-type transistor (for example, a low temperature polysilicon (LTPS) P-type thin film transistor) as an example
  • LTPS low temperature polysilicon
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art may also use N-type transistors (for example, N-type MOS transistors) to implement the embodiments of the present disclosure according to actual needs.
  • the function of one or more transistors is explained, however, the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art may also use N-type transistors (for example, N-type MOS transistors) to implement the embodiments of the present disclosure according to actual needs.
  • the function of one or more transistors are not limited to P-type transistors, and those skilled in the art may also use N-type transistors (for example, N-type MO
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of a transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain of the transistor.
  • one of the first pole and the other of the second pole are directly described. The first and second poles are interchangeable as needed.
  • FIG. 1 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 2A is a structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the pixel circuit 100 may include a storage circuit 11, a data writing circuit 12, a light emitting driving circuit 13, and a compensation circuit 14.
  • the data writing circuit 12 is connected to the storage circuit 11 and the light emitting driving circuit 13 respectively, and is configured to write a data voltage to the storage circuit 11 under the control of a scan control signal.
  • the storage circuit 11 is connected to the light-emitting driving circuit 13 and is also connected to the compensation circuit 14 via the light-emitting driving circuit 13 so that the storage circuit 11 is configured to store a data voltage and make the stored data voltage available to the compensation circuit 14 for a compensation operation.
  • the compensation circuit 14 is connected to the light-emitting driving circuit 13 and is configured to keep the compensation voltage based on the stored data voltage at the control end of the light-emitting driving circuit 13 under the control of the compensation control signal, that is, the compensation circuit 14 may Under the control of the control signal, the compensation voltage is determined based on the stored data voltage, and the compensation voltage is maintained at the control terminal of the light-emitting driving circuit 13.
  • the light emitting driving circuit 13 is also connected to the light emitting element EL, and is configured to drive the light emitting element EL to emit light under the control of the compensation voltage.
  • the data voltage stored on the storage circuit 11 and the data voltage received by the data writing circuit 12 may be different.
  • the The value of the data voltage may be smaller than the value of the data voltage received by the data writing circuit 12.
  • the pixel circuit 100 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel.
  • AMOLED active matrix organic light emitting diode
  • the AMOLED display panel includes the pixel circuit 100 provided in the embodiment of the present disclosure, so that the AMOLED display panel can have characteristics such as high refresh rate, high resolution, good brightness uniformity, medium and large size, and the like.
  • the light-emitting element EL is configured to receive a light-emitting signal (for example, it may be a current signal) during operation and emit light of an intensity corresponding to the light-emitting signal.
  • the light emitting element EL may be a light emitting diode, and the light emitting diode may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), but embodiments of the present disclosure are not limited thereto.
  • the light-emitting element EL may, for example, use different light-emitting materials to emit light of different colors, thereby performing color light emission.
  • the memory circuit 11 includes a first capacitor C1.
  • the first terminal of the first capacitor C1 is connected to the first power terminal V1
  • the second terminal of the first capacitor C1 is connected to the first node S
  • the data writing circuit 12 is also connected to the first node S, that is, the first The second terminal of the capacitor C1 is connected to the data writing circuit 12.
  • the first power terminal V1 is a DC reference voltage terminal to output a constant DC reference voltage.
  • the first power terminal V1 may be a high-voltage terminal or a low-voltage terminal, as long as it can provide a constant DC reference voltage, which is not limited in the present disclosure.
  • the first power terminal V1 may be grounded.
  • the light-emitting driving circuit 13 includes a driving transistor M1, and the control terminal of the light-emitting driving circuit 13 includes a control electrode of the driving transistor M1.
  • the first pole of the driving transistor M1 is connected to the first node S, that is, the first pole of the driving transistor M1 is connected to the data writing circuit 12 and the second terminal of the first capacitor C1.
  • the second pole and the control pole of the driving transistor M1 are both Connected to the compensation circuit 14.
  • the second electrode of the driving transistor M1 is connected to the second node D, and the control electrode of the driving transistor M1 is connected to the third node G.
  • the driving transistor M1 is a P-type transistor, and the first electrode source of the driving transistor M1 and the second electrode drain of the driving transistor M1 are described below as an example, but the embodiments of the present disclosure are not limited thereto.
  • the data writing circuit 12 includes a data writing transistor M2.
  • the first pole of the data writing transistor M2 is configured to receive the data voltage V data1
  • the second pole of the data writing transistor M2 is connected to the first node S, that is, the second pole of the data writing transistor M2 is connected to the first capacitor C1
  • the second terminal and the first pole of the driving transistor M1, and the control pole of the data writing transistor M2 are configured to receive the scanning control signal VG1.
  • the first pole of the data writing transistor M2 is connected to the data line DA to receive the data voltage V data1 ;
  • the control pole of the data writing transistor M2 is connected to the gate line G1 to receive the scan control signal VG1.
  • the compensation circuit 14 may include a compensation transistor M4 and a second capacitor C2.
  • the first pole of the compensation transistor M4 is connected to the second node D, that is, the first pole of the compensation transistor M4 is connected to the second pole of the driving transistor M1, and the second pole of the compensation transistor M4 is connected to the third node G, which is the compensation transistor M4.
  • the second pole of is connected to the control pole of the driving transistor M1, and the control pole of the compensation transistor M4 is configured to receive the compensation control signal VG2.
  • the control pole of the compensation transistor M4 is configured to be connected to the compensation control signal line G2 to receive the compensation control signal.
  • the first terminal of the second capacitor C2 is connected to the second power terminal V2, and the second terminal of the second capacitor C2 is connected to the third node G, that is, the second terminal of the second capacitor C2 is connected to the control electrode of the driving transistor M1.
  • the capacitance value of the first capacitor C1 is larger than the capacitance value of the second capacitor C2, so as to ensure that the voltage of the first node S decreases less during the compensation process.
  • the capacitance of the first capacitor C1 may be multiples of the capacitance of the second capacitor C2, such as 50 to 1000 times, and for example 200 to 500 times, so that the capacitance of the first capacitor C1 is much larger than that of the second capacitor C2. Capacitance.
  • the scan control signal VG1 and the compensation control signal VG2 are different, so that the data writing transistor M2 and the compensation transistor M4 can be controlled separately.
  • the effective time of the scan control signal VG1 is shorter than the effective time of the compensation control signal VG2, that is, the time that the data writing transistor M2 is in the on state is shorter than the time that the compensation transistor M4 is in the on state.
  • the compensation control signal VG2 may be any signal that is valid for a period of time when the data writing transistor M2 is on and a period of time after the data writing transistor M2 is turned off.
  • the second power terminal V2 may also be a DC voltage terminal to output a constant DC voltage.
  • the second power terminal V2 may be a high-voltage terminal.
  • the first voltage signal output from the first power terminal V1 and the second voltage signal output from the second power terminal V2 may be the same.
  • the first power supply terminal V1 and the second power supply terminal V2 are the same power supply terminal to save the number of power supply terminals in the pixel circuit and save production costs.
  • first voltage signal output from the first power supply terminal V1 and the second voltage signal output from the second power supply terminal V2 may also be different, which is not limited in the present disclosure.
  • the gate of the data writing transistor M2 may receive an effective scan control signal VG1 (for example, a low-level signal), so that the data writing transistor M2 is turned on.
  • the control electrode of the compensation transistor M4 can receive an effective compensation control signal VG2 (for example, a low-level signal), so that the compensation transistor M4 is turned on. Since the data writing transistor M2 is turned on, the data voltage V data1 can be written into the first capacitor C1 via the data writing transistor M2. Since the compensation transistor M4 is also turned on, the control electrode of the driving transistor M1 and the second electrode are electrically connected, so that the driving transistor M1 is in a diode connection state and is in a saturated state. The data voltage V data1 can be written into the second capacitor C2 via the driving transistor M1 and the compensation transistor M4 in this order.
  • the scan control signal VG1 becomes an invalid signal (for example, a high-level signal), that is, the data writing transistor M2 is turned off, and the compensation control signal VG2 is still a valid signal (that is, the compensation control signal VG2 is still low). Level signal), so that the compensation transistor M4 remains on. Since the first capacitor C1 can store the stored data voltage V data2 , at this time, the voltage at the first node S is still the stored data voltage V data2 . Therefore, the stored data voltage V data2 can still pass through the driving transistor M1 in order. The compensation transistor M4 is written into the second capacitor C2 to implement the compensation process.
  • a high-level signal for example, the data writing transistor M2 is turned off
  • the compensation control signal VG2 is still a valid signal (that is, the compensation control signal VG2 is still low).
  • Level signal so that the compensation transistor M4 remains on. Since the first capacitor C1 can store the stored data voltage V data2 , at this time, the voltage at the first node S is still the stored
  • the voltage of the first node S is reduced during the compensation process. Therefore, at the end of the compensation phase, the The voltage is substantially the same as the stored data voltage V data2 . That is, at the end of the compensation phase, the voltage of the first node S is about the stored data voltage V data2 , and the voltage of the third node G is about V data2 + Vth.
  • the compensation voltage is the voltage at the third node G at the end of the compensation phase, that is, the compensation voltage is V data2 + Vth.
  • V data1 V data2 .
  • the second capacitor C2 can store the data voltage V data1 , under the control of the compensation control signal VG2, the time during which the compensation transistor M3 is turned on can be extended, thereby extending the compensation time to To achieve the purpose of full compensation.
  • the scanning control signal VG1 and the compensation control signal VG2 are two independent signals, and the compensation process has nothing to do with the data writing process, that is, the compensation time has nothing to do with the refresh rate and resolution of the display panel.
  • the pixel circuit 100 further includes a light emission control circuit 15.
  • the light emitting control circuit 15 is connected to the light emitting driving circuit 13 and the light emitting element EL, respectively, and is configured to be turned on or off under the control of the light emitting control signal, thereby controlling whether a current drives the light emitting element EL to emit light through the light emitting driving circuit 13.
  • the light emission control circuit 15 may include a first light emission control transistor M6.
  • the first light emitting control transistor M6 is provided between the second power supply terminal V2 and the light emitting driving circuit 13 and is configured to control the connection between the second power supply terminal V2 and the light emitting driving circuit 13 to be turned on or off.
  • the light emission control signal includes a first light emission control sub-signal V EM1 .
  • the first pole of the first light emitting control transistor M6 is connected to the second power terminal V2, and the second pole of the first light emitting control transistor M6 is connected to the first pole of the driving transistor M1 (that is, the first node S).
  • the control electrode of the first light emission control transistor M6 is configured to receive the first light emission control sub-signal V EM1 .
  • the control electrode of the first light emission control transistor M6 is configured to be connected to the first light emission control signal line EM1 to receive the first light emission. Control sub-signal V EM1 .
  • the first pole of the first light-emitting control transistor M6 may be connected to a separate power source terminal (the second power-source terminal V2), that is, the first of the first light-emitting control transistor M6.
  • the first terminal of the electrode and the second capacitor C2 are respectively connected to different power terminals.
  • the first pole of the first light-emitting control transistor M6 may also be connected to the first power terminal V1, that is, the first pole of the first light-emitting control transistor M6 and the first terminal of the second capacitor C2. Both are connected to the same first power terminal V1.
  • the light emission control circuit 15 may further include a second light emission control transistor M7.
  • the second light emitting control transistor M7 is provided between the light emitting driving circuit 13 and the light emitting element EL, and is configured to control the connection between the light emitting driving circuit 13 and the light emitting element EL to be turned on or off.
  • the light emission control signal further includes a second light emission control sub-signal V EM2 .
  • the first pole of the second light-emitting control transistor M7 is connected to the second pole of the driving transistor M1 (ie, the second node D), and the second pole of the second light-emitting control transistor M7 is connected to the first pole of the light-emitting element EL.
  • the control electrode of the second light-emitting control transistor M7 is configured to receive the second light-emitting control sub-signal V EM2 .
  • control electrode of the second light-emitting control transistor M7 is configured to be connected to the second light-emitting control signal line EM2 to receive the first Two light emission control sub-signals V EM2 .
  • the second terminal of the light emitting element EL is connected to a third power supply terminal V3.
  • the first end of the light emitting element EL may be an anode, and the second end of the light emitting element EL may be a cathode.
  • the first emission control sub-signal V EM1 provided by the first emission control signal line EM1 and the second emission control sub-signal V EM2 provided by the second emission control signal line EM2 may be the same.
  • control electrode of the first light emission control transistor M6 and the control electrode of the second light emission control transistor M7 may be connected to different light emission control signal lines to receive different light emission control signals.
  • control electrode of the first light-emitting control transistor M6 and the control electrode of the second light-emitting control transistor M7 may also be electrically connected to the same light-emitting control signal line, such as the first light-emitting control signal line EM1, to receive the same A light-emitting control sub-signal V EM1 . This disclosure does not limit this.
  • the third power supply terminal V3 may also be a DC voltage terminal to output a constant DC voltage.
  • the third power terminal V3 may be a low-voltage terminal.
  • the third power terminal V3 may also be grounded.
  • the first voltage signal output from the first power terminal V1 and the third voltage signal output from the third power terminal V3 may be the same, that is, the first power terminal V1 and the third power terminal V3 may be the same power terminal, In order to save the number of power terminals in the pixel circuit and save production costs.
  • the pixel circuit 100 may further include a first reset circuit 16.
  • the first reset circuit 16 is connected to the control terminal and the reset signal terminal VINT of the light emitting driving circuit 13 and is configured to reset the control terminal of the light emitting driving circuit 13 under the control of the first reset control signal VRT1.
  • the first reset circuit 16 may include a first reset transistor M3.
  • a first pole of the first reset transistor M3 is connected to a reset signal terminal VINT to receive a reset signal.
  • the electrode is connected to the control terminal (ie, the third node G) of the light-emitting driving circuit 13, and the control electrode of the first reset transistor M3 is configured to be connected to the first reset control signal line RT1 to receive the first reset control signal VRT1.
  • the pixel circuit 100 may further include a second reset circuit 17.
  • the second reset circuit 17 is connected to the first terminal of the light emitting element EL and the reset signal terminal VINT, and is configured to reset the first terminal of the light emitting element EL under the control of the second reset control signal VRT2.
  • the second reset circuit 17 includes a second reset transistor M5.
  • a first pole of the second reset transistor M5 is connected to a reset signal terminal VINT to receive a reset signal.
  • a second pole of the second reset transistor M5 Connected to the first end of the light emitting element EL, the control electrode of the second reset transistor M5 is configured to be connected to the second reset control signal line RT2 to receive the second reset control signal VRT2.
  • the compensation control signal VG2 may be a separate and adjustable-width signal, but is not limited thereto.
  • the compensation control signal VG2 may also use other control signals in the pixel circuit 100. Since the reset phase and the compensation phase do not conflict, the second reset control signal VRT2 can be used as the compensation control signal VG2, that is, the compensation control signal G2 and the second reset control signal VRT2 can be the same signal, and the second reset control signal VRT2 is multiplexed into a compensation control signal VG2.
  • the control electrode of the second reset transistor M5 and the control transistor of the compensation transistor M4 are both configured to be connected to the second reset control signal line RT2 to receive the second reset control signal VRT2. Therefore, the pixel circuit may not be provided with a compensation control signal line G2 to save the number of signal lines.
  • the first voltage signal output from the first power terminal V1 and the reset signal output from the reset signal terminal VINT are the same, that is, the first power terminal V1 and the reset signal terminal VINT may be the same power terminal.
  • the first pole of the first reset transistor M3 and the first pole of the second reset transistor M5 are both connected to the same reset signal terminal VINT, but it is not limited to this, the first reset transistor M3
  • the first pole and the first pole of the second reset transistor M5 can also be connected to different reset signal terminals, as long as the first reset transistor M3 and the second reset transistor M5 can respectively implement corresponding reset functions. No restrictions.
  • the pixel circuit 100 can also compensate the IR drop on the power line.
  • the specific structures of circuits such as the data writing circuit 12, the compensation circuit 14, the light emitting control circuit 15, the first reset circuit 16, and the second reset circuit 17 can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure. .
  • FIG. 2B is a schematic structural diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • another pixel circuit 100 includes a first capacitor C1, a second capacitor C2, a driving transistor M1, a data writing transistor M2, a compensation transistor M4, and a first light emitting control transistor.
  • M6 a second light emission control transistor M7, a first reset transistor M3, and a second reset transistor M5.
  • the first pole of the data writing transistor M2 is configured to receive the data voltage Vdata1
  • the second pole of the data writing transistor M2 is connected to the second terminal of the first capacitor C1
  • the control electrode of M2 is configured to be connected to the gate line G1 to receive the scanning control signal VG1.
  • the first terminal of the first capacitor C1 is connected to the first power terminal V1, and thus the first capacitor C1 is configured as a stored data voltage V data2 written by the stored data writing transistor M2.
  • the first pole of the driving transistor M1 is connected to the second pole of the data writing transistor M2 and the second terminal of the first capacitor C1, and the second pole of the driving transistor M1 is connected to the first pole of the compensation transistor M4.
  • One pole, the control pole of the driving transistor M1 is connected to the second pole of the compensation transistor M4.
  • the control electrode of the compensation transistor M4 is configured to be connected to the compensation control signal line G2 to receive the compensation control signal VG2.
  • the first terminal of the second capacitor C2 is connected to the first power terminal V1
  • the second terminal of the second capacitor C2 is connected to the control electrode of the driving transistor M1.
  • the first pole of the first light-emitting control transistor M6 is connected to the first power terminal V1
  • the second pole of the first light-emitting control transistor M6 is connected to the first pole of the driving transistor M1
  • the first light-emitting control The control electrode of the transistor M6 is configured to be connected to the first light emission control signal line EM1 to receive the first light emission control sub-signal V EM1
  • the first electrode of the second light emission control transistor M7 is connected to the second electrode of the driving transistor M1
  • the second The second pole of the light emitting control transistor M7 is connected to the first end of the light emitting element EL
  • the control pole of the second light emitting control transistor M7 is configured to be connected to the first light emitting control signal line EM1 to receive the first light emitting control sub-signal V EM1
  • the second terminal of the light emitting element EL is connected to a third power supply terminal V3.
  • the first pole of the first reset transistor M3 is connected to the reset signal terminal VINT
  • the second pole of the first reset transistor M3 is connected to the control pole of the driving transistor M1
  • the control pole of the first reset transistor M3 Is configured to be connected to the first reset control signal line RT1 to receive the first reset control signal VRT1
  • the first pole of the second reset transistor M5 is connected to the reset signal terminal VINT
  • the second pole of the second reset transistor M5 is connected to the light emitting element EL
  • the first terminal of the second reset transistor M5 is configured to be connected to the second reset control signal line RT2 to receive the second reset control signal VRT2.
  • the light-emitting element EL the first capacitor C1, the second capacitor C2, the driving transistor M1, the data writing transistor M2, the compensation transistor M4, the first light-emitting control transistor M6, the second light-emitting control transistor M7, and the first
  • the reset transistor M3, the second reset transistor M5, and the like reference may be made to related descriptions in the pixel circuit of the embodiment shown in FIG. 2A, and details are not described herein again.
  • FIG. 3 is a schematic flowchart of a driving method of a pixel circuit provided by some embodiments of the present disclosure. As shown in FIG. 3, the driving method may include:
  • Step S101 In the data writing stage, write a data voltage to the storage circuit
  • Step S102 In the compensation phase, write a compensation voltage to the compensation circuit according to the stored data voltage
  • Step S103 In the light emitting phase, the light emitting element is driven to emit light based on the compensation voltage.
  • the driving method provided in the embodiment of the present disclosure writes a data voltage into a storage circuit during a data writing stage, so that during a compensation stage after the data writing stage, a compensation operation can still be performed based on the stored data voltage on the storage circuit, and the compensation time is extended.
  • to achieve compensation time has nothing to do with the refresh rate and resolution of the display panel, improve the uniformity of display brightness of the display panel, and improve the display effect.
  • the driving method may further include: resetting a control terminal of the light-emitting driving circuit in a first reset phase; and resetting a first terminal of the light-emitting element in a second reset phase.
  • timing diagram of the pixel circuit can be set according to actual requirements, which is not specifically limited in the embodiments of the present disclosure.
  • FIG. 4A is a schematic structural diagram of a pixel circuit
  • FIG. 4B is a timing diagram of a driving method of the pixel circuit shown in FIG. 4A
  • FIG. 5 is an exemplary timing diagram of a driving method of a pixel circuit provided by some embodiments of the present disclosure. .
  • a 7TIC pixel circuit 200 may include a data writing transistor M2 ', a driving transistor M1', a compensation transistor M4 ', a second capacitor C2', a first reset transistor M3 ', and a second reset The transistor M5 ', the first light emission control transistor M6', and the second light emission control transistor M7 '.
  • the pixel circuit 200 is used to drive the light-emitting element EL ′ to emit light.
  • the first reset control signal VRT1 provided by the first reset control signal line RT1 is a low-level signal (that is, an effective signal)
  • the scan control signal line G3 provides The scanning control signal VG3, the second reset control signal VRT2 provided by the second reset control signal line RT2, and the light emission control signal V EM provided by the light emission control signal line EM are high-level signals, so that the first reset transistor M3 ′ turns on.
  • the data writing transistor M2 ', the driving transistor M1', the compensation transistor M4 ', the second reset transistor M5', the first light emitting control transistor M6 ', and the second light emitting control transistor M7' are turned off.
  • the reset signal output from the reset signal terminal VINT can be written into the control electrode of the driving transistor M1 'via the first reset transistor M3' to reset the control electrode of the driving transistor M1 '.
  • the voltage held on the control electrode of the driving transistor M1 ' is cleared, the voltage V G' on the control electrode of the driving transistor M1 ', and the voltage V on the first electrode of the driving transistor M1'.
  • S ' are all reset to a low level signal.
  • the scanning control signal VG3 is a low-level signal (that is, an effective signal), the first reset signal VRT1, the second reset signal VRT2, and the light emission control signal.
  • V EM and the like are all high-level signals.
  • the data writing transistor M2 ′, the driving transistor M1 ′, and the compensation transistor M4 ′ are all turned on, and the first reset transistor M3 ′, the second reset transistor M5 ′, and the first light
  • the control transistor M6 'and the second light emission control transistor M7' are both turned off.
  • the data voltage V data1 is sequentially written into the driving transistor M1 ′ via the data writing transistor M2 ′, the driving transistor M1 ′, and the compensation transistor M4 ′.
  • the voltage of the control electrode of the driving transistor M1 ′ may be V data1 + Vth ′, and Vth ′ is the threshold voltage of the driving transistor M1 ′.
  • V G ′ of the control electrode of the driving transistor M1 ′ cannot reach V data1 + Vth ′, that is, V G ′ , at the end of the data writing and compensation phase 2.
  • ⁇ V data1 + Vth ' As shown in FIG. 4B, in the driving method of the pixel circuit 200, the time of the compensation process is the same as the time when the scanning control signal VG3 is a low-level signal.
  • the second reset signal VRT2 is a low-level signal (that is, an effective signal)
  • the first reset signal VRT1, the scan control signal VG3, and the light emission control signal V EM All are high-level signals. Therefore, the second reset transistor M5 'is turned on, and the remaining transistors are turned off.
  • the reset signal output from the reset signal terminal VINT can be written into the first light-emitting element EL' via the second reset transistor M5 '. One end to reset the first end of the light-emitting element EL ′. At this time, the light-emitting element EL ′ does not emit light.
  • the light-emitting control signal V EM is a low-level signal (that is, an effective signal), the first reset signal VRT1, the scan control signal VG3, the second reset signal VRT2, and so on.
  • Is a high-level signal whereby the data writing transistor M2 ', the compensation transistor M4', the first reset transistor M3 ', and the second reset transistor M5' are all turned off, and the first light emission control transistor M6 'and the second light emission control transistor M7 'are all turned on, and the voltage V S on the first pole of the driving transistor M1' rises to a high voltage V d output from the power voltage terminal VDD.
  • the voltage V G on the control electrode of the driving transistor M1 ' can control the driving transistor M1' In a saturated state, according to the saturation current formula of the driving transistor M1 ′, the light-emitting current I 1 flowing through the driving transistor M1 ′ can be expressed as:
  • V GS is the voltage difference between the gate (ie, the control electrode) and the source (ie, the first electrode) of the driving transistor M1 ′. Since V G ' ⁇ V data1 + Vth', V G ' -V d -Vth' ⁇ V data1 -V d , the light emitted by the light-emitting element EL 'does not match the written data voltage V data1 , thereby generating a Display uneven phenomenon.
  • the first reset control signal VRT1 provided by the first reset control signal line RT1 is a low-level signal (ie, an effective signal), and the scan provided by the gate line G1 Control signal VG1, compensation control signal VG2 provided by compensation control signal line G2, second reset signal VRT2 provided by second reset control signal line RT2, first light emission control sub-signal V EM1 provided by first light control signal line EM1, and first The second light emission control sub-signals V EM2 and the like provided by the two light emission control signal lines EM2 are high-level signals, so that the first reset transistor M3 is turned on, the data write transistor M2, the drive transistor M1, the compensation transistor M4, and the second reset The transistor M5, the first light emission control transistor M6, and the second light emission control transistor M7 are all turned off.
  • a reset signal (for example, a low voltage signal) output from the reset signal terminal VINT can be written into the control electrode of the driving transistor M1 to reset the control electrode of the driving transistor M1.
  • the voltage held on the control electrode of the driving transistor M1 is cleared, the voltage V G on the control electrode of the driving transistor M1 and the voltage V S on the first electrode of the driving transistor M1 are reset. Low level signal.
  • the scan control signal VG1 and the compensation control signal VG2 may both be low-level signals (that is, valid signals).
  • the reset signal VRT1, the second reset signal VRT2, the first light-emitting control sub-signal V EM1 , the second light-emitting control sub-signal V EM2, and the like are all high-level signals.
  • the data write transistor M2, the driving transistor M1, and the compensation transistor M4 is all turned on, and the first reset transistor M3, the second reset transistor M5, the first light emission control transistor M6, and the second light emission control transistor M7 are all turned off.
  • the data voltage V data1 is written into the second terminal of the first capacitor C1 (ie, the first pole of the driving transistor M1) via the data writing transistor M2.
  • the first capacitor C1 can store the stored data voltage V data2 (ie, the data voltage V data1 ).
  • the voltage V S of the first pole of the driving transistor M1 may be a stored data voltage V data2 .
  • the compensation transistor M4 is turned on, the driving transistor M1 forms a diode connection mode, and the driving transistor M1 is also turned on, so that the data voltage V data1 can also be written into the control electrode of the driving transistor M1 via the driving transistor M1 and the compensation transistor M4 (that is, the first Three nodes G), the voltage V G of the control electrode of the driving transistor M1 gradually rises, thereby starting the compensation operation.
  • the compensation control signal VG2 remains as a low-level signal (that is, an effective signal), and the scan control signal VG1 becomes a high-level signal.
  • the first reset signal VRT1, the second reset signal VRT2, the first light-emitting control sub-signal V EM1 and the second light-emitting control sub-signal V EM2 are also maintained as high-level signals, thereby driving the transistor M1 and the compensation transistor M4 remain on, the data writing transistor M2 is turned off, and the first reset transistor M3, the second reset transistor M5, the first light-emission control transistor M6, and the second light-emission control transistor M7 also remain off. Since the stored data voltage V data2 is stored on the first capacitor C1, the stored data voltage V data2 can still be written into the second capacitor C2 via the driving transistor M1 and the compensation transistor M4 in order to continue the compensation operation.
  • the voltage V S of the first pole of the driving transistor M1 is reduced during the compensation process of the compensation stage T3, and therefore, during the compensation stage T3 At the end, the voltage V S of the first pole of the driving transistor M1 is substantially the same as the stored data voltage V data2 . That is, at the end of the compensation phase T3, the voltage V S of the first electrode of the driving transistor M1 is approximately the stored data voltage V data2 , and the voltage V G of the control electrode of the driving transistor M1 is approximately V data2 + Vth.
  • the time of the compensation process includes the time of the data writing phase T2 and the time of the compensation phase T3.
  • the time when the scan control signal VG1 is a low-level signal is the same as the time when the data voltage V data1 is provided, and the time when the compensation control signal VG2 is a low-level signal is independent of the time when the data voltage V data1 is provided. .
  • the first capacitor C1 is used to temporarily store the data voltage V data1 , so that the compensation time can be indirectly prolonged, and pixel driving with high resolution and high refresh rate can be realized with a small cost.
  • the duration of the data writing phase T2 (the first compensation phase) is shorter than the duration of the compensation phase T3 (the second compensation phase), that is, the driving method provided in the embodiment of the present disclosure can extend the compensation time. To achieve the purpose of full compensation.
  • the compensation of the threshold voltage may include a first compensation phase (data writing phase T2) and a second compensation phase (compensation phase T3).
  • the second reset signal VRT2 is a low-level signal (ie, an effective signal), the first reset signal VRT1, the scan control signal VG1, the compensation control signal VG2, The first light-emitting control sub-signal V EM1 and the second light-emitting control sub-signal V EM2 are high-level signals. Therefore, the second reset transistor M5 is turned on and the remaining transistors are turned off.
  • the reset signal output from the reset signal terminal VINT can be The first end of the light-emitting element EL is written to reset the first end of the light-emitting element EL. At this time, the light-emitting element EL does not emit light.
  • the first light-emitting control sub-signal V EM1 and the second light-emitting control sub-signal V EM2 are both low-level signals (ie, effective signals), and the scanning control signals VG1,
  • the compensation control signal VG2, the first reset signal VRT1, the second reset signal VRT2, and the like are all high-level signals.
  • the data writing transistor M2, the compensation transistor M4, the first reset transistor M3, and the second reset transistor M5 are turned off.
  • the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are both turned on, and the voltage V S on the first pole of the driving transistor M1 rises to a second voltage signal V d2 output from the second power terminal V2.
  • the voltage V G on the control electrode can control the driving transistor M1 to be in a saturated state.
  • the saturation current formula of the driving transistor M1 the light-emitting current I EL flowing through the driving transistor M1 can be expressed as:
  • I EL K * (V GS --Vth) 2
  • V GS is the voltage difference between the gate and source of the driving transistor M1
  • Vth is the threshold voltage of the driving transistor M1.
  • the pixel circuit provided in the embodiments of the present disclosure can ensure the accuracy of the light-emitting current I EL , eliminate the influence of the threshold voltage of the driving transistor M1 on the light-emitting current I EL , ensure the normal operation of the light-emitting element EL, and improve the display screen. Uniformity, improve display effect.
  • K is constant in the above formula, and K can be expressed as:
  • p is the electron mobility of the driving transistor M1
  • Cox is the gate unit capacitance of the driving transistor M1
  • W is the channel width of the driving transistor M1
  • L is the channel length of the driving transistor M1.
  • the setting modes of the first reset phase, the second reset phase, the compensation phase, the data writing phase, and the light emitting phase can be set according to actual application requirements, which is not specifically limited in the embodiments of the present disclosure.
  • FIG. 6 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 80 may include a display panel 70 for displaying an image.
  • the display panel 70 includes a plurality of pixel units, and the plurality of pixel units may be arranged in an array.
  • Each pixel unit may include the pixel circuit 100 described in any one of the above embodiments.
  • the pixel circuit 100 temporarily stores the data voltage through the storage circuit, so that the compensation operation can be performed after the data writing stage, and the compensation time is extended to achieve the purpose of full compensation.
  • the compensation time is independent of the refresh rate resolution of the display panel, and the display is improved
  • the display brightness uniformity of the panel improves the display effect.
  • each pixel unit may further include the light-emitting element according to any one of the above embodiments.
  • a pixel circuit is configured to drive a light emitting element to emit light.
  • the display panel 70 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 70 may be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 70 may also have a touch function, that is, the display panel 70 may be a touch display panel.
  • the display device 80 may further include a gate driver 82.
  • the gate driver 82 is configured to be electrically connected to a data writing circuit in a pixel circuit of a pixel unit through a gate line for supplying a scanning control signal to the data writing circuit.
  • the gate driver 82 is also configured to be electrically connected to a compensation circuit in a pixel circuit of a pixel unit through a compensation control signal line for supplying a compensation control signal to the compensation circuit.
  • the display device 80 may further include a data driver 84.
  • the data driver 84 is configured to be electrically connected to a data writing circuit in a pixel circuit of a pixel unit through a data line for supplying a data voltage to the data writing circuit.
  • the gate driver 82 and the data driver 84 may be implemented by respective application-specific integrated circuit chips, or may be directly fabricated on the display panel 70 through a semiconductor fabrication process.
  • the gate driver 82 may include a gate driver circuit of the GOA (Gate Driver On Array) type.
  • the display device 80 may be any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device 80 (such as a control device, an image data encoding / decoding device, and a clock circuit) should be understood by those of ordinary skill in the art, and will not be described in detail here. As a limitation on this disclosure.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路及其驱动方法、显示装置。像素电路(100)包括：存储电路(11)、数据写入电路(12)、发光驱动电路(13)和补偿电路(14)，数据写入电路(12)与存储电路(11)连接，且被配置为在扫描控制信号的控制下将数据电压写入存储电路(11)；存储电路(11)被配置为存储数据电压并使得存储的数据电压可用于补偿电路(14)进行补偿操作；补偿电路(14)与发光驱动电路(13)连接，且被配置为在补偿控制信号的控制下将基于存储的数据电压的补偿电压保持在发光驱动电路(13)的控制端；发光驱动电路(13)还与发光元件(EL)连接，且被配置为在补偿电压的控制下驱动发光元件(EL)发光。

Description

像素电路及其驱动方法、显示装置
本申请要求于2018年09月13日递交的中国专利申请第201811069681.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。随着OLED显示面板的高速发展，OLED显示面板需要具有高分辨率高刷新率的特性。
发明内容
本公开至少一些实施例提供一种像素电路，包括：存储电路、数据写入电路、发光驱动电路和补偿电路，所述数据写入电路与所述存储电路连接，且被配置为在扫描控制信号的控制下将数据电压写入所述存储电路；所述存储电路被配置为存储所述数据电压并使得存储的数据电压可用于所述补偿电路进行补偿操作；所述补偿电路与所述发光驱动电路连接，且被配置为在补偿控制信号的控制下将基于所述存储的数据电压的补偿电压保持在所述发光驱动电路的控制端；所述发光驱动电路还与发光元件连接，且被配置为在所述补偿电压的控制下驱动发光元件发光。
例如，在本公开一些实施例提供的像素电路中，所述存储电路包括第一电容，所述第一电容的第一端连接到第一电源端，所述第一电容的第二端连接到所述数据写入电路。
例如，在本公开一些实施例提供的像素电路中，所述发光驱动电路包括驱动晶体管，所述发光驱动电路的控制端包括所述驱动晶体管的控制极，所述驱动晶体管的第一极连接到所述数据写入电路以及所述第一电容的第二端，所述驱动晶体管的第二极和控制极均连接到所述补偿电路。
例如，在本公开一些实施例提供的像素电路中，所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入晶体管的第二极连接到所述第一电容的第二端和所述驱动晶体管的第一极，所述数据写入晶体管的控制极被配置为接收所述扫描控制信号。
例如，在本公开一些实施例提供的像素电路中，所述补偿电路包括补偿晶体管和第二电容，所述补偿晶体管的第一极连接到所述驱动晶体管的第二极，所述补偿晶体管的第二极连接到所述驱动晶体管的控制极，所述补偿晶体管的控制极被配置为接收所述补偿控制信号；所述第二电容的第一端连接到第二电源端，所述第二电容的第二端连接到所述驱动晶体管的控制极；所述第一电容的电容值大于所述第二电容的电容值。
例如，本公开一些实施例提供的像素电路还包括发光控制电路，所述发光控制电路分别与所述发光驱动电路和所述发光元件连接，且被配置为在发光控制信号的控制下控制所述发光驱动电路驱动所述发光元件发光。
例如，在本公开一些实施例提供的像素电路中，所述发光控制电路包括第一发光控制晶体管，所述发光控制信号包括第一发光控制子信号，所述第一发光控制晶体管的第一极连接至所述第二电源端，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的控制极被配置为接收所述第一发光控制子信号。
例如，在本公开一些实施例提供的像素电路中，所述第一电源端输出的第一电压信号和所述第二电源端输出的第二电压信号相同。
例如，在本公开一些实施例提供的像素电路中，所述发光控制电路还包括第二发光控制晶体管，所述发光控制信号包括第二发光控制子信号，所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端，所述第二发光控制晶体管的控制极被配置为接收所述第二发光控制子信号，所述发光元件的第二端连接至第三电源端。
例如，在本公开一些实施例提供的像素电路中，所述第一电源端输出的第一电压信号和所述第三电源端输出的第三电压信号相同。
例如，本公开一些实施例提供的像素电路还包括第一复位电路，所述第一复位电路连接至所述发光驱动电路的控制端和复位信号端，且被配置为在第一复位控制信号的控制下对所述发光驱动电路的控制端进行复位。
例如，本公开一些实施例提供的像素电路还包括第二复位电路，所述第二复位电路连接至所述发光元件的第一端和复位信号端，且被配置为在第二复位控制信号的控制下对所述发光元件的第一端进行复位。
例如，在本公开一些实施例提供的像素电路中，所述补偿控制信号和所述第二复位控制信号为同一个信号。
例如，在本公开一些实施例提供的像素电路中，所述第一电源端输出的第一电压信号和所述复位信号端输出的复位信号相同。
本公开至少一些实施例还提供一种像素电路，包括：第一电容、第二电容、驱动晶体管、数据写入晶体管、补偿晶体管、第一发光控制晶体管、第二发光控制晶体管、第一复位晶体管和第二复位晶体管，所述数据写入晶体管的第一极被配置为接收数据电压，所述数据写入晶体管的第二极连接到所述第一电容的第二端，所述数据写入晶体管的控制极被配置为接收扫描控制信号；所述第一电容的第一端连接到第一电源端，所述第一电容被配置为存储所述数据写入晶体管写入的所述数据电压；所述驱动晶体管的第一极连接到所述数据写入晶体管的第二极和所述第一电容的第二端，所述驱动晶体管的第二极连接到所述补偿晶体管的第一极，所述驱动晶体管的控制极连接到所述补偿晶体管的第二极；所述补偿晶体管的控制极被配置为接收补偿控制信号；所述第二电容的第一端连接到所述第一电源端，所述第二电容的第二端连接到所述驱动晶体管的控制极；所述第一发光控制晶体管的第一极连接至所述第一电源端，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的控制极被配置为接收第一发光控制子信号；所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端，所述第二发光控制晶体管的控制极被配置为接收所述第一发光控制子信号；所述发光元件的第二端连接至第三电源端；所述第一复位晶体管的第一极连接至复位信号端，所述第一复位晶体管的第二极连接至所述驱动晶体管的控制极，所述第一复位晶体管的控制极被配置为接收第一复位控制信号；所述第二复位晶体管的第一极连接至所述复位信号端，所述第二复位晶体管的第二极连接至所述发光元件的第一端，所述第二复位晶体管的控制极被配置为接收第二复位控制信号。
本公开至少一些实施例还提供一种应用于根据上述任一项所述的像素电路的驱动方法，包括：在数据写入阶段，向所述存储电路写入所述数据电压； 在补偿阶段，根据所述存储的数据电压，向所述补偿电路写入所述补偿电压；在发光阶段，基于所述补偿电压驱动所述发光元件发光。
例如，在本公开一些实施例提供的驱动方法中，所述数据写入阶段的持续时间短于所述补偿阶段的持续时间。
本公开至少一些实施例还提供一种显示装置，包括根据上述任一项所述的像素电路。
例如，在本公开一些实施例提供的显示装置中，包括根据上述任一项所述的发光元件，所述像素电路被配置为驱动所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种像素电路的示意性框图；
图2A为本公开一些实施例提供的一种像素电路的结构图；
图2B为本公开一些实施例提供的另一种像素电路的示意性结构图；
图3为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程图；
图4A为一种像素电路的结构示意图；
图4B为图4A所示的像素电路的驱动方法的时序图；
图5为本公开一些实施例提供的一种像素电路的驱动方法的示例性时序图；
图6为本公开一些实施例提供的一种显示装置的示意性框图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
目前，具有高刷新率的OLED显示器存在一些问题。例如，对于分辨率为2400(RGB)×1600的120HZ的电子产品(例如，笔记本电脑)，一行数据写入的时间只有5微秒左右，由于电子产品的像素电路存在较大的负载，因此像素电路中的驱动晶体管的栅极电压的上升时间较长，从而导致对像素电路的补偿不足，出现显示面板亮度不均匀的现象，进而影响显示面板的显示效果。
本公开至少一个实施例提供一种像素电路及其驱动方法、显示装置，其通过存储电路临时存储数据电压，以在数据写入阶段之后仍可以进行补偿操作，延长补偿时间，达到充分补偿的目的，实现补偿时间与显示面板的刷新率、分辨率无关，改善显示面板的显示亮度均匀性，提高显示效果。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，低温多晶硅(LTPS)P型薄膜晶体管)为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第 一极和第二极根据需要是可以互换的。
下面结合附图对本公开的几个实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种像素电路的示意性框图，图2A为本公开一些实施例提供的一种像素电路的结构图。
例如，如图1所示，本公开一些实施例提供的像素电路100可以包括存储电路11、数据写入电路12、发光驱动电路13和补偿电路14。例如，数据写入电路12分别与存储电路11和发光驱动电路13连接，且被配置为在扫描控制信号的控制下将数据电压写入存储电路11。存储电路11与发光驱动电路13连接，且还经由发光驱动电路13与补偿电路14连接，从而存储电路11被配置为存储数据电压并使得存储的数据电压可用于补偿电路14进行补偿操作。补偿电路14与发光驱动电路13连接，且被配置为在补偿控制信号的控制下将基于存储的数据电压的补偿电压保持在发光驱动电路13的控制端，也就是说，补偿电路14可以在补偿控制信号的控制下将基于存储的数据电压确定补偿电压，并将补偿电压保持在发光驱动电路13的控制端。发光驱动电路13还与发光元件EL连接，且被配置为在补偿电压的控制下驱动发光元件EL发光。
例如，在存储电路11上的存储的数据电压与数据写入电路12接收的数据电压可以不相同，例如，由于传输过程中信号线上的压降等因素的影响，存储电路11上的存储的数据电压的值可以小于数据写入电路12接收到的数据电压的值。
例如，像素电路100可应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。AMOLED显示面板包括本公开实施例提供的像素电路100，从而该AMOLED显示面板可以具有高刷新率、高分辨率、亮度均匀性好、中大型尺寸等特点。
例如，发光元件EL被配置为在工作时接收发光信号(例如，可以为电流信号)，并发出与该发光信号相对应强度的光。发光元件EL可以为发光二极管，发光二极管例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等，但本公开的实施例不限于此。发光元件EL例如可以采用不同的发光材料，以发出不同颜色的光，从而进行彩色发光。
例如，如图2A所示，存储电路11包括第一电容C1。第一电容C1的第一端连接到第一电源端V1，第一电容C1的第二端连接到第一节点S，数据写入 电路12也连接到第一节点S，也就是说，第一电容C1的第二端连接到数据写入电路12。
例如，第一电源端V1为直流参考电压端，以输出恒定的直流参考电压。第一电源端V1可以为高压端，也可以为低压端，只要其能够提供恒定的直流参考电压即可，本公开对此不作限制。例如，在一些示例中，第一电源端V1可以接地。
例如，如图2A所示，发光驱动电路13包括驱动晶体管M1，发光驱动电路13的控制端包括驱动晶体管M1的控制极。驱动晶体管M1的第一极连接到第一节点S，即驱动晶体管M1的第一极连接到数据写入电路12以及第一电容C1的第二端，驱动晶体管M1的第二极和控制极均连接到补偿电路14。如图2A所示，驱动晶体管M1的第二极连接到第二节点D，驱动晶体管M1的控制极连接到第三节点G。
例如，驱动晶体管M1为P型晶体管，且驱动晶体管M1的第一极为源极，驱动晶体管M1的第二极为漏极，下面以此为例进行说明，但本公开的实施例并不限于此。
例如，如图2A所示，数据写入电路12包括数据写入晶体管M2。数据写入晶体管M2的第一极被配置为接收数据电压V data1，数据写入晶体管M2的第二极连接到第一节点S，即数据写入晶体管M2的第二极连接到第一电容C1的第二端和驱动晶体管M1的第一极，数据写入晶体管M2的控制极被配置为接收扫描控制信号VG1。例如，数据写入晶体管M2的第一极连接至数据线DA，以接收数据电压V data1；数据写入晶体管M2的控制极连接至栅线G1，以接收扫描控制信号VG1。
例如，如图2A所示，补偿电路14可以包括补偿晶体管M4和第二电容C2。补偿晶体管M4的第一极连接到第二节点D，即补偿晶体管M4的第一极连接到驱动晶体管M1的第二极，补偿晶体管M4的第二极连接到第三节点G，即补偿晶体管M4的第二极连接到驱动晶体管M1的控制极，补偿晶体管M4的控制极被配置为接收补偿控制信号VG2，例如，补偿晶体管M4的控制极被配置为连接补偿控制信号线G2以接收补偿控制信号VG2。第二电容C2的第一端连接到第二电源端V2，第二电容C2的第二端连接到第三节点G，即第二电容C2的第二端连接到驱动晶体管M1的控制极。
例如，第一电容C1的电容值大于第二电容C2的电容值，以保证第一节 点S的电压在补偿过程中的减少量较小。例如，第一电容C1的电容值可以为第二电容C2的电容值的多倍，例如50～1000倍，又例如200～500倍，从而第一电容C1的电容值远大于第二电容C2的电容值。
例如，扫描控制信号VG1和补偿控制信号VG2不相同，从而使得数据写入晶体管M2和补偿晶体管M4可以被分开单独控制。例如，扫描控制信号VG1的有效时间短于补偿控制信号VG2的有效时间，也就是说，数据写入晶体管M2处于开启状态的时间短于补偿晶体管M4处于开启状态的时间。例如，补偿控制信号VG2可以为任意一个信号，该信号在数据写入晶体管M2处于开启状态的时间段和数据写入晶体管M2截止之后的一段时间内均有效。
例如，第二电源端V2也可以为直流电压端，以输出恒定的直流电压。第二电源端V2可以为高压端。
例如，第一电源端V1输出的第一电压信号和第二电源端V2输出的第二电压信号可以相同。例如，第一电源端V1和第二电源端V2为同一个电源端，以节省像素电路中的电源端数量，节约生产成本。
需要说明的是，第一电源端V1输出的第一电压信号和第二电源端V2输出的第二电压信号也可以不相同，本公开对此不作限制。
例如，在数据写入阶段，数据写入晶体管M2的控制极可以接收有效的扫描控制信号VG1(例如，低电平信号)，从而数据写入晶体管M2导通。补偿晶体管M4的控制极可以接收有效的补偿控制信号VG2(例如，低电平信号)，从而补偿晶体管M4导通。由于数据写入晶体管M2导通，数据电压V data1可以经由数据写入晶体管M2被写入第一电容C1。由于补偿晶体管M4也导通，驱动晶体管M1的控制极和第二极电连接，从而驱动晶体管M1处于二极管连接状态，并且处于饱和状态。数据电压V data1可以依次经由驱动晶体管M1和补偿晶体管M4被写入第二电容C2。
例如，在补偿阶段，扫描控制信号VG1变为无效信号(例如，高电平信号)，即数据写入晶体管M2截止，而补偿控制信号VG2仍然为有效信号(即，补偿控制信号VG2仍然为低电平信号)，从而补偿晶体管M4保持导通。由于第一电容C1可以存储该存储的数据电压V data2，此时，第一节点S处的电压仍然为存储的数据电压V data2，由此，存储的数据电压V data2仍然可以依次经由驱动晶体管M1和补偿晶体管M4被写入第二电容C2，以实现补偿过程。在此补偿阶段，第一节点S的电压逐渐减低，第三节点G的电压逐渐提高，当第三节 点G和第一节点S的电压差V GS与驱动晶体管M1的阈值电压Vth相等，即V GS＝Vth时，驱动晶体管M1截止，补偿阶段结束。
例如，由于第一电容C1的电容值远大于第二电容C2的电容值，第一节点S的电压在补偿过程中的减少量较小，由此，在补偿阶段结束时，第一节点S的电压与存储的数据电压V data2基本相同。也就是说，在补偿阶段结束时，第一节点S的电压约为存储的数据电压V data2，第三节点G的电压约为V data2+Vth。例如，补偿电压为在补偿阶段结束时第三节点G处的电压，即补偿电压为V data2+Vth。需要说明的是，在不考虑传输过程中信号线上的压降等因素的影响时，可以认为存储电路11上的存储的数据电压的值等于数据写入电路12接收到的数据电压的值，即V data1＝V data2，本公开以V data1＝V data2为例详细描述本公开的实施例。
综上所述，在本公开的实施例中，由于第二电容C2可以存储数据电压V data1，在补偿控制信号VG2的控制下，可以延长补偿晶体管M3处于开启状态的时间，从而延长补偿时间以达到充分补偿的目的。另外，扫描控制信号VG1和补偿控制信号VG2为两个独立的信号，补偿过程与数据写入过程无关，也即补偿时间与显示面板的刷新率、分辨率无关。
例如，如图2A所示，像素电路100还包括发光控制电路15。发光控制电路15分别与发光驱动电路13和发光元件EL连接，且被配置为在发光控制信号的控制下导通或截止，由此控制电流是否通过发光驱动电路13驱动发光元件EL发光。
例如，如图2A所示，发光控制电路15可以包括第一发光控制晶体管M6。第一发光控制晶体管M6设置在第二电源端V2和发光驱动电路13之间，且被配置为控制将第二电源端V2和发光驱动电路13之间的连接导通或断开。
例如，发光控制信号包括第一发光控制子信号V EM1。如图2A所示，第一发光控制晶体管M6的第一极连接至第二电源端V2，第一发光控制晶体管M6的第二极连接至驱动晶体管M1的第一极(即第一节点S)，第一发光控制晶体管M6的控制极被配置为接收第一发光控制子信号V EM1，例如，第一发光控制晶体管M6的控制极被配置为连接第一发光控制信号线EM1以接收第一发光控制子信号V EM1。
需要说明的是，在图2A所示的示例中，第一发光控制晶体管M6的第一极可以与单独的一个电源端(第二电源端V2)连接，即第一发光控制晶体管 M6的第一极和第二电容C2的第一端分别连接至不同的电源端。但本公开的实施例不限于此，第一发光控制晶体管M6的第一极也可以与第一电源端V1连接，即第一发光控制晶体管M6的第一极和第二电容C2的第一端均连接相同的第一电源端V1。
例如，如图2A所示，发光控制电路15还可以包括第二发光控制晶体管M7。第二发光控制晶体管M7设置在发光驱动电路13与发光元件EL之间，且被配置为控制将发光驱动电路13与发光元件EL之间的连接导通或断开。
例如，发光控制信号还包括第二发光控制子信号V EM2。如图2A所示，第二发光控制晶体管M7的第一极连接至驱动晶体管M1的第二极(即第二节点D)，第二发光控制晶体管M7的第二极连接至发光元件EL的第一端，第二发光控制晶体管M7的控制极被配置为接收第二发光控制子信号V EM2，例如，第二发光控制晶体管M7的控制极被配置为连接第二发光控制信号线EM2以接收第二发光控制子信号V EM2。发光元件EL的第二端连接至第三电源端V3。
例如，发光元件EL的第一端可以为阳极，发光元件EL的第二端可以为阴极。
例如，第一发光控制信号线EM1提供的第一发光控制子信号V EM1和第二发光控制信号线EM2提供的第二发光控制子信号V EM2可以相同。
需要说明的是，在2A所示的示例中，第一发光控制晶体管M6的控制极和第二发光控制晶体管M7的控制极可以连接到不同的发光控制信号线，以接收不同的发光控制信号。但不限于此，第一发光控制晶体管M6的控制极和第二发光控制晶体管M7的控制极也可以电连接至相同的发光控制信号线，例如第一发光控制信号线EM1，以接收相同的第一发光控制子信号V EM1。本公开对此不作限制。
例如，第三电源端V3也可以为直流电压端，以输出恒定的直流电压。第三电源端V3可以为低压端。例如，在一些示例中，第三电源端V3也可以接地。
例如，第一电源端V1输出的第一电压信号和第三电源端V3输出的第三电压信号可以相同，也就是说，第一电源端V1和第三电源端V3可以为同一个电源端，以节省像素电路中的电源端数量，节约生产成本。
需要说明的是，第二电源端V2输出的第二电压信号和第三电源端V3输出的第三电压信号不相同。
例如，如图2A所示，像素电路100还可以包括第一复位电路16。第一复位电路16连接至发光驱动电路13的控制端和复位信号端VINT，且被配置为在第一复位控制信号VRT1的控制下对发光驱动电路13的控制端进行复位。
例如，如图2A所示，第一复位电路16可以包括第一复位晶体管M3，第一复位晶体管M3的第一极连接至复位信号端VINT，以接收复位信号，第一复位晶体管M3的第二极连接至发光驱动电路13的控制端(即第三节点G)，第一复位晶体管M3的控制极被配置为连接第一复位控制信号线RT1以接收第一复位控制信号VRT1。
例如，如图2A所示，像素电路100还可以包括第二复位电路17。第二复位电路17连接至发光元件EL的第一端和复位信号端VINT，且被配置为在第二复位控制信号VRT2的控制下对发光元件EL的第一端进行复位。
例如，如图2A所示，第二复位电路17包括第二复位晶体管M5，第二复位晶体管M5的第一极连接至复位信号端VINT，以接收复位信号，第二复位晶体管M5的第二极连接至发光元件EL的第一端，第二复位晶体管M5的控制极被配置为连接第二复位控制信号线RT2以接收第二复位控制信号VRT2。
例如，补偿控制信号VG2可以为单独的且宽度可调的信号，但不限于此，补偿控制信号VG2也可以采用该像素电路100中的其他控制信号。由于复位阶段与补偿阶段不冲突，因此可以利用第二复位控制信号VRT2充当补偿控制信号VG2，也就是说，补偿控制信号G2和第二复位控制信号VRT2可以为同一个信号，第二复位控制信号VRT2复用为补偿控制信号VG2。例如，第二复位晶体管M5的控制极和补偿晶体管M4控制极均被配置为连接第二复位控制信号线RT2以接收第二复位控制信号VRT2，由此，该像素电路可以不设置补偿控制信号线G2，以节省信号线的数量。
例如，第一电源端V1输出的第一电压信号和复位信号端VINT输出的复位信号相同，即第一电源端V1和复位信号端VINT可以为同一个电源端。
例如，在图2A所示的示例中，第一复位晶体管M3的第一极和第二复位晶体管M5的第一极均连接至同一个复位信号端VINT，但不限于此，第一复位晶体管M3的第一极和第二复位晶体管M5的第一极也可以分别连接至不同复位信号端，只要第一复位晶体管M3和第二复位晶体管M5能够分别实现对应的复位功能即可，本公开对此不作限制。
值得注意的是，根据实际应用需求，像素电路100还可以补偿电源线上的 电源电压降(IR drop)。数据写入电路12、补偿电路14、发光控制电路15、第一复位电路16和第二复位电路17等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
图2B为本公开一些实施例提供的另一种像素电路的示意性结构图。例如，如图2B所示，本公开实施例的提供另一种像素电路100包括第一电容C1、第二电容C2、驱动晶体管M1、数据写入晶体管M2、补偿晶体管M4、第一发光控制晶体管M6、第二发光控制晶体管M7、第一复位晶体管M3和第二复位晶体管M5。
例如，如图2B所示，数据写入晶体管M2的第一极被配置为接收数据电压V data1，数据写入晶体管M2的第二极连接到第一电容C1的第二端，数据写入晶体管M2的控制极被配置为与栅线G1连接以接收扫描控制信号VG1。第一电容C1的第一端连接到第一电源端V1，由此第一电容C1被配置为存储数据写入晶体管M2写入的存储的数据电压V data2。
例如，如图2B所示，驱动晶体管M1的第一极连接到数据写入晶体管M2的第二极和第一电容C1的第二端，驱动晶体管M1的第二极连接到补偿晶体管M4的第一极，驱动晶体管M1的控制极连接到补偿晶体管M4的第二极。补偿晶体管M4的控制极被配置为与补偿控制信号线G2连接以接收补偿控制信号VG2。
例如，如图2B所示，第二电容C2的第一端连接到第一电源端V1，第二电容C2的第二端连接到驱动晶体管M1的控制极。
例如，如图2B所示，第一发光控制晶体管M6的第一极连接至第一电源端V1，第一发光控制晶体管M6的第二极连接至驱动晶体管M1的第一极，第一发光控制晶体管M6的控制极被配置为连接至第一发光控制信号线EM1以接收第一发光控制子信号V EM1；第二发光控制晶体管M7的第一极连接至驱动晶体管M1的第二极，第二发光控制晶体管M7的第二极连接至发光元件EL的第一端，第二发光控制晶体管M7的控制极被配置为连接至第一发光控制信号线EM1以接收第一发光控制子信号V EM1；发光元件EL的第二端连接至第三电源端V3。
例如，如图2B所示，第一复位晶体管M3的第一极连接至复位信号端VINT，第一复位晶体管M3的第二极连接至驱动晶体管M1的控制极，第一复位晶体管M3的控制极被配置为连接第一复位控制信号线RT1以接收第一复位控制 信号VRT1；第二复位晶体管M5的第一极连接至复位信号端VINT，第二复位晶体管M5的第二极连接至发光元件EL的第一端，第二复位晶体管M5的控制极被配置为连接第二复位控制信号线RT2以接收第二复位控制信号VRT2。
需要说明的是，关于发光元件EL、第一电容C1、第二电容C2、驱动晶体管M1、数据写入晶体管M2、补偿晶体管M4、第一发光控制晶体管M6、第二发光控制晶体管M7、第一复位晶体管M3和第二复位晶体管M5等的描述可以参考上述图2A所示的实施例的像素电路中的相关说明，在此不再赘述。
本公开至少一些实施例还提供一种应用于根据上述任一项所述的像素电路的驱动方法。图3为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程图。如图3所示，该驱动方法可以包括：
步骤S101：在数据写入阶段，向存储电路写入数据电压；
步骤S102：在补偿阶段，根据存储的数据电压，向补偿电路写入补偿电压；
步骤S103：在发光阶段，基于补偿电压驱动发光元件发光。
本公开实施例提供的驱动方法在数据写入阶段将数据电压写入存储电路，从而在数据写入阶段之后的补偿阶段，基于存储电路上的存储的数据电压仍可以进行补偿操作，延长补偿时间，达到充分补偿的目的，实现补偿时间与显示面板的刷新率、分辨率无关，改善显示面板的显示亮度均匀性，提高显示效果。
例如，在一些实施例中，该驱动方法还可以包括：在第一复位阶段，对发光驱动电路的控制端进行复位；在第二复位阶段，对发光元件的第一端进行复位。
例如，像素电路的时序图可以根据实际需求进行设定，本公开的实施例对此不作具体限定。
图4A为一种像素电路的结构示意图，图4B为图4A所示的像素电路的驱动方法的时序图，图5为本公开一些实施例提供的一种像素电路的驱动方法的示例性时序图。
例如，如图4A所示，一种7TIC型像素电路200可以包括数据写入晶体管M2'、驱动晶体管M1'、补偿晶体管M4'、第二电容C2'、第一复位晶体管M3'、第二复位晶体管M5'、第一发光控制晶体管M6'和第二发光控制晶体管M7'。像素电路200用于驱动发光元件EL'发光。
例如，如图4A和图4B所示，在第一复位阶段1，第一复位控制信号线RT1提供的第一复位控制信号VRT1为低电平信号(即有效信号)，扫描控制 信号线G3提供的扫描控制信号VG3、第二复位控制信号线RT2提供的第二复位控制信号VRT2、发光控制信号线EM提供的发光控制信号V EM等均为高电平信号，从而第一复位晶体管M3'导通，数据写入晶体管M2'、驱动晶体管M1'、补偿晶体管M4'、第二复位晶体管M5'、第一发光控制晶体管M6'和第二发光控制晶体管M7'均截止。复位信号端VINT输出的复位信号可以经由第一复位晶体管M3'被写入驱动晶体管M1'的控制极，以对驱动晶体管M1'的控制极进行复位。由此，在前一帧中，保持在驱动晶体管M1'的控制极上的电压被清除，驱动晶体管M1'的控制极上的电压V G'和驱动晶体管M1'的第一极上的电压V S'均被复位至低电平信号。
例如，如图4A和图4B所示，在数据写入和补偿阶段2，扫描控制信号VG3为低电平信号(即有效信号)，第一复位信号VRT1、第二复位信号VRT2、发光控制信号V EM等均为高电平信号，由此，数据写入晶体管M2'、驱动晶体管M1'和补偿晶体管M4'均导通，第一复位晶体管M3'、第二复位晶体管M5'、第一发光控制晶体管M6'和第二发光控制晶体管M7'均截止。由于数据写入晶体管M2'、驱动晶体管M1'和补偿晶体管M4'均导通，数据电压V data1依次经由数据写入晶体管M2'、驱动晶体管M1'和补偿晶体管M4'被写入驱动晶体管M1'的控制极(即节点G')，如果补偿时间足够，则最终驱动晶体管M1'的控制极的电压可以为V data1+Vth'，Vth'为驱动晶体管M1'的阈值电压。但是，由于数据写入和补偿阶段2持续的时间较短，数据写入和补偿阶段2结束时，驱动晶体管M1'的控制极的电压V G'不能达到V data1+Vth'，即V G'<V data1+Vth'。如图4B所示，在该像素电路200的驱动方法中，补偿过程的时间与扫描控制信号VG3为低电平信号的时间相同。
例如，如图4A和图4B所示，在第二复位阶段3，第二复位信号VRT2为低电平信号(即有效信号)，第一复位信号VRT1、扫描控制信号VG3、发光控制信号V EM等均为高电平信号，由此，第二复位晶体管M5'导通，其余晶体管均截止，复位信号端VINT输出的复位信号可以经由第二复位晶体管M5'被写入发光元件EL'的第一端，以对发光元件EL'的第一端进行复位，此时，发光元件EL'不发光。
例如，如图4A和图4B所示，在发光阶段4，发光控制信号V EM为低电平信号(即有效信号)，第一复位信号VRT1、扫描控制信号VG3、第二复位信号VRT2等均为高电平信号，由此，数据写入晶体管M2'、补偿晶体管M4'、第一 复位晶体管M3'和第二复位晶体管M5'均截止，第一发光控制晶体管M6'和第二发光控制晶体管M7'均导通，驱动晶体管M1'的第一极上的电压V S上升为电源电压端VDD输出的高电压V d，驱动晶体管M1'的控制极上的电压V G可以控制驱动晶体管M1'处于饱和状态，根据驱动晶体管M1'的饱和电流公式，流经驱动晶体管M1'的发光电流I 1可以表示为：
I 1＝K*(V GS–Vth') 2＝K*(V G'–V d–Vth') 2
上述公式中V GS为驱动晶体管M1'的栅极(即控制极)和源极(即第一极)之间的电压差。由于V G'<V data1+Vth'，V G'–V d–Vth'<V data1–V d，发光元件EL'发出的光与写入的数据电压V data1不匹配，从而产生显示面板的显示不均匀的现象。
下面结合图2A和图5详细说明本公开实施例提供的一种像素电路的驱动方法的操作流程。
例如，如图2A和图5所示，在第一复位阶段T1，第一复位控制信号线RT1提供的第一复位控制信号VRT1为低电平信号(即有效信号)，栅线G1提供的扫描控制信号VG1、补偿控制信号线G2提供的补偿控制信号VG2、第二复位控制信号线RT2提供的第二复位信号VRT2、第一发光控制信号线EM1提供的第一发光控制子信号V EM1和第二发光控制信号线EM2提供的第二发光控制子信号V EM2等均为高电平信号，从而第一复位晶体管M3导通，数据写入晶体管M2、驱动晶体管M1、补偿晶体管M4、第二复位晶体管M5、第一发光控制晶体管M6和第二发光控制晶体管M7均截止。复位信号端VINT输出的复位信号(例如，低电压信号)可以被写入驱动晶体管M1的控制极，以对驱动晶体管M1的控制极进行复位。由此，在前一帧中，保持在驱动晶体管M1的控制极上的电压被清除，驱动晶体管M1的控制极上的电压V G和驱动晶体管M1的第一极上的电压V S均被复位至低电平信号。
例如，如图2A和图5所示，在数据写入阶段T2(例如，第一补偿阶段)，扫描控制信号VG1和补偿控制信号VG2可以均为低电平信号(即有效信号)，第一复位信号VRT1、第二复位信号VRT2、第一发光控制子信号V EM1和第二发光控制子信号V EM2等均为高电平信号，由此，数据写入晶体管M2、驱动晶体管M1和补偿晶体管M4均导通，第一复位晶体管M3、第二复位晶体管M5、第一发光控制晶体管M6和第二发光控制晶体管M7均截止。数据电压V data1经由数据写入晶体管M2被写入第一电容C1的第二端(即驱动晶体管M1的第 一极)，第一电容C1可以存储该存储的数据电压V data2(即数据电压V data1)。驱动晶体管M1的第一极的电压V S可以为存储的数据电压V data2。由于补偿晶体管M4导通，驱动晶体管M1形成二极管连接方式，驱动晶体管M1也导通，从而数据电压V data1还可以依次经由驱动晶体管M1和补偿晶体管M4被写入驱动晶体管M1的控制极(即第三节点G)，驱动晶体管M1的控制极的电压V G逐渐上升，从而开始进行补偿操作。
例如，如图2A和图5所示，在补偿阶段T3(例如，第二补偿阶段)，补偿控制信号VG2保持为低电平信号(即有效信号)，扫描控制信号VG1变为高电平信号(即无效信号)，第一复位信号VRT1、第二复位信号VRT2、第一发光控制子信号V EM1和第二发光控制子信号V EM2等也均保持为高电平信号，由此，驱动晶体管M1和补偿晶体管M4保持导通，数据写入晶体管M2截止，第一复位晶体管M3、第二复位晶体管M5、第一发光控制晶体管M6和第二发光控制晶体管M7也均保持截止。由于存储的数据电压V data2被存储在第一电容C1上，存储的数据电压V data2仍然可以依次经由驱动晶体管M1和补偿晶体管M4被写入第二电容C2，以继续进行补偿操作。此时，驱动晶体管M1的第一极的电压V S逐渐下降，驱动晶体管M1的控制极的电压V G仍然逐渐上升。由于补偿阶段T3可以足够长，最终，驱动晶体管M1的第一极和驱动晶体管M1的控制极的电压差V GS与驱动晶体管M1的阈值电压Vth相等，即V GS＝Vth时，驱动晶体管M1截止，补偿阶段T3结束。由于第一电容C1的电容值远大于第二电容C2的电容值，驱动晶体管M1的第一极的电压V S在补偿阶段T3的补偿过程中的减少量较小，由此，在补偿阶段T3结束时，驱动晶体管M1的第一极的电压V S与存储的数据电压V data2基本相同。也就是说，在补偿阶段T3结束时，驱动晶体管M1的第一极的电压V S约为存储的数据电压V data2，驱动晶体管M1的控制极的电压V G约为V data2+Vth。当第一电容C1的电容值远大于第二电容C2的电容值时，则在补偿阶段T3，驱动晶体管M1的第一极的电压的减少量可以忽略不计，即在补偿阶段T3结束时，驱动晶体管M1的第一极的电压V S＝V data2(即V data1)，驱动晶体管M1的控制极的电压V G＝V data2+Vth。
例如，如图5所示，在该像素电路的驱动方法中，补偿过程的时间包括数据写入阶段T2的时间和补偿阶段T3的时间。
例如，如图5所示，扫描控制信号VG1为低电平信号的时间与提供数据电压V data1的时间相同，而补偿控制信号VG2为低电平信号的时间与提供数据 电压V data1的时间无关。通过调整补偿控制信号VG2处于有效信号的时间，利用第一电容C1暂存数据电压V data1，从而可以间接延长补偿时间，利用较小的代价即可实现高分辨率、高刷新率的像素驱动。
例如，如图5所示，数据写入阶段T2(第一补偿阶段)的持续时间短于补偿阶段T3(第二补偿阶段)的持续时间，即本公开实施例提供的驱动方法可以延长补偿时间，达到充分补偿的目的。
需要说明的是，由于在数据写入阶段T2数据电压V data1可以被写入驱动晶体管M1的控制极，及在数据写入阶段T2即开始进行补偿操作；在补偿阶段T3，数据电压V data1仍然可以被写入驱动晶体管M1的控制极，以继续进行补偿操作。由此，在本公开的实施例中，阈值电压的补偿可以包括第一补偿阶段(数据写入阶段T2)和第二补偿阶段(补偿阶段T3)。
例如，如图2A和图5所示，在第二复位阶段T4，第二复位信号VRT2为低电平信号(即有效信号)，第一复位信号VRT1、扫描控制信号VG1、补偿控制信号VG2、第一发光控制子信号V EM1和第二发光控制子信号V EM2等均为高电平信号，由此，第二复位晶体管M5导通，其余晶体管均截止，复位信号端VINT输出的复位信号可以被写入发光元件EL的第一端，以对发光元件EL的第一端进行复位，此时，发光元件EL不发光。
例如，如图2A和图5所示，在发光阶段T5，第一发光控制子信号V EM1和第二发光控制子信号V EM2均为低电平信号(即有效信号)，扫描控制信号VG1、补偿控制信号VG2、第一复位信号VRT1、第二复位信号VRT2等均为高电平信号，由此，数据写入晶体管M2、补偿晶体管M4、第一复位晶体管M3和第二复位晶体管M5均截止，第一发光控制晶体管M6和第二发光控制晶体管M7均导通，驱动晶体管M1的第一极上的电压V S上升为第二电源端V2输出的第二电压信号V d2，驱动晶体管M1的控制极上的电压V G可以控制驱动晶体管M1处于饱和状态，根据驱动晶体管M1的饱和电流公式，流经驱动晶体管M1的发光电流I EL可以表示为：
I EL＝K*(V GS–Vth) 2
＝K*[(V data2+Vth–V d2)–Vth] 2
＝K*(V data2-V d2) 2
上述公式中V GS为驱动晶体管M1的栅极和源极之间的电压差，Vth是驱动晶体管M1的阈值电压。由上式中可以看到，发光电流I EL已经不受驱动晶 体管M1的的阈值电压Vth的影响，而只与第二电源端V2输出的第二电压信号V d2和存储的数据电压V data2(即数据电压V data1)有关。存储的数据电压V data2由数据电压线直接传输，其与驱动晶体管M1的阈值电压Vth无关，这样就可以解决驱动晶体管M1由于工艺制程及长时间的操作造成阈值电压漂移的问题。综上所述，本公开的实施例提供的像素电路可以保证发光电流I EL的准确性，消除驱动晶体管M1的阈值电压对发光电流I EL的影响，保证发光元件EL正常工作，提高显示画面的均匀性，提升显示效果。
例如，上述公式中K为常数，且K可以表示为：
K＝0.5*μ p*C ox*(W/L)
其中，μ p为驱动晶体管M1的电子迁移率，C ox为驱动晶体管M1的栅极单位电容量，W为驱动晶体管M1的沟道宽，L为驱动晶体管M1的沟道长。
需要说明的是，第一复位阶段、第二复位阶段、补偿阶段、数据写入阶段和发光阶段等的设置方式可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
本公开一些实施例还提供一种显示装置。图6为本公开一些实施例提供的一种显示装置的示意性框图。如图6所示，显示装置80可以包括显示面板70，显示面板70用于显示图像。显示面板70包括多个像素单元，多个像素单元可以阵列排布。每个像素单元可以包括上述任一实施例所述的像素电路100。该像素电路100通过存储电路临时存储数据电压，以在数据写入阶段之后仍可以进行补偿操作，延长补偿时间，达到充分补偿的目的，实现补偿时间与显示面板的刷新率分辨率无关，改善显示面板的显示亮度均匀性，提高显示效果。
例如，每个像素单元还可以包括上述任一实施例所述的发光元件。在每个像素单元中，像素电路被配置为驱动发光元件发光。
例如，显示面板70可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板70不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板70还可以具备触控功能，即显示面板70可以为触控显示面板。
例如，如图6所示，显示装置80还可以包括栅极驱动器82。栅极驱动器82被配置为通过栅线与像素单元的像素电路中的数据写入电路电连接，以用于向数据写入电路提供扫描控制信号。栅极驱动器82还被配置为通过补偿控制 信号线与像素单元的像素电路中的补偿电路电连接，以用于向补偿电路提供补偿控制信号。
例如，如图6所示，显示装置80还可以包括数据驱动器84。数据驱动器84被配置为通过数据线与像素单元的像素电路中的数据写入电路电连接，以用于向数据写入电路提供数据电压。
例如，栅极驱动器82和数据驱动器84可以分别由各自的专用集成电路芯片实现，或者也可以通过半导体制备工艺直接制备在显示面板70上来实现。例如，栅极驱动器82可以包括GOA(Gate Driver On Array)型栅极驱动电路。
例如，显示装置80可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，对于显示装置80的其它组成部分(例如控制装置、图像数据编码/解码装置、时钟电路等)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种像素电路，包括：存储电路、数据写入电路、发光驱动电路和补偿电路，
    其中，所述数据写入电路与所述存储电路连接，且被配置为在扫描控制信号的控制下将数据电压写入所述存储电路；
    所述存储电路被配置为存储所述数据电压并使得存储的数据电压可用于所述补偿电路进行补偿操作；
    所述补偿电路与所述发光驱动电路连接，且被配置为在补偿控制信号的控制下将基于所述存储的数据电压的补偿电压保持在所述发光驱动电路的控制端；
    所述发光驱动电路还与发光元件连接，且被配置为在所述补偿电压的控制下驱动所述发光元件发光。
  2. 根据权利要求1所述的像素电路，其中，所述存储电路包括第一电容，
    所述第一电容的第一端连接到第一电源端，所述第一电容的第二端连接到所述数据写入电路。
  3. 根据权利要求2所述的像素电路，其中，所述发光驱动电路包括驱动晶体管，
    所述发光驱动电路的控制端包括所述驱动晶体管的控制极，所述驱动晶体管的第一极连接到所述数据写入电路以及所述第一电容的第二端，所述驱动晶体管的第二极和控制极均连接到所述补偿电路。
  4. 根据权利要求3所述的像素电路，其中，所述数据写入电路包括数据写入晶体管，
    所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入晶体管的第二极连接到所述第一电容的第二端和所述驱动晶体管的第一极，所述数据写入晶体管的控制极被配置为接收所述扫描控制信号。
  5. 根据权利要求3或4所述的像素电路，其中，所述补偿电路包括补偿晶体管和第二电容，
    所述补偿晶体管的第一极连接到所述驱动晶体管的第二极，所述补偿晶体管的第二极连接到所述驱动晶体管的控制极，所述补偿晶体管的控制极被配置为接收所述补偿控制信号；
    所述第二电容的第一端连接到第二电源端，所述第二电容的第二端连接到所述驱动晶体管的控制极；
    所述第一电容的电容值大于所述第二电容的电容值。
  6. 根据权利要求5所述的像素电路，还包括发光控制电路，
    其中，所述发光控制电路分别与所述发光驱动电路和所述发光元件连接，且被配置为在发光控制信号的控制下控制所述发光驱动电路驱动所述发光元件发光。
  7. 根据权利要求6所述的像素电路，其中，所述发光控制电路包括第一发光控制晶体管，所述发光控制信号包括第一发光控制子信号，
    所述第一发光控制晶体管的第一极连接至所述第二电源端，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的控制极被配置为接收所述第一发光控制子信号。
  8. 根据权利要求7所述的像素电路，其中，所述第一电源端输出的第一电压信号和所述第二电源端输出的第二电压信号相同。
  9. 根据权利要求7所述的像素电路，其中，所述发光控制电路还包括第二发光控制晶体管，所述发光控制信号包括第二发光控制子信号，
    所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端，所述第二发光控制晶体管的控制极被配置为接收所述第二发光控制子信号，
    所述发光元件的第二端连接至第三电源端。
  10. 根据权利要求9所述的像素电路，其中，所述第一电源端输出的第一电压信号和所述第三电源端输出的第三电压信号相同。
  11. 根据权利要求2-10任一项所述的像素电路，还包括第一复位电路，
    其中，所述第一复位电路连接至所述发光驱动电路的控制端和复位信号端，且被配置为在第一复位控制信号的控制下对所述发光驱动电路的控制端进行复位。
  12. 根据权利要求2-11任一项所述的像素电路，还包括第二复位电路，
    其中，所述第二复位电路连接至所述发光元件的第一端和复位信号端，且被配置为在第二复位控制信号的控制下对所述发光元件的第一端进行复位。
  13. 根据权利要求12所述的像素电路，其中，所述补偿控制信号和所述第二复位控制信号为同一个信号。
  14. 根据权利要求11-13任一项所述的像素电路，其中，所述第一电源端输出的第一电压信号和所述复位信号端输出的复位信号相同。
  15. 一种像素电路，包括：第一电容、第二电容、驱动晶体管、数据写入晶体管、补偿晶体管、第一发光控制晶体管、第二发光控制晶体管、第一复位晶体管和第二复位晶体管，
    其中，所述数据写入晶体管的第一极被配置为接收数据电压，所述数据写入晶体管的第二极连接到所述第一电容的第二端，所述数据写入晶体管的控制极被配置为接收扫描控制信号；
    所述第一电容的第一端连接到第一电源端，所述第一电容被配置为存储所述数据写入晶体管写入的所述数据电压；
    所述驱动晶体管的第一极连接到所述数据写入晶体管的第二极和所述第一电容的第二端，所述驱动晶体管的第二极连接到所述补偿晶体管的第一极，所述驱动晶体管的控制极连接到所述补偿晶体管的第二极；
    所述补偿晶体管的控制极被配置为接收补偿控制信号；
    所述第二电容的第一端连接到所述第一电源端，所述第二电容的第二端连接到所述驱动晶体管的控制极；
    所述第一发光控制晶体管的第一极连接至所述第一电源端，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的控制极被配置为接收第一发光控制子信号；
    所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端，所述第二发光控制晶体管的控制极被配置为接收所述第一发光控制子信号；
    所述发光元件的第二端连接至第三电源端；
    所述第一复位晶体管的第一极连接至复位信号端，所述第一复位晶体管的第二极连接至所述驱动晶体管的控制极，所述第一复位晶体管的控制极被配置为接收第一复位控制信号；
    所述第二复位晶体管的第一极连接至所述复位信号端，所述第二复位晶体管的第二极连接至所述发光元件的第一端，所述第二复位晶体管的控制极被配置为接收第二复位控制信号。
  16. 一种应用于根据权利要求1-14任一项所述的像素电路的驱动方法，包括：
    在数据写入阶段，向所述存储电路写入所述数据电压；
    在补偿阶段，根据所述存储的数据电压，向所述补偿电路写入所述补偿电压；
    在发光阶段，基于所述补偿电压驱动所述发光元件发光。
  17. 根据权利要求16所述的驱动方法，其中，所述数据写入阶段的持续时间短于所述补偿阶段的持续时间。
  18. 一种显示装置，包括根据权利要求1-15任一项所述的像素电路。
  19. 根据权利要求18所述的显示装置，还包括根据权利要求1-15任一项所述的发光元件，
    其中，所述像素电路被配置为驱动所述发光元件发光。
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