WO2021043102A1 - 驱动电路及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021043102A1
WO2021043102A1 PCT/CN2020/112516 CN2020112516W WO2021043102A1 WO 2021043102 A1 WO2021043102 A1 WO 2021043102A1 CN 2020112516 W CN2020112516 W CN 2020112516W WO 2021043102 A1 WO2021043102 A1 WO 2021043102A1
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node
transistor
control
circuit
sub
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PCT/CN2020/112516
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English (en)
French (fr)
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玄明花
岳晗
齐琪
刘静
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京东方科技集团股份有限公司
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Priority to US17/287,536 priority Critical patent/US11341919B2/en
Publication of WO2021043102A1 publication Critical patent/WO2021043102A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/0264—Details of driving circuits
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    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a driving circuit, a driving method thereof, and a display device.
  • Micro Light Emitting Diode (Micro LED) technology is to integrate small-sized LED arrays with high density on a chip to realize the thinning, miniaturization and matrixing of LEDs.
  • the distance between the pixels can reach micrometers.
  • Level, and each pixel can be addressed and emit light individually.
  • Micro LED display panels have gradually developed into display panels used in consumer terminals due to their low driving voltage, long life, and wide temperature resistance.
  • An embodiment of the present disclosure provides a driving circuit for driving an element to be driven to work.
  • the driving circuit and the element to be driven are connected in series between a first working voltage terminal and a second working voltage terminal, and the driving circuit is configured to Control the formation of a current path between the first working voltage terminal and the second working voltage terminal;
  • the driving circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a gray-scale control sub-circuit, wherein: the driving sub-circuit , Respectively connected to the first node, the second node, and the third node, and are configured to provide a driving current to the third node under the control of the first node and the second node;
  • the writing sub-circuit is respectively connected to the first node
  • the scan signal terminal, the first data signal terminal, and the second node are connected, and are configured to write the signal of the first data signal terminal into the second node under the control of the first scan signal terminal;
  • the compensation sub-circuit
  • the drive circuit further includes: a reset sub-circuit; the reset sub-circuit is connected to the reset control signal terminal, the reset voltage terminal, and the first node, and is configured to control the reset control signal terminal. Next, the signal of the reset voltage terminal is written into the first node.
  • the reset sub-circuit includes: a first transistor
  • the write sub-circuit includes: a second transistor, wherein: the control electrode of the first transistor is connected to the reset control signal terminal, and the first transistor The first electrode of the transistor is connected to the reset voltage terminal, the second electrode of the first transistor is connected to the first node; the control electrode of the second transistor is connected to the first scanning signal terminal, and the first electrode of the second transistor is connected to the first scan signal terminal. The electrode is connected to the first data signal terminal, and the second electrode of the second transistor is connected to the second node.
  • the element to be driven is a miniature light emitting diode
  • the anode of the element to be driven is connected to the fourth node
  • the cathode of the element to be driven is connected to the second operating voltage terminal.
  • the compensation sub-circuit includes: a third transistor, a first capacitor, and a second capacitor, wherein: the control electrode of the third transistor is connected to the first scan signal terminal, and the second transistor of the third transistor One pole is connected to the first node, the second pole of the third transistor is connected to the third node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first node The voltage terminal is connected; one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the first scan signal terminal.
  • the driving sub-circuit includes: a driving transistor, a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the second node, and a second node of the driving transistor is connected.
  • the pole is connected to the third node.
  • the grayscale control sub-circuit includes: a first control sub-circuit and a second control sub-circuit, wherein: the first control sub-circuit is connected to the first operating voltage terminal and the drive control signal respectively The terminal, the second node, the third node, and the fifth node are connected, and are configured to provide the signal of the first operating voltage terminal to the second node and the signal of the third node to the fifth node under the control of the drive control signal terminal;
  • the second control sub-circuit is respectively connected to the fourth node, the fifth node, the second scan signal terminal, the second data signal terminal, and the first voltage terminal, and is configured to be connected to the second scan signal terminal and the second data signal terminal. Under control, the signal of the fifth node is provided to the fourth node.
  • the first control sub-circuit includes: a fourth transistor and a fifth transistor, wherein the control electrode of the fourth transistor is connected to the drive control signal terminal, and the first electrode of the fourth transistor is connected to the drive control signal terminal.
  • the first operating voltage terminal is connected, the second electrode of the fourth transistor is connected to the second node; the control electrode of the fifth transistor is connected to the drive control signal terminal, and the first electrode of the fifth transistor is connected to the first node.
  • the third node is connected, and the second pole of the fifth transistor is connected to the fourth node.
  • the second control sub-circuit includes: a sixth transistor, a third capacitor, and a seventh transistor, wherein: the control terminal of the sixth transistor is connected to the second scan signal terminal, and the first The first end of the six transistor is connected to the second data signal end, the second end of the sixth transistor is connected to the sixth node; one end of the third capacitor is connected to the sixth node, and the third The other end of the capacitor is connected to the first operating voltage end; the control end of the seventh transistor is connected to the sixth node, the first end of the seventh transistor is connected to the fourth node, and the seventh transistor The second end of is connected to the fifth node.
  • the reset sub-circuit includes a first transistor
  • the writing sub-circuit includes a second transistor
  • the compensation sub-circuit includes a third transistor, a first capacitor, and a second capacitor
  • the driving sub-circuit includes a driving transistor
  • the first control sub-circuit includes a fourth transistor and a fifth transistor
  • the second control sub-circuit includes a sixth transistor, a third capacitor, and a seventh transistor, wherein: the first The control electrode of the transistor is connected to the reset control signal terminal, the first electrode of the first transistor is connected to the reset voltage terminal, the second electrode of the first transistor is connected to the first node; the control electrode of the second transistor is connected to the The first scan signal terminal is connected, the first electrode of the second transistor is connected to the first data signal terminal, the second electrode of the second transistor is connected to the second node; the control electrode of the third transistor is connected to the first The scan signal terminal is connected, the first electrode of the third transistor is connected to the first node, the second electrode of the third transistor is connected to the
  • the data signal terminal is connected, the second terminal of the sixth transistor is connected to the sixth node; one end of the third capacitor is connected to the sixth node, and the other end of the third capacitor is connected to the first working voltage terminal; the control of the seventh transistor The terminal is connected to the sixth node, the first terminal of the seventh transistor is connected to the fifth node, and the second terminal of the seventh transistor is connected to the fourth node.
  • the capacitance, ⁇ V is the difference between the actual voltage value and the ideal voltage value of the first node after compensation for the first node, and ⁇ Vg is the jump voltage value of the first scan signal terminal.
  • the embodiment of the present disclosure also provides a display device, including a display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel is provided with the driving circuit and the element to be driven as described in any one of the above, the The driving circuit is configured to provide a driving signal to the element to be driven.
  • the embodiment of the present disclosure also provides a driving method of a driving circuit, which is used to drive the driving circuit as described above.
  • the gray-scale control sub-circuit includes: a first control sub-circuit and a second control sub-circuit.
  • the driving circuit has a plurality of scanning periods; in one scanning period, the driving method includes: providing a first operating voltage to a first operating voltage terminal, providing a first scanning signal to the first scanning signal terminal, and providing a first data signal to a The display data signal is written to the second node through the writing sub-circuit, the driving sub-circuit is turned on under the control of the first node and the second node, and the compensation sub-circuit is under the control of the first operating voltage terminal.
  • the compensation sub-circuit compensates the first node again; provides a drive control signal to the drive control signal terminal, and the first operating voltage is transmitted to the first node through the first control sub-circuit.
  • the method further includes: under the control of the first scan signal terminal, the compensation sub-circuit compensates the first node again until the voltage value of the signal of the first node is an ideal voltage value, The ideal voltage value of the first node is equal to the sum of the voltage value of the first data signal terminal and the threshold voltage of the driving transistor.
  • FIG. 1 is a first structural diagram of an exemplary driving circuit according to an embodiment of the disclosure
  • FIG. 2 is a second structural diagram of an exemplary driving circuit according to an embodiment of the disclosure.
  • FIG. 3 is an equivalent circuit diagram of a reset sub-circuit and a write sub-circuit provided by an embodiment of the disclosure
  • FIG. 5 is an equivalent circuit diagram of a driving sub-circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of a gray-scale control sub-circuit provided by an embodiment of the disclosure.
  • FIG. 7 is an equivalent circuit diagram of a first control sub-circuit provided by an embodiment of the disclosure.
  • FIG. 8 is an equivalent circuit diagram of a second control sub-circuit provided by an embodiment of the disclosure.
  • FIG. 9 is an equivalent circuit diagram of a driving circuit provided by an embodiment of the disclosure.
  • FIG. 10 is a working timing diagram of an exemplary driving circuit according to an embodiment of the disclosure.
  • FIG. 11 is a schematic structural diagram of an exemplary display panel according to an embodiment of the disclosure.
  • FIG. 12 is a flowchart of an exemplary driving method of a driving circuit according to an embodiment of the disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
  • one of the electrodes is called the first pole, and the other is called the second pole.
  • the first pole can be a source or a drain
  • the second The electrode can be a drain or a source.
  • Some display panels drive Micro LEDs to emit light through pixel circuits.
  • the threshold voltage compensation of the driving transistor is compensated by the self-feedback turn-off of the driving transistor.
  • the gate-source voltage Vgs decreases, which leads to weakening of the compensation effect and incomplete compensation. , It affects the precise control of gray scale, and then affects the display effect.
  • FIG. 1 is a schematic structural diagram of a driving circuit provided by an embodiment of the disclosure. As shown in FIG. 1, the driving circuit and the component L to be driven are connected in series. Between a working voltage terminal VL1 and a second working voltage terminal VL2, the driving circuit is configured to control a current path formed between the first working voltage terminal VL1 and the second working voltage terminal VL2.
  • the element L to be driven may be a light-emitting element, such as a micro light-emitting diode, such as a Micro LED.
  • the anode of the element L to be driven is connected to the fourth node N4, and the cathode of the element to be driven is connected to the second operating voltage terminal. VL2 connection.
  • the size level of Micro LED is micron ( ⁇ m) level.
  • the driving circuit provided by the embodiment of the present disclosure includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, and a gray-scale control sub-circuit.
  • the driving sub-circuit is respectively connected to the first node N1, the second node N2, and the third node N3, and is configured to provide a driving current to the third node N3 under the control of the first node N1 and the second node N2; write The sub-circuits are respectively connected to the first scan signal terminal G_A, the first data signal terminal D_A, and the second node N2, and are configured to combine the signal of the first data signal terminal D_A under the control of the first scan signal terminal G_A (ie, The first data voltage V D_A ) is written into the second node N2; the compensation sub-circuit is respectively connected to the first operating voltage terminal VL1, the first scan signal terminal G_A, the first node N1, and the third node N3, and is configured to Under the control of the scanning signal terminal G_A and the first working voltage terminal VL1, the first node N1 is compensated; the gray scale control sub-circuit is respectively connected with the first working voltage terminal VL1, the light emitting control terminal EM (
  • the two nodes N2, the third node N3, the fourth node N4, the second scan signal terminal G_B, the second data signal terminal D_B, and the first voltage terminal V1 are connected, and are configured to be at the light emitting control terminal EM and the second scan signal terminal G_B Under the control of the second data signal terminal D_B and the second data signal terminal D_B, a driving current is provided to the fourth node N4 to control the conduction time of the current path.
  • the writing sub-circuit can output the first data voltage V D_A related to the display gray scale to the driving sub-circuit, so that the driving sub-circuit can generate the driving current I for driving the light-emitting element L to emit light.
  • the gray-scale control sub-circuit can control the on-duration of the current path formed when the driving current I flows into the light-emitting element L, thereby controlling the light-emitting duration of the light-emitting element L.
  • the effective brightness of the light-emitting element L can be controlled by the size of the first data voltage V D_A and the gray-scale control sub-circuit. Luminous brightness, to achieve the purpose of adjusting the display gray scale.
  • each driving circuit is provided with a gray-scale control sub-circuit, and for multiple driving circuits corresponding to sub-pixels in the same row, each included gray-scale control sub-circuit is connected to a different The data signal line (that is, controlled by the independent second data voltage V D_B ), therefore, the driving circuit provided in the embodiment of the present disclosure can directly separate the brightness of the light-emitting element L (for example, Micro LED) in the driving circuit. Take control.
  • the driving circuit provided by the embodiment of the present disclosure may be fabricated on the glass substrate or the resin substrate in the display panel of the display device through a patterning process. When the light-emitting element is a Micro LED, it is possible to provide a low-cost, simple manufacturing process, and an implementation method of a Micro LED display device that can be mass-produced.
  • the driving circuit provided by the embodiment of the present disclosure compensates the first node N1 under the control of the first scanning signal terminal G_A and the first working voltage terminal VL1 through the compensation sub-circuit, so as to realize the precise control of the gray scale and improve the display The display quality of the panel.
  • the driving circuit is configured to provide a driving current I and control the conduction time of the current path between the first working voltage terminal VL1 and the second working voltage terminal VL2.
  • the first working voltage VDD output from the first working voltage terminal VL1 and the second working voltage VSS output from the second working voltage terminal VL2 can provide a potential difference to the current path, so that the driving current I can be transmitted along the current path To light-emitting element L.
  • the first working voltage VDD may be a constant high level
  • the second working voltage VSS may be a constant low level
  • the light emitting element L is configured to receive the driving current I in the current path and emit light.
  • the driving circuit may further include a reset sub-circuit.
  • the reset sub-circuit is respectively connected to the reset control signal terminal RST, the reset voltage terminal VINT and the first node N1, and is configured to write the signal of the reset voltage terminal VINT to the first node N1 under the control of the reset control signal terminal RST .
  • the reset sub-circuit can reset the gate of the driving transistor Td to prevent the voltage remaining on the driving transistor Td in the previous image frame from affecting the display of the current image frame.
  • the voltage of the first node N1 is the reset voltage provided by the reset voltage terminal VINT.
  • FIG. 3 is an equivalent circuit diagram of the reset sub-circuit and the write sub-circuit provided by the embodiments of the present disclosure.
  • the reset sub-circuit provided by the embodiments of the present disclosure includes: a first transistor T1
  • the writing sub-circuit includes: a second transistor T2.
  • the control electrode of the first transistor T1 is connected to the reset control signal terminal RST, the first electrode of the first transistor T1 is connected to the reset voltage terminal VINT, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode is connected to the first scan signal terminal G_A, the first electrode of the second transistor T2 is connected to the first data signal terminal D_A, and the second electrode of the second transistor T2 is connected to the second node N2.
  • FIG. 3 An exemplary structure of the reset sub-circuit and the write sub-circuit is shown in FIG. 3. It is easily understood by those skilled in the art that the implementation of the reset sub-circuit and the write sub-circuit is not limited to this, as long as their respective functions can be realized.
  • FIG. 4 is an equivalent circuit diagram of the compensation sub-circuit provided by the embodiment of the present disclosure.
  • the compensation sub-circuit provided by the embodiment of the present disclosure includes: a third transistor T3, a first capacitor C1 and the second capacitor C2.
  • the control electrode of the third transistor T3 is connected to the first scan signal terminal G_A, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first working voltage terminal VL1.
  • One end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the first scan signal terminal G_A.
  • FIG. 4 An exemplary structure of the compensation sub-circuit is shown in FIG. 4. Those skilled in the art can easily understand that the implementation of the compensation sub-circuit is not limited to this, as long as its function can be realized.
  • FIG. 5 is an equivalent circuit diagram of the driving sub-circuit provided in the embodiment of the present disclosure.
  • the driving sub-circuit provided in the embodiment of the present disclosure includes a driving transistor Td.
  • the control electrode of the driving transistor Td is connected to the first node N1, the first electrode of the driving transistor Td is connected to the second node N2, and the second electrode of the driving transistor Td is connected to the third node N3.
  • FIG. 5 An exemplary structure of the driving sub-circuit is shown in FIG. 5. Those skilled in the art can easily understand that the implementation of the driving sub-circuit is not limited to this, as long as its function can be realized.
  • the compensation sub-circuit is configured to compensate the first node N1 under the control of the first scan signal terminal G_A and the first operating voltage terminal VL1 until the voltage of the signal at the first node N1
  • the value is an ideal voltage value, and the ideal voltage value of the first node N1 is equal to the sum of the voltage value V D_A of the first data signal terminal and the threshold voltage Vth of the driving transistor.
  • the gray scale control sub-circuit includes: a first control sub-circuit and a second control sub-circuit.
  • the first control sub-circuit is connected to the first operating voltage terminal VL1, the light-emitting control terminal EM, the second node N2, the third node N3, and the fifth node N5, respectively, and is configured to move toward the first operating voltage terminal EM under the control of the light-emitting control terminal EM.
  • the second node N2 provides the signal of the first operating voltage terminal VL1
  • the fifth node N5 provides the signal of the third node N3.
  • the second control sub-circuit is respectively connected to the fourth node N4, the fifth node N5, the second scan signal terminal G_B, the second data signal terminal D_B, and the first voltage terminal V1 (the first voltage terminal V1 may be the ground terminal GND)
  • the connection is configured to provide a signal of the fifth node N5 to the fourth node N4 under the control of the second scan signal terminal G_B and the second data signal terminal D_B.
  • the current path can be turned on, and the driving current I generated by the driving sub-circuit can be output to the light emitting element L through the current path.
  • the effective light-emitting brightness of the light-emitting element L can be controlled by the driving current I, the first control sub-circuit, and the second control sub-circuit.
  • the factors affecting the effective light-emitting brightness of the light-emitting element L are increased, so that the driving circuit is provided.
  • the sub-pixels can display more diversified grayscale values.
  • FIG. 7 is an equivalent circuit diagram of the first control sub-circuit provided by the embodiments of the present disclosure.
  • the first control sub-circuit provided by the embodiments of the present disclosure includes a fourth transistor T4 and The fifth transistor T5.
  • the control electrode of the fourth transistor T4 is connected to the light emission control terminal EM, the first electrode of the fourth transistor T4 is connected to the first operating voltage terminal VL1, and the second electrode of the fourth transistor T4 is connected to the second node N2; the fifth transistor T5 The control electrode of the fifth transistor T5 is connected to the light emitting control terminal EM, the first electrode of the fifth transistor T5 is connected to the third node N3, and the second electrode of the fifth transistor T5 is connected to the fifth node N5.
  • FIG. 7 An exemplary structure of the first control sub-circuit is shown in FIG. 7. Those skilled in the art can easily understand that the implementation of the first control sub-circuit is not limited to this, as long as its function can be realized.
  • FIG. 8 is an equivalent circuit diagram of the second control sub-circuit provided by the embodiment of the present disclosure.
  • the second control sub-circuit provided by the embodiment of the present disclosure includes a third capacitor C3, The sixth transistor T6 and the seventh transistor T7.
  • the control electrode of the sixth transistor T6 is connected to the second scan signal terminal G_B, the first electrode of the sixth transistor T6 is connected to the second data signal terminal D_B, and the second electrode of the sixth transistor T6 is connected to the sixth node N6;
  • the control electrode of the transistor T7 is connected to the sixth node N6, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the fourth node N4; one end of the third capacitor C3 is connected to the fourth node N4.
  • the six nodes N6 are connected, and the other end of the third capacitor C3 is connected to the first voltage terminal V1.
  • FIG. 8 An exemplary structure of the second control sub-circuit is shown in FIG. 8. Those skilled in the art can easily understand that the implementation of the second control sub-circuit is not limited to this, as long as its function can be realized.
  • FIG. 9 is an equivalent circuit diagram of the driving circuit provided by the embodiment of the present disclosure.
  • the reset sub-circuit includes: a first transistor T1;
  • the writing sub-circuit includes: a second transistor T2;
  • the compensation sub-circuit includes: a third transistor T3, a first capacitor C1 and a second capacitor C2;
  • the driving sub-circuit includes: a driving transistor Td;
  • the first control sub-circuit includes: a fourth transistor T4 and a fifth transistor T5;
  • the second control sub-circuit includes: a third capacitor C3, a sixth transistor T6 and a seventh transistor T7.
  • the control electrode of the first transistor T1 is connected to the reset control signal terminal RST, the first electrode of the first transistor T1 is connected to the reset voltage terminal VINT, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode is connected to the first scan signal terminal G_A, the first electrode of the second transistor T2 is connected to the first data signal terminal D_A, the second electrode of the second transistor T2 is connected to the second node N2;
  • the control electrode of the third transistor T3 Connected to the first scan signal terminal G_A, the first electrode of the third transistor T3 is connected to the first node N1, the second electrode of the third transistor T3 is connected to the third node N3; one end of the first capacitor C1 is connected to the first node N1 Connected, the other end of the first capacitor C1 is connected to the first working voltage terminal VL1; one end of the second capacitor C2 is connected to the first node N1, the other end of the second capacitor C2 is connected to the first scanning signal terminal G
  • the first electrode of the transistor T5 is connected to the third node N3, the second electrode of the fifth transistor T5 is connected to the fifth node N5; the control electrode of the sixth transistor T6 is connected to the second scan signal terminal G_B, and the second electrode of the sixth transistor T6 is connected to the second scan signal terminal G_B.
  • One electrode is connected to the second data signal terminal D_B, the second electrode of the sixth transistor T6 is connected to the sixth node N6; the control electrode of the seventh transistor T7 is connected to the sixth node N6, and the first electrode of the seventh transistor T7 is connected to the sixth node N6.
  • the fifth node N5 is connected, the second electrode of the seventh transistor T7 is connected to the fourth node N4; one end of the third capacitor C3 is connected to the sixth node N6, and the other end of the third capacitor C3 is connected to the first voltage terminal V1.
  • FIG. 9 shows exemplary structures of the driving sub-circuit, the reset sub-circuit, the writing sub-circuit, the compensation sub-circuit, the first control sub-circuit, and the second control sub-circuit in the driving circuit. It is easily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their respective functions can be realized.
  • the compensation sub-circuit of the embodiment of the present disclosure includes a second capacitor C2.
  • the signal of the first data signal terminal D_A is written to the second node N2 through the second transistor T2, and the voltage (V D_A +Vth) of the third node N3 is written to the first node N1 through the third transistor T3. That is, the first node N1 is charged, where Vth is the threshold voltage of the driving transistor Td.
  • the charging speed of the first node N1, that is, the magnitude of the charging current depends on the open state of the driving transistor Td.
  • the open state of the driving transistor Td is controlled by the voltage difference between its gate and source.
  • the voltage of the first node N1 V N1 slowly approaches (V D_A +Vth), and the closer it is to (V D_A +Vth), the slower its charging speed.
  • the first A node N1 voltage V N1 is charged to (V D_A +Vth), assuming that the difference between the first node N1 voltage V N1 and (V D_A +Vth) is ⁇ V, that is, the first node N1 is charged to (V D_A +Vth) - ⁇ V).
  • the difference in brightness caused by the gap voltage ⁇ V is different.
  • the input level of the first scan signal terminal G_A changes from low to high. Assuming that the transition voltage of the first scan signal terminal G_A is ⁇ Vg, it passes through the second capacitor C2 connected to the first node N1 The potential of the first node N1 is pulled high to compensate for the gap voltage ⁇ V.
  • the first transistor T1 to the seventh transistor T7 and the driving transistor Td can all be N-type thin film transistors or P-type thin film transistors, which can unify the process flow, reduce the number of processes, and help improve product yield.
  • all the transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin film transistors, and the thin film transistors may be thin film transistors with bottom gate structure or top gate structure, as long as they can Just realize the switch function.
  • the first capacitor C1 to the third capacitor C3 may be liquid crystal capacitors composed of a pixel electrode and a common electrode, or an equivalent liquid crystal capacitor composed of a pixel electrode and a common electrode and a storage capacitor. Capacitance, this disclosure does not limit this.
  • FIG. 10 is a working timing diagram of the driving circuit provided by the embodiment of the present disclosure, as shown in FIGS. 9 and 10 .
  • the driving circuit provided by the embodiments of the present disclosure includes 8 transistor units (T1 to T7, Td), 3 capacitor units (C1 to C3), 7 signal input terminals (G_A, G_B, RST, D_A, D_B, VINT and EM) and three power terminals (VL1, VL2, and V1).
  • FIG. 9 also shows the light-emitting element L.
  • the driving circuit is electrically connected to the anode of the light-emitting element L and drives the light-emitting element L to emit light, and the cathode of the light-emitting element L is connected to the second operating voltage terminal VL2.
  • the driving circuit is configured to drive the light emitting element L to emit light.
  • the driving circuit and the light emitting element L are connected in series between the first working voltage terminal VL1 and the second working voltage terminal VL2, and the driving circuit is configured to control the first working voltage terminal VL1.
  • a current path is formed between the second working voltage terminal VL2; the driving circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit and a gray-scale control sub-circuit.
  • the cathode of the light-emitting element L may also be connected to the first voltage terminal V1 (common voltage line) to receive the common voltage provided by the first voltage terminal V1.
  • the cathode of the light-emitting element L is grounded.
  • the driving circuit has a reset stage S1, a compensation stage S2, and a plurality of light-emitting stages EM1 to EMn.
  • the reset stage S1, a compensation stage S2, and a plurality of light-emitting stages EM1 to EMn can be Set sequentially in time.
  • each light-emitting phase includes time data signal writing sub-phases S3, S5..., and effective light-emitting sub-phases S4, S6....
  • the input signal of the reset control signal terminal RST is low, the first transistor T1 is turned on, and the signal of the reset voltage terminal RST is provided to the first node N1 to reset the first node N1, which is the compensation stage.
  • the drive transistor Td is turned on to prepare.
  • the compensation stage S2 the input signal of the first scan signal terminal G_A is low, the second transistor T2 and the third transistor T3 are turned on, and the second transistor T2 writes the display data signal of the first data signal terminal D_A to the second At node N2, since the voltage difference between the signals of the first node N1 and the second node N2 is smaller than the threshold voltage Vth of the driving transistor Td, the driving transistor Td is turned on, and the first node N1, the second node N2, and the third node N3 are mutually connected.
  • the first working voltage terminal VL1 charges the first node N1.
  • the voltage value V N1 of the signal of the first node N1 is equal to V D_A +Vth- ⁇ V.
  • the charging speed of the first node N1 depends on the open state of the drive transistor Td.
  • the open state of the drive transistor Td is controlled by the voltage difference between its gate and source.
  • the voltage difference between the gate and source is (V N1 -V D_A ), where V N1 is the voltage value of the signal of the first node N1.
  • V N1 is the voltage value of the signal of the first node N1.
  • V D_A +Vth the closer it is to (V D_A +Vth)
  • the voltage V N1 of the first node N1 cannot be charged to (V D_A +Vth) within the time 1H).
  • the time data signal is written into the sub-stage S3, the input signal of the second scan signal terminal G_B is low, and the sixth transistor T6 is turned on.
  • the sixth transistor T6 writes the time data signal of the second data signal terminal D_B to the sixth node N6 and stores it in the third capacitor C3. Whether the seventh transistor T7 is turned on or not depends on the time data signal stored in the third capacitor C3. For example, when the time data signal is at an active level (for example, a low level), the seventh transistor T7 is turned on.
  • the level of the input signal of the first scan signal terminal G_A changes from low to high.
  • the first scan signal terminal G_A is connected to the first node N1.
  • the second capacitor C2 pulls up the potential of the first node N1 to compensate for the gap voltage ⁇ V.
  • the magnitude of ⁇ V N1 is (C2* ⁇ Vg)/(C1+C2).
  • the fourth transistor T4 and the fifth transistor T5 are turned on, in addition, the driving transistor Td is turned on, and the driving current Ids generated in the driving transistor Td Satisfy the following expressions:
  • Ids K(Vg-Vs-Vth) 2
  • K 1/2 ⁇ W/L ⁇ C ⁇ , where W is the width of the channel of the drive transistor Td, L is the length of the channel of the drive transistor Td, and W/L is the channel of the drive transistor Td
  • the aspect ratio that is, the ratio of the width to the length
  • ⁇ is the electron mobility
  • C is the capacitance per unit area.
  • the driving current Ids generated in the driving transistor Td is supplied to the light emitting element L via the turned-on fifth transistor T5 and the seventh transistor T7. Since the driving current Ids generated in the driving transistor Td is independent of the threshold voltage Vth of the driving transistor Td, the gray scale accuracy of the pixel unit including the driving circuit is improved.
  • a driving circuit includes a plurality of light-emitting stages, for example, including a first light-emitting stage EM1, a second light-emitting stage EM2, ... and an Nth light-emitting stage EMn, FIG. 10 Only two light-emitting stages are shown in, the first light-emitting stage EM1 and the second light-emitting stage EM2. In each lighting stage, the duty cycle of the lighting control signal provided by the lighting control terminal EM may be different.
  • the overall brightness of the pixel unit including the driving circuit in the process of displaying one frame of picture can be obtained by superimposing the brightness of the light-emitting element L in the pixel sub-circuit in multiple light-emitting stages.
  • each frame of the above-mentioned picture can perform multiple time data signal writing operations through the second control sub-circuit.
  • the above-mentioned driving circuit and driving method of the driving circuit can make the micro LED of the pixel unit work at a high current density and display, for example, a low gray scale.
  • the pixel unit including the micro LED can display a low gray scale.
  • the light-emitting time and/or the current density of the driving current of the micro LED operating at a high current density can be controlled to make the pixel unit including the micro LED display a desired gray scale.
  • Some embodiments of the present disclosure further provide a display device, including a display panel.
  • the display area of the display panel has a plurality of sub-pixels 02 as shown in FIG. 11, and at least one of the sub-pixels 02 is provided with any one of the above Drive circuit 01.
  • the sub-pixel 02 may be defined by the first scan signal line G_A and the first data signal line D_A that cross horizontally and vertically.
  • the second scan signal line G_B may be arranged in parallel with the first scan signal line G_A
  • the second data signal line D_B may be arranged in parallel with the first data signal line D_A.
  • the fourth transistor T4 in the driving circuit 01 of the sub-pixels located in the same row is connected to the same light-emitting control signal terminal EM.
  • the emission control signal terminal EM provides a valid signal, such as a low level as shown in FIG. 10
  • the fourth transistors T4 and the fifth transistors T5 in the same row are all turned on.
  • the second scan signal terminal G_B can input an effective signal to control the sixth transistor T6 to turn on, and then, after the sixth transistor T6 is turned on, pass the second scan signal terminal G_B.
  • the seventh transistor T7 is controlled to be turned on, so that the current path between the first working voltage terminal VL1 and the second working voltage terminal VL2 is turned on.
  • the driving current I generated by the driving transistor Td can be transmitted to the light emitting element L through the current path.
  • the size of the driving current I can also be adjusted by adjusting the size of the first data voltage Vdata_A provided by the first data signal terminal D_A. The larger the driving current I, the higher the effective light-emitting brightness of the light-emitting element L in one scanning period.
  • the corresponding one or more light-emitting stages can be selected according to the expected light-emitting duration of the light-emitting element, so that the light-emitting element emits light during the one or more light-emitting stages, so that a variety of different grayscale brightness can be obtained.
  • multiple light-emitting stages of one image frame may be the same as each other.
  • one or more light-emitting stages can also be selected according to the expected light-emitting duration of the light-emitting element, so that the light-emitting element emits light during the one or more light-emitting stages, so as to change the light-emitting duration of the light-emitting element, and a variety of different gray levels can be obtained.
  • the adjustable range of the light-emitting duration and effective brightness of the light-emitting element can be expanded, and the display panel can be enriched. Number of orders.
  • the light emission control signal terminal EM, the first scan signal terminal G_A, the second scan signal terminal G_B, the first data signal terminal D_A, and the second data signal terminal D_B can be coordinated together.
  • the brightness adjustment of a single sub-pixel is realized.
  • the display device can be any product or component with a display function, such as a display, a TV, a digital photo frame, a mobile phone, or a tablet computer. Wherein, the display device has the same technical effect as the driving circuit 01 provided in the foregoing embodiment, and will not be repeated here.
  • Some embodiments of the present disclosure also provide a driving method of a driving circuit, which is applied to the driving circuit provided in the foregoing embodiments.
  • the driving circuit In an image frame, the driving circuit has a plurality of scanning periods.
  • the gray scale control sub-circuit in the driving circuit includes a first control sub-circuit and a second control sub-circuit.
  • the driving method of the driving circuit includes steps 100 to 103.
  • Step 101 Provide the first operating voltage to the first operating voltage terminal, provide the first scan signal to the first scan signal terminal, and provide the display data signal to the first data signal terminal.
  • the display data signal is written to the first operating voltage terminal through the writing sub-circuit.
  • the driving sub-circuit is turned on under the control of the first node and the second node, and the compensation sub-circuit compensates the first node under the control of the first operating voltage terminal.
  • the voltage of the first node cannot be charged to a value between the voltage value of the data signal terminal and the threshold voltage of the driving transistor within a limited time. And, suppose that the difference between the first node voltage and the sum of the voltage value of the data signal terminal and the threshold voltage of the driving transistor is ⁇ V.
  • Step 102 Provide a second scan signal to the second scan signal terminal, and provide a duration data signal to the second data signal terminal, so that the second control sub-circuit is turned on or off under the control of the second scan signal and the duration data signal to compensate The sub-circuit compensates for the first node again under the control of the first scan signal terminal.
  • the compensation sub-circuit compensates the first node again under the control of the first scan signal terminal until the voltage value of the signal of the first node is the ideal voltage value, and the ideal voltage value of the first node is equal to The sum of the voltage value of the first data signal terminal and the threshold voltage of the driving transistor.
  • the potential of the first node is pulled up by the second capacitor connected to the control terminal of the driving sub-circuit (C2* ⁇ Vg)/(C1+ C2), thereby compensating for the gap voltage ⁇ V, where C2 is the capacitance of the second capacitor, and C1 is the capacitance of the first capacitor.
  • Step 103 Provide a light-emitting control signal to the light-emitting control terminal, and the first operating voltage is transmitted to the fourth node through the first control sub-circuit, so that the light-emitting element is in the light-emitting control signal, the first scan signal, the second scan signal and the duration data signal. Under the control of the display data signal and the first operating voltage, light is emitted.
  • the driving current Ids generated by the driving sub-circuit is provided to the light emitting element L via the gray-scale control sub-circuit.
  • the driving method of the driving circuit further includes:
  • Step 100 Provide a reset control signal to the reset control signal terminal, and provide a reset voltage to the reset voltage terminal, and the reset voltage is transmitted to the first node through the reset sub-circuit.
  • the reset voltage may be at a low level, so that the driving transistor is close to conduction but the driving transistor fails to conduct, so that the gate of the driving transistor is performed during the next data writing phase.
  • the charging is prepared so that the first data voltage provided by the first data signal terminal can more quickly charge the gate of the driving transistor. Therefore, in the subsequent data writing period, when different data voltages are written to the driving transistors, the time for writing the data voltages can be reduced, so that for all the driving circuits of the entire display panel, the response of all the driving transistors is The time is almost the same, and the writing time of the data voltage is about the same. For the entire display panel, this setting method makes the display effect more uniform.
  • the technical solution provided by the present disclosure compensates the first node through the compensation sub-circuit under the control of the first scanning signal terminal and the first working voltage terminal, so as to realize the precise control of the gray scale and improve the display quality of the display panel.

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Abstract

公开了一种驱动电路及其驱动方法、显示装置。该驱动电路用于驱动待驱动元件工作，驱动电路与待驱动元件串联于第一工作电压端（VL1）和第二工作电压端（VL2）之间，驱动电路被配置为控制第一工作电压端（VL1）和第二工作电压端（VL2）之间形成电流通路，驱动电路包括：驱动子电路、写入子电路、补偿子电路和灰阶控制子电路，其中，补偿子电路分别与第一工作电压端（VL1）、第一扫描信号端（G_A）、第一节点（N1）以及第三节点（N3）连接，被配置为在第一扫描信号端（G_A）和第一工作电压端（VL1）的控制下，对第一节点（N1）进行补偿。

Description

驱动电路及其驱动方法、显示装置
本申请要求2019年9月3日递交到CNIPA的、申请号为201910827559.4的中国专利申请的优先权，其内容在此通过引用的方式并入本申请。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种驱动电路及其驱动方法、显示装置。
背景技术
微型发光二极管(Micro Light Emitting Diode，Micro LED)技术是通过在一个芯片上高密度地集成微小尺寸的LED阵列，以实现LED的薄膜化、微小化和矩阵化，其像素间的距离能够达到微米级别，而且每一个像素都能定址、单独发光。Micro LED显示面板因其低驱动电压、长寿命、耐宽温等特点，逐渐向消费者终端机所用的显示面板发展。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种驱动电路，用于驱动待驱动元件工作，所述驱动电路与待驱动元件串联于第一工作电压端和第二工作电压端之间，所述驱动电路被配置为控制第一工作电压端和第二工作电压端之间形成电流通路；所述驱动电路包括：驱动子电路、写入子电路、补偿子电路和灰阶控制子电路，其中：所述驱动子电路，分别与第一节点、第二节点和第三节点连接，被配置为在第一节点和第二节点的控制下，向第三节点提供驱动电流；所述写入子电路，分别与第一扫描信号端、第一数据信号端以及第二节点连接，被配置为在第一扫描信号端的控制下，将第一数据信号端的信号写入第二节点；所述补偿子电路，分别与第一工作电压端、第一扫描信号端、第一节点以及第三节点连接，被配置为在第一扫描信号端和第一工作电压端的控制下， 对第一节点进行补偿；所述灰阶控制子电路，分别与驱动控制信号端、第一工作电压端、第二节点、第三节点、第四节点、第二扫描信号端、第二数据信号端、第一电压端连接，被配置为在驱动控制信号端、第二扫描信号端和第二数据信号端的控制下，向第四节点提供驱动电流，以控制所述电流通路的导通时长。
在一些可能的实现方式中，所述驱动电路还包括：复位子电路；所述复位子电路，分别与复位控制信号端、复位电压端以及第一节点连接，被配置为在复位控制信号端的控制下，将复位电压端的信号写入第一节点。
在一些可能的实现方式中，所述复位子电路包括：第一晶体管，所述写入子电路包括：第二晶体管，其中：第一晶体管的控制极与所述复位控制信号端连接，第一晶体管的第一极与所述复位电压端连接，第一晶体管的第二极与所述第一节点连接；第二晶体管的控制极与所述第一扫描信号端连接，第二晶体管的第一极与第一数据信号端连接，第二晶体管的第二极与所述第二节点连接。
在一些可能的实现方式中，所述待驱动元件为微型发光二极管，待驱动元件的阳极与第四节点连接，待驱动元件的阴极与第二工作电压端连接。
在一些可能的实现方式中，所述补偿子电路包括：第三晶体管、第一电容和第二电容，其中：第三晶体管的控制极与所述第一扫描信号端连接，第三晶体管的第一极与所述第一节点连接，第三晶体管的第二极与所述第三节点连接；第一电容的一端与所述第一节点连接，第一电容的另一端与所述第一工作电压端连接；第二电容的一端与所述第一节点连接，第二电容的另一端与所述第一扫描信号端连接。
在一些可能的实现方式中，所述驱动子电路包括：驱动晶体管、驱动晶体管的控制极与所述第一节点连接，驱动晶体管的第一极与所述第二节点连接，驱动晶体管的第二极与所述第三节点连接。
在一些可能的实现方式中，所述灰阶控制子电路包括：第一控制子电路和第二控制子电路，其中：所述第一控制子电路，分别与第一工作电压端、驱动控制信号端、第二节点、第三节点和第五节点连接，被配置为在驱动控制信号端的控制下，向第二节点提供第一工作电压端的信号，向第五节点提 供第三节点的信号；所述第二控制子电路，分别与第四节点、第五节点、第二扫描信号端、第二数据信号端和第一电压端连接，被配置为在第二扫描信号端和第二数据信号端的控制下，向第四节点提供第五节点的信号。
在一些可能的实现方式中，所述第一控制子电路包括：第四晶体管和第五晶体管，其中：第四晶体管的控制极与所述驱动控制信号端连接，第四晶体管的第一极与所述第一工作电压端连接，第四晶体管的第二极与所述第二节点连接；第五晶体管的控制极与所述驱动控制信号端连接，第五晶体管的第一极与所述第三节点连接，第五晶体管的第二极与第四节点连接。
在一些可能的实现方式中，所述第二控制子电路包括：第六晶体管、第三电容和第七晶体管，其中：所述第六晶体管的控制端与第二扫描信号端连接，所述第六晶体管的第一端与所述第二数据信号端连接，所述第六晶体管的第二端与第六节点连接；所述第三电容的一端与所述第六节点连接，所述第三电容的另一端与第一工作电压端连接；所述第七晶体管的控制端与所述第六节点连接，所述第七晶体管的第一端与所述第四节点连接，所述第七晶体管的第二端与所述第五节点连接。
在一些可能的实现方式中，所述复位子电路包括：第一晶体管，所述写入子电路包括：第二晶体管，所述补偿子电路包括：第三晶体管、第一电容和第二电容，所述驱动子电路包括：驱动晶体管，所述第一控制子电路包括：第四晶体管和第五晶体管，第二控制子电路包括：第六晶体管、第三电容和第七晶体管，其中：第一晶体管的控制极与所述复位控制信号端连接，第一晶体管的第一极与所述复位电压端连接，第一晶体管的第二极与所述第一节点连接；第二晶体管的控制极与所述第一扫描信号端连接，第二晶体管的第一极与第一数据信号端连接，第二晶体管的第二极与所述第二节点连接；第三晶体管的控制极与所述第一扫描信号端连接，第三晶体管的第一极与所述第一节点连接，第三晶体管的第二极与所述第三节点连接；第一电容的一端与所述第一节点连接，第一电容的另一端与所述第一工作电压端连接；第二电容的一端与所述第一节点连接，第二电容的另一端与所述第一扫描信号端连接；驱动晶体管的控制极与所述第一节点连接，驱动晶体管的第一极与所述第二节点连接，驱动晶体管的第二极与所述第三节点连接；第四晶体管的 控制极与所述驱动控制信号端连接，第四晶体管的第一极与所述第一工作电压端连接，第四晶体管的第二极与所述第二节点连接；第五晶体管的控制极与所述驱动控制信号端连接，第五晶体管的第一极与所述第三节点连接，第五晶体管的第二极与第五节点连接；第六晶体管的控制端与第二扫描信号端连接，第六晶体管的第一端与所述第二数据信号端连接，第六晶体管的第二端与第六节点连接；第三电容的一端与所述第六节点连接，第三电容的另一端与第一工作电压端连接；第七晶体管的控制端与所述第六节点连接，第七晶体管的第一端与所述第五节点连接，第七晶体管的第二端与所述第四节点连接。
在一些可能的实现方式中，所述第一电容与所述第二电容满足：C2/(C1+C2)＝ΔV/ΔVg；其中，C1为第一电容的电容量，C2为第二电容的电容量，ΔV为对所述第一节点补偿后，第一节点的实际电压值与理想电压值之间的差值，ΔVg为所述第一扫描信号端的跳变电压值。
本公开实施例还提供了一种显示装置，包括包括显示基板，所述显示基板包括多个亚像素，至少一个亚像素内设置有如以上任一项所述的驱动电路和待驱动元件，所述驱动电路被配置为向所述待驱动元件提供驱动信号。
本公开实施例还提供了一种驱动电路的驱动方法，用于驱动如以上任一所述的驱动电路，所述灰阶控制子电路包括：第一控制子电路和第二控制子电路，所述驱动电路具有多个扫描周期；在一个扫描周期内，所述驱动方法包括：向第一工作电压端提供第一工作电压，向第一扫描信号端提供第一扫描信号，向第一数据信号端提供显示数据信号，显示数据信号通过写入子电路写入至第二节点，驱动子电路在第一节点和第二节点的控制下开启，补偿子电路在第一工作电压端的控制下对第一节点进行补偿；向第二扫描信号端提供第二扫描信号，向第二数据信号端提供时长数据信号，以使得所述第二控制子电路在所述第二扫描信号和时长数据信号的控制下开启或关闭，补偿子电路在第一扫描信号端的控制下，对第一节点再次进行补偿；向驱动控制信号端提供驱动控制信号，所述第一工作电压通过第一控制子电路传输至第四节点，以使得待驱动元件在所述驱动控制信号、第一扫描信号、第二扫描 信号以及时长数据信号的控制下，基于所述显示数据信号和所述第一工作电压工作。
在一些可能的实现方式中，所述方法还包括：所述补偿子电路在第一扫描信号端的控制下，对第一节点再次进行补偿，直至第一节点的信号的电压值为理想电压值，所述第一节点的理想电压值等于第一数据信号端的电压值与驱动晶体管的阈值电压之和。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例的一种示例性的驱动电路的结构示意图一；
图2为本公开实施例的一种示例性的驱动电路的结构示意图二；
图3为本公开实施例提供的复位子电路和写入子电路的等效电路图；
图4为本公开实施例提供的补偿子电路的等效电路图；
图5为本公开实施例提供的驱动子电路的等效电路图；
图6为本公开实施例提供的灰阶控制子电路的结构示意图；
图7为本公开实施例提供的第一控制子电路的等效电路图；
图8为本公开实施例提供的第二控制子电路的等效电路图；
图9为本公开实施例提供的驱动电路的等效电路图；
图10为本公开实施例的一种示例性的驱动电路的工作时序图；
图11为本公开实施例的一种示例性的显示面板的结构示意图；
图12为本公开实施例一种示例性的驱动电路的驱动方法的流程图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语一直出该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在一些示例性实施例中，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。
一些显示面板通过像素电路驱动Micro LED发光。在一些像素电路中，驱动晶体管的阈值电压补偿采用驱动晶体管的自反馈关断进行补偿，随着阈值电压Vth补偿的进行，栅源电压Vgs减小，导致补偿效果减弱，产生补偿不完全的现象，影响灰阶精确控制，进而影响显示效果。
本公开实施例提供一种驱动电路，用于驱动待驱动元件工作，图1为本公开实施例提供的驱动电路的结构示意图，如图1所示，该驱动电路与待驱动元件L串联于第一工作电压端VL1和第二工作电压端VL2之间，该驱动电路被配置为控制第一工作电压端VL1和第二工作电压端VL2之间形成电流通路。
在一些示例性实施例中，待驱动元件L可以为发光元件，例如微型发光二极管，例如Micro LED，待驱动元件L的阳极与第四节点N4连接，待驱动元件的阴极与第二工作电压端VL2连接。Micro LED的尺寸级别为微米(μm)级别。本公开实施例是以待驱动元件L为发光元件作为示例进行描述。可以理解，待驱动元件L可以为其他流控型电子元器件。
如图1所示，本公开实施例提供的驱动电路包括：驱动子电路、写入子电路、补偿子电路和灰阶控制子电路。
驱动子电路，分别与第一节点N1、第二节点N2和第三节点N3连接， 被配置为在第一节点N1和第二节点N2的控制下，向第三节点N3提供驱动电流；写入子电路分别与第一扫描信号端G_A、第一数据信号端D_A以及第二节点N2连接，被配置为在第一扫描信号端G_A的控制下，将第一数据信号端D_A的信号(即，第一数据电压V D_A)写入第二节点N2；补偿子电路分别与第一工作电压端VL1、第一扫描信号端G_A、第一节点N1以及第三节点N3连接，被配置为在第一扫描信号端G_A和第一工作电压端VL1的控制下，对第一节点N1进行补偿；灰阶控制子电路分别与第一工作电压端VL1、发光控制端EM(作为驱动控制信号端)、第二节点N2、第三节点N3、第四节点N4、第二扫描信号端G_B、第二数据信号端D_B、第一电压端V1连接，被配置为在发光控制端EM、第二扫描信号端G_B和第二数据信号端D_B的控制下，向第四节点N4提供驱动电流，以控制电流通路的导通时长。
综上所述，写入子电路能够将与显示灰阶有关的第一数据电压V D_A输出至驱动子电路，以使得驱动子电路能够产生用于驱动发光元件L发光的驱动电流I。此外，灰阶控制子电路可以控制驱动电流I在流入发光元件L的过程中，所形成的电流通路的导通时长，从而控制发光元件L的发光时长。由于驱动电流I的大小和导通时长影响发光元件的L的有效亮度，这样一来，在一个扫描周期内，通过第一数据电压V D_A的大小以及灰阶控制子电路可以控制发光元件L有效发光亮度，达到调节显示灰阶的目的。根据本公开实施例，由于每个驱动电路中均设置有灰阶控制子电路，并且对于同一行的亚像素对应的多个驱动电路而言，所包括的每个灰阶控制子电路连接至不同的数据信号线(即，受到彼此独立的第二数据电压V D_B的控制)，因此，本公开实施例提供的驱动电路可以直接对该驱动电路中的发光元件L(例如Micro LED)的亮度单独进行控制。此外。本公开实施例提供的驱动电路可以通过构图工艺制作于显示装置的显示面板中的玻璃衬底或树脂衬底上。在发光元件为Micro LED时，能够提供一种成本较低、制作工艺简单，可量产的Micro LED显示装置的实现方式。
本公开实施例提供的驱动电路，通过补偿子电路在第一扫描信号端G_A和第一工作电压端VL1的控制下，对第一节点N1进行补偿，实现了灰阶的精确控制，提升了显示面板的显示品质。
本公开实施例中，该驱动电路被配置为提供驱动电流I，并控制第一工作电压端VL1和第二工作电压端VL2之间电流通路的导通时长。
在电流通路导通时，第一工作电压端VL1输出的第一工作电压VDD与第二工作电压端VL2输出的第二工作电压VSS可以向电流通路提供电势差，使得驱动电流I能够沿电流通路传输至发光元件L。
在一些示例性实施例中，第一工作电压VDD可以为恒定的高电平，第二工作电压VSS可以为恒定的低电平。
发光元件L被配置为在电流通路中接收驱动电流I，并发光。
在一些示例性实施例中，如图2所示，该驱动电路还可包括复位子电路。
该复位子电路，分别与复位控制信号端RST、复位电压端VINT以及第一节点N1连接，被配置为在复位控制信号端RST的控制下，将复位电压端VINT的信号写入第一节点N1。
该复位子电路可以对驱动晶体管Td的栅极进行复位，避免上一图像帧残留于驱动晶体管Td的电压对本图像帧的显示造成影响。此时，第一节点N1的电压为复位电压端VINT提供的复位电压。
在一些示例性实施例中，图3为本公开实施例提供的复位子电路和写入子电路的等效电路图，如图3所示，本公开实施例提供的复位子电路包括：第一晶体管T1，写入子电路包括：第二晶体管T2。
第一晶体管T1的控制极与复位控制信号端RST连接，第一晶体管T1的第一极与复位电压端VINT连接，第一晶体管T1的第二极与第一节点N1连接；第二晶体管T2的控制极与第一扫描信号端G_A连接，第二晶体管T2的第一极与第一数据信号端D_A连接，第二晶体管T2的第二极与第二节点N2连接。
图3中示出了复位子电路和写入子电路的一种示例性结构。本领域技术人员容易理解是，复位子电路和写入子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在一些示例性实施例中，图4为本公开实施例提供的补偿子电路的等效电路图，如图4所示，本公开实施例提供的补偿子电路包括：第三晶体管T3、 第一电容C1和第二电容C2。
第三晶体管T3的控制极与第一扫描信号端G_A连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。
第一电容C1的一端与第一节点N1连接，第一电容C1的另一端与第一工作电压端VL1连接。
第二电容C2的一端与第一节点N1连接，第二电容C2的另一端与第一扫描信号端G_A连接。
图4中示出了补偿子电路的一种示例性结构。本领域技术人员容易理解是，补偿子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施例中，图5为本公开实施例提供的驱动子电路的等效电路图，如图5所示，本公开实施例提供的驱动子电路包括：驱动晶体管Td。
驱动晶体管Td的控制极与第一节点N1连接，驱动晶体管Td的第一极与第二节点N2连接，驱动晶体管Td的第二极与第三节点N3连接。
图5中示出了驱动子电路的一种示例性结构。本领域技术人员容易理解是，驱动子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施例中，补偿子电路，被配置为在第一扫描信号端G_A和第一工作电压端VL1的控制下，对第一节点N1进行补偿，直至第一节点N1的信号的电压值为理想电压值，该第一节点N1的理想电压值等于第一数据信号端的电压值V D_A与驱动晶体管的阈值电压Vth之和。
在一些示例性实施例中，如图6所示，灰阶控制子电路包括：第一控制子电路和第二控制子电路。
第一控制子电路，分别与第一工作电压端VL1、发光控制端EM、第二节点N2、第三节点N3和第五节点N5连接，被配置为在发光控制端EM的控制下，向第二节点N2提供第一工作电压端VL1的信号，向第五节点N5提供第三节点N3的信号。
第二控制子电路，分别与第四节点N4、第五节点N5、第二扫描信号端G_B、第二数据信号端D_B和第一电压端V1(该第一电压端V1可以为接地端GND)连接，被配置为在第二扫描信号端G_B和第二数据信号端D_B的 控制下，向第四节点N4提供第五节点N5的信号。
由上述可知，只有当第一控制子电路和第二控制子电路均处于开启状态时，电流通路才能够导通，驱动子电路产生的驱动电流I才能够通过电流通路输出至发光元件L。这样一来，发光元件L的有效发光亮度可以受到驱动电流I、第一控制子电路以及第二控制子电路的协同控制，增加了影响发光元件L的有效发光亮度的因素，使得具有该驱动电路的亚像素能够显示的灰阶值更加多样化。
在一些示例性实施例中，图7为本公开实施例提供的第一控制子电路的等效电路图，如图7所示，本公开实施例提供的第一控制子电路包括第四晶体管T4和第五晶体管T5。
第四晶体管T4的控制极与发光控制端EM连接，第四晶体管T4的第一极与第一工作电压端VL1连接，第四晶体管T4的第二极与第二节点N2连接；第五晶体管T5的控制极与发光控制端EM连接，第五晶体管T5的第一极与第三节点N3连接，第五晶体管T5的第二极与第五节点N5连接。
图7中示出了第一控制子电路的一种示例性结构。本领域技术人员容易理解是，第一控制子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施例中，图8为本公开实施例提供的第二控制子电路的等效电路图，如图8所示，本公开实施例提供的第二控制子电路包括第三电容C3、第六晶体管T6和第七晶体管T7。
第六晶体管T6的控制极与第二扫描信号端G_B连接，第六晶体管T6的第一极与第二数据信号端D_B连接，第六晶体管T6的第二极与第六节点N6连接；第七晶体管T7的控制极与第六节点N6连接，第七晶体管T7的第一极与第五节点N5连接，第七晶体管T7的第二极与第四节点N4连接；第三电容C3的一端与第六节点N6连接，第三电容C3的另一端与第一电压端V1连接。
图8中示出了第二控制子电路的一种示例性结构。本领域技术人员容易理解是，第二控制子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施例中，图9为本公开实施例提供的驱动电路的等效电 路图，如图9所示，本公开实施例提供的驱动电路中，复位子电路包括：第一晶体管T1；写入子电路包括：第二晶体管T2；补偿子电路包括：第三晶体管T3、第一电容C1和第二电容C2；驱动子电路包括：驱动晶体管Td；第一控制子电路包括：第四晶体管T4和第五晶体管T5；第二控制子电路包括：第三电容C3、第六晶体管T6和第七晶体管T7。
第一晶体管T1的控制极与复位控制信号端RST连接，第一晶体管T1的第一极与复位电压端VINT连接，第一晶体管T1的第二极与第一节点N1连接；第二晶体管T2的控制极与第一扫描信号端G_A连接，第二晶体管T2的第一极与第一数据信号端D_A连接，第二晶体管T2的第二极与第二节点N2连接；第三晶体管T3的控制极与第一扫描信号端G_A连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接；第一电容C1的一端与第一节点N1连接，第一电容C1的另一端与第一工作电压端VL1连接；第二电容C2的一端与第一节点N1连接，第二电容C2的另一端与第一扫描信号端G_A连接；驱动晶体管Td的控制极与第一节点N1连接，驱动晶体管Td的第一极与第二节点N2连接，驱动晶体管Td的第二极与第三节点N3连接；第四晶体管T4的控制极与发光控制端EM连接，第四晶体管T4的第一极与第一工作电压端VL1连接，第四晶体管T4的第二极与第二节点N2连接；第五晶体管T5的控制极与发光控制端EM连接，第五晶体管T5的第一极与第三节点N3连接，第五晶体管T5的第二极与第五节点N5连接；第六晶体管T6的控制极与第二扫描信号端G_B连接，第六晶体管T6的第一极与第二数据信号端D_B连接，第六晶体管T6的第二极与第六节点N6连接；第七晶体管T7的控制极与第六节点N6连接，第七晶体管T7的第一极与第五节点N5连接，第七晶体管T7的第二极与第四节点N4连接；第三电容C3的一端与第六节点N6连接，第三电容C3的另一端与第一电压端V1连接。
图9中示出了驱动电路中驱动子电路、复位子电路、写入子电路、补偿子电路、第一控制子电路和第二控制子电路的示例性结构。本领域技术人员容易理解是，以上各子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在一些示例性实施例中，第一电容C1的电容量与第二电容C2的电容量满足：C2/(C1+C2)＝ΔV/ΔVg，其中，ΔV为对第一节点N1补偿后，第一节点N1的实际电压值与理想电压值之间的差值，第一节点N1的理想电压值等于第一数据信号端D_A的电压值V D_A与驱动晶体管的阈值电压Vth之和，ΔVg为第一扫描信号端G_A的跳变电压值。
本公开实施例的补偿子电路包括一个第二电容C2。在补偿阶段，第一数据信号端D_A的信号通过第二晶体管T2写入至第二节点N2，第三节点N3的电压(V D_A+Vth)经由第三晶体管T3写入至第一节点N1，即对第一节点N1进行充电，此处，Vth为驱动晶体管Td的阈值电压。第一节点N1充电的快慢，即充电电流的大小取决于驱动晶体管Td的打开状态，驱动晶体管Td的打开状态受其栅源之间的压差控制，随着补偿的进行，第一节点N1电压V N1慢慢接近(V D_A+Vth)，且越接近(V D_A+Vth)，其充电速度越慢，在有限的时间(例如，1H，1H表示1行像素的充电时间)内不能将第一节点N1电压V N1充电至(V D_A+Vth)，假设第一节点N1电压V N1与(V D_A+Vth)之间的差距值为ΔV，即将第一节点N1充电至(V D_A+Vth-ΔV)。对于不同的灰阶，差距电压ΔV引起的亮度差异不同。在时间数据信号写入子阶段，第一扫描信号端G_A输入的电平由低变高，假设第一扫描信号端G_A的跳变电压为ΔVg，通过与第一节点N1相连的第二电容C2将第一节点N1电位拉高，从而补偿差距电压ΔV。
在本实施例中，第一晶体管T1至第七晶体管T7、驱动晶体管Td均可以为N型薄膜晶体管或P型薄膜晶体管，可以统一工艺流程，能够减少工艺制程，有助于提高产品的良率。此外，考虑到低温多晶硅薄膜晶体管的漏电流较小，因此，本公开实施例的所有晶体管可以为低温多晶硅薄膜晶体管，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。
在一些示例性实施例中，第一电容C1至第三电容C3可以是由像素电极与公共电极构成的液晶电容，也可以是由像素电极与公共电极构成的液晶电容以及存储电容构成的等效电容，本公开对此不作限定。
下面以第一级驱动电路的工作过程为例，通过驱动电路的工作过程来说 明本公开实施例的技术方案。
以本公开实施例提供的驱动电路中的晶体管T1至T7、Td均为P型薄膜晶体管为例，图10为本公开实施例提供的驱动电路的工作时序图，如图9和图10所示，本公开实施例提供的驱动电路包括8个晶体管单元(T1～T7、Td)、3个电容单元(C1～C3)、7个信号输入端(G_A、G_B、RST、D_A、D_B、VINT和EM)和3个电源端(VL1、VL2和V1)，为描述方便，图9还示出了发光元件L。
如图9所示，该驱动电路与发光元件L的阳极电连接，并驱动发光元件L发光，发光元件L的阴极与第二工作电压端VL2连接。该驱动电路被配置为驱动发光元件L发光，该驱动电路与发光元件L串联于第一工作电压端VL1和第二工作电压端VL2之间，该驱动电路被配置为控制第一工作电压端VL1和第二工作电压端VL2之间形成电流通路；该驱动电路包括：驱动子电路、写入子电路、补偿子电路和灰阶控制子电路。在本实施例中，发光元件L的阴极也可以与第一电压端V1(公共电压线)相连，以接收第一电压端V1提供的公共电压，例如，发光元件L的阴极接地。
下面结合图10对图9所示的驱动电路的工作原理进行示例性说明。
如图10所示，在显示一帧画面的过程中，驱动电路具有复位阶段S1、补偿阶段S2以及多个发光阶段EM1至EMn，复位阶段S1、补偿阶段S2以及多个发光阶段EM1至EMn可以在时间上顺次设置。如图9所示，每个发光阶段包括时间数据信号写入子阶段S3、S5……，和有效发光子阶段S4、S6……。
复位阶段S1，复位控制信号端RST的输入信号为低电平，第一晶体管T1导通，向第一节点N1提供复位电压端RST的信号，以对第一节点N1进行复位，为补偿阶段导通驱动晶体管Td做准备。
补偿阶段S2，第一扫描信号端G_A的输入信号为低电平，第二晶体管T2和第三晶体管T3导通，第二晶体管T2将第一数据信号端D_A的显示数据信号写入至第二节点N2，由于第一节点N1与第二节点N2的信号的电压差小于驱动晶体管Td的阈值电压Vth，因此，驱动晶体管Td导通，第一节点N1、第二节点N2和第三节点N3相互导通，第一工作电压端VL1向第一 节点N1进行充电，此时，第一节点N1的信号的电压值V N1等于V D_A+Vth-ΔV。
第一节点N1充电的快慢取决于驱动晶体管Td的打开状态，驱动晶体管Td的打开状态受其栅源之间的压差控制，在此种情况下，栅源之间的压差为(V N1-V D_A)，其中，V N1为第一节点N1的信号的电压值。随着补偿的进行，第一节点N1电压V N1慢慢接近(V D_A+Vth)，且越接近(V D_A+Vth)，其充电速度越慢，在有限的时间(例如，一行像素的充电时间1H)内不能将第一节点N1电压V N1充电至(V D_A+Vth)，假设第一节点N1电压V N1与(V D_A+Vth)之间的差距值为ΔV，即将第一节点N1充电至(V D_A+Vth-ΔV)。对于不同的灰阶，差距电压ΔV引起的亮度差异不同。
时间数据信号写入子阶段S3，第二扫描信号端G_B的输入信号为低电平，第六晶体管T6导通。第六晶体管T6将第二数据信号端D_B的时间数据信号写入至第六节点N6，并存储在第三电容C3。第七晶体管T7的导通与否取决于存储在第三电容C3中的时间数据信号。例如，在时间数据信号为有效电平(例如，低电平)的情况下，第七晶体管T7导通。
在时间数据信号写入子阶段S3，第一扫描信号端G_A输入信号的电平由低变高，假设第一扫描信号端G_A的电压跳变值为ΔVg，通过与第一节点N1相连的第二电容C2将第一节点N1电位拉高，从而补偿差距电压ΔV。假设由第一扫描信号端G_A的跳变电压ΔVg引起的第一节点N1的电位跳变值为ΔV N1，则ΔV N1的大小为(C2*ΔVg)/(C1+C2)。令(C2*ΔVg)/(C1+C2)＝ΔV，得到C2/(C1+C2)＝ΔV/ΔVg，从而在电路设计时，将第一电容C1、第二电容C2的电容量按照该比例进行设置。一般情况下，ΔVg为十几伏，例如14伏；ΔV仅为零点几伏，例如0.2伏，举例所示的C2/(C1+C2)的值为0.2/14＝1.4％，由于第二电容C2的电容量较小，第二电容C2的加入在提升显示效果的同时不会影响高像素密度(Pixels Per Inch，简称PPI)。
有效发光子阶段S4，发光控制端EM的输入信号为低电平，因此，第四晶体管T4和第五晶体管T5导通，此外，驱动晶体管Td导通，且驱动晶体 管Td中产生的驱动电流Ids满足以下的表达式：
Ids＝K(Vg-Vs-Vth) 2
＝K((V D_A+Vth)-VDD-Vth) 2
＝K(V D_A-VDD) 2；
这里，K＝1/2×W/L×C×μ，其中，W为驱动晶体管Td的沟道的宽度，L为驱动晶体管Td的沟道的长度，W/L为驱动晶体管Td的沟道的宽长比(即，宽度与长度的比值)，μ为电子迁移率，C为单位面积的电容。
在时间数据信号使得第七晶体管T7导通的情况下，驱动晶体管Td中产生的驱动电流Ids经由导通的第五晶体管T5和第七晶体管T7提供给发光元件L。由于驱动晶体管Td中产生的驱动电流Ids与驱动晶体管Td的阈值电压Vth无关，由此提升了包含上述驱动电路的像素单元的灰阶准确性。
如图10所示，在一帧画面的时间段内，一个驱动电路包括多个发光阶段，例如，包括第一发光阶段EM1、第二发光阶段EM2、……以及第N发光阶段EMn，图10中只示出了两个发光阶段：第一发光阶段EM1、第二发光阶段EM2。在各个发光阶段中，发光控制端EM提供的发光控制信号的占空比可以不同。
在本实施例中，包含该驱动电路的像素单元在显示一帧画面的过程中的总体亮度可通过叠加该像素子电路中的发光元件L在多个发光阶段发光亮度获得。相应地，上述每帧画面可以通过第二控制子电路进行多次时间数据信号写入操作。
在本实施例中，上述驱动电路以及驱动电路的驱动方法可以使得像素单元的微LED工作在高电流密度的情况下显示例如低灰阶。例如，可以通过降低工作在高电流密度下的微LED的发光时间来使得包括该微LED的像素单元显示低灰阶。例如，可以通过控制工作在高电流密度下的微LED的发光时间和/或驱动电流的电流密度来使得包括该微LED的像素单元显示所需的灰阶。
本公开一些实施例还提供一种显示装置，包括显示面板，该显示面板的 显示区域具有多个如图11所示的亚像素02，至少一个亚像素02内设置有如上所述的任意一种驱动电路01。
亚像素02可以由横纵交叉的第一扫描信号线G_A与第一数据信号线D_A交叉界定。此外，第二扫描信号线G_B可以与第一扫描信号线G_A平行设置，第二数据信号线D_B可以与第一数据信号线D_A平行设置。
由图11可以看出，位于同一行的亚像素，其驱动电路01中的第四晶体管T4连接同一条发光控制信号端EM。在此情况下，当该发光控制信号端EM提供有效信号，例如如图10所示的低电平时，位于同一行的多个第四晶体管T4和第五晶体管T5均导通。
基于此，为了使得同一行中不同亚像素的发光亮度可以单独控制，可以通过第二扫描信号端G_B输入有效信号控制第六晶体管T6导通，然后，在第六晶体管T6导通后，通过第二数据信号端D_B提供的第二数据电压Vdata_B为有效信号时，控制第七晶体管T7的导通，从而使得第一工作电压端VL1与第二工作电压端VL2之间的电流通路导通。
驱动晶体管Td产生的驱动电流I能够通过电流通路传输至发光元件L。该电流通路导通的时间越长，发光元件L在一个扫描周期内的有效发光亮度越高。此外，还可以通过调整第一数据信号端D_A提供的第一数据电压Vdata_A的大小，达到调整驱动电流I的大小。该驱动电流I越大，发光元件L在一个扫描周期内的有效发光亮度越高。
根据本公开的实施例，如图10所示，在一个图像帧内存在多个发光阶段EM1至EMn。各个发光阶段彼此不同。因此，可以根据发光元件的期望的发光时长来选择相应的一个或多个发光阶段，使得在该一个或多个发光阶段发光元件发光，从而能够得到多种不同的灰阶亮度。根据本公开的另一实施例，一个图像帧的多个发光阶段可以彼此相同。因此也可以根据发光元件的期望的发光时长来选择一个或多个发光阶段，使得在该一个或多个发光阶段发光元件发光，以改变发光元件的发光时长，并可以得到多种不同的灰阶。
可以看出，在一个图像帧内存在多个发光阶段且每个发光阶段的长度都不同的情况下，能够扩大发光元件的发光时长和有效亮度的可调节范围，丰富显示面板的能够显示的灰阶数量。
综上所述，在发光控制信号端EM提供的发光控制信号的控制下，一行驱动电路01中的所有亚像素可以实现同时发光，但是无法单独控制各亚像素的发光亮度和发光时长。然而，根据本公开实施例提供的驱动电路，可以在发光控制信号端EM、第一扫描信号端G_A、第二扫描信号端G_B、第一数据信号端D_A以及第二数据信号端D_B的共同协作下，实现单个亚像素发光亮度的调节。
显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。其中，该显示装置具有与前述实施例提供的驱动电路01相同的技术效果，此处不再赘述。
本公开一些实施例还提供一种驱动电路的驱动方法，应用于前述实施例提供的驱动电路中，在一图像帧内，驱动电路具有多个扫描周期。驱动电路中的灰阶控制子电路包括第一控制子电路和第二控制子电路。
在一个扫描周期S(例如第一扫描周期S1)内，该驱动电路的驱动方法，如图12所示，包括步骤100至103。
步骤101、向第一工作电压端提供第一工作电压，向第一扫描信号端提供第一扫描信号，向第一数据信号端提供显示数据信号，显示数据信号通过写入子电路写入至第二节点，驱动子电路在第一节点和第二节点的控制下开启，补偿子电路在第一工作电压端的控制下对第一节点进行补偿。
在一些示例性实施例中，在将第一数据信号端的显示数据信号写入驱动子电路时，在有限的时间内不能将第一节点电压充电至数据信号端的电压值与驱动晶体管的阈值电压之和，假设第一节点电压与数据信号端的电压值与驱动晶体管的阈值电压之和之间的差距值为ΔV。
步骤102、向第二扫描信号端提供第二扫描信号，向第二数据信号端提供时长数据信号，以使得第二控制子电路在第二扫描信号和时长数据信号的控制下开启或关闭，补偿子电路在第一扫描信号端的控制下，对第一节点再次进行补偿。
在一些示例性实施例中，补偿子电路在第一扫描信号端的控制下，对第一节点再次进行补偿，直至第一节点的信号的电压值为理想电压值，第一节 点的理想电压值等于第一数据信号端的电压值与驱动晶体管的阈值电压之和。
在一些示例性实施例中，假设第一扫描信号端的电压跳变值为ΔVg，通过与驱动子电路的控制端相连的第二电容将第一节点电位拉高(C2*ΔVg)/(C1+C2)，从而补偿差距电压ΔV，其中，C2为第二电容的电容量，C1为第一电容的电容量。
步骤103、向发光控制端提供发光控制信号，第一工作电压通过第一控制子电路传输至第四节点，以使得发光元件在发光控制信号、第一扫描信号、第二扫描信号以及时长数据信号的控制下，基于显示数据信号和第一工作电压发光。
在一些示例性实施例中，驱动子电路产生的驱动电流Ids经由灰阶控制子电路提供给发光元件L。
此外，在驱动电路还包括复位子电路的情况下，步骤101之前，该驱动电路的驱动方法，如图12所示，还包括：
步骤100、向复位控制信号端提供复位控制信号，向复位电压端提供复位电压，该复位电压通过复位子电路传输至第一节点。
在一些示例性实施例中，复位电压可以为低电平，使驱动晶体管处于接近导通而驱动晶体管未能导通的状态，从而为接下来的数据写入阶段期间对驱动晶体管的栅极进行充电做准备，使得第一数据信号端提供的第一数据电压能够更快速地为驱动晶体管的栅极进行充电。因此，在后续的数据写入期间中，当不同的数据电压写入到驱动晶体管时，可以减少数据电压写入的时间，从而使得对于整个显示面板的所有驱动电路而言，所有驱动晶体管的响应时间几乎相同，数据电压的写入时间大致相同，对整个显示面板而言，这种设置方式使得显示效果均一性更高。
本公开提供的技术方案，通过补偿子电路在第一扫描信号端和第一工作电压端的控制下，对第一节点进行补偿，实现了灰阶的精确控制，提升了显示面板的显示品质。
有以下几点需要说明：
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考 通常设计。
在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种驱动电路，用于驱动待驱动元件工作，所述驱动电路与所述待驱动元件串联于第一工作电压端和第二工作电压端之间，所述驱动电路被配置为控制所述第一工作电压端和所述第二工作电压端之间形成电流通路；
    所述驱动电路包括：驱动子电路、写入子电路、补偿子电路和灰阶控制子电路，其中：
    所述驱动子电路，分别与第一节点、第二节点和第三节点连接，被配置为在所述第一节点和所述第二节点的控制下，向所述第三节点提供驱动电流；
    所述写入子电路，分别与第一扫描信号端、第一数据信号端以及所述第二节点连接，被配置为在所述第一扫描信号端的控制下，将所述第一数据信号端的信号写入所述第二节点；
    所述补偿子电路，分别与所述第一工作电压端、所述第一扫描信号端、所述第一节点以及所述第三节点连接，被配置为在所述第一扫描信号端和所述第一工作电压端的控制下，对所述第一节点进行补偿；
    所述灰阶控制子电路，分别与驱动控制信号端、所述第一工作电压端、所述第二节点、所述第三节点、第四节点、第二扫描信号端、第二数据信号端、第一电压端连接，被配置为在所述驱动控制信号端、所述第二扫描信号端和所述第二数据信号端的控制下，向所述第四节点提供驱动电流，以控制所述电流通路的导通时长。
  2. 根据权利要求1所述的驱动电路，还包括：复位子电路；
    所述复位子电路，分别与复位控制信号端、复位电压端以及所述第一节点连接，被配置为在所述复位控制信号端的控制下，将所述复位电压端的信号写入所述第一节点。
  3. 根据权利要求2所述的驱动电路，其中，所述复位子电路包括：第一晶体管，所述写入子电路包括：第二晶体管，其中：
    所述第一晶体管的控制极与所述复位控制信号端连接，所述第一晶体管的第一极与所述复位电压端连接，所述第一晶体管的第二极与所述第一节点 连接；
    所述第二晶体管的控制极与所述第一扫描信号端连接，所述第二晶体管的第一极与所述第一数据信号端连接，所述第二晶体管的第二极与所述第二节点连接。
  4. 根据权利要求1至3任一所述的驱动电路，其中，所述待驱动元件为微型发光二极管，所述待驱动元件的阳极与所述第四节点连接，所述待驱动元件的阴极与所述第二工作电压端连接。
  5. 根据权利要求1至3任一所述的驱动电路，其中，所述补偿子电路包括：第三晶体管、第一电容和第二电容，其中：
    所述第三晶体管的控制极与所述第一扫描信号端连接，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第三节点连接；
    所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一工作电压端连接；
    所述第二电容的一端与所述第一节点连接，所述第二电容的另一端与所述第一扫描信号端连接。
  6. 根据权利要求1至3任一所述的驱动电路，其中，所述驱动子电路包括：驱动晶体管，所述驱动晶体管的控制极与所述第一节点连接，所述驱动晶体管的第一极与所述第二节点连接，所述驱动晶体管的第二极与所述第三节点连接。
  7. 根据权利要求1至3任一所述的驱动电路，其中，所述灰阶控制子电路包括：第一控制子电路和第二控制子电路，其中：
    所述第一控制子电路，分别与所述第一工作电压端、所述驱动控制信号端、所述第二节点、所述第三节点和第五节点连接，被配置为在所述驱动控制信号端的控制下，向所述第二节点提供所述第一工作电压端的信号，向所述第五节点提供所述第三节点的信号；
    所述第二控制子电路，分别与所述第四节点、所述第五节点、所述第二扫描信号端、所述第二数据信号端和所述第一电压端连接，被配置为在所述第二扫描信号端和所述第二数据信号端的控制下，向所述第四节点提供所述第五节点的信号。
  8. 根据权利要求7所述的驱动电路，其中，所述第一控制子电路包括：第四晶体管和第五晶体管，其中：
    所述第四晶体管的控制极与所述驱动控制信号端连接，所述第四晶体管的第一极与所述第一工作电压端连接，所述第四晶体管的第二极与所述第二节点连接；
    所述第五晶体管的控制极与所述驱动控制信号端连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述第四节点连接。
  9. 根据权利要求7所述的驱动电路，其中，所述第二控制子电路包括：第六晶体管、第三电容和第七晶体管，其中：
    所述第六晶体管的控制端与所述第二扫描信号端连接，所述第六晶体管的第一端与所述第二数据信号端连接，所述第六晶体管的第二端与第六节点连接；
    所述第三电容的一端与所述第六节点连接，所述第三电容的另一端与所述第一工作电压端连接；
    所述第七晶体管的控制端与所述第六节点连接，所述第七晶体管的第一端与所述第四节点连接，所述第七晶体管的第二端与所述第五节点连接。
  10. 根据权利要求1所述的驱动电路，还包括：复位子电路，所述灰阶控制子电路包括：第一控制子电路和第二控制子电路，所述复位子电路包括：第一晶体管，所述写入子电路包括：第二晶体管，所述补偿子电路包括：第三晶体管、第一电容和第二电容，所述驱动子电路包括：驱动晶体管，所述第一控制子电路包括：第四晶体管和第五晶体管，第二控制子电路包括：第六晶体管、第三电容和第七晶体管，其中：
    所述第一晶体管的控制极与所述复位控制信号端连接，所述第一晶体管的第一极与所述复位电压端连接，所述第一晶体管的第二极与所述第一节点连接；
    所述第二晶体管的控制极与所述第一扫描信号端连接，所述第二晶体管的第一极与所述第一数据信号端连接，所述第二晶体管的第二极与所述第二节点连接；
    所述第三晶体管的控制极与所述第一扫描信号端连接，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第三节点连接；
    所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一工作电压端连接；
    所述第二电容的一端与所述第一节点连接，所述第二电容的另一端与所述第一扫描信号端连接；
    所述驱动晶体管的控制极与所述第一节点连接，所述驱动晶体管的第一极与所述第二节点连接，所述驱动晶体管的第二极与所述第三节点连接；
    所述第四晶体管的控制极与所述驱动控制信号端连接，所述第四晶体管的第一极与所述第一工作电压端连接，所述第四晶体管的第二极与所述第二节点连接；
    所述第五晶体管的控制极与所述驱动控制信号端连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与第五节点连接；
    所述第六晶体管的控制端与所述第二扫描信号端连接，所述第六晶体管的第一端与所述第二数据信号端连接，所述第六晶体管的第二端与第六节点连接；
    所述第三电容的一端与所述第六节点连接，所述第三电容的另一端与所述第一工作电压端连接；
    所述第七晶体管的控制端与所述第六节点连接，所述第七晶体管的第一端与所述第五节点连接，所述第七晶体管的第二端与所述第四节点连接。
  11. 根据权利要求10所述的驱动电路，其中，所述第一电容与所述第二电容满足：C2/(C1+C2)＝ΔV/ΔVg；
    其中，C1为所述第一电容的电容量，C2为所述第二电容的电容量，ΔV为对所述第一节点补偿后，所述第一节点的实际电压值与理想电压值之间的差值，ΔVg为所述第一扫描信号端的跳变电压值。
  12. 一种显示装置，包括显示基板，所述显示基板包括多个亚像素，至少一个所述亚像素内设置有如权利要求1至11任一项所述的驱动电路和待驱动元件，所述驱动电路被配置为向所述待驱动元件提供驱动信号。
  13. 一种驱动电路的驱动方法，用于驱动如权利要求1至11任一所述的驱动电路，所述灰阶控制子电路包括：第一控制子电路和第二控制子电路，所述驱动电路具有多个扫描周期；在一个所述扫描周期内，所述驱动方法包括：
    向所述第一工作电压端提供第一工作电压，向所述第一扫描信号端提供第一扫描信号，向所述第一数据信号端提供显示数据信号，所述显示数据信号通过所述写入子电路写入至所述第二节点，所述驱动子电路在所述第一节点和所述第二节点的控制下开启，所述补偿子电路在所述第一工作电压端的控制下对所述第一节点进行补偿；
    向所述第二扫描信号端提供第二扫描信号，向所述第二数据信号端提供时长数据信号，以使得所述第二控制子电路在所述第二扫描信号和所述时长数据信号的控制下开启或关闭，所述补偿子电路在所述第一扫描信号端的控制下，对所述第一节点再次进行补偿；
    向所述驱动控制信号端提供驱动控制信号，所述第一工作电压通过所述第一控制子电路传输至所述第四节点，以使得所述待驱动元件在所述驱动控制信号、所述第一扫描信号、所述第二扫描信号以及所述时长数据信号的控制下，基于所述显示数据信号和所述第一工作电压工作。
  14. 根据权利要求13所述的驱动电路的驱动方法，所述方法还包括：所 述补偿子电路在所述第一扫描信号端的控制下，对所述第一节点再次进行补偿，直至所述第一节点的信号的电压值为理想电压值，所述第一节点的理想电压值等于所述第一数据信号端的电压值与驱动晶体管的阈值电压之和。
  15. 根据权利要求13所述的驱动电路的驱动方法，所述方法还包括：向复位控制信号端提供复位控制信号，向复位电压端提供复位电压，该复位电压通过复位子电路传输至第一节点。
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