WO2020001027A1 - 像素驱动电路及方法、显示装置 - Google Patents

像素驱动电路及方法、显示装置 Download PDF

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Publication number
WO2020001027A1
WO2020001027A1 PCT/CN2019/074025 CN2019074025W WO2020001027A1 WO 2020001027 A1 WO2020001027 A1 WO 2020001027A1 CN 2019074025 W CN2019074025 W CN 2019074025W WO 2020001027 A1 WO2020001027 A1 WO 2020001027A1
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Prior art keywords
node
signal
terminal
transistor
circuit
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PCT/CN2019/074025
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English (en)
French (fr)
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陈小海
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/476,673 priority Critical patent/US11380256B2/en
Publication of WO2020001027A1 publication Critical patent/WO2020001027A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit, a pixel driving method, and a display device.
  • OLED Organic Light Emitting Diode
  • the threshold voltages of the driving transistors in different positions may be different due to process variations.
  • the threshold voltage of the driving transistor will drift, which will cause uneven light emission of the OLED display and deteriorate the look and feel of the display screen.
  • An object of the present disclosure is to provide a pixel driving circuit, a pixel driving method, and a display device, so as to at least to some extent overcome the problem of uneven display brightness caused by threshold voltage drift.
  • a pixel driving circuit for driving an electroluminescent element.
  • the pixel driving circuit includes a first switching circuit connected to a first node and configured to be turned on in response to a scanning signal to Transmitting a data signal to the first node; a second switching circuit connected to the first node for conducting a response in response to a control signal to transmit a reference signal to the first node; a first initialization circuit, Connected to the first node and configured to be turned on in response to a reset signal to transmit an initialization signal to the first node; a driving circuit connected to the second node and a third node to respond to the second node Signal is turned on, and a driving current is output to the third node under the action of a first power signal; a second initialization circuit is connected to the second node, and is used to turn on in response to the reset signal to Transmitting the initialization signal to the second node; a compensation circuit is connected to the second node and the third node, and
  • the first switching circuit includes a first transistor, wherein a first terminal of the first transistor is configured to receive the data signal, and a second terminal is connected to the first transistor. A node and a control end for receiving the scanning signal.
  • the second switching circuit includes a second transistor, wherein a first terminal of the second transistor is configured to receive the reference signal, and a second terminal is connected to the first transistor. A node and a control end for receiving the control signal.
  • the first initialization circuit includes a third transistor, wherein a first terminal of the third transistor is configured to receive the initialization signal, and a second terminal is connected to the first transistor. A node and a control end for receiving the reset signal.
  • the second initialization circuit includes a fourth transistor, wherein a first terminal of the fourth transistor is configured to receive the initialization signal, and a second terminal is connected to the second transistor. A node and a control end for receiving the reset signal.
  • the driving circuit includes a driving transistor, wherein a first terminal of the driving transistor is configured to receive the first power signal, and a second terminal is connected to the third node, The control end is connected to the second node.
  • the compensation circuit includes a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second node, a second terminal is connected to the third node, and the control The terminal is used for receiving the scanning signal.
  • the isolation circuit includes a sixth transistor, wherein a first terminal of the sixth transistor is connected to the third node, and a second terminal is connected to the electroluminescent element, The control terminal is configured to receive the control signal.
  • a pixel driving circuit for driving an electroluminescent element including: a first transistor, a first terminal for receiving a data signal, a second terminal connected to a first node, and a control terminal for receiving Scan signal; second transistor, the first terminal is used to receive the reference signal, the second terminal is connected to the first node, the control terminal is used to receive the control signal; the third transistor, the first terminal is used to receive the initialization signal, and the second terminal Connected to the first node, the control terminal is used to receive the reset signal; the driving transistor, the first terminal is used to receive the first power signal, the second terminal is connected to the third node, and the control terminal is connected to the second node; the fourth transistor, the first A terminal is used to receive the initialization signal, a second terminal is connected to the second node, and a control terminal is used to receive the reset signal; a fifth transistor, a first terminal is connected to the second node, and a second terminal is connected to the first node Three
  • the pixel driving method includes: in a reset phase, using the reset signal to turn on the first An initialization circuit and a second initialization circuit, so that the initialization signal is written into the first node and the second node; in the charging phase, the scan signal is used to turn on the first switching circuit and the compensation circuit, so as to Writing the data signal and the threshold voltage of the driving circuit into the energy storage circuit; in the light-emitting stage, using the control signal to turn on the second switching circuit and the isolation circuit, so that the driving circuit is The signal of the second node is turned on, and a driving current is output to the electroluminescent element through the isolation circuit under the action of the first power signal.
  • the voltage of the initialization signal is zero.
  • a display device including the pixel driving circuit according to any one of the above.
  • FIG. 1 is a schematic diagram of a pixel driving circuit according to the present disclosure
  • FIG. 2 is a schematic diagram of a specific structure of a pixel driving circuit according to the present disclosure
  • FIG. 3 is a working timing diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a simulation result of a pixel driving circuit provided by the present disclosure.
  • the pixel driving circuit may include:
  • the first switching circuit 100 is connected to the first node N1 and is configured to be turned on in response to the scanning signal Gate to transmit a data signal VData to the first node N1;
  • the second switching circuit 200 is connected to the first node N1 and is configured to be turned on in response to the control signal EM to transmit the reference signal Vref to the first node N1;
  • the first initialization circuit 300 is connected to the first node N1 and is configured to be turned on in response to a reset signal Reset to transmit an initialization signal Vint to the first node N1;
  • a second initialization circuit 400 connected to the second node N2 and configured to be turned on in response to the reset signal Reset to transmit the initialization signal Vint to the second node N2;
  • the compensation circuit 500 is connected to the second node N2 and the third node N3, and is configured to be turned on in response to the scan signal Gate to connect the second node N2 and the third node N3;
  • the driving circuit 700 is connected to the second node N2 and the third node N3, and is configured to be turned on in response to a signal of the second node, and output a driving current to the third node N3 under the action of the first power signal VDD. ;
  • the isolation circuit 600 is connected to the third node N3 and is configured to be turned on in response to the control signal EM to transmit the driving current to the electroluminescent element;
  • the energy storage circuit 800 is connected between the first node N1 and the second node N2.
  • the second node N2 and the third node N3 are connected, so that the control terminal of the driving circuit and the second terminal are connected to write the threshold voltage of the transistor in the driving circuit and the first power signal.
  • the second node that is, compensating the threshold voltage of the driving circuit, eliminating the influence of the threshold voltage of the driving circuit on the driving current, ensuring that the driving current of each pixel driving circuit is consistent, and thereby ensuring the uniformity of the display brightness of each pixel;
  • the compensation circuit can also eliminate the influence of the first power signal on the voltage between the control terminal and the first terminal of the driving circuit, thereby eliminating the influence of the IR voltage drop of the power supply on the display brightness of each pixel, ensuring the driving of the output of each pixel driving circuit.
  • the current is consistent to ensure the uniformity of the display brightness of each pixel.
  • the first switching circuit includes a first transistor M1
  • the second switching circuit includes a second transistor M2
  • the first initialization circuit includes a third transistor M3
  • the second initialization circuit includes a fourth transistor M4
  • the driving circuit includes a driving transistor M7
  • the compensation circuit includes a fifth transistor M5
  • the isolation circuit includes a sixth transistor M6, and the energy storage circuit includes a storage capacitor C.
  • each of the first to sixth transistors and the driving transistor has a control terminal, a first terminal, and a second terminal.
  • the connection relationship between the first to sixth transistors (M1 to M6) and the driving transistor M7 in the pixel driving circuit is as follows:
  • a first terminal of the first transistor M1 is used to receive the data signal VData, a second terminal is connected to the first node N1, and a control terminal is used to receive the scan signal Gate; the first terminal of the second transistor M2 A terminal is used to receive the reference signal Vref, a second terminal is connected to the first node N1, a control terminal is used to receive the control signal EM, and a first terminal of the third transistor M3 is used to receive the initialization signal Vint
  • a second terminal is connected to the first node N1, a control terminal is used to receive the reset signal Reset; a first terminal of the driving transistor M7 is used to receive the first power signal VDD, and a second terminal is connected to the first node Three nodes N3, the control terminal is connected to the second node N2; the first terminal of the fourth transistor M4 is used to receive the initialization signal Vint, the second terminal is connected to the second node N2, and the control terminal is used to receive all The reset signal is reset; a first terminal of the fifth transistor M5 is connected
  • each transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or, the first terminal and the second terminal of the transistor may be interchanged.
  • all transistors can be N-type thin film transistors or P-type thin film transistors. It should be noted that, for different transistor types, the level signal at each signal terminal needs to be adjusted and changed accordingly.
  • the thin film transistor may be one or more of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor.
  • the first terminal of the transistor may be a source, and the second terminal of the transistor may be a drain.
  • the first end of the transistor may be a drain, and the second end of the transistor may be a source.
  • the above-mentioned transistor may also be another type of transistor, which is not particularly limited in this exemplary embodiment.
  • each transistor may be an enhancement type transistor or a depletion type transistor, which is not particularly limited in this exemplary embodiment. It should be noted that the source and drain of the transistor are symmetrical, so the source and drain of the transistor are interchangeable.
  • the driving transistor M7 has a control terminal, a first terminal, and a second terminal.
  • the control terminal of the driving transistor M7 may be a gate
  • the first terminal may be a source
  • the second terminal may be a drain.
  • the control terminal of the driving transistor M7 may be a gate
  • the first terminal may be a drain
  • the second terminal may be a source.
  • the driving transistor M7 may be an enhancement type driving transistor or a depletion type driving transistor, which is not particularly limited in this exemplary embodiment.
  • the type of the storage capacitor C may be selected according to a specific circuit.
  • it may be a MOS capacitor, a metal capacitor, or a dual poly capacitor, and the present exemplary embodiment does not specifically limit this.
  • the electroluminescent element L is a current-driven electroluminescent element, which is controlled to emit light by the current flowing through the driving transistor M7.
  • the electroluminescent element may be an OLED, but the electroluminescence in the exemplary embodiment The element L is not limited to this.
  • the electroluminescent element L has a first electrode and a second electrode.
  • the first pole of the electroluminescent element L may be an anode, and the second pole may be a cathode.
  • the first and second electrodes of the electroluminescent element L are also interchangeable.
  • the first electrode of the electroluminescent element L is connected to the first terminal of the sixth transistor, and the second electrode is connected to the second power supply signal VSS.
  • the scanning signal Gate in each pixel driving circuit can be multiplexed to realize progressive scanning.
  • the pixel driving circuit and The N-1th and Nth scanning signal lines are connected; wherein the Nth scanning signal line is used to output the scanning signal Gate, and the N-1th scanning signal line is used to output the reset signal Reset; and N is a positive integer.
  • a pixel driving method is also provided for driving a pixel driving circuit as shown in FIGS. 1 and 2.
  • the transistors are P-type thin film transistors
  • the first end of the transistor is a source
  • the second end of the transistor is a drain
  • the on-signals of the transistors are low-level signals
  • the off-signals of the transistors are High-level signal.
  • the driving timing diagram shows a control signal EM, a scan signal Gate, an initialization signal Vint, a data signal VData, a reference signal Vref, a reset signal Reset, and a first power signal VDD, where the first power signal VDD maintains a high-level signal and does not
  • the reference signal Vref remains smaller than the data signal VData, and the voltage of the initialization signal Vint may be 0, for example. It should be noted that keeping the initialization signal Vint at a low level signal can reduce or eliminate the influence of the initialization signal on the driving current.
  • the working process of the pixel driving circuit may specifically include the following stages:
  • the first initialization circuit and the second initialization circuit may be turned on by using the reset signal Reset, so that the initialization signals are written into the first node and the second node.
  • the second transistor M2 and the sixth transistor M6 are turned off by the high-level signal of the control signal EM, and the first transistor M1 and the fifth transistor are turned off by the high-level signal of the scan signal Gate.
  • the transistor M5 is turned off; under the action of the low-level signal of the reset signal Reset, the third transistor M3 and the fourth transistor M4 are turned on.
  • the initialization signal Vint can be transmitted to the first node N1 through the third transistor M3, and the initialization signal Vint can be transmitted to the second node N2 through the fourth transistor M4. Since the initialization signal Vint in the T1 stage is a low-level signal, Therefore, the first node and the second node are both low-level signals, and further driven by the low-level signal of the second node N2, the driving transistor M7 is turned on to transmit the first power signal VDD to the third node through the driving transistor M7. Node N3.
  • the first switching circuit 100 and the compensation circuit 500 may be turned on by using the scanning signal Gate, so that the data signal and the threshold voltage of the driving circuit 700 are written into the energy storage circuit. 800.
  • the first transistor M1 and the fifth transistor M5 are turned on by the low-level signal of the scan signal Gate; the third transistor M3 and the third transistor M3 are turned on by the high-level signal of the reset signal Reset.
  • the fourth transistor M4 is turned off; under the action of the high-level signal of the control signal EM, the second transistor M2 and the sixth transistor M6 are turned off.
  • the data signal VData can be transmitted to the first node N1 through the first transistor M1, and the voltage of the first node is VData at this time; since the fifth transistor M5 is turned on, the control terminal of the driving transistor M7 and the second The terminals are connected, so that the first power supply signal VDD and the threshold voltage Vth of the driving transistor M7 are written to the second node N2. Therefore, the voltage of the second node N2 is VDD + Vth, so that the storage capacitor is processed by the first node and the second node. Charging realizes the function of writing the data signal VData and the threshold voltage Vth of the driving circuit into the energy storage circuit.
  • the driving transistor M7 since the driving transistor M7 is turned on, the first power supply signal VDD and the threshold voltage Vth of the driving transistor M7 can be written. Enter the third node N3. In this stage, the storage capacitor C can be directly charged by the first power supply signal VDD, so that the capacity charging speed can be greatly improved.
  • the scanning signal Gate will pull up the voltage of the first node N1 and the second node N2 through the parasitic capacitance coupling.
  • the control signal EM can be used to turn on the second switching circuit 200 and the isolation circuit 600, so that the driving circuit 700 is turned on under the action of the voltage signal of the second node N2, and the first A power supply signal VDD outputs a driving current to the electroluminescent element L through the isolation circuit 600.
  • the first transistor M1 and the fifth transistor M5 are turned off by the high-level signal of the scanning signal Gate; the third transistor M3 and the fourth transistor are turned off by the high-level signal of the reset signal Reset.
  • the transistor M4 is turned off; under the action of the low-level signal of the control signal EM, the second transistor M2 and the sixth transistor M6 are turned on.
  • the reference signal Vref can be transmitted to the first node N1 through the second transistor M2.
  • the voltage of the first node N1 is Vref
  • the voltage change of the first node relative to the previous stage is Vref-VData.
  • the voltage of the second node N2 changes by the same amount on the basis of the T2 phase, that is, the voltage of the second node N2 changes from VDD + Vth in the T2 phase to VDD + Vth in the T3 phase. + Vref-VData.
  • the change amount Vref-VData of the voltage at the T3 stage of the N1 node with respect to the voltage at the T2 stage is negative.
  • Vref-VData In the voltage VDD + Vth + Vref-VData of the second node N2, Vref-VData is negative, so the difference between VDD + Vth + Vref-VData and the first power signal VDD is less than the threshold voltage Vth of the driving transistor M7, then the driving transistor M7 can be turned on by the voltage signal of the second node N2, and can output a driving current under the function of the first power signal VDD. The driving current is transmitted to the electroluminescent element L through the sixth transistor M6 to drive the electroluminescent element. Glow.
  • the reference signal Vref can be set to be smaller than the data signal VData, so that the driving transistor M7 is turned on.
  • the reference signal Vref can be set to -1V or 0V or 1V, and the data signal VData can be set to between 2V and 5V. As long as the reference signal Vref is less than the minimum value of the data signal VData, the driving transistor M7 can be turned on.
  • the threshold voltage Vth is negative here. If the difference between VDD + Vth + Vref-VData and the first power signal VDD is smaller than the threshold voltage Vth of the driving transistor M7 , The driving transistor M7 can be turned on by the voltage signal of the second node N2 and output the driving current under the function of the first power signal VDD. The driving current is transmitted to the electroluminescent element L through the sixth transistor M6 to drive The electroluminescent element emits light.
  • the voltage of the first electrode of the electroluminescent element L becomes the on-voltage VL of the electroluminescent element L
  • the voltage of the first node N1 is a reference voltage Vref
  • the voltage of the second node N2 becomes VX.
  • the charge in the pixel driving circuit in the T2 stage is the same as that in the pixel driving circuit in the T3 stage:
  • VX VDD + Vth-VData + Vref
  • the driving current is independent of the threshold voltage Vth of the driving transistor M7 and the voltage of the first power supply signal VDD.
  • the first power signal VDD is written into the second node N2, that is, the threshold voltage Vth of the driving transistor M7 is compensated, the influence of the threshold voltage Vth of the driving transistor M7 on the driving current is eliminated, and the driving current output by each pixel driving circuit is consistent, Furthermore, the uniformity of the display brightness of each pixel is ensured; at the same time, the influence of the first power signal VDD on the voltage between the control terminal and the first terminal of the driving transistor M7 is eliminated, thereby eliminating the influence of the voltage drop loss of the power IR on the display brightness of each pixel. In order to ensure that the driving current output by the driving circuit of each pixel is consistent at the light emitting stage, the uniformity of display brightness of each pixel is ensured. In addition, the pixel driving circuit in this example can also reduce the jitter of the first power signal VDD, and can also reduce the power consumption by lowering the reference voltage.
  • the use of full P-type thin film transistors has the following advantages: strong noise suppression; low-level conduction, and low-level charge management is easy to achieve; P-type thin film transistors have a simple manufacturing process and a relative price Lower; P-type thin film transistor has better stability.
  • all transistors are P-type thin film transistors; however, those skilled in the art can easily obtain a pixel driving circuit in which all transistors are N-type thin film transistors according to the pixel driving circuit provided by the present disclosure. .
  • all the transistors may be N-type thin film transistors. Since the transistors are all N-type thin film transistors, the turn-on signals of the transistors are all high levels, and the first ends of the transistors are all Is the drain, and the second end of the transistor is the source.
  • the pixel driving circuit provided in the present disclosure can also be changed to a CMOS (Complementary Metal Oxide Semiconductor) circuit, etc., which is not limited to the pixel driving circuit provided in this embodiment, and is not repeated here.
  • CMOS Complementary Metal Oxide Semiconductor
  • the exemplary embodiment further provides a display device including the pixel driving circuit described above.
  • the display device may further include: a plurality of scanning lines for providing a scanning signal; a plurality of data lines for providing a data signal; a plurality of pixel driving circuits electrically connected to the scanning lines and the data lines described above; wherein, the The display device may include, for example, any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
  • the control terminal and the second terminal of the driving transistor are connected to write the threshold voltage of the driving transistor and the first power signal to the second node, that is, the threshold value of the driving transistor.
  • the voltage is compensated to eliminate the influence of the threshold voltage of the driving transistor on the driving current, and to ensure that the driving current output by the driving circuit of each pixel is consistent, thereby ensuring the uniformity of the display brightness of each pixel; In addition, it can also eliminate the effect of the first power signal on the driving transistor.
  • the influence of the voltage between the control terminal and the first terminal eliminates the influence of the IR voltage drop of the power supply on the display brightness of each pixel, ensures that the driving current output by each pixel drive circuit is consistent, and ensures the uniformity of display brightness of each pixel.
  • modules or circuits of the device for action execution are mentioned in the detailed description above, this division is not mandatory.
  • the features and functions of two or more modules or circuits described above may be embodied in one module or circuit.
  • the features and functions of a module or circuit described above can be further divided into multiple modules or circuits to be embodied.

Abstract

一种像素驱动电路及像素驱动方法、显示装置。像素驱动电路包括第一开关电路（100）、第二开关电路（200）、第一初始化电路（300）、驱动电路（700）、第二初始化电路（400）、补偿电路（500）、隔离电路（600）和储能电路（800）。

Description

像素驱动电路及方法、显示装置
交叉引用
本申请要求于2018年6月26日提交的申请号为201810705976.7的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及像素驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点越来越多地被应用于高性能显示领域当中。
但是驱动晶体管在制作过程中，由于工艺偏差会导致不同位置的驱动晶体管的阈值电压存在差异。并且随着工作时间延长及使用环境改变，驱动晶体管的阈值电压会发生漂移，则会导致OLED显示器的发光不均匀，使显示画面的观感变差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种像素驱动电路及像素驱动方法、显示装置，进而至少在一定程度上克服由于阈值电压漂移导致的显示亮度不均匀的问题。
根据本公开的一个方面，提供一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：第一开关电路，与第一节点连接，用于响应扫描信号而导通，以将数据信号传输至所述第一节点；第二开关电路，与所述第一节点连接，用于响应控制信号而导通，以将参考信号传 输至所述第一节点；第一初始化电路，与所述第一节点连接，用于响应复位信号而导通，以将初始化信号传输至所述第一节点；驱动电路，与第二节点以及第三节点连接，用于响应所述第二节点的信号而导通，并在第一电源信号的作用下输出驱动电流至所述第三节点；第二初始化电路，与所述第二节点连接，用于响应所述复位信号而导通，以将所述初始化信号传输至所述第二节点；补偿电路，与所述第二节点以及所述第三节点连接，用于响应所述扫描信号而导通，以联通所述第二节点和所述第三节点；隔离电路，与所述第三节点连接，用于响应所述控制信号而导通，以将所述驱动电流传输至所述电致发光元件；储能电路，连接于所述第一节点和所述第二节点之间。
在本公开的一种示例性实施例中，所述第一开关电路包括第一晶体管，其中：所述第一晶体管的第一端用于接收所述数据信号，第二端连接所述第一节点，控制端用于接收所述扫描信号。
在本公开的一种示例性实施例中，所述第二开关电路包括第二晶体管，其中：所述第二晶体管的第一端用于接收所述参考信号，第二端连接所述第一节点，控制端用于接收所述控制信号。
在本公开的一种示例性实施例中，所述第一初始化电路包括第三晶体管，其中：所述第三晶体管的第一端用于接收所述初始化信号，第二端连接所述第一节点，控制端用于接收所述复位信号。
在本公开的一种示例性实施例中，所述第二初始化电路包括第四晶体管，其中：所述第四晶体管的第一端用于接收所述初始化信号，第二端连接所述第二节点，控制端用于接收所述复位信号。
在本公开的一种示例性实施例中，所述驱动电路包括驱动晶体管，其中：所述驱动晶体管的第一端用于接收所述第一电源信号，第二端连接所述第三节点，控制端连接所述第二节点。
在本公开的一种示例性实施例中，所述补偿电路包括第五晶体管，其中：所述第五晶体管的第一端连接所述第二节点，第二端连接所述第三节点，控制端用于接收所述扫描信号。
在本公开的一种示例性实施例中，所述隔离电路包括第六晶体管，其中：所述第六晶体管的第一端连接所述第三节点，第二端连接所述电 致发光元件，控制端用于接收所述控制信号。
根据本公开的一个方面，提供一种像素驱动电路，用于驱动电致发光元件，包括：第一晶体管，第一端用于接收数据信号，第二端连接第一节点，控制端用于接收扫描信号；第二晶体管，第一端用于接收参考信号，第二端连接所述第一节点，控制端用于接收控制信号；第三晶体管，第一端用于接收初始化信号，第二端连接所述第一节点，控制端用于接收复位信号；驱动晶体管，第一端用于接收第一电源信号，第二端连接第三节点，控制端连接第二节点；第四晶体管，第一端用于接收所述初始化信号，第二端连接所述第二节点，控制端用于接收所述复位信号；第五晶体管，第一端连接所述第二节点，第二端连接所述第三节点，控制端用于接收所述扫描信号；第六晶体管，第一端连接所述第三节点，第二端连接所述电致发光元件，控制端用于接收所述控制信号；存储电容，第一端连接所述第一节点，第二端连接所述第二节点。
根据本公开的一个方面，提供一种像素驱动方法，用于驱动上述任意一项所述的像素驱动电路，所述像素驱动方法包括：在复位阶段，利用所述复位信号导通所述第一初始化电路以及第二初始化电路，以使所述初始化信号写入所述第一节点和所述第二节点；在充电阶段，利用所述扫描信号导通所述第一开关电路以及补偿电路，以使所述数据信号以及所述驱动电路的阈值电压写入所述储能电路；在发光阶段，利用所述控制信号导通所述第二开关电路以及隔离电路，以使所述驱动电路在所述第二节点的信号的作用下导通，并在所述第一电源信号的作用下通过所述隔离电路向所述电致发光元件输出驱动电流。
在本公开的一种示例性实施例中，所述初始化信号的电压为0。
在本公开的一种示例性实施例中，所述复位信号和所述扫描信号的导通时段之间具有一缓冲时段。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的像素驱动电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
附图说明
通过参照附图来详细描述其示例性实施例，本公开的上述和其它特征及优点将变得更加明显。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为本公开一种像素驱动电路的示意图；
图2为本公开一种像素驱动电路的具体结构示意图；
图3为本公开一示例性实施例中提供的像素驱动电路的工作时序图；
图4为本公开提供的像素驱动电路的仿真结果示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免模糊本公开的各方面。
此外，附图仅为本公开的示意性图解，并非一定是按照比例绘制。图中相同的附图标记标识相同或相似的部分，因而将省略对它们的重复描述。
发明人发现，显示器各像素所处的位置不同会导致电源的压降(IR Drop)不同，从而对OLED的驱动电流产生影响。如果不能对阈值电压和电源IR Drop进行补偿，则会导致OLED显示器的发光不均匀，使显示画面的观感变差。
本示例实施方式中提供了一种像素驱动电路，用于驱动电致发光元件，参照图1所示，该像素驱动电路可以包括：
第一开关电路100，与第一节点N1连接，用于响应扫描信号Gate 而导通，以将数据信号VData传输至所述第一节点N1；
第二开关电路200，与所述第一节点N1连接，用于响应控制信号EM而导通，以将参考信号Vref传输至所述第一节点N1；
第一初始化电路300，与所述第一节点N1连接，用于响应复位信号Reset而导通，以将初始化信号Vint传输至所述第一节点N1；
第二初始化电路400，与所述第二节点N2连接，用于响应所述复位信号Reset而导通，以将所述初始化信号Vint传输至所述第二节点N2；
补偿电路500，与所述第二节点N2以及第三节点N3连接，用于响应所述扫描信号Gate而导通，以联通所述第二节点N2和第三节点N3；
驱动电路700，与第二节点N2以及第三节点N3连接，用于响应所述第二节点的信号而导通，并在第一电源信号VDD的作用下输出驱动电流至所述第三节点N3；
隔离电路600，与所述第三节点N3连接，用于响应所述控制信号EM而导通，以将所述驱动电流传输至所述电致发光元件；
储能电路800，连接于所述第一节点N1和所述第二节点N2之间。
通过如上所述补偿电路，一方面，将第二节点N2和第三节点N3联通，从而将驱动电路的控制端和第二端联通，以将驱动电路中晶体管的阈值电压和第一电源信号写入第二节点，即对驱动电路的阈值电压进行补偿，消除驱动电路的阈值电压对驱动电流的影响，确保各像素驱动电路驱动电流一致，进而保证各像素显示亮度的均一性；另一方面，通过该补偿电路还可消除第一电源信号对驱动电路的控制端和第一端之间的电压的影响，从而消除电源IR压降对各像素显示亮度的影响，确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。
下面结合附图对本示例实施方式中的像素驱动电路中各个电路进行详细的说明。参考图2所示，第一开关电路包括第一晶体管M1，所述第二开关电路包括第二晶体管M2，所述第一初始化电路包括第三晶体管M3，所述第二初始化电路包括第四晶体管M4，所述驱动电路包括驱动晶体管M7，所述补偿电路包括第五晶体管M5，所述隔离电路包括第六晶体管M6，所述储能电路包括存储电容C。
如图2中所示，第一晶体管至第六晶体管以及驱动晶体管均具有控 制端、第一端和第二端。在此基础上，上述像素驱动电路中的第一晶体管至第六晶体管(M1～M6)和驱动晶体管M7的连接关系如下：
所述第一晶体管M1的第一端用于接收所述数据信号VData，第二端连接所述第一节点N1，控制端用于接收所述扫描信号Gate；所述第二晶体管M2的第一端用于接收所述参考信号Vref，第二端连接所述第一节点N1，控制端用于接收所述控制信号EM；所述第三晶体管M3的第一端用于接收所述初始化信号Vint，第二端连接所述第一节点N1，控制端用于接收所述复位信号Reset；所述驱动晶体管M7的第一端用于接收所述第一电源信号VDD，第二端连接所述第三节点N3，控制端连接所述第二节点N2；所述第四晶体管M4的第一端用于接收所述初始化信号Vint，第二端连接所述第二节点N2，控制端用于接收所述复位信号Reset；所述第五晶体管M5的第一端连接所述第二节点N2，第二端连接所述第三节点N3，控制端用于接收所述扫描信号Gate；所述第六晶体管M6的第一端连接所述第三节点N3，第二端连接所述电致发光元件L，控制端用于接收所述控制信号EM；所述存储电容C的第一端连接所述第一节点N1，第二端连接所述第二节点N2。
需要说明的是，各晶体管的控制端可以为栅极、第一端可以为源极、第二端可以为漏极；或者，晶体管的第一端和第二端可以互换。在本示例实施方式中，所有晶体管均可以均采用N型薄膜晶体管或者P型薄膜晶体管。需要说明的是：针对不同的晶体管类型，各个信号端的电平信号需要相应的调整变化。所述薄膜晶体管可以为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种或多种。
例如，第一晶体管至第六晶体管均为P型薄膜晶体管时，所述晶体管的第一端均可以为源极，所述晶体管的第二端均可以为漏极。再例如，在所述第一晶体管至第六晶体管均为N型薄膜晶体管时，所述晶体管的第一端均可以为漏极，所述晶体管的第二端可以均为源极。需要说明的是，上述晶体管还可以为其他类型的晶体管，本示例性实施例对此不作特殊限定。
此外，各晶体管可以为增强型晶体管或者耗尽型晶体管，本示例性实施例对此不作特殊限定。需要说明的是，由于晶体管的源极和漏极对 称，因此，晶体管的源极、漏极可以互换。
所述驱动晶体管M7具有控制端、第一端以及第二端。例如，驱动晶体管M7的控制端可以为栅极，第一端可以为源极、第二端可以为漏极。再例如，驱动晶体管M7的控制端可以为栅极，第一端可以为漏极，第二端可以为源极。此外，驱动晶体管M7可以为增强型驱动晶体管或耗尽型驱动晶体管，本示例性实施例对此不作特殊限定。
所述存储电容C的类型可以根据具体的电路进行选择。例如，可以为MOS电容、金属电容或双多晶电容等，本示例性实施例对此不作特殊限定。
所述电致发光元件L为电流驱动型电致发光元件，由流经驱动晶体管M7的电流控制其进行发光，例如，电致发光元件可为OLED，但本示例性实施例中的电致发光元件L不限于此。此外，电致发光元件L具有第一极和第二极。例如，电致发光元件L的第一极可以为阳极，第二极可以为阴极。除此之外，电致发光元件L的第一极和第二极也可互换。电致发光元件L的第一极与第六晶体管的第一端连接，第二极连接第二电源信号VSS。
在阵列排布的多个像素驱动电路中，为了简化阵列排布的多个像素驱动电路的电路结构，可复用各像素驱动电路中的扫描信号Gate实现逐行扫描，所述像素驱动电路与第N-1行以及第N行扫描信号线连接；其中，第N行扫描信号线用于输出所述扫描信号Gate，第N-1行扫描信号线用于输出所述复位信号Reset；且其中的N为正整数。
在本公开的示例性实施例中，还提供了一种像素驱动方法，用于驱动如图1和图2所示的像素驱动电路。下面，以所述晶体管均为P型薄膜晶体管、驱动晶体管为P型驱动晶体管为例，结合图3所示的像素驱动电路的工作时序图对图1和图2中的像素驱动电路的工作过程加以详细的说明。由于晶体管均为P型薄膜晶体管，因此，晶体管的第一端均为源极，晶体管的第二端均为漏极，且晶体管的导通信号均为低电平信号，晶体管的关断信号为高电平信号。该驱动时序图示出了控制信号EM、扫描信号Gate、初始化信号Vint、数据信号VData、参考信号Vref、复位信号Reset、第一电源信号VDD，其中，第一电源信号VDD保持高电平 信号不变，参考信号Vref保持小于数据信号VData，初始化信号Vint的电压例如可为0。需要注意的是，将初始化信号Vint保持低电平信号不变能够减小或消除初始化信号对于驱动电流的影响。
基于此，所述像素驱动电路的工作过程具体可以包括以下阶段：
在T1阶段即复位阶段，可利用所述复位信号Reset导通所述第一初始化电路以及第二初始化电路，以使所述初始化信号写入所述第一节点和所述第二节点。具体而言，在T1阶段，在控制信号EM的高电平信号作用下，第二晶体管M2和第六晶体管M6关闭；在扫描信号Gate的高电平信号作用下，第一晶体管M1和第五晶体管M5关闭；在复位信号Reset的低电平信号作用下，第三晶体管M3和第四晶体管M4导通。如此一来，可将初始化信号Vint通过第三晶体管M3传输至第一节点N1，并将初始化信号Vint通过第四晶体管M4传输至第二节点N2，由于T1阶段初始化信号Vint为低电平信号，因此第一节点和第二节点均为低电平信号，进而在第二节点N2的低电平信号作用下，驱动晶体管M7导通，以将第一电源信号VDD经过驱动晶体管M7传输至第三节点N3。
在T2阶段即充电阶段，可利用所述扫描信号Gate导通所述第一开关电路100以及补偿电路500，以使所述数据信号以及所述驱动电路700的阈值电压写入所述储能电路800。具体而言，在T2阶段，在扫描信号Gate的低电平信号作用下，第一晶体管M1和第五晶体管M5导通；在复位信号Reset的高电平信号作用下，第三晶体管M3和第四晶体管M4关闭；在控制信号EM的高电平信号作用下，第二晶体管M2和第六晶体管M6关闭。如此一来，可将数据信号VData通过第一晶体管M1传输至第一节点N1，此时第一节点的电压为VData；由于第五晶体管M5导通，可将驱动晶体管M7的控制端和第二端联通，从而将第一电源信号VDD和驱动晶体管M7的阈值电压Vth写入第二节点N2，因此第二节点N2的电压为VDD+Vth，以通过第一节点和第二节点对存储电容进行充电，实现将数据信号VData以及所述驱动电路的阈值电压Vth写入所述储能电路的功能，同时由于驱动晶体管M7导通，可将第一电源信号VDD和驱动晶体管M7的阈值电压Vth写入第三节点N3。在该阶段中，可直接通过第一电源信号VDD对存储电容C进行充电，因此能够大幅度提 高电容充电速度。在T2阶段和T3阶段之间，由于存在信号突变，扫描信号Gate会通过寄生电容耦合作用拉高第一节点N1和第二节点N2的电压。
需要说明的是，参考图3所示，在T1阶段和T2阶段之间，复位信号Reset和扫描信号Gate的导通时段之间具有一缓冲时段。通过设置缓冲时段，可减少复位信号和扫描信号之间的串扰。
在T3阶段即发光阶段，可利用控制信号EM导通第二开关电路200以及隔离电路600，以使驱动电路700在所述第二节点N2的电压信号的作用下导通，并在所述第一电源信号VDD的作用下通过所述隔离电路600向所述电致发光元件L输出驱动电流。具体而言，在T3阶段，在扫描信号Gate的高电平信号作用下，第一晶体管M1和第五晶体管M5关闭；在复位信号Reset的高电平信号作用下，第三晶体管M3和第四晶体管M4关闭；在控制信号EM的低电平信号作用下，第二晶体管M2和第六晶体管M6导通。如此一来，可将参考信号Vref经过第二晶体管M2传输至第一节点N1，此时第一节点N1的电压为Vref，且第一节点相对于上一阶段的电压变化量为Vref-VData，同时由于存储电容C的自举作用，第二节点N2的电压在T2阶段的基础上发生同样的变化量，即第二节点N2的电压由T2阶段的VDD+Vth变化为T3阶段的VDD+Vth+Vref-VData。由图4中的仿真结果可得，N1节点T3阶段电压相对于T2阶段电压的变化量Vref-VData为负值。
第二节点N2的电压VDD+Vth+Vref-VData中，Vref-VData为负值，因此VDD+Vth+Vref-VData与第一电源信号VDD之差小于驱动晶体管M7的阈值电压Vth，则驱动晶体管M7能够在第二节点N2的电压信号的作用下导通，并在第一电源信号VDD的作用下输出驱动电流，驱动电流通过第六晶体管M6传输至电致发光元件L以驱动电致发光元件发光。结合仿真图进行说明，当阈值电压为-2.3V左右，第一电源信号VDD为5V时，第二节点N2的电压VDD+Vth+Vref-VData为1.7V，与第一电源信号VDD之差小于驱动晶体管M7的阈值电压Vth。需要说明的是，可设置参考信号Vref小于数据信号VData，以使驱动晶体管M7导通。例如，可将参考信号Vref设置为-1V或0V或1V等，可将数据信号VData设置 在2V到5V之间。只要参考信号Vref小于数据信号VData的最小值，即可导通驱动晶体管M7。
第二节点N2的电压VDD+Vth+Vref-VData中，阈值电压Vth在此处表现为负值，如果VDD+Vth+Vref-VData与第一电源信号VDD之差小于驱动晶体管M7的阈值电压Vth，则驱动晶体管M7能够在第二节点N2的电压信号的作用下导通，并在第一电源信号VDD的作用下输出驱动电流，驱动电流通过第六晶体管M6传输至电致发光元件L以驱动电致发光元件发光。此时，假设电致发光元件L的第一极的电压变为电致发光元件L的导通电压VL，第一节点N1的电压为参考电压Vref，第二节点N2的电压变为VX。
在此基础上，驱动晶体管M7的驱动电流的计算公式可表示为：Ion＝K×(Vgs-Vth) 2＝K×(VX-VDD-Vth) 2。
下面，根据电荷守恒原理，即T2阶段中像素驱动电路中的电荷与T3阶段像素驱动电路中的电荷相同可得：
(VDD+Vth-VData)C＝(VX-Vref)C
求解上述公式可得：VX＝VDD+Vth-VData+Vref
将VX代入驱动晶体管M7的驱动电流的计算公式可得：
Ion＝K×(VDD+Vth-VData+Vref-VDD-Vth) 2＝K×(Vref-VData) 2
由此可知，驱动电流与驱动晶体管M7的阈值电压Vth和第一电源信号VDD的电压均无关。
结合图4中的第一节点和第二节点的电压仿真结果而言，通过在T2阶段导通第五晶体管，将驱动晶体管M7的控制端和第二端联通，将驱动晶体管M7的阈值电压Vth和第一电源信号VDD写入第二节点N2，即对驱动晶体管M7的阈值电压Vth进行补偿，消除驱动晶体管M7的阈值电压Vth对驱动电流的影响，确保各像素驱动电路输出的驱动电流一致，进而保证各像素显示亮度的均一性；同时消除第一电源信号VDD对驱动晶体管M7的控制端和第一端之间的电压的影响，从而消除电源IR的压降损耗对各像素显示亮度的影响，以在发光阶段确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。除此之外，本示例中的像素驱动电路还可减少第一电源信号VDD的抖动，还可通 过较低的参考电压达到降低功耗的目的。
本示例性实施例中，采用全P型薄膜晶体管具有以下优点：对噪声抑制力强；由于是低电平导通，而充电管理中低电平容易实现；P型薄膜晶体管制程简单，相对价格较低；P型薄膜晶体管的稳定性更好。
需要说明的是：在上述具体的实施例中，所有晶体管均为P型薄膜晶体管；但本领域技术人员容易根据本公开所提供的像素驱动电路得到所有晶体管均为N型薄膜晶体管的像素驱动电路。在本公开的一种示例性实施方式中，所有晶体管可以均为N型薄膜晶体管，由于晶体管均为N型薄膜晶体管，因此，晶体管的导通信号均为高电平，晶体管的第一端均为漏极，晶体管的第二端均为源极。当然，本公开所提供的像素驱动电路也可以改为CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)电路等，并不局限于本实施例中所提供的像素驱动电路，这里不再赘述。
本示例实施方式还提供一种显示装置，包括上述的像素驱动电路。该显示装置还可包括：多条扫描线，用于提供扫描信号；多条数据线，用于提供数据信号；多个像素驱动电路，电连接于上述的扫描线和数据线；其中，所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。通过如上所述的像素驱动电路中的第五晶体管，将驱动晶体管的控制端和第二端联通，以将驱动晶体管的阈值电压和第一电源信号写入第二节点，即对驱动晶体管的阈值电压进行补偿，消除驱动晶体管的阈值电压对驱动电流的影响，确保各像素驱动电路输出的驱动电流一致，进而保证各像素显示亮度的均一性；另外，还可消除第一电源信号对驱动晶体管的控制端和第一端之间的电压的影响，从而消除电源IR压降对各像素显示亮度的影响，确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。
需要说明的是：所述显示装置中各模块电路的具体细节已经在对应的像素驱动电路中进行了详细的描述，因此这里不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者电路，但是这种划分并非强制性的。实际上，根据本公开的 实施方式，上文描述的两个或更多模块或者电路的特征和功能可以在一个模块或者电路中具体化。反之，上文描述的一个模块或者电路的特征和功能可以进一步划分为由多个模块或者电路来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的实施方式后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：
    第一开关电路，与第一节点连接，用于响应扫描信号而导通，以将数据信号传输至所述第一节点；
    第二开关电路，与所述第一节点连接，用于响应控制信号而导通，以将参考信号传输至所述第一节点；
    第一初始化电路，与所述第一节点连接，用于响应复位信号而导通，以将初始化信号传输至所述第一节点；
    驱动电路，与第二节点以及第三节点连接，用于响应所述第二节点的信号而导通，并在第一电源信号的作用下输出驱动电流至所述第三节点；
    第二初始化电路，与所述第二节点连接，用于响应所述复位信号而导通，以将所述初始化信号传输至所述第二节点；
    补偿电路，与所述第二节点以及所述第三节点连接，用于响应所述扫描信号而导通，以联通所述第二节点和所述第三节点；
    隔离电路，与所述第三节点连接，用于响应所述控制信号而导通，以将所述驱动电流传输至所述电致发光元件；
    储能电路，连接于所述第一节点和所述第二节点之间。
  2. 根据权利要求1所述的像素驱动电路，所述第一开关电路包括第一晶体管，其中：
    所述第一晶体管的第一端用于接收所述数据信号，第二端连接所述第一节点，控制端用于接收所述扫描信号。
  3. 根据权利要求1所述的像素驱动电路，所述第二开关电路包括第二晶体管，其中：
    所述第二晶体管的第一端用于接收所述参考信号，第二端连接所述第一节点，控制端用于接收所述控制信号。
  4. 根据权利要求1所述的像素驱动电路，所述第一初始化电路包括第三晶体管，其中：
    所述第三晶体管的第一端用于接收所述初始化信号，第二端连接所 述第一节点，控制端用于接收所述复位信号。
  5. 根据权利要求1所述的像素驱动电路，所述第二初始化电路包括第四晶体管，其中：
    所述第四晶体管的第一端用于接收所述初始化信号，第二端连接所述第二节点，控制端用于接收所述复位信号。
  6. 根据权利要求1所述的像素驱动电路，所述驱动电路包括驱动晶体管，其中：
    所述驱动晶体管的第一端用于接收所述第一电源信号，第二端连接所述第三节点，控制端连接所述第二节点。
  7. 根据权利要求1所述的像素驱动电路，所述补偿电路包括第五晶体管，其中：
    所述第五晶体管的第一端连接所述第二节点，第二端连接所述第三节点，控制端用于接收所述扫描信号。
  8. 根据权利要求7所述的像素驱动电路，所述补偿电路包括第五晶体管，其中：
    所述第五晶体管将所述第二节点和所述第三节点联通，从而将驱动电路的控制端和第二端联通，以将驱动电路中晶体管的阈值电压和第一电源信号写入第二节点。
  9. 根据权利要求1所述的像素驱动电路，所述隔离电路包括第六晶体管，其中：
    所述第六晶体管的第一端连接所述第三节点，第二端连接所述电致发光元件，控制端用于接收所述控制信号。
  10. 一种像素驱动电路，用于驱动电致发光元件，包括：
    第一晶体管，第一端用于接收数据信号，第二端连接第一节点，控制端用于接收扫描信号；
    第二晶体管，第一端用于接收参考信号，第二端连接所述第一节点，控制端用于接收控制信号；
    第三晶体管，第一端用于接收初始化信号，第二端连接所述第一节点，控制端用于接收复位信号；
    驱动晶体管，第一端用于接收第一电源信号，第二端连接第三节点， 控制端连接第二节点；
    第四晶体管，第一端用于接收所述初始化信号，第二端连接所述第二节点，控制端用于接收所述复位信号；
    第五晶体管，第一端连接所述第二节点，第二端连接所述第三节点，控制端用于接收所述扫描信号；
    第六晶体管，第一端连接所述第三节点，第二端连接所述电致发光元件，控制端用于接收所述控制信号；
    存储电容，第一端连接所述第一节点，第二端连接所述第二节点。
  11. 一种像素驱动方法，用于驱动权利要求1所述的像素驱动电路，所述像素驱动方法包括：
    在复位阶段，利用所述复位信号导通所述第一初始化电路以及第二初始化电路，以使所述初始化信号写入所述第一节点和所述第二节点；
    在充电阶段，利用所述扫描信号导通所述第一开关电路以及补偿电路，以使所述数据信号以及所述驱动电路的阈值电压写入所述储能电路；
    在发光阶段，利用所述控制信号导通所述第二开关电路以及隔离电路，以使所述驱动电路在所述第二节点的信号的作用下导通，并在所述第一电源信号的作用下通过所述隔离电路向所述电致发光元件输出驱动电流。
  12. 根据权利要求11所述的像素驱动方法，利用所述扫描信号导通所述第一开关电路以及补偿电路，以使所述数据信号以及所述驱动电路的阈值电压写入所述储能电路包括：
    所述数据信号通过所述第一开关电路传输至所述第一节点；
    所述补偿电路导通使得所述驱动电路导通，从而将所述第一电源信号和所述驱动电路的阈值电压写入所述第二节点N2；
    所述第一节点和所述第二节点对所述储能电路进行充电，以使所述数据信号以及所述驱动电路的阈值电压写入所述储能电路。
  13. 根据权利要求11所述的像素驱动方法，所述初始化信号的电压为0。
  14. 根据权利要求11所述的像素驱动方法，所述复位信号和所述扫描信号的导通时段之间具有一缓冲时段。
  15. 一种显示装置，包括权利要求1～10中任意一项所述的像素驱动电路。
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