WO2017193630A1 - 像素电路、驱动方法、阵列基板、显示面板及显示装置 - Google Patents

像素电路、驱动方法、阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2017193630A1
WO2017193630A1 PCT/CN2017/071519 CN2017071519W WO2017193630A1 WO 2017193630 A1 WO2017193630 A1 WO 2017193630A1 CN 2017071519 W CN2017071519 W CN 2017071519W WO 2017193630 A1 WO2017193630 A1 WO 2017193630A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
transistor
driving
voltage
pixel circuit
Prior art date
Application number
PCT/CN2017/071519
Other languages
English (en)
French (fr)
Inventor
周茂秀
江鹏
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/554,516 priority Critical patent/US10037730B2/en
Priority to EP17755043.1A priority patent/EP3457393A4/en
Publication of WO2017193630A1 publication Critical patent/WO2017193630A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Exemplary embodiments of the present disclosure relate to the field of display technologies, and more particularly, to a pixel circuit and a method of driving the same, and a corresponding array substrate, display panel, and display device.
  • OLEDs Organic light emitting diodes
  • PMOLEDs passive matrix organic light emitting diodes
  • AMOLED active matrix organic light emitting diode
  • Vth threshold voltage of a thin film transistor (TFT) for an AMOLED may be shifted, resulting in uneven currents of different pixels, resulting in unevenness of the display image.
  • An exemplary embodiment of the present disclosure provides a pixel circuit and a driving method thereof, and a corresponding array substrate, display panel, and display device capable of eliminating current fluctuation due to a deviation of a threshold voltage Vth, thereby stabilizing picture quality.
  • a pixel circuit including: a charging module, a storage module, an adjustment module, a data writing module, a driving module, and a light emitting device.
  • the first end of the charging module is configured to receive a first voltage signal, and the second end of the charging module and the illuminator
  • the first end of the charging module is coupled to the first end of the storage module, the second end of the light emitting device, and the first end of the driving module.
  • the second end of the storage module is coupled to the first end of the adjustment module, and the second end of the adjustment module is coupled to the second end of the data write module and the third end of the drive module .
  • the first end of the data writing module is configured to receive a data signal.
  • the second end of the driving module is configured to receive a second voltage signal.
  • the charging module is configured to charge the storage module, the adjustment module is configured to perform voltage compensation on the driving module, and the driving module is configured to drive the light emitting device to emit light.
  • the charging module includes a first transistor and a third transistor.
  • a first pole of the first transistor is configured to receive the first voltage signal
  • a control pole of the first transistor is configured to receive a first control signal
  • a second pole of the first transistor and the third transistor The first pole and the first end of the light emitting device are coupled.
  • a control electrode of the third transistor is configured to receive a second control signal, a second pole of the third transistor and a first end of the memory module, a second end of the light emitting device, and a portion of the driving module One end is coupled.
  • the memory module includes a capacitor. a first end of the capacitor is coupled to a first end of the driving module, a second end of the light emitting device, and a third end of the charging module, the second end of the capacitor and the adjusting module The first end is coupled.
  • the adjustment module includes a second transistor, a first pole of the second transistor is coupled to a second end of the capacitor, and a second pole of the second transistor is coupled to the data
  • the second end of the input module and the third end of the driving module are coupled, and the control electrode of the second transistor is configured to receive the first control signal.
  • the driving module includes a driving transistor, and a first electrode of the driving transistor is coupled to a first end of the capacitor, a second end of the light emitting device, and a third end of the charging module
  • the second pole of the driving transistor is configured to receive a second voltage signal
  • a control electrode of the driving transistor is coupled to a second pole of the second transistor and a second end of the data writing module.
  • the data writing module includes a fourth transistor, a first pole of the fourth transistor is configured to receive a data signal, and a second pole of the fourth transistor and a control electrode of the driving transistor And the second pole of the second transistor is coupled, and the fourth transistor is controlled The pole is used to receive the scan signal.
  • the transistors in the pixel circuit are all N-type transistors.
  • the transistors in the pixel circuit are all P-type transistors.
  • a pixel circuit group comprising: a plurality of pixel circuits of any of the above, wherein data writing modules of the plurality of pixel circuits are coupled to the same data line.
  • a driving method for driving a pixel circuit of any of the above comprising:
  • the driving module is voltage-adjusted such that the voltage of the first end of the memory module is the sum of the data voltage and the threshold voltage of the driving transistor in the driving module;
  • the illuminating device In the illuminating phase, the illuminating device is kept illuminated, and the voltage of the third end of the driving module is the first voltage minus the data voltage and the threshold voltage of the driving transistor in the driving module is subtracted.
  • a driving method for driving the pixel circuit group described above including:
  • the memory modules of the plurality of pixel circuits are charged such that the voltage of the first end of the memory module of each pixel circuit is a first voltage
  • voltage adjustment is performed on the driving modules of the plurality of pixel circuits in sequence, such that the voltage of the first end of the memory module of each pixel circuit is a data voltage corresponding to the pixel circuit and corresponds to the pixel circuit
  • the light emitting device In the light emitting phase, the light emitting device is kept to emit light, and the voltage of the third end of the driving module of each pixel circuit is a first voltage minus a data voltage corresponding to the pixel circuit and subtracted corresponding to the pixel The threshold voltage of the drive transistor in the drive module of the circuit.
  • an array substrate comprising the pixel circuit of any of the above.
  • an array substrate comprising the above-described pixel circuit group.
  • a display panel comprising the array substrate of any of the above.
  • a display device comprising the display panel of any of the above.
  • FIG. 1 is a block diagram showing the structure of a pixel circuit in accordance with one embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of driving signals for driving a pixel circuit as shown in FIG. 2, in accordance with an embodiment of the present disclosure
  • FIG. 4 is a structural block diagram of a pixel circuit group in accordance with one embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a pixel circuit group in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of driving signals for driving a pixel circuit group as shown in FIG. 5, according to an embodiment of the present disclosure.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor
  • the conduction currents are opposite in direction, so in the embodiments of the present disclosure, the controlled intermediate end of the transistor is referred to as the control pole, the signal input terminal is referred to as the first pole, and the signal output terminal is referred to as the second pole.
  • the transistors employed in the embodiments of the present disclosure are mainly switching transistors and driving transistors.
  • the capacitors employed in the embodiments of the present disclosure may also be replaced by energy storage elements having similar functions.
  • FIG. 1 shows a block diagram of a structure of a pixel circuit in accordance with one embodiment of the present disclosure.
  • a pixel circuit 10 includes a charging module 11 , a storage module 13 , an adjustment module 15 , a data writing module 16 , a driving module 14 , and a light emitting device 12 .
  • the first end of the charging module 11 is configured to receive a first voltage signal (eg, a power supply voltage Vdd), and the second end of the charging module 11 is coupled to the first end of the light emitting device 12, and the third end of the charging module 11
  • a first voltage signal eg, a power supply voltage Vdd
  • the second end of the storage module 13 is coupled to the first end of the adjustment module 15 .
  • the second end of the adjustment module 15 is coupled to the second end of the data write module 16 and the third end of the drive module 14.
  • the first end of the data write module 16 is for receiving a data signal.
  • the second end of the drive module 14 is for receiving a second voltage signal, such as a ground voltage.
  • the charging module 11 is used to charge the storage module 13.
  • the storage module 13 is for storing electric charge and can be charged and discharged.
  • the adjustment module 15 is used to voltage compensate the drive module 14.
  • the driving module 14 is used to drive the light emitting device 12 to emit light.
  • the pixel circuit 10 can eliminate current fluctuation due to the deviation of the threshold voltage Vth of the driving transistor, thereby stabilizing the picture quality .
  • FIG. 2 shows a circuit diagram of a pixel circuit in accordance with one embodiment of the present disclosure.
  • an N-type transistor is taken as an example for description.
  • the first pole of the organic light emitting diode OLED refers to the anode of the organic light emitting diode OLED
  • the second pole of the organic light emitting diode OLED refers to the cathode of the organic light emitting diode OLED.
  • the charging module 11 includes a first transistor T1 and a third transistor T3, the memory module 13 may include a capacitor C, the light emitting device 12 may be an organic light emitting diode OLED, and the adjustment module 15 may include a second transistor T2, data writing.
  • the ingress module 16 can include a fourth transistor T4, and the drive module 14 can include a drive transistor T5.
  • the first end of the charging module 11 is the first pole of the first transistor T1
  • the second end of the charging module 11 is the second pole of the first transistor T1
  • the third end of the charging module 11 is the third transistor T3.
  • the control electrode of the first transistor T1 is configured to receive the first control signal EN1
  • the second electrode of the first transistor T1 is coupled to the first electrode of the third transistor T3 and the first electrode of the organic light emitting diode OLED
  • the first transistor T1 The first pole is for receiving the power supply voltage Vdd.
  • the control electrode of the third transistor T3 is for receiving the second control signal EN2, the second terminal of the third transistor T3 and the first end of the capacitor C (ie, node a), the second electrode of the organic light emitting diode OLED, and the driving transistor T5
  • the first pole of the third transistor T3 is coupled to the second pole of the first transistor T1 and the first pole of the organic light emitting diode OLED.
  • the first end of the adjustment module 15 is the first pole of the second transistor T2, and the second end of the adjustment module 15 is the second pole of the second transistor T2.
  • the control electrode of the second transistor T2 is for receiving the first control signal EN1, the first electrode of the second transistor T2 is coupled to the second end of the capacitor C (ie, the node b), and the second and fourth terminals of the second transistor T2 are coupled.
  • the second pole of the transistor T4 and the control electrode of the driving transistor T5 are coupled.
  • the first end of the driving module 14 is the first pole of the driving transistor T5, the second end of the driving module 14 is the second pole of the driving transistor T5, and the third end of the driving module 14 is the control electrode of the driving transistor T5.
  • Driving the first pole of the transistor T5 with the first end of the capacitor C (ie, node a) The second pole of the organic light emitting diode OLED and the second pole of the third transistor T3 are coupled, the second pole of the driving transistor T5 is grounded, and the control electrode of the driving transistor T5 and the second pole of the second transistor T2 and the fourth transistor T4 The second pole is coupled.
  • the first end of the data writing module 16 is the first pole of the fourth transistor T4, and the second end of the data writing module 16 is the second pole of the fourth transistor T4.
  • the control electrode of the fourth transistor T4 is for receiving the scan signal SCAN
  • the first pole of the fourth transistor T4 is for receiving the data signal Data
  • the second pole of the fourth transistor T4 is opposite to the control electrode of the driving transistor T5 and the second transistor T2 The second pole is coupled.
  • the pixel circuit 10 may include 5 transistors and 1 capacitor to solve the display unevenness problem caused by the threshold voltage (Vth) drift of the driving transistor.
  • the pixel circuit according to an embodiment of the present disclosure is more compact than the pixel circuit including more transistors and capacitors in the prior art, so that the aperture ratio of the pixel display can be improved.
  • Embodiments of the present disclosure also provide a driving method for driving the above pixel circuit.
  • the driving method may include: charging the memory module 13 during the charging phase; performing voltage adjustment on the driving module 14 during the voltage adjustment phase; and performing voltage compensation on the driving module 14 during the lighting phase, and causing the light emitting device 12 to remain illuminated .
  • FIG. 3 is a timing diagram of a driving signal for driving a pixel circuit as shown in FIG. 2, in accordance with one embodiment of the present disclosure.
  • the first control signal EN1, the second control signal EN2, and the data scan signal SCAN are set to a high level, and the data signal Data is set to a low level.
  • the transistors T1, T2, T3, and T4 are turned on, and the transistor T5 is turned off, and the current path at this time is Vdd-T1-T3-T2-T5-Data, thereby realizing charging of the capacitor C, so that the capacitor The voltage at the first end of C (ie, node a) is the supply voltage Vdd.
  • the first control signal EN1 and the second control signal EN2 are set to a low level, and the scan signal SCAN and the data signal Data are set to a high level.
  • transistors T1, T2, and T3 are turned off, and transistors T4 and T5 are turned on.
  • the current path is the node a-T4-ground, so that the voltage of the node a is the sum of the data voltage V and the threshold voltage Vth5 of the driving transistor T5 (ie, V+Vth5).
  • the first control signal EN1 is set to a high level
  • the second control signal EN2 the scan signal SCAN, and the data signal Data are set to a low level.
  • the transistors T3 and T4 are turned off, and the transistors T1, T2, and T5 are turned on.
  • transistor T1 is turned on, node a is connected to voltage Vdd, and the second end of capacitor C (ie, node b) is floating. Due to the presence of capacitor C, the original voltage difference is maintained between the various nodes.
  • the voltage of the gate of the driving transistor T5 that is, the voltage of the node d
  • Vd Vdd - V - Vth5.
  • K is a constant, which is related to the carrier mobility of the driving transistor T5, the gate oxide capacitance, and the aspect ratio of the driving transistor T5.
  • first control signal EN1, the second control signal EN2, the scan signal SCAN, and the data signal Data in FIG. 3 and each stage is only schematic. According to an embodiment of the present disclosure, it is also possible to switch the scan signal SCAN and the data signal Data to a low level, respectively, before the end of the voltage adjustment phase.
  • FIG. 4 shows a structural block diagram of a pixel circuit group in accordance with one embodiment of the present disclosure.
  • a pixel circuit group 20 may include a plurality of pixel circuits 10.
  • the first ends of the data writing modules 16 in the plurality of pixel circuits 10 are coupled to each other.
  • a pixel circuit group 20 for data multiplexing can control a plurality of sub-pixels through one data line, thereby reducing the number of data lines and saving the number of integrated circuit pins, thereby Reduce the cost of integrated circuits.
  • FIG. 5 illustrates the present invention in accordance with the present disclosure.
  • the pixel circuit group according to an embodiment of the present disclosure includes three cascaded pixel circuits as shown in FIG. 2.
  • the embodiment of FIG. 5 is for exemplary purposes only, and it is not difficult for those skilled in the art to understand that the pixel circuit group according to another embodiment of the present disclosure may further include two cascaded pixel circuits, or more than three cascaded pixels. Circuit.
  • the data writing module of the pixel circuit in FIG. 5 is coupled to the same data line, that is, the first poles of the transistors T10, T13, and T14 are coupled to each other and used to receive the data signal Data.
  • the gates of the data writing transistors T10, T13, and T14 are respectively coupled to the scanning signals of the sub-pixels corresponding to each of the pixel circuits.
  • a plurality of sub-pixels can be controlled by one data line, thereby reducing the number of data lines, saving the number of integrated circuit pins, and thereby reducing the cost of the integrated circuit.
  • the driving method includes: charging a memory module in a plurality of pixel circuits during a charging phase; sequentially performing voltage adjustment on a driving module in the plurality of pixel circuits in a voltage adjusting phase; and, in a light emitting phase, a plurality of pixel circuits
  • the drive transistor in the drive module performs voltage compensation and causes the light emitting device to remain illuminated.
  • FIG. 6 shows a timing diagram for driving a driving signal for driving a pixel circuit group as shown in FIG. 5 according to an embodiment of the present disclosure.
  • the first control signal EN1, the second control signal EN2, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 are set to a high level, and the data signal is set. Data is set to low.
  • transistors T1-T10, T13, and T14 are turned on, and transistors T11, T12, and T15 are turned off.
  • the current paths in the first to third pixel circuits are Vdd-T1-T4-T7-T10-Data, Vdd-T2-T5-T8-T13-Data, and Vdd-T3-T6-T9-T14-Data, respectively.
  • the first control signal EN1 and the second control signal are EN2 is set to a low level, and the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the data signal Data are divided into three sub-phases.
  • the first scan signal SCAN1 is set to a high level
  • the second scan signal SCAN2 the third scan signal SCAN3 is set to a low level
  • the data signal Data is set to correspond to the first sub-pixel.
  • the transistors T1, T4, and T7 are turned off, and the transistors T10 and T11 are turned on.
  • the current path in the first pixel circuit is the node a1-T11-ground such that the voltage of the node a1 is the sum V1+Vth11 of the data voltage V1 and the threshold voltage Vth11 of the driving transistor T11.
  • the second scan signal SCAN2 is set to a high level
  • the first scan signal SCAN1 and the third scan signal SCAN3 are set to a low level
  • the data signal Data is set to correspond to the second sub-pixel.
  • the transistors T2, T5, and T8 are turned off, and the transistors T12 and T13 are turned on.
  • the current path in the second pixel circuit is the node a2-T12-ground such that the voltage of the node a2 is the sum V2+Vth12 of the data voltage V2 and the threshold voltage Vth12 of the driving transistor T12.
  • the third scan signal SCAN3 is set to a high level
  • the first scan signal SCAN1 and the second scan signal SCAN2 are set to a low level
  • the data signal Data is set to correspond to the third sub-pixel.
  • the transistors T3, T6, and T9 are turned off, and the transistors T14 and T15 are turned on.
  • the current path in the third pixel circuit is the node a3-T15-ground such that the voltage of the node a3 is the sum of the data voltage V3 and the threshold voltage Vth15 of the driving transistor T15, V3 + Vth15.
  • the first control signal EN1 is set to a high level
  • the second control signal EN2 the first to third scan signals SCAN1-SCAN3, and the data signal Data are set to a low level.
  • the transistors T4 and T10 are turned off, and the transistors T1, T7, and T11 are turned on.
  • the transistor T1 is turned on, the node a1 is connected to the voltage Vdd, and the second end of the capacitor C1 (i.e., the node b1) is floated. Due to the presence of capacitor C1, the original voltage difference is maintained between the various nodes.
  • Id1 K1(Vgs1-Vth11) 2
  • K1 is a constant, which is related to the carrier mobility of the driving transistor T11, the gate oxide capacitance, and the aspect ratio of the driving transistor T11.
  • the transistors T5 and T13 are turned off, and the transistors T2, T8, and T12 are turned on.
  • transistor T2 is turned on, node a2 is connected to voltage Vdd, and the second end of capacitor C2 (i.e., node b2) is floating. Due to the presence of capacitor C2, the original voltage difference is maintained between the various nodes.
  • Id2 K2 (Vgs2-Vth12) 2
  • K2 is a constant, which is related to the carrier mobility of the driving transistor T12, the gate oxide capacitance, and the aspect ratio of the driving transistor T12.
  • the transistors T6 and T14 are turned off, and the transistors T3, T9, and T15 are turned on.
  • transistor T3 When transistor T3 is turned on, node a3 is connected to voltage Vdd, and the second end of capacitor C3 (i.e., node b3) is floating. Due to the presence of capacitor C3, the original voltage difference is maintained between the various nodes.
  • Id3 K3(Vgs3-Vth15) 2
  • K3 is a constant, which is related to the carrier mobility of the driving transistor T15, the gate oxide capacitance, and the aspect ratio of the driving transistor T15.
  • the relationship between the first control signal EN1, the second control signal EN2, the scan signals SCAN1-SCAN3, and the data signal Data in FIG. 6 and each stage is only illustrative. According to an embodiment of the present disclosure, it is also possible to switch the scan signals SCAN1-SCAN 3 and the data signal Data to a low level, respectively, before the end of the voltage adjustment phase. It should be understood by those skilled in the art that the voltages V1-V3 on the data signal Data are only used to schematically illustrate the gray scale voltages of the first to third sub-pixels, and the gray scale voltages V1-V3 of the first to third sub-pixels. Relationships are not limited to this.
  • an embodiment of the present disclosure further provides an array substrate including any one of the above-described pixel circuits or pixel circuit groups, which is capable of eliminating current fluctuation due to a deviation of a threshold voltage Vth of a driving transistor, thereby stabilizing picture quality .
  • an embodiment of the present disclosure also provides a display panel including any of the above array substrates, which is capable of eliminating current fluctuation due to a deviation of a threshold voltage Vth of a driving transistor, thereby stabilizing picture quality.
  • an embodiment of the present disclosure further provides a display device including the display panel of any of the above.
  • a display device according to an embodiment of the present disclosure is capable of eliminating current fluctuation due to a deviation of a threshold voltage Vth of a driving transistor, thereby stabilizing picture quality.
  • the display device in this embodiment may be: display panel, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc. A product or part that exhibits functionality.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路（10）、驱动方法、阵列基板、显示面板及显示装置。像素电路（10）包括：充电模块（11）、存储模块（13）、调整模块（15）、数据写入模块（16）、驱动模块（14）以及发光器件（12）。充电模块（11）的第一端用于接收第一电压信号（Vdd），充电模块（11）的第二端与发光器件（12）的第一端耦接，充电模块（11）的第三端与存储模块（13）的第一端、发光器件（12）的第二端以及驱动模块（14）的第一端耦接。存储模块（13）的第二端与调整模块（15）的第一端耦接。调整模块（15）的第二端与数据写入模块（16）的第二端以及驱动模块（14）的第三端耦接。数据写入模块（16）的第一端用于接收数据信号（Data）。驱动模块（14）的第二端用于接收第二电压信号（Gnd）。充电模块（11）用于对存储模块（13）进行充电，调整模块（15）用于对驱动模块（14）进行电压补偿，驱动模块（14）用于驱动发光器件（12）发光。

Description

像素电路、驱动方法、阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求于2016年05月11日递交的中国专利申请第201610305849.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的示例性实施例涉及显示技术领域，更加具体地，涉及一种像素电路及其驱动方法，以及相应的阵列基板、显示面板和显示装置。
背景技术
有机发光二极管(OLED)作为一种电流型发光器件已越来越多地被应用于高性能显示装置中。传统的无源矩阵有机发光二极管(PMOLED)随着显示尺寸的增大，需要更短的单个像素的驱动时间，因而需要增大瞬态电流，增加功耗。而有源矩阵有机发光二极管(AMOLED)通过开关管以逐行扫描的方式输入OLED电流，可以很好地解决这些问题。
由于工艺偏差或者长时间操作，用于AMOLED的薄膜晶体管(TFT)的阈值电压(Vth)会发生偏移，导致不同像素的电流出现不均匀的现象，从而造成显示画面的不均匀。
发明内容
本公开的示例性实施例提供了一种像素电路及其驱动方法，以及相应的阵列基板、显示面板和显示装置，其能够消除因为阈值电压Vth的偏差导致的电流波动，从而稳定画面品质。
根据本公开的第一方面，提供了一种像素电路，包括：充电模块、存储模块、调整模块、数据写入模块、驱动模块以及发光器件。所述充电模块的第一端用于接收第一电压信号，所述充电模块的第二端与所述发光器 件的第一端耦接，所述充电模块的第三端与所述存储模块的第一端、所述发光器件的第二端以及所述驱动模块的第一端耦接。所述存储模块的第二端与所述调整模块的第一端耦接，所述调整模块的第二端与所述数据写入模块的第二端以及所述驱动模块的第三端耦接。所述数据写入模块的第一端用于接收数据信号。所述驱动模块的第二端用于接收第二电压信号。所述充电模块用于对所述存储模块进行充电，所述调整模块用于对所述驱动模块进行电压补偿，所述驱动模块用于驱动所述发光器件发光。
根据本公开的实施例，所述充电模块包括第一晶体管和第三晶体管。所述第一晶体管的第一极用于接收所述第一电压信号，所述第一晶体管的控制极用于接收第一控制信号，所述第一晶体管的第二极与所述第三晶体管的第一极以及所述发光器件的第一端耦接。所述第三晶体管的控制极用于接收第二控制信号，所述第三晶体管的第二极与所述存储模块的第一端、所述发光器件的第二端以及所述驱动模块的第一端耦接。
根据本公开的实施例，所述存储模块包括电容器。所述电容器的第一端与所述驱动模块的第一端、所述发光器件的第二端以及所述充电模块的第三端耦接，所述电容器的第二端与所述调整模块的第一端耦接。
根据本公开的实施例，所述调整模块包括第二晶体管，所述第二晶体管的第一极与所述电容器的第二端耦接，所述第二晶体管的第二极与所述数据写入模块的第二端以及所述驱动模块的第三端耦接，所述第二晶体管的控制极用于接收第一控制信号。
根据本公开的实施例，所述驱动模块包括驱动晶体管，所述驱动晶体管的第一极与所述电容器的第一端、所述发光器件的第二端以及所述充电模块的第三端耦接，所述驱动晶体管的第二极用于接收第二电压信号，所述驱动晶体管的控制极与所述第二晶体管的第二极以及所述数据写入模块的第二端耦接。
根据本公开的实施例，所述数据写入模块包括第四晶体管，所述第四晶体管的第一极用于接收数据信号，所述第四晶体管的第二极与所述驱动晶体管的控制极以及所述第二晶体管的第二极耦接，所述第四晶体管的控 制极用于接收扫描信号。
根据本公开的实施例，所述像素电路中的晶体管都为N型晶体管。
根据本公开的实施例，所述像素电路中的晶体管都为P型晶体管。
根据本公开的第二方面，提供了一种像素电路组，包括：多个上述任一种的像素电路，其中，所述多个像素电路的数据写入模块与相同的数据线耦接。
根据本公开的第三方面，提供了一种用于驱动上述任一种的像素电路的驱动方法，包括：
在充电阶段，对所述存储模块进行充电，使得所述存储模块的第一端的电压为第一电压；
在电压调整阶段，对所述驱动模块进行电压调整，使得所述存储模块的第一端的电压为数据电压与所述驱动模块中的驱动晶体管的阈值电压之和；以及
在发光阶段，使得所述发光器件保持发光，并使得所述驱动模块的第三端的电压为第一电压减去数据电压以及减去所述驱动模块中的驱动晶体管的阈值电压。
根据本公开的第四方面，提供了一种用于驱动上述的像素电路组的驱动方法，包括：
在充电阶段，对多个像素电路的存储模块进行充电，使得各个像素电路的所述存储模块的第一端的电压为第一电压；
在电压调整阶段，依次对多个像素电路的驱动模块进行电压调整，使得各个像素电路的所述存储模块的第一端的电压为对应于所述像素电路的数据电压与对应于所述像素电路的所述驱动模块中的驱动晶体管的阈值电压之和；以及
在发光阶段，使得所述发光器件保持发光，并使得各个像素电路的所述驱动模块的第三端的电压为第一电压减去对应于所述像素电路的数据电压以及减去对应于所述像素电路的驱动模块中的驱动晶体管的阈值电压。
根据本公开的第五方面，提供了一种阵列基板，包括上述任一种的像素电路。
根据本公开的第六方面，提供了一种阵列基板，包括上述的像素电路组。
根据本公开的第七方面，提供了一种显示面板，包括上述任一种的阵列基板。
根据本公开的第八方面，提供了一种显示装置，包括上述任一种的显示面板。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本公开的一个实施例的像素电路的结构框图；
图2是根据本公开的一个实施例的像素电路的电路图；
图3是根据本公开的一个实施例的用于驱动如图2所示的像素电路的驱动信号的时序图；
图4是根据本公开的一个实施例的像素电路组的结构框图；
图5是根据本公开的一个实施例的像素电路组的电路图；以及
图6是根据本公开的一个实施例的用于驱动如图5所示的像素电路组的驱动信号的时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他的实施例，都属于本公开保护的范围。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管和驱动晶体管。另外，本公开的实施例中所采用的电容器也可以由具有类似功能的储能元件来代替。
此外，在本公开的描述中，除非另有说明，“多个”的含义是指两个或更多。此处，术语“第一”、“第二”等仅用于区分不同的部件或者步骤，不应理解为是对部件或者步骤的具体限定。
图1示出了根据本公开的一个实施例的像素电路的结构框图。
如图1所示，根据本公开的实施例的一种像素电路10，包括：充电模块11、存储模块13、调整模块15、数据写入模块16、驱动模块14以及发光器件12。
具体地，充电模块11的第一端用于接收第一电压信号(例如，电源电压Vdd)，充电模块11的第二端与发光器件12的第一端耦接，充电模块11的第三端与存储模块13的第一端、发光器件12的第二端以及驱动模块14的第一端耦接。存储模块13的第二端与调整模块15的第一端耦接。调整模块15的第二端与数据写入模块16的第二端以及驱动模块14的第三端耦接。数据写入模块16的第一端用于接收数据信号。驱动模块14的第二端用于接收第二电压信号，例如接地电压。充电模块11用于对存储模块13进行充电。存储模块13用于存储电荷并且能够被充放电。调整模块15用于对驱动模块14进行电压补偿。驱动模块14用于驱动发光器件12发光。
通过用于对驱动模块14中的驱动晶体管的阈值电压Vth进行补偿的上述配置，根据本公开实施例的像素电路10能够消除因为驱动晶体管的阈值电压Vth的偏差导致的电流波动，从而稳定画面品质。
与图1中的像素电路的结构框图相对应地，图2示出了根据本公开的一个实施例的像素电路的电路图。
在本公开的实施例中，以N型晶体管为例进行描述。但是根据本公开实施例给出的教导，本领域技术人员能够想到，还可以将本实施例中全部或者部分N型晶体管替换为P型晶体管。在本公开的实施例中，有机发光二极管OLED的第一极是指有机发光二极管OLED的阳极，有机发光二极管OLED的第二极是指有机发光二极管OLED的阴极。
如图2所示，充电模块11包括第一晶体管T1和第三晶体管T3，存储模块13可以包括电容器C，发光器件12可以是有机发光二极管OLED，调整模块15可以包括第二晶体管T2，数据写入模块16可以包括第四晶体管T4，以及驱动模块14可以包括驱动晶体管T5。
具体地，充电模块11的第一端为第一晶体管T1的第一极，充电模块11的第二端为第一晶体管T1的第二极，充电模块11的第三端为第三晶体管T3的第二极。第一晶体管T1的控制极用于接收第一控制信号EN1，第一晶体管T1的第二极耦接第三晶体管T3的第一极以及有机发光二极管OLED的第一极，而第一晶体管T1的第一极用于接收电源电压Vdd。第三晶体管T3的控制极用于接收第二控制信号EN2，第三晶体管T3的第二极与电容器C的第一端(即节点a)、有机发光二极管OLED的第二极、以及驱动晶体管T5的第一极耦接，而第三晶体管T3的第一极与第一晶体管T1的第二极以及有机发光二极管OLED的第一极耦接。
调整模块15的第一端为第二晶体管T2的第一极，调整模块15的第二端为第二晶体管T2的第二极。第二晶体管T2的控制极用于接收第一控制信号EN1，第二晶体管T2的第一极与电容器C的第二端(即节点b)耦接，第二晶体管T2的第二极与第四晶体管T4的第二极以及驱动晶体管T5的控制极耦接。
驱动模块14的第一端为驱动晶体管T5的第一极，驱动模块14的第二端为驱动晶体管T5的第二极，并且驱动模块14的第三端为驱动晶体管T5的控制极。驱动晶体管T5的第一极与电容器C的第一端(即节点a)、 有机发光二极管OLED的第二极以及第三晶体管T3的第二极耦接，驱动晶体管T5的第二极接地，而驱动晶体管T5的控制极与第二晶体管T2的第二极以及第四晶体管T4的第二极耦接。
数据写入模块16的第一端为第四晶体管T4的第一极，数据写入模块16的第二端为第四晶体管T4的第二极。第四晶体管T4的控制极用于接收扫描信号SCAN，第四晶体管T4的第一极用于接收数据信号Data，以及第四晶体管T4的第二极与驱动晶体管T5的控制极以及第二晶体管T2的第二极耦接。
如图2所示，根据本公开实施例的像素电路10可包括5个晶体管以及1个电容器，以解决驱动晶体管的阈值电压(Vth)漂移而造成的显示不均匀问题。与现有技术中包含更多的晶体管与电容器的像素电路相比，根据本公开实施例的像素电路更加简洁，从而能够提升像素显示的开口率。
本公开的实施例还提供了一种用于驱动上述像素电路的驱动方法。该驱动方法可包括：在充电阶段，对存储模块13进行充电；在电压调整阶段，对驱动模块14进行电压调整；以及在发光阶段，对驱动模块14进行电压补偿，并使得发光器件12保持发光。
图3是根据本公开的一个实施例的用于驱动如图2所示的像素电路的驱动信号的时序图。
如图3所示，在充电阶段，将第一控制信号EN1、第二控制信号EN2，以及数据扫描信号SCAN设置为高电平，将数据信号Data设置为低电平。如图2所示，晶体管T1、T2、T3、T4导通，而晶体管T5关闭，此时的电流路径为Vdd-T1-T3-T2-T5-Data，从而实现对电容器C的充电，使得电容器C的第一端(即节点a)的电压为电源电压Vdd。
如图3所示，在电压调整阶段，将第一控制信号EN1以及第二控制信号EN2设置为低电平，而将扫描信号SCAN以及数据信号Data设置为高电平。如图2所示，晶体管T1，T2以及T3关闭，晶体管T4和T5导通。此时，电流路径为节点a-T4-地，从而使得节点a的电压为数据电压V与驱动晶体管T5的阈值电压Vth5之和(即V+Vth5)。
如图2和图3所示，在发光阶段，将第一控制信号EN1设置为高电平，而将第二控制信号EN2、扫描信号SCAN以及数据信号Data设置为低电平。此时，晶体管T3和T4关闭，而晶体管T1、T2和T5导通。当晶体管T1导通时，节点a接入电压Vdd，电容器C的第二端(即节点b)浮空。由于电容器C的存在，因此各个节点之间保持原来的电压差。此时，驱动晶体管T5的栅极的电压(即，节点d的电压)变为Vd＝Vdd-V-Vth5。
根据电流计算公式：
Id＝K(Vgs-Vth5)2
＝K((Vdd-Vd)-Vth5)2
＝K(Vdd-Vdd+V+Vth5-Vth5)2
＝K V2
其中，K为常量，其与驱动晶体管T5的载流子迁移率、栅氧化层电容以及驱动晶体管T5的宽长比相关。
由此，根据本公开的一个实施例的用于驱动像素电路的驱动方法,可以消除因为驱动晶体管T5的阈值电压Vth5的偏差导致的电流波动，从而稳定画面品质。
需要说明的是，图3中的第一控制信号EN1、第二控制信号EN2、扫描信号SCAN以及数据信号Data与各个阶段的关系仅为示意性的。根据本公开的实施例，还可以在电压调整阶段结束之前分别将扫描信号SCAN和数据信号Data切换为低电平。
图4示出了根据本公开的一个实施例的像素电路组的结构框图。
如图4所示，根据本公开实施例的一种像素电路组20，可包括：多个像素电路10。在该像素电路组20中，多个像素电路10中的数据写入模块16的第一端彼此耦接。
由此，根据本公开实施例的一种用于数据复用的像素电路组20，可以通过一根数据线控制多个子像素，从而能够减少数据线的数量，节约集成电路管脚的数目，从而降低集成电路的成本。
与图4中的像素电路的结构框图相对应地，图5示出了根据本公开的 一个实施例的像素电路组的电路图。
从图5可见，根据本公开实施例的像素电路组包括3个级联的如图2所示的像素电路。当然图5的实施例仅为示例性目的，本领域技术人员不难理解，根据本公开另一实施例的像素电路组还可包括2个级联的像素电路，或者3个以上级联的像素电路。
与图2不同的是，图5中的像素电路的数据写入模块与相同的数据线耦接，即晶体管T10、T13以及T14的第一极彼此耦接，并用于接收数据信号Data。此外，数据写入晶体管T10、T13以及T14的栅极分别耦接于与每个像素电路对应的子像素的扫描信号。
由此，根据本公开实施例的一种像素电路组，可以通过一根数据线控制多个子像素，从而能够减少数据线的数量，节约集成电路管脚的数目，从而降低集成电路的成本。
根据本公开的实施例，还提供了一种用于驱动上述的像素电路组的驱动方法。该驱动方法包括：在充电阶段，对多个像素电路中的存储模块进行充电；在电压调整阶段，依次对多个像素电路中的驱动模块进行电压调整；以及在发光阶段，对多个像素电路的驱动模块中的驱动晶体管进行电压补偿，并使得发光器件保持发光。
图6示出了根据本公开的一个实施例的用于驱动如图5所示的像素电路组的驱动信号的时序图。
如图6所示，在充电阶段，将第一控制信号EN1、第二控制信号EN2、第一扫描信号SCAN1、第二扫描信号SCAN2以及第三扫描信号SCAN3设置为高电平，而将数据信号Data设置为低电平。如图5所示，晶体管T1-T10、T13和T14导通，而晶体管T11、T12以及T15关闭。此时，第一至第三像素电路中电流路径分别为Vdd-T1-T4-T7-T10-Data、Vdd-T2-T5-T8-T13-Data以及Vdd-T3-T6-T9-T14-Data，从而分别实现对电容器C1-C3的充电，使得电容器C1-C3的第一端与晶体管T11，T12以及T15的第一极之间的节点a1-a3的电压为电源电压Vdd。
如图6所示，在电压调整阶段，将第一控制信号EN1、第二控制信号 EN2设置为低电平，同时将第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3以及数据信号Data分为三个子阶段。
在第一子阶段，将第一扫描信号SCAN1设置为高电平，将第二扫描信号SCAN2、第三扫描信号SCAN3设置为低电平，同时将数据信号Data设置为与第一子像素对应的灰阶电压V1。此时，如图5所示，晶体管T1、T4、T7关闭，晶体管T10和T11导通。第一像素电路中的电流路径为节点a1-T11-地，从而使得节点a1的电压为数据电压V1与驱动晶体管T11的阈值电压Vth11之和V1+Vth11。
在第二子阶段，将第二扫描信号SCAN2设置为高电平，将第一扫描信号SCAN1、第三扫描信号SCAN3设置为低电平，同时将数据信号Data设置为与第二子像素对应的灰阶电压V2。此时，如图5所示，晶体管T2、T5、T8关闭，晶体管T12和T13导通。第二像素电路中的电流路径为节点a2-T12-地，从而使得节点a2的电压为数据电压V2与驱动晶体管T12的阈值电压Vth12之和V2+Vth12。
在第三子阶段，将第三扫描信号SCAN3设置为高电平，将第一扫描信号SCAN1、第二扫描信号SCAN2设置为低电平，同时将数据信号Data设置为与第三子像素对应的灰阶电压V3。此时，如图5所示，晶体管T3、T6、T9关闭，晶体管T14和T15导通。第三像素电路中的电流路径为节点a3-T15-地，从而使得节点a3的电压为数据电压V3与驱动晶体管T15的阈值电压Vth15之和V3+Vth15。
如图6所示，在发光阶段，将第一控制信号EN1设置为高电平，而将第二控制信号EN2、第一至第三扫描信号SCAN1-SCAN3以及数据信号Data设置为低电平。
此时，如图5所示，在第一像素电路中，晶体管T4和T10关闭，而晶体管T1，T7以及T11导通。当晶体管T1导通时，节点a1接入电压Vdd，电容器C1的第二端(即，节点b1)浮空。由于电容器C1的存在，因此各个节点之间保持原来的电压差。此时，驱动晶体管T11的栅极的电压(即，节点d1的电压)变为Vd1＝Vdd-V1-Vth11。
根据电流计算公式：
Id1＝K1(Vgs1-Vth11)2
＝K1((Vdd-Vd1)-Vth11)2
＝K1(Vdd-Vdd+V1+Vth11-Vth11)2
＝K1V12
其中，K1为常量，其与驱动晶体管T11的载流子迁移率、栅氧化层电容以及驱动晶体管T11的宽长比相关。
由此，可以消除第一像素电路中因为驱动晶体管T11的阈值电压Vth11的偏差导致的电流波动，从而稳定OLED的画面品质。
此时，如图5所示，第二像素电路中，晶体管T5和T13关闭，而晶体管T2，T8以及T12导通。当晶体管T2导通时，节点a2接入电压Vdd，电容器C2的第二端(即，节点b2)浮空。由于电容器C2的存在，因此各个节点之间保持原来的电压差。此时，驱动晶体管T12的栅极的电压(即，节点d2的电压)变为Vd2＝Vdd-V2-Vth12。
根据电流计算公式：
Id2＝K2(Vgs2-Vth12)2
＝K2((Vdd-Vd2)-Vth12)2
＝K2(Vdd-Vdd+V2+Vth12-Vth12)2
＝K2V22
其中，K2为常量，其与驱动晶体管T12的载流子迁移率、栅氧化层电容以及驱动晶体管T12的宽长比相关。
由此，可以消除第二像素电路中因为阈值电压Vth12的偏差导致的电流波动，稳定OLED的画面品质。
此时，如图5所示，第三像素电路中，晶体管T6和T14关闭，而晶体管T3，T9以及T15导通。当晶体管T3导通时，节点a3接入电压Vdd，电容器C3的第二端(即，节点b3)浮空。由于电容器C3的存在，因此各个节点之间保持原来的电压差。此时，驱动晶体管T15的栅极的电压(即，节点d3的电压)变为Vd3＝Vdd-V3-Vth15。
根据电流计算公式：
Id3＝K3(Vgs3-Vth15)2
＝K3((Vdd-Vd3)-Vth15)2
＝K3(Vdd-Vdd+V3+Vth15-Vth15)2
＝K3V32
其中，K3为常量，其与驱动晶体管T15的载流子迁移率、栅氧化层电容以及驱动晶体管T15的宽长比相关。
由此，可以消除第三像素电路中因为驱动晶体管T15的阈值电压Vth15的偏差导致的电流波动，从而稳定OLED的画面品质。
需要说明的是，图6中的第一控制信号EN1、第二控制信号EN2、扫描信号SCAN1-SCAN3以及数据信号Data与各个阶段的关系仅为示意性的。根据本公开的实施例，还可以在电压调整阶段结束之前分别将扫描信号SCAN1-SCAN 3和数据信号Data切换为低电平。本领域技术人员应当理解，数据信号Data上的电压V1-V3仅用于示意性说明第一至第三子像素的灰阶电压，而第一至第三子像素的灰阶电压V1-V3的关系不仅限于此。
基于同样的发明构思，本公开的实施例还提供了包括上述任一种像素电路或者像素电路组的阵列基板，其能够消除因为驱动晶体管的阈值电压Vth的偏差导致的电流波动，从而稳定画面品质。
基于同样的发明构思，本公开的实施例还提供了包括上述任一种阵列基板的显示面板，其能够消除因为驱动晶体管的阈值电压Vth的偏差导致的电流波动，从而稳定画面品质。
基于同样的发明构思，本公开的实施例还提供了一种显示装置，该显示装置包括上述任意一种的显示面板。根据本公开实施例提供的显示装置，其能够消除因为驱动晶体管的阈值电压Vth的偏差导致的电流波动，从而稳定画面品质。
需要说明的是，本实施例中的显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显 示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但是，本公开的保护范围不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替代，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素电路，包括：充电模块、存储模块、调整模块、数据写入模块、驱动模块以及发光器件，
    其中，所述充电模块的第一端用于接收第一电压信号，所述充电模块的第二端与所述发光器件的第一端耦接，所述充电模块的第三端与所述存储模块的第一端、所述发光器件的第二端以及所述驱动模块的第一端耦接；
    所述存储模块的第二端与所述调整模块的第一端耦接；
    所述调整模块的第二端与所述数据写入模块的第二端以及所述驱动模块的第三端耦接；
    所述数据写入模块的第一端用于接收数据信号；
    所述驱动模块的第二端用于接收第二电压信号；
    其中，所述充电模块用于对所述存储模块进行充电，所述调整模块用于对所述驱动模块进行电压补偿，所述驱动模块用于驱动所述发光器件发光。
  2. 根据权利要求1所述的像素电路，其中，所述充电模块包括第一晶体管和第三晶体管，
    其中，所述第一晶体管的第一极用于接收所述第一电压信号，所述第一晶体管的控制极用于接收第一控制信号，所述第一晶体管的第二极与所述第三晶体管的第一极以及所述发光器件的第一端耦接，
    所述第三晶体管的控制极用于接收第二控制信号，所述第三晶体管的第二极与所述存储模块的第一端、所述发光器件的第二端以及所述驱动模块的第一端耦接。
  3. 根据权利要求1或2所述的像素电路，其中，所述存储模块包括电容器，所述电容器的第一端与所述驱动模块的第一端、所述发光器件的第二端以及所述充电模块的第三端耦接，所述电容器的第二端与所述调整模块的第一端耦接。
  4. 根据权利要求3所述的像素电路，其中，所述调整模块包括第二晶 体管，所述第二晶体管的第一极与所述电容器的第二端耦接，所述第二晶体管的第二极与所述数据写入模块的第二端以及所述驱动模块的第三端耦接，所述第二晶体管的控制极用于接收第一控制信号。
  5. 根据权利要求4所述的像素电路，其中，所述驱动模块包括驱动晶体管，所述驱动晶体管的第一极与所述电容器的第一端、所述发光器件的第二端以及所述充电模块的第三端耦接，所述驱动晶体管的第二极用于接收第二电压信号，所述驱动晶体管的控制极与所述第二晶体管的第二极以及所述数据写入模块的第二端耦接。
  6. 根据权利要求5所述的像素电路，其中，所述数据写入模块包括第四晶体管，所述第四晶体管的第一极用于接收数据信号，所述第四晶体管的第二极与所述驱动晶体管的控制极以及所述第二晶体管的第二极耦接，所述第四晶体管的控制极用于接收扫描信号。
  7. 根据权利要求1-6中任一项所述的像素电路，其中，所述像素电路中的晶体管都为N型晶体管。
  8. 根据权利要求1-6中任一项所述的像素电路，其中，所述像素电路中的晶体管都为P型晶体管。
  9. 一种像素电路组，包括：多个如权利要求1-8中任一项所述的像素电路，其中，所述多个像素电路的数据写入模块与相同的数据线耦接。
  10. 一种用于驱动权利要求1-8中任一项所述的像素电路的驱动方法，包括：
    在充电阶段，对所述存储模块进行充电，使得所述存储模块的第一端的电压为第一电压；
    在电压调整阶段，对所述驱动模块进行电压调整，使得所述存储模块的第一端的电压为数据电压与所述驱动模块中的驱动晶体管的阈值电压之和；以及
    在发光阶段，使得所述发光器件保持发光，并使得所述驱动模块的第三端的电压为所述第一电压减去所述数据电压以及减去所述驱动模块中的驱动晶体管的阈值电压。
  11. 一种用于驱动权利要求9所述的像素电路组的驱动方法，包括：
    在充电阶段，对多个像素电路的存储模块进行充电，使得各个像素电路的所述存储模块的第一端的电压为第一电压；
    在电压调整阶段，依次对多个像素电路的驱动模块进行电压调整，使得各个像素电路的所述存储模块的第一端的电压为对应于所述像素电路的数据电压与对应于所述像素电路的所述驱动模块中的驱动晶体管的阈值电压之和；以及
    在发光阶段，使得所述发光器件保持发光，并使得各个像素电路的所述驱动模块的第三端的电压为所述第一电压减去对应于所述像素电路的数据电压以及减去对应于所述像素电路的所述驱动模块中的驱动晶体管的阈值电压。
  12. 一种阵列基板，包括权利要求1-8中任一项所述的像素电路。
  13. 一种阵列基板，包括权利要求9所述的像素电路组。
  14. 一种显示面板，包括权利要求12或13所述的阵列基板。
  15. 一种显示装置，包括权利要求14所述的显示面板。
PCT/CN2017/071519 2016-05-11 2017-01-18 像素电路、驱动方法、阵列基板、显示面板及显示装置 WO2017193630A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/554,516 US10037730B2 (en) 2016-05-11 2017-01-18 Pixel circuit, drive method, array substrate, display panel and display device
EP17755043.1A EP3457393A4 (en) 2016-05-11 2017-01-18 PIXEL CIRCUIT, EXCITATION METHOD, MATRIX SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610305849.9 2016-05-11
CN201610305849.9A CN105761676B (zh) 2016-05-11 2016-05-11 像素电路、驱动方法、阵列基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2017193630A1 true WO2017193630A1 (zh) 2017-11-16

Family

ID=56322782

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/071519 WO2017193630A1 (zh) 2016-05-11 2017-01-18 像素电路、驱动方法、阵列基板、显示面板及显示装置

Country Status (4)

Country Link
US (1) US10037730B2 (zh)
EP (1) EP3457393A4 (zh)
CN (1) CN105761676B (zh)
WO (1) WO2017193630A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105761676B (zh) * 2016-05-11 2017-12-05 京东方科技集团股份有限公司 像素电路、驱动方法、阵列基板、显示面板及显示装置
CN106448567B (zh) 2016-12-08 2020-06-05 合肥鑫晟光电科技有限公司 像素驱动电路、驱动方法、像素单元和显示装置
CN108648696B (zh) * 2018-03-22 2020-02-18 京东方科技集团股份有限公司 像素电路、阵列基板、显示装置和像素驱动方法
CN116631335A (zh) * 2023-05-24 2023-08-22 重庆惠科金渝光电科技有限公司 显示驱动电路、驱动方法、显示面板及可读存储介质

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859791A (zh) * 2009-04-09 2010-10-13 友达光电股份有限公司 有源矩阵式显示装置的像素结构
CN101996579A (zh) * 2010-10-26 2011-03-30 华南理工大学 有源有机电致发光显示器的像素驱动电路及其驱动方法
US20120120042A1 (en) * 2010-11-11 2012-05-17 Hsuan-Ming Tsai Pixel driving circuit of an organic light emitting diode
CN104021763A (zh) * 2014-06-11 2014-09-03 合肥鑫晟光电科技有限公司 像素电路、显示装置和像素电路的驱动方法
CN104485074A (zh) * 2014-12-30 2015-04-01 合肥鑫晟光电科技有限公司 像素驱动电路、方法和显示装置
US20160055792A1 (en) * 2014-08-25 2016-02-25 Samsung Display Co., Ltd. Pixel and organic light-emitting diode (oled) display
CN105761676A (zh) * 2016-05-11 2016-07-13 京东方科技集团股份有限公司 像素电路、驱动方法、阵列基板、显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3259774B2 (ja) * 1999-06-09 2002-02-25 日本電気株式会社 画像表示方法および装置
TWI467541B (zh) * 2004-09-16 2015-01-01 Semiconductor Energy Lab 顯示裝置和其驅動方法
KR100659155B1 (ko) * 2005-12-05 2006-12-19 한국과학기술원 전류 피드백형 ａｍｏｌｅｄ 구동 회로
CN102930819B (zh) * 2011-08-11 2015-05-06 群康科技(深圳)有限公司 显示器及其驱动方法
CN102654976B (zh) * 2012-01-12 2014-12-24 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN104464638B (zh) * 2014-12-29 2017-05-10 合肥鑫晟光电科技有限公司 像素驱动电路、驱动方法、阵列基板和显示设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859791A (zh) * 2009-04-09 2010-10-13 友达光电股份有限公司 有源矩阵式显示装置的像素结构
CN101996579A (zh) * 2010-10-26 2011-03-30 华南理工大学 有源有机电致发光显示器的像素驱动电路及其驱动方法
US20120120042A1 (en) * 2010-11-11 2012-05-17 Hsuan-Ming Tsai Pixel driving circuit of an organic light emitting diode
CN104021763A (zh) * 2014-06-11 2014-09-03 合肥鑫晟光电科技有限公司 像素电路、显示装置和像素电路的驱动方法
US20160055792A1 (en) * 2014-08-25 2016-02-25 Samsung Display Co., Ltd. Pixel and organic light-emitting diode (oled) display
CN104485074A (zh) * 2014-12-30 2015-04-01 合肥鑫晟光电科技有限公司 像素驱动电路、方法和显示装置
CN105761676A (zh) * 2016-05-11 2016-07-13 京东方科技集团股份有限公司 像素电路、驱动方法、阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN105761676A (zh) 2016-07-13
CN105761676B (zh) 2017-12-05
EP3457393A1 (en) 2019-03-20
US10037730B2 (en) 2018-07-31
US20180166008A1 (en) 2018-06-14
EP3457393A4 (en) 2019-11-06

Similar Documents

Publication Publication Date Title
CN107342044B (zh) 像素电路、显示面板和像素电路的驱动方法
US10565933B2 (en) Pixel circuit, driving method thereof, array substrate, display device
US10083658B2 (en) Pixel circuits with a compensation module and drive methods thereof, and related devices
WO2020001026A1 (zh) 像素驱动电路及方法、显示面板
JP6882591B2 (ja) Ａｍｏｌｅｄピクセル駆動回路及びピクセル駆動方法
US11410600B2 (en) Pixel driving circuit and method, display apparatus
WO2016161866A1 (zh) 像素电路及其驱动方法、显示装置
US9734763B2 (en) Pixel circuit, driving method and display apparatus
US11417280B2 (en) Pixel circuit and driving method therefor, and display substrate and display device
US9489893B2 (en) AMOLED pixel driving circuit and driving method thereof, and array substrate
WO2018076719A1 (zh) 像素驱动电路及其驱动方法、显示面板和显示装置
US9966006B2 (en) Organic light-emitting diode pixel circuit, display apparatus and control method
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
WO2019056813A1 (zh) 像素电路及其控制方法、显示基板、显示装置
US11176886B2 (en) Pixel compensation circuit, driving method thereof, display panel, and display device
WO2016141681A1 (zh) 像素电路及其驱动方法、显示装置
US20140132642A1 (en) Pixel circuit, display device and driving method of pixel circuit
US10304381B2 (en) Pixel compensation circuits, driving devices, and display devices
CN109887464B (zh) 像素电路及其驱动方法、显示面板和显示设备
US11270638B2 (en) Display compensation circuit and method for controlling the same, and display apparatus
WO2019052435A1 (zh) 像素驱动电路及方法、显示装置
WO2018014645A1 (zh) 像素电路、其驱动方法及显示面板
JP6794576B2 (ja) Ａｍｏｌｅｄピクセル駆動回路及びピクセル駆動方法
US11341909B2 (en) Pixel drive circuit and drive method thereof, and display device
US10553159B2 (en) Pixel circuit, display panel and display device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15554516

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2017755043

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17755043

Country of ref document: EP

Kind code of ref document: A1