WO2016161866A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2016161866A1
WO2016161866A1 PCT/CN2016/076054 CN2016076054W WO2016161866A1 WO 2016161866 A1 WO2016161866 A1 WO 2016161866A1 CN 2016076054 W CN2016076054 W CN 2016076054W WO 2016161866 A1 WO2016161866 A1 WO 2016161866A1
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Prior art keywords
transistor
pole
voltage
gate
signal
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PCT/CN2016/076054
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English (en)
French (fr)
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李云飞
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京东方科技集团股份有限公司
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Priority to US15/321,010 priority Critical patent/US10163394B2/en
Publication of WO2016161866A1 publication Critical patent/WO2016161866A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method of the pixel circuit, and a display device including the pixel circuit.
  • OLED Organic Light Emitting Diode
  • the driving current of all the pixels is provided by the backplane power supply, and since the backplane power supply line has a certain resistance, the power supply voltage near the power supply power supply region is higher than the power supply voltage away from the power supply position region.
  • the phenomenon is called the IR drop.
  • a set of thin film transistors and storage capacitors are integrated in each pixel circuit, and the current through the OLED is not only controlled by the data voltage but also by the threshold voltage of the thin film transistor (TFT).
  • the threshold voltages of the thin film transistors in different pixel circuits are different, so that the current flowing through the OLED device may also be different, thereby affecting the entire display screen. Uniformity of brightness.
  • An object of the present invention is to provide a pixel circuit and a driving method thereof, and a display device for reducing the influence of a threshold voltage and a voltage drop of a power supply on display uniformity.
  • a pixel circuit including a driving transistor, a light emitting device, a storage capacitor, a gate module, a compensation module, and a switch module.
  • the gating module is connected between the data line and the gate of the driving transistor, and the first end of the storage capacitor is connected to the gate of the driving transistor, and the storing A second end of the storage capacitor is coupled to the first pole of the drive transistor.
  • the compensation module includes: a reset sub-module, an output end of the reset sub-module is connected to a second pole of the driving transistor, and is configured to charge a first pole of the driving transistor in a reset phase to drive the driving a threshold voltage of the transistor is stored in the storage capacitor; and a voltage dividing submodule, a first end of the voltage dividing submodule is connected to a first pole of the driving transistor, and a second end of the voltage dividing submodule is A high level input is coupled such that the divided submodule is in series with the storage capacitor.
  • the switch module is respectively connected to the high-level input terminal and the driving transistor for turning on the high-level input terminal and the first pole of the driving transistor in a light-emitting phase.
  • the light emitting device is configured to emit light under the driving of the driving transistor.
  • the reset sub-module may include a first transistor, a reset control terminal, and a reference voltage terminal, a gate of the first transistor being connected to the reset control terminal, a first pole of the first transistor and the reference voltage terminal Connected, the second pole of the first transistor is coupled to the second pole of the drive transistor.
  • the reset sub-module may include a first transistor and a reset control terminal, a gate of the first transistor is connected to the reset control terminal, and a first pole of the first transistor is connected to a gate of the driving transistor, The second pole of the first transistor is coupled to the second pole of the drive transistor.
  • the voltage dividing submodule package may include a voltage dividing capacitor, a first end of the voltage dividing capacitor is formed as a first end of the voltage dividing submodule, and a second end of the voltage dividing capacitor is formed as the voltage dividing The second end of the submodule.
  • the switch module may include a second transistor and a light emission control signal end, a gate of the second transistor is connected to the light emission control signal end, and a first pole of the second transistor is connected to a high level input end. A second pole of the second transistor is coupled to the first pole of the drive transistor.
  • the switch module may be further connected between the second pole of the driving transistor and the light emitting device such that the second pole of the driving transistor and the anode of the light emitting device are electrically connected to each other in a light emitting phase.
  • the switch module may include a second transistor, a third transistor, and a light emission control signal end, and a gate of the second transistor is connected to the light emission control signal end, the second a first pole of the transistor is connected to the high level input terminal, a second pole of the second transistor is connected to the first pole of the driving transistor, and a gate of the third transistor is connected to the light emitting control signal end.
  • a first pole of the third transistor is coupled to a second pole of the drive transistor, and a second pole of the third transistor is coupled to the light emitting device.
  • the gate module may include a fourth transistor, a gate of the fourth transistor is connected to the scan line, a first pole of the fourth transistor is connected to the data line, and a second pole of the fourth transistor is The gates of the drive transistors are connected.
  • a driving method of a pixel circuit which is the pixel circuit provided by the above aspect of the invention, the driving method comprising a reset phase, a compensation phase, and an illumination phase.
  • the data line supplies a data voltage signal to the gate of the driving transistor via the gating module, and the first sub-pole of the driving transistor is charged by the reset sub-module to set a threshold of the driving transistor A voltage signal is stored within the storage capacitor.
  • the compensation phase the data line is supplied with a preset voltage signal from the gate module to the gate of the driving transistor to collectively store the data voltage signal and the threshold voltage signal into the storage capacitor.
  • the gating module is turned off, and the high level input terminal and the first pole of the driving transistor are electrically connected to each other through the switching module to cause the light emitting device to emit light.
  • the reset sub-module may include a first transistor, a reset control terminal, and a reference voltage terminal, a gate of the first transistor being connected to the reset control terminal, a first pole of the first transistor and the reference voltage terminal Connected, the second pole of the first transistor is coupled to the second pole of the drive transistor.
  • the voltage dividing submodule includes a voltage dividing capacitor, a first end of the voltage dividing capacitor is formed as a first end of the voltage dividing submodule, and a second end of the voltage dividing capacitor is formed as the voltage dividing submodule The second end.
  • the switch module includes an emission control signal terminal, a second transistor and a third transistor, a gate of the second transistor, a gate of the third transistor is connected to the light emission control signal end, and the second transistor a first pole is connected to the high level input terminal, a second pole of the second transistor is connected to a first pole of the driving transistor, a first pole of the third transistor and a second pole of the driving transistor The poles are connected, and the second pole of the third transistor is connected to the light emitting device.
  • the gating module includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a gate of the fourth transistor is connected to the scan line.
  • an open signal is provided to both the reset control terminal and the scan line, a data voltage signal is supplied to the data line, and a turn-off signal is provided to the light-emitting control signal terminal, and the reference voltage terminal is via the first transistor And driving the transistor to charge the first pole of the driving transistor.
  • a shutdown signal is provided to the reset control terminal, an enable signal is provided to the scan line, a predetermined voltage signal is supplied to the data line, and a turn-off signal is provided to the light emission control signal terminal.
  • a shutdown signal is provided to the reset control terminal, a shutdown signal is provided to the scan line, a predetermined voltage signal is provided to the data line, and an enable signal is provided to the illumination control signal terminal.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor and the driving transistor may be P-type transistors, and the turn-on signal is a low level signal, and the turn-off signal is a high level signal.
  • a display device comprising the pixel circuit provided by the above aspect of the invention.
  • the storage capacitor can store the threshold voltage signal of the driving transistor and the data voltage signal information supplied from the data line before the light emitting phase, and the gate-source voltage of the driving transistor is compensated due to the bootstrap action of the storage capacitor.
  • the phase is the same as the illuminating phase, and therefore, the magnitude of the driving current supplied to the illuminating device is independent of the threshold voltage and the voltage supplied from the high-level input terminal, thereby reducing the influence of the threshold voltage and the internal resistance drop of the power supply on display uniformity, thereby The display effect of the display device is improved.
  • FIG. 1 is a block diagram showing the structure of a pixel circuit in an embodiment of the present invention.
  • FIG. 2 is a detailed structural diagram of a pixel circuit in a first embodiment of the present invention.
  • FIG. 3 is a detailed structural diagram of a pixel circuit in a second embodiment of the present invention.
  • FIG. 4 is a timing chart of driving of signal terminals of a pixel circuit in an embodiment of the present invention.
  • the reference numerals are: 10, a light-emitting device; 20, a gating module; 30, a compensation module; 31, a reset sub-module; 32, a voltage-dividing sub-module; 40, a switch module; T1, a first transistor; Two transistors; T3, third transistor; T4, fourth transistor; DTFT, driving transistor; C1, storage capacitor; C2, voltage dividing capacitor; VDD, high level input terminal; VSS, low level input terminal; GATE, scanning Line; DATA, data line; RESET, reset control terminal; EM, lighting control signal terminal; SUS, reference voltage terminal.
  • the pixel circuit includes a driving transistor DTFT, a light emitting device 10, a storage capacitor C1, and a gate module 20.
  • the input end of the gating module 20 is connected to the data line DATA, and the output end of the gating module 20 is connected to the gate of the driving transistor DTFT (ie, the Cst node shown in FIG. 1), the first end of the storage capacitor C1 and the driving transistor
  • the gate of the DTFT is connected, and the second end of the storage capacitor C1 is connected to the first pole of the driving transistor DTFT (i.e., the S node shown in FIG. 1).
  • the pixel circuit further includes a compensation module 30 and a switch module 40.
  • the compensation module 30 includes a reset sub-module 31.
  • the output end of the reset sub-module 31 is connected to the second pole of the driving transistor DTFT (ie, the D-node shown in FIG. 1) for the first to the driving transistor DTFT in the reset phase.
  • the pole is charged to store the threshold voltage Vth of the driving transistor DTFT in the storage capacitor C1; and the voltage dividing sub-module 32, the first end of the voltage dividing sub-module 32 is connected to the first pole of the driving transistor DTFT, and the voltage dividing sub-module 32
  • the second terminal is coupled to the high level input terminal VDD such that the voltage dividing sub-module 32 is connected in series with the storage capacitor C1.
  • the switch module 40 is connected to the high level input terminal VDD and the driving transistor DTFT, respectively, for electrically connecting the high level input terminal VDD and the first pole of the driving transistor DTFT to each other in the light emitting phase.
  • the data line DATA supplies the data voltage signal V data to the gate (Cst node) of the driving transistor DTFT in the reset phase, respectively, and the predetermined voltage signal V ref in the compensation phase. Since the voltage dividing sub-module 32 is connected in series with the storage capacitor C1, the voltage of the S node also changes correspondingly in the reset phase and the compensation phase, and the ratio of the change amount of the S node voltage to the change amount of the Cst node voltage is less than 1.
  • the constant ⁇ is such that the voltage stored by the storage capacitor C1 includes both the information of the threshold voltage Vth stored in the reset phase and the voltage information supplied to the Cst node by the data line in the reset phase and the compensation phase, respectively.
  • the voltage stored by the storage capacitor C1 is: V ref -[(V data -V th )+ ⁇ (V ret -V data )]; the voltage value and the voltage of the high-level input terminal VDD None.
  • V gs V ref - [(V data - V th ) + ⁇ (V ref - V data )]; therefore, in the light-emitting phase, the driving current of the light-emitting device is:
  • I oled 0.5 ⁇ n C ox (W/L)(V gs -V th ) ⁇ 2
  • ⁇ n is the carrier mobility
  • C ox is the gate oxide oxide of the driving transistor
  • W/L is the aspect ratio of the conductive channel of the driving transistor.
  • the reset sub-module 31 includes a first transistor T1, a reset control terminal RESET, and a reference voltage terminal SUS.
  • the gate of the first transistor T1 is connected to the reset control terminal RESET.
  • a first pole of a transistor T1 is connected to a reference voltage terminal SUS, and a second pole of the first transistor T1 is connected to a second pole of the driving transistor DTFT.
  • the reset control terminal RESET provides an ON signal to turn on the first transistor T1, and the reference voltage signal of the reference voltage terminal SUS is input to the second electrode (D node) of the driving transistor DTFT through the first transistor T1.
  • the gate module 20 is turned on, and the data voltage signal V data is input to the gate (Cst node) of the driving transistor DTFT, and at this time, the first pole of the driving transistor DTFT is driven.
  • the voltage of the (S node) maintains the voltage value of the previous stage (ie, the high level signal V dd supplied from the high level input terminal VDD ), so that V gs of the driving transistor DTFT is ⁇ 0, thereby turning on the driving transistor DTFT, reference
  • the voltage terminal SUS charges the S node until the driving transistor DTFT is turned off. At this time, the voltage of the S node is V data -V th , the voltage of the Cst node is V data , and the voltage across the storage capacitor C1 is V th .
  • the reset sub-module 31 includes a first transistor T1 and a reset control terminal RESET.
  • the gate of the first transistor T1 is connected to the reset control terminal RESET, and the first transistor T1 is One pole is connected to the output of the gate module 20, and the second pole of the first transistor T1 is connected to the second pole of the driving transistor DTFT.
  • the first electrode of the driving transistor DTFT may be a source, and the second electrode may be a drain.
  • the gate of the driving transistor DTFT is charged by the data line DATA so that the Cst node voltage reaches the data signal voltage Vdata while The data line DATA is charged to the S node through the first transistor T1. It can be understood by those skilled in the art that in the second embodiment of FIG. 3, charging of the S node can be completed only when the driving transistor DTFT is an enhancement type thin film transistor, and the driving transistor DTFT is depleted. Thin film transistors cannot charge their first poles.
  • the conduction condition of the depletion thin film transistor is that the voltage of the first electrode needs to be larger than the gate voltage, and the data line DATA is simultaneously charged by the gate and source of the driving transistor DTFT.
  • the embodiment of FIG. 2 can be used for both an enhanced thin film transistor and a depletion mode thin film transistor.
  • the voltage dividing sub-module 32 includes a voltage dividing capacitor C2.
  • the first end of the voltage dividing capacitor C2 is formed as a first end of the voltage dividing submodule 32, and the second voltage dividing capacitor C2 is formed.
  • the terminal is formed as a second end of the voltage dividing sub-module 32, that is, the first end of the voltage dividing capacitor C2 is connected to the first pole of the driving transistor DTFT, and the second end of the voltage dividing capacitor C2 is connected to the high level input terminal VDD.
  • the switch module 40 includes a second transistor T2 and a light-emission control signal terminal EM.
  • the gate of the second transistor T2 is connected to the light-emission control signal terminal EM, and the first pole and the high-voltage of the second transistor T2.
  • Flat input terminal VDD connected, second transistor T2 The second pole is connected to the first pole of the driving transistor DTFT.
  • the light emission control signal terminal EM provides an on signal to turn on the second transistor T2, so that the high level signal of the high level input terminal VDD is input to the first electrode of the driving transistor DTFT via the second transistor T2.
  • the switch module 40 may also be connected to the light emitting device such that the second pole of the driving transistor DTFT and the anode of the light emitting device 10 are electrically connected to each other in the light emitting phase. In the reset phase and the compensation phase, the switch modules 40 are all turned off to prevent current from passing through the light emitting device to cause the light emitting device to emit light.
  • the switch module 40 further includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the light emission control signal terminal EM, and the first electrode of the third transistor T3 and the driving transistor DTFT are The second pole is connected, and the second pole of the third transistor T3 is connected to the anode of the light emitting device 10.
  • the gate module 20 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the scan line GATE, the first pole of the fourth transistor T4 is connected to the data line DATA, and the second pole of the fourth transistor T4 is coupled to the drive transistor DTFT.
  • the gates are connected. When the scan line GATE provides an on signal, the fourth transistor T4 is turned on, so that the signal on the data line DATA is output to the gate of the driving transistor DTFT via the fourth transistor T4.
  • the first transistor T1 to the fourth transistor T4 and the driving transistor DTFT are P-type transistors, and the first source and the second terminal of each of the transistors are correspondingly, and the turn-on signal is low.
  • the shutdown signal is a high level signal; of course, each transistor can also be an N-type transistor, or a part of an N-type transistor, a part of a P-type transistor, as long as the voltage signal input to its gate is adjusted accordingly, so that each The conduction state of the transistor at each stage may be the same as in the present invention.
  • the driving process of the pixel circuit of the present invention comprises three phases: a reset phase, a compensation phase, and an illumination phase.
  • the structure of the first embodiment (shown in FIG. 2) will be taken as an example, and each stage will be described in conjunction with FIG. 4.
  • the scan line GATE and the reset control terminal RESET provide a low level signal
  • the light emission control signal terminal EM and the data line DATA provide a high level signal.
  • the first transistor T1 and The fourth transistor T4 is turned on, and the second transistor T2 and the third transistor T3 are turned off.
  • the high-level data signal V data on the data line DATA is input to the gate of the driving transistor DTFT via the fourth transistor T4, the driving transistor DTFT is turned on, and the reference voltage terminal SUS charges the S node through the first transistor T1 and the driving transistor DTFT. Until the voltage at the S node reaches V data -V th .
  • the high level signal V dd of the high level input terminal VDD should satisfy: V dd >V data,max -V th ; the reference voltage signal V sus of the reference voltage terminal SUS It should satisfy: V sus ⁇ V data,min -Vth; where V data,max is the maximum value among the plurality of data voltage signals V data corresponding to the writing of different gray signals, and V data,min is the plurality of The minimum value in the data voltage signal V data .
  • the scan line GATE and the data line DATA provide a low level signal
  • the illumination control signal terminal EM and the reset control terminal RESET provide a high level signal, wherein the data line DATA is low.
  • the flat signal is the preset voltage signal V ref .
  • the fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, and the third transistor T3 are turned off.
  • the Cst node voltage is changed from the data voltage signal V data in the reset phase to the preset voltage signal V ref in the compensation phase, the S node is in a floating state, and the voltage at the node is affected by the Cst node voltage.
  • the amount of change ⁇ V cst between the reset phase and the compensation phase of the voltage at the Cst node is fed back to the S node. Due to the voltage division of the voltage dividing capacitor C2, the amount of change ⁇ V s of the S node voltage in the reset phase and the compensation phase is [C1 /(C1+C2)](V ref -V data ), so the voltage of the S node in the compensation phase is: (V data - V th ) + [C1/(C1 + C2)] (V ref - V data ). It can be seen that in the compensation phase, the voltage information stored by the storage capacitor C1 includes voltage information of V data and V th simultaneously.
  • the low level signal V ref of the data line can be equal to or slightly larger than the data voltage provided in the reset phase.
  • the minimum value of the signal is V data,min .
  • the light-emission control signal terminal EM and the data line DATA provide a low-level signal
  • the reset control terminal RESET and the scan line GATE provide a high-level signal.
  • the first transistor T1 and The fourth transistor T4 is turned off, the second transistor T2 and the third transistor T3 are turned on, and the high-level signal terminal VDD is charged to the first-pole S node of the driving transistor DTFT through the second transistor T2, so that the voltage of the S node is (V data -V th )+[C1/(C1+C2)](V ref -V data ) is raised to Vdd, and the gate-source voltage of the driving transistor DTFT is maintained and stored in the compensation phase due to the bootstrap action of the first capacitor C1
  • the voltage across capacitor C1 is the same, ie:
  • V gs V ref - ⁇ (V data -V th )+[C1/(C1+C2)](V ref -V data ) ⁇ ;
  • the current through the light emitting device is:
  • ⁇ n is the carrier mobility
  • C ox is the gate oxide oxide of the driving transistor DTFT
  • W/L is the width to length ratio of the conductive channel of the driving transistor DTFT
  • a driving method of a pixel circuit which is the above-described pixel circuit, the driving method including a reset phase, a compensation phase, and an emission phase.
  • the data line DATA supplies a high-level data voltage signal V data to the gate of the driving transistor DTFT via the gating module 20, and charges the first electrode of the driving transistor DTFT through the reset sub-module 31 to drive the driving transistor DTFT.
  • the threshold voltage signal V th is stored in the storage capacitor C1;
  • the data line DATA supplies a low-level preset voltage signal V ref to the gate of the driving transistor DTFT via the gating module 20 to set the high-level data voltage signal V data and the threshold voltage signal V th is collectively stored into the storage capacitor C1;
  • the gating module 20 is turned off, and the high-level input terminal VDD and the first electrode of the driving transistor DTFT are electrically connected to each other through the switching module 40 to cause the light-emitting device 10 to emit light.
  • the reset sub-module 31 includes a first transistor T1, a reset control terminal RESET and a reference voltage terminal SUS
  • the voltage dividing sub-module 32 includes a voltage dividing capacitor C2
  • the switch module 40 includes an emission control signal terminal EM
  • the second transistor T2 and the third transistor T3 the gate module 20 includes a fourth transistor T4.
  • the first transistor T1, the driving transistor and the fourth transistor T4 are turned on DTFT, the high-level data voltage V data signal input to the gate of the driving transistor T4 DTFT fourth transistor, the reference voltage terminal SUS
  • the reference voltage signal V SUS is charged to the S node through the first transistor T1 and the driving transistor DTFT until the driving transistor DTFT is turned off, at which time the S node voltage reaches V data -V th , the Cst node voltage is V data , and the storage capacitor C1 is inside.
  • the stored voltage is V th .
  • a shutdown signal is supplied to the reset control terminal RESET, an ON signal is supplied to the scan line GATE, and a low-level preset voltage signal V ref is supplied to the data line DATA.
  • the first transistor T1 is turned off
  • the fourth transistor T4 is turned on
  • the data line DATA inputs a low-level preset voltage signal V ref to the Cst node.
  • the signals of the illumination control signal terminal EM are all off signals, so that the second transistor T2 and the third transistor T3 are turned off in two stages, the S node is in a floating state, and the node voltage is subjected to Cst.
  • the influence of the node voltage change becomes (V data - V th ) + [C1/(C1 + C2)] (V ref - V data ).
  • a turn-off signal is supplied to the scan line GATE, and an turn-on signal is supplied to the light emission control signal terminal EM, so that the fourth transistor T4 is turned off, and the second transistor T2 and the third transistor T3 are turned on, and the high voltage is turned on.
  • the high level voltage V dd of the flat input terminal VDD is input to the S node, and the light emitting device 10 is driven to emit light.
  • the bootstrap action of the storage capacitor C1 causes the voltage between the gate and the source of the driving transistor DTFT to remain the same as in the compensation phase, that is, regardless of the high level signal V dd .
  • the first transistor T1 to the fourth transistor T4 and the driving transistor DTFT are both P-type transistors, and accordingly, the turn-on signal is a low level signal, and the turn-off signal is a high level signal.
  • the voltage stored in the storage capacitor contains the information of the threshold voltage
  • the voltage stored in the storage capacitor is independent of the voltage of the high-level input terminal, and thus flows through
  • the current of the light-emitting device is independent of the threshold voltage and the voltage of the high-level input terminal, so that the threshold voltage non-uniformity and the internal resistance drop of the power supply can be compensated, thereby improving the uniformity of display brightness.
  • a display device including the present invention
  • the above drive circuit is provided.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the stability of the pixel circuit provided by the present invention is better, it is not affected by the threshold voltage of the transistor inside the circuit and the internal resistance voltage drop of the backplane power supply, so that the driving current is not affected by the threshold voltage of the transistor and the backplane unit. Improve display performance while extending the life of the light-emitting device.

Abstract

一种像素电路及其驱动方法和一种显示装置，所述像素电路包括：驱动晶体管（DTFT）、发光器件（10）、存储电容器（C1）、选通模块（20）、补偿模块（30）和开关模块（40）。存储电容器（C1）的第一端与驱动晶体管（DTFT）的栅极相连，存储电容器（C1）的第二端与驱动晶体管（DTFT）的第一极相连。补偿模块（30）包括：复位子模块（31），所述复位子模块（31）的输出端与驱动晶体管（DTFT）的第二极相连，用于在复位阶段（t1）向驱动晶体管（DTFT）的第一极充电，以将驱动晶体管（DTFT）的阈值电压（Vth）存储在存储电容器（C1）内；以及分压子模块（32），所述分压子模块（32）的第一端与所述驱动晶体管（DTFT）的第一极相连，所述分压子模块（32）的第二端与高电平输入端（VDD）相连，以使得所述分压子模块（32）与所述存储电容器（C1）串联。该方案能够减小阈值电压（Vth）和电源内阻压降对显示均匀性的影响，改善显示效果。

Description

像素电路及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，具体涉及一种像素电路、该像素电路的驱动方法以及包括所述像素电路的显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于显示领域中。
在OLED器件发光时，所有像素的驱动电流由背板电源提供，而由于背板电源线存在一定电阻，因此，靠近电源供电位置区域的电源电压比远离供电位置区域的电源电压要高，这种现象被称为电源内阻压降(IR drop)，OLED显示器的尺寸越大，电源内阻压降现象越明显。另外，每个像素电路中都集成了一组薄膜晶体管和存储电容器，通过OLED的电流不仅会受数据电压的控制，还会受到薄膜晶体管(TFT)的阈值电压的影响。由于多个像素电路中的薄膜晶体管不可能具备完全一致的性能，导致不同像素电路中的薄膜晶体管的阈值电压存在差异，从而使得流过OLED器件的电流也会存在差异，进而影响整个显示屏显示亮度的均匀性。
发明内容
本发明的目的在于提供一种像素电路及其驱动方法、一种显示装置，以减小阈值电压和电源内阻压降对显示均匀性的影响。
为了实现上述目的，根据本发明的一方面，提供一种像素电路，包括：驱动晶体管、发光器件、存储电容器、选通模块、补偿模块和开关模块。所述选通模块连接在数据线和所述驱动晶体管的栅极之间，所述存储电容器的第一端与所述驱动晶体管的栅极相连，所述存 储电容器的第二端与所述驱动晶体管的第一极相连。所述补偿模块包括：复位子模块，所述复位子模块的输出端与所述驱动晶体管的第二极相连，用于在复位阶段向所述驱动晶体管的第一极充电，以将所述驱动晶体管的阈值电压存储在所述存储电容器内；以及分压子模块，所述分压子模块的第一端与所述驱动晶体管的第一极相连，所述分压子模块的第二端与高电平输入端相连，以使得所述分压子模块与所述存储电容器串联。所述开关模块与所述高电平输入端、所述驱动晶体管分别相连，用于在发光阶段使得所述高电平输入端与所述驱动晶体管的第一极导通。所述发光器件用于在所述驱动晶体管的驱动下发光。
所述复位子模块可以包括第一晶体管、复位控制端和参考电压端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述参考电压端相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连。
所述复位子模块可以包括第一晶体管和复位控制端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述驱动晶体管的栅极相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连。
所述分压子模块包可以括分压电容器，所述分压电容器的第一端形成为所述分压子模块的第一端，所述分压电容器的第二端形成为所述分压子模块的第二端。
所述开关模块可以包括第二晶体管和发光控制信号端，所述第二晶体管的栅极与所述发光控制信号端相连，所述第二晶体管的第一极与高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连。
所述开关模块还可以连接在所述驱动晶体管的第二极与所述发光器件之间，以使得所述驱动晶体管的第二极与所述发光器件的阳极在发光阶段彼此电连接。
所述开关模块可以包括第二晶体管、第三晶体管和发光控制信号端，所述第二晶体管的栅极与所述发光控制信号端相连，所述第二 晶体管的第一极与高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连；所述第三晶体管的栅极与所述发光控制信号端相连，所述第三晶体管的第一极与所述驱动晶体管的第二极相连，所述第三晶体管的第二极与所述发光器件相连。
所述选通模块可以包括第四晶体管，所述第四晶体管的栅极与扫描线相连，所述第四晶体管的第一极与数据线相连，所述第四晶体管的第二极与所述驱动晶体管的栅极相连。
根据本发明的另一方面，提供一种像素电路的驱动方法，所述像素电路为本发明上述方面提供的像素电路，所述驱动方法包括复位阶段、补偿阶段和发光阶段。在复位阶段，数据线经由所述选通模块向所述驱动晶体管的栅极提供数据电压信号，由所述复位子模块向所述驱动晶体管的第一极充电，以将所述驱动晶体管的阈值电压信号存储在所述存储电容器内。在补偿阶段，所述数据线由所述选通模块向所述驱动晶体管的栅极提供预设电压信号，以将所述数据电压信号和所述阈值电压信号共同存储至所述存储电容器中。在发光阶段，将所述选通模块关断，并通过所述开关模块将高电平输入端和所述驱动晶体管的第一极彼此电连接，以使所述发光器件发光。
所述复位子模块可以包括第一晶体管、复位控制端和参考电压端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述参考电压端相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连。所述分压子模块包括分压电容器，所述分压电容器的第一端形成为所述分压子模块的第一端，所述分压电容器的第二端形成为所述分压子模块的第二端。所述开关模块包括发光控制信号端、第二晶体管和第三晶体管，所述第二晶体管的栅极、所述第三晶体管的栅极与所述发光控制信号端相连，所述第二晶体管的第一极与所述高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连，所述第三晶体管的第一极与所述驱动晶体管的第二极相连，所述第三晶体管的第二极与所述发光器件相连。所述选通模块包括第四晶体管，所述第四晶体管的第一极与数据线相连，所述第四晶体管的栅极与扫描线相连。
在复位阶段，向所述复位控制端和扫描线均提供开启信号，向数据线提供数据电压信号，并且向所述发光控制信号端提供关断信号，所述参考电压端经由所述第一晶体管和所述驱动晶体管向所述驱动晶体管的第一极充电。
在补偿阶段，向所述复位控制端提供关断信号，向所述扫描线提供开启信号，向所述数据线提供预设电压信号，并且向所述发光控制信号端提供关断信号。
在发光阶段，向所述复位控制端提供关断信号，向所述扫描线提供关断信号，向所述数据线提供预设电压信号，向所述发光控制信号端提供开启信号。
所述第一晶体管、第二晶体管、第三晶体管和第四晶体管以及所述驱动晶体管可以为P型晶体管，并且所述开启信号为低电平信号，所述关断信号为高电平信号。
根据本发明的再一方面，提供了一种显示装置，所述显示装置包括本发明上述方面提供的像素电路。
根据本发明各方面，存储电容器在发光阶段之前可以对驱动晶体管的阈值电压信号以及数据线提供的数据电压信号信息进行存储，且由于存储电容器的自举作用，使得驱动晶体管的栅源电压在补偿阶段和发光阶段相同，因此，提供给发光器件的驱动电流的大小与阈值电压和高电平输入端提供的电压无关，减小了阈值电压和电源内阻压降对显示均匀性的影响，从而改善了显示装置的显示效果。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明的实施方式中像素电路的模块结构示意图；
图2是本发明的第一实施方式中像素电路的详细结构示意图；
图3是本发明的第二实施方式中像素电路的详细结构示意图；
图4是本发明的实施方式中像素电路的信号端的驱动时序图。
其中，附图标记为：10、发光器件；20、选通模块；30、补偿模块；31、复位子模块；32、分压子模块；40、开关模块；T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；DTFT、驱动晶体管；C1、存储电容器；C2、分压电容器；VDD、高电平输入端；VSS、低电平输入端；GATE、扫描线；DATA、数据线；RESET、复位控制端；EM、发光控制信号端；SUS、参考电压端。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的一方面，提供一种像素电路，如图1所示，所述像素电路包括：驱动晶体管DTFT、发光器件10、存储电容器C1和选通模块20。选通模块20的输入端连接至数据线DATA，选通模块20的输出端连接至驱动晶体管DTFT的栅极(即图1中所示的Cst节点)，存储电容器C1的第一端与驱动晶体管DTFT的栅极相连，存储电容器C1的第二端与驱动晶体管DTFT的第一极(即图1中所示的S节点)相连。
所述像素电路还包括补偿模块30和开关模块40。补偿模块30包括：复位子模块31，复位子模块31的输出端与驱动晶体管DTFT的第二极(即图1中所示的D节点)相连，用于在复位阶段向驱动晶体管DTFT的第一极充电，以将驱动晶体管DTFT的阈值电压Vth存储在存储电容器C1内；以及分压子模块32，分压子模块32的第一端与驱动晶体管DTFT的第一极相连，分压子模块32的第二端与高电平输入端VDD相连，以使得分压子模块32与存储电容器C1串联。开关模块40与高电平输入端VDD、驱动晶体管DTFT分别相连，用于在发光阶段使得高电平输入端VDD与驱动晶体管DTFT的第一极彼此电连接。
数据线DATA分别在复位阶段向驱动晶体管DTFT的栅极(Cst 节点)提供数据电压信号Vdata、以及在补偿阶段提供预设电压信号Vref。由于分压子模块32与存储电容器C1串联，因此，S节点的电压在复位阶段和补偿阶段也相应地发生变化，且S节点电压的变化量与Cst节点电压的变化量之比为小于1的常数α，以使得存储电容器C1所存储的电压既包括复位阶段中所存储的阈值电压Vth的信息，也包括数据线在复位阶段和补偿阶段分别提供给Cst节点的电压信息。具体地，在补偿阶段，存储电容器C1所存储的电压为：Vref-[(Vdata-Vth)+α(Vret-Vdata)]；该电压值与高电平输入端VDD的电压无关。当在发光阶段高电平输入端VDD的高电平信号Vdd经由开关模块40输入至S节点时，由于存储电容器C1的自举作用，使得驱动晶体管DTFT的栅源电压保持与补偿阶段中存储电容器C1两端电压相同，即：Vgs＝Vref-[(Vdata-Vth)+α(Vref-Vdata)]；因此，在发光阶段，发光器件的驱动电流为：
Ioled＝0.5μnCox(W/L)(Vgs-Vth)^2
＝0.5μnCox(W/L){Vref-[(Vdata-Vth)+α(Vref-Vdata)]-Vth}^2
＝0.5μnCox(W/L)[(1-α)(Vref-Vdata)]^2
其中，μn为载流子迁移率，Cox为驱动晶体管栅氧化层电容，W/L为驱动晶体管导电沟道的宽长比。可以看出，驱动电流的大小与阈值电压Vth和高电平信号Vdd均无关，从而有效地对阈值电压和电源内阻压降进行补偿，进而提高了显示画面的均匀性。
作为本发明的第一实施方式，如图2所示，复位子模块31包括第一晶体管T1、复位控制端RESET和参考电压端SUS，第一晶体管T1的栅极与复位控制端RESET相连，第一晶体管T1的第一极与参考电压端SUS相连，第一晶体管T1的第二极与驱动晶体管DTFT的第二极相连。
在复位阶段，复位控制端RESET提供开启信号，从而使第一晶体管T1导通，参考电压端SUS的参考电压信号通过第一晶体管T1输入至驱动晶体管DTFT的第二极(D节点)。
以驱动晶体管DTFT为P型晶体管为例，在复位阶段，选通模块20导通，数据电压信号Vdata输入至驱动晶体管DTFT的栅极(Cst 节点)，而此时驱动晶体管DTFT的第一极(S节点)的电压保持上一阶段的电压值(即高电平输入端VDD提供的高电平信号Vdd)，使得驱动晶体管DTFT的Vgs＜0，从而使得驱动晶体管DTFT导通，参考电压端SUS向S节点充电，直至驱动晶体管DTFT关断，此时，S节点的电压为Vdata-Vth，Cst节点电压为Vdata，存储电容器C1两端的电压为Vth。
作为本发明的第二实施方式，如图3所示，复位子模块31包括第一晶体管T1和复位控制端RESET，第一晶体管T1的栅极与复位控制端RESET相连、第一晶体管T1的第一极与选通模块20的输出端相连、第一晶体管T1的第二极与驱动晶体管DTFT的第二极相连。例如，驱动晶体管DTFT的第一极可为源极，第二极可为漏极。
和第一实施方式相比，在第二实施方式的复位子模块31中，在复位阶段，由数据线DATA向驱动晶体管DTFT的栅极充电，以使Cst节点电压达到数据信号电压Vdata，同时数据线DATA通过第一晶体管T1向S节点充电。本领域技术人员可以理解的是，在如图3的第二实施方式中，只有当驱动晶体管DTFT为增强型薄膜晶体管时，才可以完成对S节点的充电，而在驱动晶体管DTFT为耗尽型薄膜晶体管时则不能对其第一极充电。这是由于耗尽型薄膜晶体管的导通条件是：第一极的电压需要大于栅极电压，而数据线DATA同时为驱动晶体管DTFT的栅极和源极充电无法满足这一导通条件。与此相反，如图2的实施方式既可以用于增强型的薄膜晶体管，也可以用于耗尽型的薄膜晶体管。
具体地，如图2和图3所示，分压子模块32包括分压电容器C2，分压电容器C2的第一端形成为分压子模块32的第一端，分压电容器C2的第二端形成为分压子模块32的第二端，即，分压电容器C2的第一端与驱动晶体管DTFT的第一极相连，分压电容器C2的第二端与高电平输入端VDD相连。
如图2和图3所示，开关模块40包括第二晶体管T2和发光控制信号端EM，第二晶体管T2的栅极与发光控制信号端EM相连，第二晶体管T2的第一极与高电平输入端VDD相连，第二晶体管T2 的第二极与驱动晶体管DTFT的第一极相连。在发光阶段，发光控制信号端EM提供开启信号，以使得第二晶体管T2导通，从而使高电平输入端VDD的高电平信号经由第二晶体管T2输入至驱动晶体管DTFT的第一极。
更进一步地，开关模块40还可以与发光器件相连，在发光阶段使得驱动晶体管DTFT的第二极与发光器件10的阳极彼此电连接。在复位阶段和补偿阶段，开关模块40均关断，以防止有电流经过发光器件而使得发光器件发光。
具体地，如图2和图3所示，开关模块40还包括第三晶体管T3，第三晶体管T3的栅极与发光控制信号端EM相连，第三晶体管T3的第一极与驱动晶体管DTFT的第二极相连，第三晶体管T3的第二极与发光器件10的阳极相连。
选通模块20包括第四晶体管T4，第四晶体管T4的栅极与扫描线GATE相连，第四晶体管T4的第一极与数据线DATA相连，第四晶体管T4的第二极与驱动晶体管DTFT的栅极相连。扫描线GATE提供开启信号时，第四晶体管T4导通，从而使得数据线DATA上的信号经由第四晶体管T4输出至驱动晶体管DTFT的栅极。
本发明实施例中第一晶体管T1至第四晶体管T4以及驱动晶体管DTFT均为P型晶体管，上述各个晶体管的第一极为源极，第二极为漏极，相应地，上述开启信号为低电平信号，关断信号为高电平信号；当然，各个晶体管也可以均为N型晶体管，或者部分为N型晶体管、部分为P型晶体管，只要相应地调节输入其栅极的电压信号，使得各晶体管在各阶段的导通状态与本发明中一致即可。
本发明像素电路的驱动过程包括三个阶段：复位阶段、补偿阶段和发光阶段。下面以第一实施方式的结构(如图2所示)为例，结合图4对每个阶段进行介绍。
在复位阶段(如图4中的t1阶段)，扫描线GATE和复位控制端RESET提供低电平信号，发光控制信号端EM和数据线DATA提供高电平信号，此时，第一晶体管T1和第四晶体管T4导通，第二晶体管T2和第三晶体管T3关断。数据线DATA上的高电平数据信 号Vdata经由第四晶体管T4输入至驱动晶体管DTFT的栅极，驱动晶体管DTFT导通，参考电压端SUS通过第一晶体管T1和驱动晶体管DTFT向S节点充电，直至S节点的电压达到Vdata-Vth。
在此阶段，为了保证驱动晶体管DTFT的导通，高电平输入端VDD的高电平信号Vdd应满足：Vdd＞Vdata，max-Vth；参考电压端SUS的参考电压信号Vsus应满足：Vsus＜Vdata，min-Vth；其中，Vdata，max为写入不同灰度信号时对应的多个数据电压信号Vdata中的最大值，Vdata，min为所述多个数据电压信号Vdata中的最小值。
在补偿阶段(如图4中的t2阶段)，扫描线GATE和数据线DATA提供低电平信号，发光控制信号端EM和复位控制端RESET提供高电平信号，其中数据线DATA上的低电平信号为预设电压信号Vref。在该阶段中，第四晶体管T4导通，第一晶体管T1、第二晶体管T2和第三晶体管T3关断。Cst节点电压由复位阶段中的数据电压信号Vdata变为补偿阶段中的预设电压信号Vref，S节点处于悬空状态(Floating)，该节点处的电压受到Cst节点电压的影响。Cst节点处的电压在复位阶段至补偿阶段之间的变化量ΔVcst反馈至S节点，由于分压电容器C2的分压作用，S节点电压在复位阶段和补偿阶段的变化量ΔVs为[C1/(C1+C2)](Vref-Vdata)，因此S节点在补偿阶段的电压为：(Vdata-Vth)+[C1/(C1+C2)](Vref-Vdata)。可以看出，在补偿阶段，存储电容器C1所存储的电压信息中同时包括Vdata和Vth的电压信息。
在此阶段，为了保证驱动晶体管DTFT的正常开启，同时减小通过发光模块的电流，以保证黑态效果，数据线的低电平信号Vref可以等于或略大于复位阶段中所提供的数据电压信号的最小值Vdata，min。
在发光阶段(如图4中的t3阶段)，发光控制信号端EM和数据线DATA提供低电平信号，复位控制端RESET和扫描线GATE提供高电平信号，此时，第一晶体管T1和第四晶体管T4关断，第二晶体管T2和第三晶体管T3开启，高电平信号端VDD通过第二晶体管T2向驱动晶体管DTFT的第一极S节点充电，使得S节点的电压 由(Vdata-Vth)+[C1/(C1+C2)](Vref-Vdata)升高至Vdd，由于第一电容器C1的自举作用，使得驱动晶体管DTFT的栅源电压保持与补偿阶段中存储电容器C1两端电压相同，即：
Vgs＝Vref-{(Vdata-Vth)+[C1/(C1+C2)](Vref-Vdata)}；
因此，通过发光器件的电流为：
Ioled＝0.5μnCox(W/L)(Vgs-Vth)^2
＝0.5μnCox(W/L){[1-C1/(C1+C2)](Vref-Vdata)}^2
＝0.5μnCox(W/L){[(C2)/(C1+C2)](Vref-Vdata)}^2
其中，μn为载流子迁移率，Cox为驱动晶体管DTFT栅氧化层电容，W/L为驱动晶体管DTFT导电沟道的宽长比，可以看出，经过发光器件10的电流与Vdd和Vth均无关，从而有效地补偿了阈值电压的不均匀和电源内阻压降，提高了显示亮度的均匀性。
作为本发明的另一方面，提供一种像素电路的驱动方法，所述像素单元为上述像素电路，所述驱动方法包括复位阶段、补偿阶段和发光阶段。
在复位阶段，数据线DATA经由选通模块20向驱动晶体管DTFT的栅极提供高电平的数据电压信号Vdata，通过复位子模块31向驱动晶体管DTFT的第一极充电，以将驱动晶体管DTFT的阈值电压信号Vth存储在存储电容器C1内；
在补偿阶段，数据线DATA经由选通模块20向驱动晶体管DTFT的栅极提供低电平的预设电压信号Vref，以将所述高电平的数据电压信号Vdata和所述阈值电压信号Vth共同存储至存储电容器C1内；
在发光阶段，关断选通模块20，通过开关模块40将高电平输入端VDD和驱动晶体管DTFT的第一极彼此电连接，以使发光器件10发光。
具体地，如图2所示，复位子模块31包括第一晶体管T1、复位控制端RESET和参考电压端SUS，分压子模块32包括分压电容器C2，开关模块40包括发光控制信号端EM、第二晶体管T2和第三晶体管T3，选通模块20包括第四晶体管T4。
如图4所示，在复位阶段(t1阶段)中，向复位控制端RESET 和扫描线GATE均提供开启信号，向数据线DATA提供高电平的数据电压信号Vdata，参考电压端SUS向所述驱动晶体管DTFT的第一极充电。在此阶段，第一晶体管T1、第四晶体管T4和驱动晶体管DTFT均导通，所述高电平的数据电压信号Vdata通过第四晶体管T4输入至驱动晶体管DTFT的栅极，参考电压端SUS的参考电压信号VSUS通过第一晶体管T1和驱动晶体管DTFT向S节点充电，直至驱动晶体管DTFT关断，此时S节点电压达到Vdata-Vth，Cst节点电压为Vdata，存储电容器C1内所存储的电压为Vth。
在补偿阶段(t2阶段)，向复位控制端RESET提供关断信号，向扫描线GATE提供开启信号，向数据线DATA提供低电平的预设电压信号Vref。从而使得第一晶体管T1关断，第四晶体管T4导通，数据线DATA向Cst节点输入低电平的预设电压信号Vref。在复位阶段和补偿阶段，发光控制信号端EM的信号均为关断信号，以使得第二晶体管T2和第三晶体管T3在两个阶段均关断，S节点处于悬空状态，该节点电压受Cst节点电压改变的影响，变为(Vdata-Vth)+[C1/(C1+C2)](Vref-Vdata)。
在发光阶段(t3阶段)，向扫描线GATE提供关断信号，向发光控制信号端EM提供开启信号，从而使得第四晶体管T4关断，第二晶体管T2和第三晶体管T3导通，高电平输入端VDD的高电平电压Vdd输入至S节点，并驱动所述发光器件10发光。而由于存储电容器C1的自举作用使得驱动晶体管DTFT的栅极和源极之间的电压保持与补偿阶段中相同，即与高电平信号Vdd无关。
第一晶体管T1至第四晶体管T4以及驱动晶体管DTFT均为P型晶体管，相应地，开启信号为低电平信号，关断信号为高电平信号。
在本发明提供的像素电路中，在发光阶段前，存储电容器中所存储的电压包含了阈值电压的信息，且发光阶段，存储电容器所存储的电压与高电平输入端的电压无关，因此流过发光器件的电流与阈值电压和高电平输入端的电压均无关，因此可以补偿阈值电压的不均匀性和电源内阻压降，从而提高了显示亮度的均匀性。
作为本发明的再一个方面，提供一种显示装置，包括本发明提 供的上述驱动电路。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于本发明中提供的像素电路的稳定性较好，不受电路内部的晶体管阈值电压和背板电源的内阻压降的影响，从而使得驱动电流不受晶体管阈值电压和背板单元的影响，改善显示效果，同时延长发光器件的寿命。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种像素电路，包括：驱动晶体管、发光器件、存储电容器、选通模块、补偿模块和开关模块，其中，
    所述选通模块连接在数据线和所述驱动晶体管的栅极之间；
    所述存储电容器的第一端与所述驱动晶体管的栅极相连，所述存储电容器的第二端与所述驱动晶体管的第一极相连；
    所述补偿模块包括：
    复位子模块，所述复位子模块的输出端与所述驱动晶体管的第二极相连，用于在复位阶段向所述驱动晶体管的第一极充电，以将所述驱动晶体管的阈值电压存储在所述存储电容器内；
    分压子模块，所述分压子模块的第一端与所述驱动晶体管的第一极相连，所述分压子模块的第二端与高电平输入端相连，以使得所述分压子模块与所述存储电容器串联；
    所述开关模块与所述高电平输入端、所述驱动晶体管分别相连，用于在发光阶段使得所述高电平输入端与所述驱动晶体管的第一极电连接；
    所述发光器件用于在所述驱动晶体管的驱动下发光。
  2. 根据权利要求1所述的像素电路，其中，所述复位子模块包括第一晶体管、复位控制端和参考电压端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述参考电压端相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连。
  3. 根据权利要求1所述的像素电路，其中，所述复位子模块包括第一晶体管和复位控制端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述驱动晶体管的栅极相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连。
  4. 根据权利要求1至3中任意一项所述的像素电路，其中，所 述分压子模块包括分压电容器，所述分压电容器的第一端形成为所述分压子模块的第一端，所述分压电容器的第二端形成为所述分压子模块的第二端。
  5. 根据权利要求1至3中任意一项所述的像素电路，其中，所述开关模块包括第二晶体管和发光控制信号端，所述第二晶体管的栅极与所述发光控制信号端相连，所述第二晶体管的第一极与高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连。
  6. 根据权利要求1至3中任意一项所述的像素电路，其中，所述开关模块还连接在所述驱动晶体管的第二极与所述发光器件之间，以使得所述驱动晶体管的第二极与所述发光器件的阳极在发光阶段彼此电连接。
  7. 根据权利要求6所述的像素电路，其中，所述开关模块包括第二晶体管、第三晶体管和发光控制信号端，所述第二晶体管的栅极与所述发光控制信号端相连，所述第二晶体管的第一极与高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连；所述第三晶体管的栅极与所述发光控制信号端相连，所述第三晶体管的第一极与所述驱动晶体管的第二极相连，所述第三晶体管的第二极与所述发光器件相连。
  8. 根据权利要求1至3中任意一项所述的像素电路，其中，所述选通模块包括第四晶体管，所述第四晶体管的栅极与扫描线相连，所述第四晶体管的第一极与数据线相连，所述第四晶体管的第二极与所述驱动晶体管的栅极相连。
  9. 一种像素电路的驱动方法，所述像素电路为权利要求1所述的像素电路，所述驱动方法包括：
    在复位阶段，数据线经由所述选通模块向所述驱动晶体管的栅极提供数据电压信号，由所述复位子模块向所述驱动晶体管的第一极充电，以将所述驱动晶体管的阈值电压信号存储在所述存储电容器内；
    在补偿阶段，所述数据线经由所述选通模块向所述驱动晶体管的栅极提供预设电压信号，以将所述数据电压信号和所述阈值电压信号共同存储至所述存储电容器中；以及
    在发光阶段，将所述选通模块关断，并通过所述开关模块将高电平输入端和所述驱动晶体管的第一极彼此电连接，以使所述发光器件发光。
  10. 根据权利要求9所述的驱动方法，其中，所述复位子模块包括第一晶体管、复位控制端和参考电压端，所述第一晶体管的栅极与所述复位控制端相连，所述第一晶体管的第一极与所述参考电压端相连，所述第一晶体管的第二极与所述驱动晶体管的第二极相连；所述分压子模块包括分压电容器，所述分压电容器的第一端形成为所述分压子模块的第一端，所述分压电容器的第二端形成为所述分压子模块的第二端；所述开关模块包括发光控制信号端、第二晶体管和第三晶体管，所述第二晶体管的栅极、所述第三晶体管的栅极与所述发光控制信号端相连，所述第二晶体管的第一极与所述高电平输入端相连，所述第二晶体管的第二极与所述驱动晶体管的第一极相连，所述第三晶体管的第一极与所述驱动晶体管的第二极相连，所述第三晶体管的第二极与所述发光器件相连；所述选通模块包括第四晶体管，所述第四晶体管的第一极与数据线相连，所述第四晶体管的栅极与扫描线相连；
    在复位阶段，向所述复位控制端和所述扫描线均提供开启信号，向所述数据线提供数据电压信号，并且向所述发光控制信号端提供关断信号，所述参考电压端经由所述第一晶体管和所述驱动晶体管向所述驱动晶体管的第一极充电；
    在补偿阶段，向所述复位控制端提供关断信号，向所述扫描线 提供开启信号，向所述数据线提供预设电压信号，并且向所述发光控制信号端提供关断信号；
    在发光阶段，向所述复位控制端提供关断信号，向所述扫描线提供关断信号，向所述数据线提供预设电压信号，并且向所述发光控制信号端提供开启信号。
  11. 根据权利要求10所述的驱动方法，其中，所述第一晶体管、第二晶体管、第三晶体管和第四晶体管以及所述驱动晶体管为P型晶体管，并且所述开启信号为低电平信号，所述关断信号为高电平信号。
  12. 一种显示装置，其中，所述显示装置包括权利要求1至8中任意一项所述的像素电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106448560A (zh) * 2016-12-21 2017-02-22 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104751799B (zh) * 2015-04-10 2016-12-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN105427803B (zh) * 2016-01-04 2018-01-02 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN105609050B (zh) * 2016-01-04 2018-03-06 京东方科技集团股份有限公司 像素补偿电路及amoled显示装置
CN105632404B (zh) * 2016-03-11 2019-07-12 上海天马有机发光显示技术有限公司 一种有机发光显示电路及其驱动方法
CN105895017B (zh) * 2016-06-08 2018-06-08 京东方科技集团股份有限公司 像素驱动电路、驱动方法、显示面板和装置
US10127859B2 (en) * 2016-12-29 2018-11-13 Lg Display Co., Ltd. Electroluminescent display
CN107025883B (zh) * 2017-04-28 2019-05-03 深圳市华星光电半导体显示技术有限公司 显示面板、像素驱动电路及其驱动方法
CN107068066A (zh) 2017-06-22 2017-08-18 京东方科技集团股份有限公司 像素补偿电路及显示装置、驱动方法
KR102434474B1 (ko) * 2017-09-28 2022-08-23 삼성디스플레이 주식회사 화소 및 이를 포함하는 유기전계발광 표시장치
CN108062932B (zh) * 2017-12-20 2020-05-26 北京航空航天大学 一种有机薄膜晶体管构造的像素电路
CN107919093A (zh) * 2018-01-05 2018-04-17 京东方科技集团股份有限公司 一种像素补偿电路及其驱动方法、显示装置
CN110021273B (zh) * 2018-01-10 2021-12-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN108206008B (zh) * 2018-01-11 2019-12-31 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN108288453B (zh) * 2018-04-28 2023-04-07 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN108806605A (zh) * 2018-06-15 2018-11-13 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
TWI676978B (zh) * 2018-10-12 2019-11-11 友達光電股份有限公司 畫素電路
CN109545148B (zh) * 2019-01-24 2020-06-19 京东方科技集团股份有限公司 显示电压的补偿方法及其装置
CN109935205B (zh) * 2019-04-02 2020-12-08 深圳市华星光电半导体显示技术有限公司 像素驱动电路以及像素驱动电路的补偿方法
CN111836433A (zh) * 2019-04-22 2020-10-27 厦门赢科光电有限公司 一种供电电源的控制电路
CN110047435B (zh) * 2019-04-23 2020-12-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN112309332B (zh) * 2019-07-31 2022-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示面板
US10885843B1 (en) * 2020-01-13 2021-01-05 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with a source follower
CN111179820A (zh) * 2020-03-12 2020-05-19 武汉华星光电半导体显示技术有限公司 一种像素电路及显示面板
CN111223447A (zh) * 2020-03-12 2020-06-02 武汉华星光电半导体显示技术有限公司 一种像素电路和显示面板
CN114093294B (zh) * 2020-08-24 2023-12-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN112086070A (zh) * 2020-09-17 2020-12-15 武汉华星光电技术有限公司 像素驱动电路及显示面板
US20230317012A1 (en) * 2022-03-31 2023-10-05 Meta Platforms Technologies, Llc Self-compensation of driving transistor threshold voltage using body effect
CN114913802A (zh) * 2022-05-31 2022-08-16 Tcl华星光电技术有限公司 像素驱动电路和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227903A1 (en) * 2010-03-17 2011-09-22 Sang-Moo Choi Pixel and organic light emitting display device using the same
US20120019498A1 (en) * 2010-07-22 2012-01-26 Samsung Mobile Display Co., Ltd Pixel and organic light emitting display device using the same
CN102593151A (zh) * 2011-12-30 2012-07-18 友达光电股份有限公司 像素结构、其驱动方法及使用其的自发光显示器
CN103198793A (zh) * 2013-03-29 2013-07-10 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN103226931A (zh) * 2013-04-27 2013-07-31 京东方科技集团股份有限公司 像素电路和有机发光显示器
CN104183215A (zh) * 2013-05-22 2014-12-03 三星显示有限公司 像素和使用像素的有机发光显示器
CN104751799A (zh) * 2015-04-10 2015-07-01 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937215B2 (en) * 2003-11-03 2005-08-30 Wintek Corporation Pixel driving circuit of an organic light emitting diode display panel
TWI462080B (zh) * 2012-08-14 2014-11-21 Au Optronics Corp 主動式有機發光二極體電路及其操作方法
CN102982766A (zh) * 2012-12-10 2013-03-20 友达光电股份有限公司 一种像素补偿电路
CN103035202A (zh) * 2012-12-25 2013-04-10 友达光电股份有限公司 一种像素补偿电路
CN104282263A (zh) * 2014-09-25 2015-01-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227903A1 (en) * 2010-03-17 2011-09-22 Sang-Moo Choi Pixel and organic light emitting display device using the same
US20120019498A1 (en) * 2010-07-22 2012-01-26 Samsung Mobile Display Co., Ltd Pixel and organic light emitting display device using the same
CN102593151A (zh) * 2011-12-30 2012-07-18 友达光电股份有限公司 像素结构、其驱动方法及使用其的自发光显示器
CN103198793A (zh) * 2013-03-29 2013-07-10 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN103226931A (zh) * 2013-04-27 2013-07-31 京东方科技集团股份有限公司 像素电路和有机发光显示器
CN104183215A (zh) * 2013-05-22 2014-12-03 三星显示有限公司 像素和使用像素的有机发光显示器
CN104751799A (zh) * 2015-04-10 2015-07-01 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106448560A (zh) * 2016-12-21 2017-02-22 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
US10297202B2 (en) 2016-12-21 2019-05-21 Shanghai Tianma AM-OLED Co., Ltd. Organic light-emitting display panel, driving method thereof, and organic light-emitting display device

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