WO2021227764A1 - 一种像素驱动电路及其驱动方法、显示装置 - Google Patents

一种像素驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021227764A1
WO2021227764A1 PCT/CN2021/087446 CN2021087446W WO2021227764A1 WO 2021227764 A1 WO2021227764 A1 WO 2021227764A1 CN 2021087446 W CN2021087446 W CN 2021087446W WO 2021227764 A1 WO2021227764 A1 WO 2021227764A1
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Prior art keywords
circuit
transistor
control
sub
reset
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PCT/CN2021/087446
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English (en)
French (fr)
Inventor
王博
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京东方科技集团股份有限公司
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Priority to US17/761,544 priority Critical patent/US11804180B2/en
Publication of WO2021227764A1 publication Critical patent/WO2021227764A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a driving method thereof, and a display device.
  • AMOLED Active-matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • AMOLED Active-matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • has many advantages such as self-luminous, ultra-thin, fast response, high contrast, and wide viewing angle. It is currently a display device that has received widespread attention .
  • Such an AMOLED display device includes a plurality of pixel driving circuits and a plurality of light-emitting elements, and the pixel driving circuit is used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the AMOLED display device.
  • the existing pixel driving circuit is driven at a low frequency, the gate of the driving transistor in the pixel driving circuit leaks seriously, which makes the display device prone to flicker during display.
  • the purpose of the present disclosure is to provide a pixel driving circuit, a driving method thereof, and a display device.
  • a first aspect of the present disclosure provides a pixel driving circuit for driving a light-emitting element, including:
  • a driving sub-circuit includes a driving transistor, the second pole of the driving transistor is connected to the light-emitting element;
  • a storage sub-circuit a first end of the storage sub-circuit is connected to the gate of the driving transistor, and a second end of the storage sub-circuit is connected to a power signal input end;
  • the power control sub-circuit is respectively connected to the first control terminal, the power signal input terminal and the first pole of the driving transistor;
  • the data writing sub-circuit is respectively connected to the corresponding row gate line, the corresponding column data line and the first pole of the driving transistor;
  • the compensation sub-circuit is respectively connected to the corresponding row gate line, the gate of the driving transistor and the second pole of the driving transistor;
  • the first reset sub-circuit is respectively connected to the reset control terminal, the first control terminal, the gate of the driving transistor, the common node, the first initialization voltage input terminal and the second initialization voltage input terminal; Under the control of the reset control terminal, the connection between the gate of the driving transistor and the common node is controlled to be turned on or off, and the connection between the common node and the first initialization voltage input terminal is controlled to be turned on or off. It is also used to control the conduction or disconnection of the connection between the common node and the second initialization voltage input terminal under the control of the first control terminal;
  • the difference between the potential of the second initialization signal input from the second initialization voltage input terminal and the potential of the gate of the driving transistor during the light-emitting period is less than a threshold.
  • the first reset sub-circuit includes:
  • the first reset control sub-circuit is respectively connected to the reset control terminal, the gate of the drive transistor and the common node; used to control the turning on or off of the drive transistor under the control of the reset control terminal The connection between the gate and the common node;
  • the second reset control sub-circuit is respectively connected to the reset control terminal, the common node and the first initialization voltage input terminal; and is used to control the conduction or disconnection of the common under the control of the reset control terminal The connection between the node and the first initialization voltage input terminal;
  • the third reset control sub-circuit is respectively connected to the first control terminal, the common node and the second initialization voltage input terminal; it is used to control the conduction or disconnection of all the terminals under the control of the first control terminal.
  • the connection between the common node and the second initialization voltage input terminal is respectively connected to the first control terminal, the common node and the second initialization voltage input terminal; it is used to control the conduction or disconnection of all the terminals under the control of the first control terminal.
  • the first reset control sub-circuit includes a first transistor, the gate of the first transistor is connected to the reset control terminal, and the first pole of the first transistor is connected to the common node, so The second electrode of the first transistor is connected to the gate of the driving transistor;
  • the second reset control sub-circuit includes a second transistor, the gate of the second transistor is connected to the reset control terminal, the first pole of the second transistor is connected to the first initialization voltage input terminal, so The second pole of the second transistor is connected to the common node;
  • the third reset control sub-circuit includes a third transistor, the gate of the third transistor is connected to the first control terminal, and the first electrode of the third transistor is connected to the second initialization voltage input terminal, The second electrode of the third transistor is connected to the common node.
  • the pixel driving circuit further includes:
  • the second reset sub-circuit is respectively connected to the reset control terminal, the light-emitting element, and the third initialization voltage input terminal; and is used for controlling to turn on or disconnect the third initialization voltage under the control of the reset control terminal The connection between the input terminal and the light-emitting element.
  • the third initialization voltage input terminal is coupled to the first initialization voltage input terminal.
  • the second reset sub-circuit includes a fourth transistor, the gate of the fourth transistor is connected to the reset control terminal, and the first electrode of the fourth transistor is connected to the third initialization voltage input terminal. Connected, and the second electrode of the fourth transistor is connected to the light-emitting element.
  • the pixel driving circuit further includes a light-emitting control sub-circuit, and the second electrode of the driving transistor is connected to the light-emitting element through the light-emitting control sub-circuit;
  • the light-emitting control sub-circuit is respectively connected to the first control terminal, the second pole of the driving transistor, and the light-emitting element, and is used for controlling to turn on or off the light-emitting element under the control of the first control terminal.
  • the connection between the second electrode of the driving transistor and the light-emitting element is respectively connected to the first control terminal, the second pole of the driving transistor, and the light-emitting element, and is used for controlling to turn on or off the light-emitting element under the control of the first control terminal.
  • the light emission control sub-circuit includes a fifth transistor, the gate of the fifth transistor is connected to the first control terminal, and the first electrode of the fifth transistor is connected to the second electrode of the driving transistor. Connected, the second electrode of the fifth transistor is connected to the light-emitting element.
  • the power control sub-circuit includes a sixth transistor, the gate of the sixth transistor is connected to the first control terminal, and the first pole of the sixth transistor is connected to the power signal input terminal, The second electrode of the sixth transistor is connected to the first electrode of the driving transistor;
  • the data writing sub-circuit includes a seventh transistor, the gate of the seventh transistor is connected to the corresponding row gate line, the first electrode of the seventh transistor is connected to the corresponding column data line, and the first electrode of the seventh transistor is connected to the corresponding column data line.
  • the two poles are connected with the first pole of the driving transistor;
  • the compensation sub-circuit includes an eighth transistor, the gate of the eighth transistor is connected to the corresponding row gate line, the first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the eighth transistor The second pole of is connected to the gate of the driving transistor.
  • a second aspect of the present disclosure provides a display device, including the pixel drive circuit provided in the above embodiment.
  • the display device includes a display area and a peripheral area surrounding the display area, the display device further includes a first initialization signal line and a second initialization signal line located in the peripheral area, the first initialization The signal line and the second initialization signal line both extend along the first direction,
  • the display device includes a plurality of the pixel drive circuits arranged in an array in the display area, in each pixel drive circuit located in the same row along the second direction, the first initialization voltage input terminal connected to the first reset sub-circuit all passes through The same first connection line is connected to the first initialization signal line;
  • the second initialization voltage input terminals connected to the first reset sub-circuit are all connected to the second initialization signal line through the same second connection line, and the first direction Intersect the second direction.
  • a third aspect of the present disclosure provides a driving method of a pixel driving circuit, which is applied to the pixel driving circuit provided in the above embodiment, and the driving method includes: in each work cycle,
  • the first initialization voltage input terminal inputs the first initialization voltage Vinit1, and under the control of the reset control terminal, the first reset sub-circuit controls the connection between the first initialization voltage input terminal and the common node to be turned on, And turn on the connection between the common node and the gate of the driving transistor in the driving sub-circuit; under the control of the first control terminal, the first reset sub-circuit controls to disconnect the second initialization voltage input terminal from the common Connection between nodes;
  • the first reset sub-circuit controls the disconnection between the first initialization voltage input terminal and the common node, and controls the disconnection between the common node and the common node.
  • the connection between the gates of the driving transistors; the data voltage Vdata is input to the corresponding column data line, and under the control of the corresponding row gate line, the data writing sub-circuit controls to turn on the corresponding column data line and the first pole of the driving transistor
  • the compensation sub-circuit controls the connection between the gate of the driving transistor and the second electrode of the driving transistor, so that the driving transistor is formed into a diode structure, and the gate of the driving transistor is The potential becomes Vdata+Vth, and Vth is the threshold voltage of the driving transistor;
  • the power signal input terminal is input with a power supply voltage Vdd, and under the control of the first control terminal, the power control sub-circuit controls to turn on the power signal input terminal and the first pole of the driving transistor.
  • the first reset sub-circuit controls the connection between the second initialization voltage input terminal and the common node; the second initialization voltage input terminal The difference between the potential of the second initialization signal and the potential of the gate of the driving transistor during the light-emitting period is smaller than the threshold.
  • the first reset sub-circuit includes a first reset control sub-circuit, a second reset control sub-circuit, and a third reset control sub-circuit
  • the first reset control sub-circuit controls to turn on the connection between the gate of the driving transistor and the common node, and at the same time, the second reset control The sub-circuit controls the connection between the common node and the first initialization voltage input terminal; under the control of the first control terminal, the third reset control sub-circuit controls the disconnection of the common node and the first initialization voltage input terminal.
  • the first reset control sub-circuit controls the disconnection of the connection between the gate of the drive transistor and the common node, and at the same time the second reset control sub-circuit Controlling to disconnect the connection between the common node and the first initialization voltage input terminal;
  • the third reset control sub-circuit controls to turn on the connection between the second initialization voltage input terminal and the common node.
  • the pixel driving circuit further includes a light-emitting control sub-circuit, and the second electrode of the driving transistor is connected to the light-emitting element through the light-emitting control sub-circuit; the light-emitting control sub-circuit is respectively connected to the first The control terminal and the second electrode of the driving transistor are connected to the light-emitting element; the driving method further includes:
  • the light emission control sub-circuit controls to disconnect the connection between the second electrode of the driving transistor and the light emitting element, So that the light emitting element does not emit light during the reset period and the write compensation period.
  • the pixel driving circuit further includes a second reset sub-circuit, and the second reset sub-circuit is respectively connected to the reset control terminal, the light-emitting element, and a third initialization voltage input terminal;
  • the second reset sub-circuit controls to turn on the connection between the third initialization voltage input terminal and the light-emitting element.
  • the potential of the third initialization signal input from the third initialization voltage input terminal is the same as the potential of the first initialization signal input from the first initialization voltage input terminal.
  • FIG. 1 is a schematic diagram of a first structure of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a first circuit of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a second structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a second circuit of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a third structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a third circuit of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a fourth structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a fourth circuit of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 9 is a driving timing diagram of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of the layout of a display device provided by an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a pixel driving circuit for driving a light-emitting element EL, and the pixel driving circuit includes:
  • a driving sub-circuit 3, the driving sub-circuit 3 includes a driving transistor DT, the second pole of the driving transistor DT is connected to the light-emitting element EL;
  • the storage sub-circuit 4 the first end of the storage sub-circuit 4 is connected to the gate (ie node G) of the driving transistor DT, and the second end of the storage sub-circuit 4 is connected to the power signal input terminal ELVDD;
  • the power control sub-circuit 1 is respectively connected to the first control terminal EM, the power signal input terminal ELVDD and the first pole (ie node S) of the driving transistor DT;
  • the data writing sub-circuit 2 is respectively connected to the corresponding row gate line GT, the corresponding column data line DA and the first pole of the driving transistor DT;
  • the compensation sub-circuit 6 is respectively connected to the corresponding row gate line GT, the gate of the driving transistor DT and the second pole of the driving transistor DT;
  • the first reset sub-circuit 51 is connected to the reset control terminal RE, the first control terminal EM, the gate of the driving transistor DT, the common node N1, the first initialization voltage input terminal Vinit1, and the second initialization voltage input terminal Vinit2, respectively. Connection; used to control the connection between the gate of the driving transistor DT and the common node N1 under the control of the reset control terminal RE, and to control the connection or disconnection of the common node N1 The connection between the node N1 and the first initialization voltage input terminal Vinit1; and is also used to control the conduction or disconnection of the common node N1 and the second initialization voltage under the control of the first control terminal EM The connection between the input terminals Vinit2;
  • the difference between the potential of the second initialization signal input from the second initialization voltage input terminal Vinit2 and the potential of the gate of the driving transistor DT during the light-emitting period is less than a threshold.
  • the pixel driving circuit is applied to a display device, and the display device includes a substrate, a plurality of pixel driving circuits arrayed on the substrate, and a side of the plurality of pixel driving circuits facing away from the substrate, And the light-emitting elements EL correspond to the plurality of pixel driving circuits one-to-one.
  • the light-emitting element EL specifically includes an anode, a light-emitting functional layer, and a cathode that are sequentially stacked in a direction away from the substrate.
  • the anode of the light-emitting element EL can be connected to the corresponding pixel driving circuit to receive the corresponding pixel drive circuit.
  • the driving signal provided by the pixel driving circuit, the cathode can be connected to the negative power signal line ELVSS in the display device, and the negative power signal provided by the negative power signal line is received.
  • the cathode emits light under the combined action of the cathode.
  • the potential of the second initialization signal input from the second initialization voltage input terminal Vinit2 is substantially the same as the potential of the gate of the driving transistor DT during the light-emitting period.
  • the second initialization voltage input terminal Vinit2 is input
  • the difference between the potential of the second initialization signal and the potential of the gate of the driving transistor DT during the light-emitting period is less than the threshold.
  • the threshold value can be set according to actual needs. Exemplarily, the condition that the threshold value should meet is that the current change amount on the light-emitting element EL is less than 7% within one frame of display time.
  • the potential of the first initialization signal input from the first initialization voltage input terminal Vinit1 is V1
  • the reset signal input from the reset control terminal RE is at an effective level, so that under the control of the reset control terminal RE, the first initialization signal
  • the reset sub-circuit 51 controls to turn on the connection between the first initialization voltage input terminal Vinit1 and the common node N1, and turns on the connection between the common node N1 and the gate of the driving transistor DT, so that The potential of the gate of the driving transistor DT becomes V1 to reset the gate of the driving transistor DT, so that the gate-source voltage Vgs held on the driving transistor DT in the previous frame is initialized; in the reset period P1,
  • the first control signal input by the first control terminal EM is at an inactive level, so that under the control of the first control terminal EM, the first reset sub-circuit 51 also controls to disconnect the second initialization voltage input terminal Vinit2 from the The connection between the public nodes N1.
  • the reset signal input by the reset control terminal RE is at an inactive level, so that under the control of the reset control terminal RE, the first reset sub-circuit 51 controls to turn off the first initialization voltage input terminal The connection between Vinit1 and the common node N1, and control to disconnect the connection between the common node N1 and the gate of the driving transistor DT; under the control of the first control terminal EM, the first reset The sub-circuit 51 continues to control the disconnection of the connection between the second initialization voltage input terminal Vinit2 and the common node N1; the corresponding column data line DA inputs the data voltage Vdata, and the corresponding row gate line GT input scan signal is at an effective level, so that Under the control of the corresponding row gate line GT, the data writing sub-circuit 2 controls the connection between the corresponding column data line DA and the first electrode of the driving transistor DT to change the potential of the first electrode of the driving transistor DT.
  • the compensation sub-circuit 6 controls to turn on the connection between the gate of the driving transistor DT and the second electrode of the driving transistor DT, so that the driving transistor DT It is formed into a diode structure, so the data writing sub-circuit 2, the driving transistor DT and the compensation sub-circuit 6 work together to realize the threshold voltage compensation of the driving transistor DT.
  • the compensation time is long enough, the gate of the driving transistor DT can be controlled.
  • the electrode potential finally reaches Vdata+Vth, and Vth is the threshold voltage of the driving transistor DT.
  • the power signal input terminal ELVDD is input with the power supply voltage Vdd, and the first control signal input by the first control terminal EM is at an effective level, so that under the control of the first control terminal EM, the The power control sub-circuit 1 controls to turn on the connection between the power signal input terminal ELVDD and the first pole of the driving transistor DT, so that the potential of the first pole of the driving transistor DT changes from Vdata to Vdd;
  • the potential of the second initialization signal input from the second initialization voltage input terminal Vinit2 is V2
  • the first reset sub-circuit 51 controls to turn on the second initialization voltage input terminal Vinit2 and the
  • the connection between the common node N1 makes the potential of the common node N1 change to V2; the potential V2 of the second initialization signal input from the second initialization voltage input terminal Vinit2, and the gate of the driving transistor DT during the light-emitting period P3
  • the difference between the potentials of the poles is less
  • the voltage Vgs between the gate of the driving transistor DT and the first electrode of the driving transistor DT is:
  • Vgs Vdata+Vth-Vdd, formula (1)
  • the driving current I generated when the driving transistor DT is turned on and working in a saturated state is:
  • k is a constant.
  • the driving current I is only related to the power supply voltage Vdd and the data voltage Vdata, and has nothing to do with the threshold voltage Vth of the driving transistor DT; therefore, even if the same is input to a plurality of driving transistors DT with different threshold voltages Vth At the time of the data voltage, the drive transistors DT with different threshold voltages Vth generate the same drive current in the saturation state, so that when the drive transistors DT with different threshold voltages Vth drive the corresponding light emitting elements EL to emit light, the light emitting brightness of the light emitting elements EL is the same.
  • driving transistors DT with different threshold voltages Vth to drive the light-emitting element EL to emit light, the problem of uneven light emission of the light-emitting element EL due to threshold voltage drift is avoided.
  • the first reset sub-circuit 51 is provided, so that in the reset period P1, the first reset sub-circuit 51 can The connection between the gate of the driving transistor DT and the first initialization voltage input terminal Vinit1 is turned on, so that the potential of the gate of the driving transistor DT becomes lower than that input from the first initialization voltage input terminal Vinit1.
  • the potential V1 of the drive transistor DT is reset; at the same time in the reset period P1, the first reset sub-circuit 51 can disconnect the gate of the drive transistor DT and the second initialization voltage input terminal Connection between Vinit2.
  • the first reset sub-circuit 51 can disconnect the gate of the driving transistor DT and the first initialization voltage input terminal Vinit1, and turn on the gate of the driving transistor DT
  • the connection with the second initialization voltage input terminal Vinit2 makes the potential of the common node N1 substantially the same as the potential of the gate of the driving transistor DT.
  • the pixel driving circuit provided by the embodiment of the present disclosure effectively reduces the leakage current of the gate of the driving transistor DT through the first reset sub-circuit 51 during the light-emitting period P3, so that in the case of low-frequency driving, The electric potential of the gate of the driving transistor DT can also be maintained well, so that the problem that the display device is prone to flicker during display is greatly improved. Therefore, the pixel driving circuit provided in the embodiments of the present disclosure not only ensures the display quality of the display device but also reduces the power consumption of the display device in the case of low-frequency driving.
  • the pixel driving circuit provided by the embodiments of the present disclosure can well maintain the potential of the gate of the driving transistor DT during the light-emitting period in both the low-gray-scale display situation and the high-gray-scale display situation, thereby improving the display device performance It is prone to flicker when displaying.
  • FIG. 9 shows the driving timings corresponding to the two rows of pixel driving circuits, where EM2 represents the first control terminal corresponding to the second row of pixel driving circuits, and the reset control terminal corresponding to the second row of pixel driving circuits on the RE2 generation.
  • GT2 represents the gate line corresponding to the second row of pixel drive circuits
  • N1' represents the common node in the second row of pixel drive circuits.
  • P1' represents the reset period corresponding to the pixel drive circuit of the second row
  • P2' represents the write compensation period corresponding to the pixel drive circuit of the second row
  • P3' represents the light emission period corresponding to the pixel drive circuit of the second row.
  • the first reset sub-circuit 51 includes:
  • the first reset control sub-circuit 511 is respectively connected to the reset control terminal RE, the gate of the drive transistor DT and the common node N1; it is used to control the conduction or conduction under the control of the reset control terminal RE. Disconnecting the connection between the gate of the driving transistor DT and the common node N1;
  • the second reset control sub-circuit 512 is respectively connected to the reset control terminal RE, the common node N1 and the first initialization voltage input terminal Vinit1; used to control the conduction under the control of the reset control terminal RE Or disconnect the connection between the common node N1 and the first initialization voltage input terminal Vinit1;
  • the third reset control sub-circuit 513 is respectively connected to the first control terminal EM, the common node N1 and the second initialization voltage input terminal Vinit2; it is used for controlling under the control of the first control terminal EM Turning on or disconnecting the connection between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the specific structure of the first reset sub-circuit 51 is various.
  • the first reset sub-circuit 51 includes the first reset control sub-circuit 511 and the second reset control sub-circuit 512.
  • a third reset control sub-circuit 513 the first reset control sub-circuit 511 is connected between the gate of the driving transistor DT and the common node N1, and the second reset control sub-circuit 512 is connected to the Between the common node N1 and the first initialization voltage input terminal Vinit1, the third reset control sub-circuit 513 is connected between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the working process of the first reset sub-circuit 51 is as follows:
  • the first reset control sub-circuit 511 controls to turn on the connection between the gate of the driving transistor DT and the common node N1.
  • the second reset control sub-circuit 512 controls to turn on the connection between the common node N1 and the first initialization voltage input terminal Vinit1, so that the potential of the gate of the driving transistor DT becomes V1, so as to realize the connection of the driving transistor DT
  • the gate is reset, so that the gate-source voltage Vgs held on the driving transistor DT in the previous frame is initialized.
  • the third reset control sub-circuit 513 controls to disconnect the connection between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the first reset control sub-circuit 511 controls to disconnect the connection between the gate of the driving transistor DT and the common node N1, so The second reset control sub-circuit 512 controls to disconnect the connection between the common node N1 and the first initialization voltage input terminal Vinit1.
  • the third reset control sub-circuit 513 continues to control the disconnection between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the first reset control sub-circuit 511 continues to control the disconnection between the gate of the driving transistor DT and the common node N1
  • the The second reset control sub-circuit 512 continues to control the disconnection between the common node N1 and the first initialization voltage input terminal Vinit1.
  • the third reset control sub-circuit 513 controls to turn on the connection between the common node N1 and the second initialization voltage input terminal Vinit2, so that the common node N1 The potential becomes V2 which is substantially the same as the gate potential of the drive transistor DT.
  • the reasons for the leakage of the gate of the driving transistor DT include: during the light-emitting period P3, the electric potential of the initialization signal connected to the first reset sub-circuit 51 is low, so that the gate potential of the driving transistor DT is different from the initialization signal. A large potential difference is generated between the potentials of the signals, which in turn causes the gate of the driving transistor DT to leak through the first reset sub-circuit 51 to the initialization voltage input terminal that provides the initialization signal.
  • the initialization signal input from the initialization voltage input terminal may be considered to set to an AC signal.
  • the potential of the initialization signal input from the initialization voltage input terminal is set to A low potential between -1V and -3V; during the light-emitting period, the potential of the initialization signal input from the initialization voltage input terminal is adjusted to a high potential that is substantially the same as the gate potential of the driving transistor DT.
  • the above method of setting the initialization signal input by the initialization voltage input terminal as an AC signal can improve the problem of flickering of the display device during display, because the OLED drive architecture is line-by-line light emission, that is, the initialization voltage input terminal
  • the potential of the input initialization signal also needs to be adjusted row by row, so it is necessary to set a special GOA circuit for the initialization voltage input terminal corresponding to each row of pixel drive circuit, that is, add a column of the GOA circuit to the display device, and a column of the GOA circuit.
  • the GOA circuit occupies a relatively large space, which is not conducive to the development demand for narrow bezels of display devices.
  • the first control terminal EM can control the second A reset sub-circuit 51 can also control the power control sub-circuit 1 at the same time. Therefore, the first control terminal EM connected to the first reset sub-circuit 51 and the power control sub-circuit 1 only needs to be provided with a corresponding GOA circuit, Similarly, the reset control terminal RE connected to the first reset sub-circuit 51 only needs to be provided with a corresponding GOA circuit.
  • the pixel driving circuit provided in the foregoing embodiment adopts the existing GOA scheme to achieve the
  • the common node N1 provides an initialization signal with a suitable potential, and there is no need to add an additional GOA circuit specifically for realizing the conversion of the initialization signal potential.
  • the existing GOA solution includes a column of EMGOA and a column of GTGOA.
  • the EMGOA is used to provide a first control signal to its correspondingly connected first control terminal
  • the GTGOA is used to provide a scan signal to its correspondingly connected gate line.
  • the pixel driving circuit provided by the above-mentioned embodiment only needs to use one column of EMGOA and one column of GTGOA, and there is no need to add an additional GOA circuit specifically for realizing initialization signal potential conversion.
  • the first initialization voltage input terminal Vinit1 and the second initialization voltage input terminal Vinit2 are all DC signals, which avoids power consumption caused by setting AC initialization signals. Increase.
  • the first reset control sub-circuit 511 includes a first transistor T1, the gate of the first transistor T1 is connected to the reset control terminal RE, and the first electrode of the first transistor T1 is connected to the reset control terminal RE.
  • the common node N1 is connected, and the second electrode of the first transistor T1 is connected to the gate of the driving transistor DT;
  • the second reset control sub-circuit 512 includes a second transistor T2, the gate of the second transistor T2 is connected to the reset control terminal RE, and the first electrode of the second transistor T2 is connected to the first initialization voltage
  • the input terminal Vinit1 is connected, and the second electrode of the second transistor T2 is connected to the common node N1;
  • the third reset control sub-circuit 513 includes a third transistor T3, the gate of the third transistor T3 is connected to the first control terminal EM, and the first electrode of the third transistor T3 is connected to the second initialization terminal EM.
  • the voltage input terminal Vinit2 is connected, and the second electrode of the third transistor T3 is connected to the common node N1.
  • the specific structures of the first reset control sub-circuit 511, the second reset control sub-circuit 512, and the third reset control sub-circuit 513 are various.
  • the first reset control sub-circuit The circuit 511 includes a first transistor T1
  • the second reset control sub-circuit 512 includes a second transistor T2
  • the third reset control sub-circuit 513 includes a third transistor T3.
  • the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 is turned off, so that the first initialization voltage input terminal Vinit1 and the driving transistor DT are controlled to be turned on.
  • the connection between the gates of disconnects the connection between the second initialization voltage input terminal Vinit2 and the gate of the driving transistor DT.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all turned off, thereby controlling to disconnect the gate of the driving transistor DT from the first initialization voltage
  • the connection between the input terminal Vinit1 is controlled to disconnect the connection between the gate of the driving transistor DT and the second initializing voltage input terminal Vinit2 at the same time.
  • the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on, thereby controlling to disconnect the gate of the driving transistor DT from the first initialization voltage
  • the connection between the input terminal Vinit1 and the connection between the gate of the driving transistor DT and the second initialization voltage input terminal Vinit2 are controlled.
  • the pixel driving circuit further includes:
  • the second reset sub-circuit 52 is respectively connected to the reset control terminal RE, the light-emitting element EL, and the third initialization voltage input terminal Vinit3; and is used to control the conduction or disconnection under the control of the reset control terminal RE The connection between the third initialization voltage input terminal Vinit3 and the light-emitting element EL.
  • the second reset sub-circuit 52 controls to turn on the connection between the third initialization voltage input terminal Vinit3 and the light-emitting element EL. Connected, using the third initialization signal input from the third initialization voltage input terminal Vinit3 to reset the anode of the light-emitting element EL.
  • the second reset sub-circuit 52 controls to disconnect the third initialization voltage input terminal Vinit3 and the light emitting element EL. the connection between.
  • the third initialization voltage input terminal Vinit3 is coupled to the first initialization voltage input terminal Vinit1.
  • the third initialization signal input from the third initialization voltage input terminal Vinit3 is used to reset the anode of the light-emitting element EL, so the potential of the third initialization signal is low.
  • the first initialization signal input from the first initialization voltage input terminal Vinit1 is also a signal for resetting, and also has a lower potential. Therefore, the third initialization voltage input terminal Vinit3 can be connected to the first initialization signal.
  • the voltage input terminal Vinit1 is coupled, so that only one initialization signal line capable of providing initialization signals with a lower potential for the first initialization voltage input terminal Vinit1 and the third initialization voltage input terminal Vinit3 at the same time needs to be provided in the display device Therefore, in the pixel driving circuit provided by the above embodiment, by setting the third initialization voltage input terminal Vinit3 to be coupled to the first initialization voltage input terminal Vinit1, the number of initialization signal lines in the display device is effectively reduced. This is more conducive to reducing the layout difficulty of the display device.
  • the second reset sub-circuit 52 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the reset control terminal RE, and the The first pole of the four transistor T4 is connected to the third initialization voltage input terminal Vinit3, and the second pole of the fourth transistor T4 is connected to the light emitting element EL.
  • the specific structure of the second reset sub-circuit 52 is various.
  • the second reset sub-circuit 52 includes the fourth transistor T4.
  • the fourth transistor T4 is turned on, thereby turning on the connection between the third initialization voltage input terminal Vinit3 and the light-emitting element EL to achieve Reset of the anode of the light-emitting element EL.
  • the fourth transistor T4 is turned off, thereby disconnecting the third initialization voltage input terminal Vinit3 from the light emission Connection between elements EL.
  • the pixel driving circuit further includes a light-emitting control sub-circuit 8, and the second electrode of the driving transistor DT passes through the light-emitting control sub-circuit 8 and the light-emitting element.
  • EL connection
  • the light emission control sub-circuit 8 is respectively connected to the first control terminal EM, the second pole of the driving transistor DT, and the light emitting element EL, and is used to: under the control of the first control terminal EM, control The connection between the second electrode of the driving transistor DT and the light emitting element EL is turned on or off.
  • the light emission control sub-circuit 8 controls the connection between the second pole of the turn-on driving transistor DT and the anode of the light emitting element EL.
  • the light emission control sub-circuit 8 controls to disconnect the connection between the second electrode of the driving transistor DT and the anode of the light emitting element EL, which is very good This prevents the light emitting element EL from emitting abnormally during the reset period P1 and the write compensation period P2.
  • the light emission control sub-circuit 8 includes a fifth transistor T5, and the gate of the fifth transistor T5 is connected to the first control terminal EM, and the first control terminal EM is connected to the gate of the fifth transistor T5.
  • the first electrode of the five transistor T5 is connected to the second electrode of the driving transistor DT, and the second electrode of the fifth transistor T5 is connected to the light emitting element EL.
  • the specific structure of the light emission control sub-circuit 8 is various.
  • the light emission control sub-circuit 8 includes the fifth transistor T5.
  • the fifth transistor T5 is turned on, thereby controlling the connection between the second electrode of the driving transistor DT and the anode of the light emitting element EL.
  • the fifth transistor T5 is turned off, thereby controlling the disconnection between the second electrode of the driving transistor DT and the anode of the light emitting element EL Therefore, abnormal light emission of the light-emitting element EL during the reset period P1 and the write compensation period P2 is well avoided.
  • the power control sub-circuit 1 may be configured to include a sixth transistor T6, and the gate of the sixth transistor T6 is connected to the first control terminal EM, so The first electrode of the sixth transistor T6 is connected to the power signal input terminal, and the second electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor DT;
  • the data writing sub-circuit 2 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the corresponding row gate line GT, and the first electrode of the seventh transistor T7 is connected to the corresponding column data line DA, so The second electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor DT;
  • the compensation sub-circuit 6 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the corresponding row gate line GT, and the first electrode of the eighth transistor T8 is connected to the second electrode of the driving transistor DT , The second electrode of the eighth transistor T8 is connected to the gate of the driving transistor DT.
  • the storage sub-circuit 4 includes a first capacitor C1.
  • the sixth transistor T6 is turned off, thereby controlling to disconnect the power signal input terminal ELVDD and the first electrode of the driving transistor DT.
  • the seventh transistor T7 is turned off, thereby controlling the disconnection of the connection between the corresponding column data line DA and the first pole of the driving transistor DT;
  • the eighth transistor T8 is turned off, thereby controlling the disconnection between the second electrode of the driving transistor DT and the gate of the driving transistor DT.
  • the sixth transistor T6 is turned off, and continues to control the disconnection between the power signal input terminal ELVDD and the first pole of the driving transistor DT
  • the seventh transistor T7 is turned on, thereby controlling the connection between the corresponding column data line DA and the first pole of the driving transistor DT
  • the eighth transistor T8 is turned on, thereby controlling to turn on the connection between the second electrode of the driving transistor DT and the gate of the driving transistor DT.
  • the sixth transistor T6 is turned on, thereby controlling the conduction between the power signal input terminal ELVDD and the first electrode of the driving transistor DT.
  • the seventh transistor T7 is turned off, thereby controlling to disconnect the connection between the corresponding column data line DA and the first electrode of the driving transistor DT; in the corresponding row gate Under the control of the line GT, the eighth transistor T8 is turned off, thereby controlling the disconnection between the second electrode of the driving transistor DT and the gate of the driving transistor DT.
  • the transistors used are all PMOS transistors. Therefore, the transistors included in the pixel drive circuit can be manufactured at the same time using the same process, which avoids the need to pass through when manufacturing the pixel drive circuit. Complicated processes produce PMOS transistors and oxide transistors at the same time, resulting in complicated production processes and increased production costs.
  • An embodiment of the present disclosure also provides a display device, which includes the pixel driving circuit provided in the foregoing embodiment.
  • the driving current I is only related to the power supply voltage Vdd and the data voltage Vdata, and has nothing to do with the threshold voltage Vth of the driving transistor DT; therefore, even if the same is input to a plurality of driving transistors DT with different threshold voltages Vth At the time of the data voltage, the drive transistors DT with different threshold voltages Vth generate the same drive current in the saturation state, so that when the drive transistors DT with different threshold voltages Vth drive the corresponding light emitting elements EL to emit light, the light emitting brightness of the light emitting elements EL is the same.
  • driving transistors DT with different threshold voltages Vth to drive the light-emitting element EL to emit light, the problem of uneven light emission of the light-emitting element EL due to threshold voltage drift is avoided.
  • the first reset sub-circuit 51 is provided so that in the reset period P1, the first reset sub-circuit 51 can turn on the gate of the driving transistor DT and the second The connection between an initialization voltage input terminal Vinit1 makes the potential of the gate of the driving transistor DT change to a lower potential V1 input from the first initialization voltage input terminal Vinit1 to reset the gate of the driving transistor DT; At the same time, in the reset period P1, the first reset sub-circuit 51 can disconnect the gate of the driving transistor DT and the second initialization voltage input terminal Vinit2.
  • the first reset sub-circuit 51 can disconnect the gate of the driving transistor DT and the first initialization voltage input terminal Vinit1, and turn on the gate of the driving transistor DT
  • the connection with the second initialization voltage input terminal Vinit2 makes the potential of the common node N1 substantially the same as the potential of the gate of the driving transistor DT. Therefore, the pixel driving circuit provided by the above-mentioned embodiment effectively reduces the leakage current of the gate of the driving transistor DT through the first reset sub-circuit 51 during the light-emitting period P3, so that even in the case of low-frequency driving, The electric potential of the gate of the driving transistor DT can be well maintained, so that the problem that the display device is prone to flicker during display is well improved. Therefore, the pixel driving circuit provided in the embodiments of the present disclosure not only ensures the display quality of the display device but also reduces the power consumption of the display device in the case of low-frequency driving.
  • the display device provided by the embodiment of the present disclosure includes the pixel driving circuit provided by the above-mentioned embodiment, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and so on.
  • the display device includes a display area AA and a peripheral area surrounding the display area AA, and the display device further includes a first initialization signal line Init1 and a peripheral area located in the peripheral area.
  • a second initialization signal line Init2 the first initialization signal line Init1 and the second initialization signal line Init2 both extend along a first direction;
  • the display device includes a plurality of the pixel drive circuits arranged in an array in the display area AA, in each pixel drive circuit located in the same row along the second direction, a first initialization voltage input terminal connected to the first reset sub-circuit 51 Vinit1 is connected to the first initialization signal line Init1 through the same first connection line 91;
  • the second initialization voltage input terminal Vinit2 connected to the first reset sub-circuit 51 is connected to the second initialization signal line Init2 through the same second connection line 92, so The first direction intersects the second direction.
  • first initialization signal line Init1 and the second initialization signal line Init2 there are various specific layouts of the first initialization signal line Init1 and the second initialization signal line Init2.
  • the first initialization signal line Init1 and the second initialization signal line Init2 are both arranged in the peripheral area.
  • first initialization signal line Init1 and the second initialization signal line Init2 are provided on opposite sides along the second direction.
  • the first direction is the same as the extension direction of the data line
  • the second direction is the same as the extension direction of the gate line.
  • the first initialization signal line Init1 and the second initialization signal line Init2 are made of the same material and made in the same layer, and the first initialization signal line Init1 and the second initialization signal line Init2 are arranged in order along the second direction. .
  • the first initialization signal line Init1 and the second initialization signal line Init2 are arranged in different layers, and the orthographic projection of the first initialization signal line Init1 on the substrate of the display device and the second initialization signal The orthographic projection of the line Init2 on the substrate of the display device overlaps.
  • first connection line 91 and the second connection line 92 are arranged in different layers.
  • first initialization signal line Init1 and the second initialization signal line Init2 are laid out in the peripheral area in the above manner, it is more conducive to reduce the occupation of the first initialization signal line Init1 and the second initialization signal line Init2.
  • first initialization signal line Init1 and the second initialization signal line Init2 provide corresponding initialization signals for each pixel driving circuit in the display area AA, it is more conducive to the narrow frame of the display device. develop.
  • the figure also shows the first fan-out area F1, the second fan-out area F2, the bending area BA, the electrostatic discharge unit ESD, the first test circuit CT1, the second test circuit CT2, and the test circuit contact area ET. , Chip-on-Film COF and multiplexer MUX.
  • the embodiments of the present disclosure also provide a driving method of the pixel driving circuit, which is applied to the pixel driving circuit provided in the above-mentioned embodiments, and the driving method includes: in each working cycle,
  • the first reset sub-circuit 51 controls to turn on the first initialization voltage input terminal Vinit1 and the common The connection between the node N1 and the connection between the common node N1 and the gate of the driving transistor DT in the driving sub-circuit; under the control of the first control terminal EM, the first reset sub-circuit 51 controls Disconnect the connection between the second initialization voltage input terminal Vinit2 and the common node N1;
  • the first reset sub-circuit 51 controls to disconnect the connection between the first initialization voltage input terminal Vinit1 and the common node N1, and controls to disconnect all The connection between the common node N1 and the gate of the driving transistor DT;
  • the data voltage Vdata is input to the corresponding column data line DA, and under the control of the corresponding row gate line GT, the data writing sub-circuit 2 controls the corresponding column data to be turned on The connection between the line DA and the first pole of the drive transistor DT
  • the compensation sub-circuit 6 controls to turn on the connection between the gate of the drive transistor DT and the second pole of the drive transistor DT, so that the The driving transistor DT is formed in a diode structure, so that the potential of the gate of the driving transistor DT becomes Vdata+Vth, and Vth is the threshold voltage of the driving transistor DT;
  • the power signal input terminal ELVDD inputs the power supply voltage Vdd
  • the power control sub-circuit 1 controls to turn on the power signal input terminal ELVDD and the drive The connection between the first pole of the transistor DT; under the control of the first control terminal EM, the first reset sub-circuit 51 controls to turn on the connection between the second initialization voltage input terminal Vinit2 and the common node N1 Connection; the second initialization voltage input terminal Vinit2 input voltage of the second initialization signal, and the light-emitting period P3 the difference between the potential of the gate of the driving transistor DT is less than the threshold.
  • the potential of the first initialization signal input from the first initialization voltage input terminal Vinit1 is V1
  • the reset signal input from the reset control terminal RE is at an effective level, so that under the control of the reset control terminal RE, the first initialization signal
  • the reset sub-circuit 51 controls to turn on the connection between the first initialization voltage input terminal Vinit1 and the common node N1, and turns on the connection between the common node N1 and the gate of the driving transistor DT, so that The potential of the gate of the driving transistor DT becomes V1 to reset the gate of the driving transistor DT, so that the gate-source voltage Vgs held on the driving transistor DT in the previous frame is initialized; in the reset period P1,
  • the first control signal input by the first control terminal EM is at an inactive level, so that under the control of the first control terminal EM, the first reset sub-circuit 51 also controls to disconnect the second initialization voltage input terminal Vinit2 from the The connection between the public nodes N1.
  • the reset signal input by the reset control terminal RE is at an inactive level, so that under the control of the reset control terminal RE, the first reset sub-circuit 51 controls to turn off the first initialization voltage input terminal The connection between Vinit1 and the common node N1, and control to disconnect the connection between the common node N1 and the gate of the driving transistor DT; under the control of the first control terminal EM, the first reset The sub-circuit 51 continues to control the disconnection of the connection between the second initialization voltage input terminal Vinit2 and the common node N1; the corresponding column data line DA inputs the data voltage Vdata, and the corresponding row gate line GT input scan signal is at an effective level, so that Under the control of the corresponding row gate line GT, the data writing sub-circuit 2 controls the connection between the corresponding column data line DA and the first electrode of the driving transistor DT to change the potential of the first electrode of the driving transistor DT.
  • the compensation sub-circuit 6 controls to turn on the connection between the gate of the driving transistor DT and the second electrode of the driving transistor DT, so that the driving transistor DT It is formed into a diode structure, so the data writing sub-circuit 2, the driving transistor DT and the compensation sub-circuit 6 work together to realize the threshold voltage compensation of the driving transistor DT.
  • the compensation time is long enough, the gate of the driving transistor DT can be controlled.
  • the electrode potential finally reaches Vdata+Vth, and Vth is the threshold voltage of the driving transistor DT.
  • the power signal input terminal ELVDD is input with the power supply voltage Vdd, and the first control signal input by the first control terminal EM is at an effective level, so that under the control of the first control terminal EM, the The power control sub-circuit 1 controls to turn on the connection between the power signal input terminal ELVDD and the first pole of the drive transistor DT, so that the potential of the first pole of the drive transistor DT changes from Vdata to Vdd;
  • the potential of the second initialization signal input from the second initialization voltage input terminal Vinit2 is V2
  • the first reset sub-circuit 51 controls to turn on the second initialization voltage input terminal Vinit2 and the
  • the connection between the common node N1 makes the potential of the common node N1 change to V2; the potential V2 of the second initialization signal input from the second initialization voltage input terminal Vinit2, and the gate of the driving transistor DT during the light-emitting period P3
  • the difference between the potentials of the poles is less
  • the driving current I is only related to the power supply voltage Vdd and the data voltage Vdata, and has nothing to do with the threshold voltage Vth of the driving transistor DT; therefore, even if When the same data voltage is input to a plurality of drive transistors DT with different threshold voltages Vth, the drive transistors DT with different threshold voltages Vth generate the same drive current in the saturation state, so that the drive transistors DT with different threshold voltages Vth drive corresponding drive transistors.
  • the light-emitting brightness of the light-emitting element EL is the same, which avoids the problem of uneven light emission of the light-emitting element EL due to threshold voltage drift when driving transistors DT with different threshold voltages Vth to drive the light-emitting element EL to emit light.
  • the first reset sub-circuit 51 can turn on the gate of the driving transistor DT and the first initialization voltage input terminal Vinit1
  • the connection between the driving transistor DT makes the potential of the gate of the driving transistor DT change to the lower potential V1 input from the first initialization voltage input terminal Vinit1 to reset the gate of the driving transistor DT; and at the same time during the reset period P1, the first reset sub-circuit 51 can disconnect the gate of the driving transistor DT and the second initialization voltage input terminal Vinit2.
  • the first reset sub-circuit 51 can disconnect the gate of the driving transistor DT and the first initialization voltage input terminal Vinit1, and turn on the gate of the driving transistor DT
  • the connection with the second initialization voltage input terminal Vinit2 makes the potential of the common node N1 substantially the same as the potential of the gate of the driving transistor DT.
  • the driving method provided by the embodiment of the present disclosure to drive the above-mentioned pixel driving circuit effectively reduces the leakage current of the gate of the driving transistor DT through the first reset sub-circuit 51 during the light-emitting period P3, so that at low frequencies In the case of driving, the potential of the gate of the driving transistor DT can also be well maintained, so that the problem that the display device is prone to flicker during display is greatly improved. Therefore, the pixel driving circuit provided in the embodiments of the present disclosure not only ensures the display quality of the display device but also reduces the power consumption of the display device in the case of low-frequency driving.
  • the first reset sub-circuit includes a first reset control sub-circuit 511, a second reset control sub-circuit 512, and a third reset control sub-circuit 513,
  • the first reset control sub-circuit 511 controls to turn on the connection between the gate of the driving transistor DT and the common node N1, and at the same time
  • the second reset control sub-circuit 512 controls the connection between the common node N1 and the first initialization voltage input terminal Vinit1; under the control of the first control terminal EM, the third reset control
  • the sub-circuit 513 controls to disconnect the connection between the common node N1 and the second initialization voltage input terminal Vinit2;
  • the first reset control sub-circuit 511 controls to disconnect the connection between the gate of the driving transistor DT and the common node N1, while the The second reset control sub-circuit 512 controls to disconnect the connection between the common node N1 and the first initialization voltage input terminal Vinit1;
  • the third reset control sub-circuit 513 controls to turn on the connection between the second initialization voltage input terminal Vinit2 and the common node N1.
  • the first reset control sub-circuit 511 controls to turn on the connection between the gate of the driving transistor DT and the common node N1
  • the second reset control sub-circuit 512 controls to turn on the connection between the common node N1 and the first initialization voltage input terminal Vinit1, so that the potential of the gate of the driving transistor DT becomes V1 to realize the driving
  • the gate of the transistor DT is reset, so that the gate-source voltage Vgs held on the driving transistor DT in the previous frame is initialized.
  • the third reset control sub-circuit 513 controls to disconnect the connection between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the first reset control sub-circuit 511 controls to disconnect the connection between the gate of the driving transistor DT and the common node N1, so The second reset control sub-circuit 512 controls to disconnect the connection between the common node N1 and the first initialization voltage input terminal Vinit1.
  • the third reset control sub-circuit 513 continues to control the disconnection between the common node N1 and the second initialization voltage input terminal Vinit2.
  • the first reset control sub-circuit 511 continues to control the disconnection between the gate of the driving transistor DT and the common node N1
  • the The second reset control sub-circuit 512 continues to control the disconnection between the common node N1 and the first initialization voltage input terminal Vinit1.
  • the third reset control sub-circuit 513 controls to turn on the connection between the common node N1 and the second initialization voltage input terminal Vinit2, so that the common node N1 The potential becomes V2 which is substantially the same as the gate potential of the drive transistor DT.
  • the first control terminal EM can not only Controlling the first reset sub-circuit 51 can also control the power control sub-circuit 1 at the same time. Therefore, the first control terminal EM connected to the first reset sub-circuit 51 and the power control sub-circuit 1 only needs to be provided with one corresponding For the same GOA circuit, the reset control terminal RE connected to the first reset sub-circuit 51 only needs to be provided with a corresponding GOA circuit.
  • the existing The GOA scheme of the above can provide the common node N1 with an initialization signal with a suitable potential in different time periods, without the need to add an additional GOA circuit specifically for realizing the conversion of the initialization signal potential.
  • the first initialization voltage input terminal Vinit1 and the second initialization voltage input terminal Vinit2 are all DC signals, which avoids the setting of AC initialization signals. The resulting increase in power consumption.
  • the pixel driving circuit further includes a light-emitting control sub-circuit 8, and the second pole of the driving transistor DT is connected to the light-emitting element EL through the light-emitting control sub-circuit 8; the light-emitting control sub-circuit 8 are respectively connected to the first control terminal EM, the second pole of the driving transistor DT, and the light emitting element EL; the driving method further includes: during the reset period P1 and the write compensation period P2, Under the control of the first control terminal EM, the light emission control sub-circuit 8 controls to disconnect the connection between the second electrode of the driving transistor DT and the light emitting element EL, so that the light emitting element EL is The reset period P1 and the write compensation period P2 do not emit light.
  • the light emitting control sub-circuit 8 controls the connection between the second electrode of the driving transistor DT and the anode of the light emitting element EL.
  • the light emission control sub-circuit 8 controls to disconnect the connection between the second electrode of the driving transistor DT and the anode of the light emitting element EL, which is very good This prevents the light emitting element EL from emitting abnormally during the reset period P1 and the write compensation period P2.
  • the pixel driving circuit further includes a second reset sub-circuit 52, and the second reset sub-circuit 52 is connected to the reset control terminal RE, the light emitting element EL, and the third initialization voltage input terminal Vinit3, respectively. Connection; in the reset period P1, under the control of the reset control terminal RE, the second reset sub-circuit 52 controls to turn on the connection between the third initialization voltage input terminal Vinit3 and the light-emitting element EL .
  • the second reset sub-circuit 52 controls to turn on the connection between the third initialization voltage input terminal Vinit3 and the light-emitting element EL. Connected, using the third initialization signal input from the third initialization voltage input terminal Vinit3 to reset the anode of the light-emitting element EL.
  • the second reset sub-circuit 52 controls to disconnect the third initialization voltage input terminal Vinit3 and the light emitting element EL. the connection between.
  • the potential of the third initialization signal input from the third initialization voltage input terminal Vinit3 can be set to be the same as the potential of the first initialization signal input from the first initialization voltage input terminal Vinit1.
  • the third initialization signal input from the third initialization voltage input terminal Vinit3 is used to reset the anode of the light-emitting element EL, so the potential of the third initialization signal is low.
  • the first initialization signal input from the first initialization voltage input terminal Vinit1 is also a signal for resetting, and also has a lower potential. Therefore, the third initialization voltage input terminal Vinit3 can be connected to the first initialization signal.
  • the voltage input terminal Vinit1 is coupled, so that only one device needs to be provided in the display device to provide the same initialization signal with a lower potential for the first initialization voltage input terminal Vinit1 and the third initialization voltage input terminal Vinit3 at the same time.
  • the signal line therefore, when the pixel driving circuit is driven by the driving method provided in the above embodiment, the number of initialization signal lines in the display device can be effectively reduced, which is more conducive to reducing the layout difficulty of the display device.

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Abstract

一种像素驱动电路及其驱动方法、显示装置。像素驱动电路的第一复位子电路(51)用于控制导通或断开驱动晶体管(DT)的栅极与公共节点(N1)、公共节点(N1)与第一初始化电压输入端(Vinit1)之间的连接，还控制导通或断开公共节点(N1)与第二初始化电压输入端(Vinit2)之间的连接；第二初始化电压输入端(Vinit2)输入信号的电位与发光时段驱动晶体管(DT)的栅极的电位之间的差值小于阈值。显示装置包括像素驱动电路。像素驱动电路的驱动方法，在每一工作周期的复位时段、写入补偿时段和发光时段，分别对第一复位子电路(51)进行控制。在低频驱动时保持驱动晶体管的栅极电位，保证显示质量，降低功耗。

Description

一种像素驱动电路及其驱动方法、显示装置
相关申请的交叉引用
本申请主张在2020年05月14日在中国提交的中国专利申请号No.202010406866.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示装置。
背景技术
AMOLED(Active-matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)显示器件具有自发光、超薄、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示器件。
这种AMOLED显示器件包括多个像素驱动电路和多个发光元件，像素驱动电路用于驱动对应的发光元件发光，从而实现AMOLED显示器件的显示功能。但是现有的像素驱动电路在低频驱动时，像素驱动电路中的驱动晶体管栅极漏电严重，使显示器件在显示时容易出现闪烁的现象。
发明内容
本公开的目的在于提供一种像素驱动电路及其驱动方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种像素驱动电路，用于驱动发光元件，包括：
驱动子电路，所述驱动子电路包括驱动晶体管，驱动晶体管的第二极与所述发光元件连接；
存储子电路，所述存储子电路的第一端与所述驱动晶体管的栅极连接，所述存储子电路的第二端与电源信号输入端连接；
电源控制子电路，分别与第一控制端、所述电源信号输入端和所述驱动 晶体管的第一极连接；
数据写入子电路，分别与相应行栅线、相应列数据线和所述驱动晶体管的第一极连接；
补偿子电路，分别与相应行栅线、所述驱动晶体管的栅极和所述驱动晶体管的第二极连接；
第一复位子电路，分别与复位控制端、所述第一控制端、所述驱动晶体管的栅极、公共节点、第一初始化电压输入端和第二初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述驱动晶体管的栅极与所述公共节点之间的连接，以及控制导通或断开所述公共节点与所述第一初始化电压输入端之间的连接；还用于在所述第一控制端的控制下，控制导通或断开所述公共节点与所述第二初始化电压输入端之间的连接；
所述第二初始化电压输入端输入的第二初始化信号的电位，与发光时段所述驱动晶体管的栅极的电位之间的差值小于阈值。
可选的，所述第一复位子电路包括：
第一复位控制子电路，分别与所述复位控制端、所述驱动晶体管的栅极和所述公共节点连接；用于在所述复位控制端的控制下，控制导通或断开所述驱动晶体管的栅极与所述公共节点之间的连接；
第二复位控制子电路，分别与所述复位控制端、所述公共节点和所述第一初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述公共节点与所述第一初始化电压输入端之间的连接；
第三复位控制子电路，分别与所述第一控制端、所述公共节点和所述第二初始化电压输入端连接；用于在所述第一控制端的控制下，控制导通或断开所述公共节点与所述第二初始化电压输入端之间的连接。
可选的，所述第一复位控制子电路包括第一晶体管，所述第一晶体管的栅极与所述复位控制端连接，所述第一晶体管的第一极与所述公共节点连接，所述第一晶体管的第二极与所述驱动晶体管的栅极连接；
所述第二复位控制子电路包括第二晶体管，所述第二晶体管的栅极与所述复位控制端连接，所述第二晶体管的第一极与所述第一初始化电压输入端连接，所述第二晶体管的第二极与所述公共节点连接；
所述第三复位控制子电路包括第三晶体管，所述第三晶体管的栅极与所述第一控制端连接，所述第三晶体管的第一极与所述第二初始化电压输入端连接，所述第三晶体管的第二极与所述公共节点连接。
可选的，所述像素驱动电路还包括：
第二复位子电路，分别与所述复位控制端、所述发光元件和第三初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述第三初始化电压输入端与所述发光元件之间的连接。
可选的，所述第三初始化电压输入端与所述第一初始化电压输入端耦接。
可选的，所述第二复位子电路包括第四晶体管，所述第四晶体管的栅极与所述复位控制端连接，所述第四晶体管的第一极与所述第三初始化电压输入端连接，所述第四晶体管的第二极与所述发光元件连接。
可选的，所述像素驱动电路还包括发光控制子电路，所述驱动晶体管的第二极通过所述发光控制子电路与所述发光元件连接；
所述发光控制子电路分别与所述第一控制端、所述驱动晶体管的第二极和所述发光元件连接，用于：在所述第一控制端的控制下，控制导通或断开所述驱动晶体管的第二极与所述发光元件之间的连接。
可选的，所述发光控制子电路包括第五晶体管，所述第五晶体管的栅极与所述第一控制端连接，所述第五晶体管的第一极与所述驱动晶体管的第二极连接，所述第五晶体管的第二极与所述发光元件连接。
可选的，所述电源控制子电路包括第六晶体管，所述第六晶体管的栅极与所述第一控制端连接，所述第六晶体管的第一极与所述电源信号输入端连接，所述第六晶体管的第二极与所述驱动晶体管的第一极连接；
所述数据写入子电路包括第七晶体管，所述第七晶体管的栅极与相应行栅线连接，所述第七晶体管的第一极与相应列数据线连接，所述第七晶体管的第二极与所述驱动晶体管的第一极连接；
所述补偿子电路包括第八晶体管，所述第八晶体管的栅极与相应行栅线连接，所述第八晶体管的第一极与所述驱动晶体管的第二极连接，所述第八晶体管的第二极与所述驱动晶体管的栅极连接。
基于上述像素驱动电路的技术方案，本公开的第二方面提供一种显示装 置，包括上述实施例提供的像素驱动电路。
可选的，所述显示装置包括显示区域和围绕所述显示区域的周边区域，所述显示装置还包括位于所述周边区域的第一初始化信号线和第二初始化信号线，所述第一初始化信号线和所述第二初始化信号线均沿第一方向延伸，
所述显示装置包括阵列分布在所述显示区域的多个所述像素驱动电路，沿第二方向位于同一行的各像素驱动电路中，第一复位子电路连接的第一初始化电压输入端均通过同一条第一连接线与所述第一初始化信号线连接；
沿第二方向位于同一行的各像素驱动电路中，第一复位子电路连接的第二初始化电压输入端均通过同一条第二连接线与所述第二初始化信号线连接，所述第一方向与所述第二方向相交。
基于上述像素驱动电路的技术方案，本公开的第三方面提供一种像素驱动电路的驱动方法，应用于上述实施例提供的像素驱动电路，所述驱动方法包括：在每一工作周期，
在复位时段，第一初始化电压输入端输入第一初始化电压Vinit1，在复位控制端的控制下，第一复位子电路控制导通所述第一初始化电压输入端与所述公共节点之间的连接，并导通所述公共节点与驱动子电路中驱动晶体管的栅极之间的连接；在所述第一控制端的控制下，第一复位子电路控制断开第二初始化电压输入端与所述公共节点之间的连接；
在写入补偿时段，在复位控制端的控制下，第一复位子电路控制断开所述第一初始化电压输入端与所述公共节点之间的连接，并控制断开所述公共节点与所述驱动晶体管的栅极之间的连接；相应列数据线输入数据电压Vdata，在相应行栅线的控制下，数据写入子电路控制导通相应列数据线和所述驱动晶体管的第一极之间的连接，补偿子电路控制导通所述驱动晶体管的栅极和所述驱动晶体管的第二极之间的连接，使所述驱动晶体管形成为二极管结构，使所述驱动晶体管的栅极的电位变为Vdata+Vth，Vth为驱动晶体管的阈值电压；
在发光时段，所述电源信号输入端输入电源电压Vdd，在所述第一控制端的控制下，所述电源控制子电路控制导通所述电源信号输入端与所述驱动晶体管的第一极之间的连接；在所述第一控制端的控制下，第一复位子电路 控制导通所述第二初始化电压输入端与所述公共节点之间的连接；所述第二初始化电压输入端输入的第二初始化信号的电位，与发光时段所述驱动晶体管的栅极的电位之间的差值小于阈值。
可选的，当所述第一复位子电路包括第一复位控制子电路、第二复位控制子电路和第三复位控制子电路时，
在所述复位时段，在所述复位控制端的控制下，所述第一复位控制子电路控制导通所述驱动晶体管的栅极与所述公共节点之间的连接，同时所述第二复位控制子电路控制导通所述公共节点与所述第一初始化电压输入端之间的连接；在所述第一控制端的控制下，所述第三复位控制子电路控制断开所述公共节点与所述第二初始化电压输入端之间的连接；
在写入补偿时段，在复位控制端的控制下，所述第一复位控制子电路控制断开所述驱动晶体管的栅极与所述公共节点之间的连接，同时所述第二复位控制子电路控制断开所述公共节点与所述第一初始化电压输入端之间的连接；
在发光时段，在所述第一控制端的控制下，所述第三复位控制子电路控制导通所述第二初始化电压输入端与所述公共节点之间的连接。
可选的，所述像素驱动电路还包括发光控制子电路，所述驱动晶体管的第二极通过所述发光控制子电路与所述发光元件连接；所述发光控制子电路分别与所述第一控制端、所述驱动晶体管的第二极和所述发光元件连接；所述驱动方法还包括：
在所述复位时段和所述写入补偿时段，在所述第一控制端的控制下，所述发光控制子电路控制断开所述驱动晶体管的第二极与所述发光元件之间的连接，以使所述发光元件在所述复位时段和所述写入补偿时段不发光。
可选的，所述像素驱动电路还包括第二复位子电路，所述第二复位子电路分别与所述复位控制端、所述发光元件和第三初始化电压输入端连接；
在所述复位时段，在所述复位控制端的控制下，所述第二复位子电路控制导通所述第三初始化电压输入端与所述发光元件之间的连接。
可选的，所述第三初始化电压输入端输入的第三初始化信号的电位，与所述第一初始化电压输入端输入的第一初始化信号的电位相同。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的像素驱动电路的第一结构示意图；
图2为本公开实施例提供的像素驱动电路的第一电路示意图；
图3为本公开实施例提供的像素驱动电路的第二结构示意图；
图4为本公开实施例提供的像素驱动电路的第二电路示意图；
图5为本公开实施例提供的像素驱动电路的第三结构示意图；
图6为本公开实施例提供的像素驱动电路的第三电路示意图；
图7为本公开实施例提供的像素驱动电路的第四结构示意图；
图8为本公开实施例提供的像素驱动电路的第四电路示意图；
图9为本公开实施例提供的像素驱动电路的驱动时序图；
图10为本公开实施例提供的显示装置的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的像素驱动电路及其驱动方法、显示装置，下面结合说明书附图进行详细描述。
请参阅图1和图2，本公开实施例提供了一种像素驱动电路，用于驱动发光元件EL，所述像素驱动电路包括：
驱动子电路3，所述驱动子电路3包括驱动晶体管DT，所述驱动晶体管DT的第二极与所述发光元件EL连接；
存储子电路4，所述存储子电路4的第一端与所述驱动晶体管DT的栅极(即节点G)连接，所述存储子电路4的第二端与电源信号输入端ELVDD连接；
电源控制子电路1，分别与第一控制端EM、所述电源信号输入端ELVDD 和所述驱动晶体管DT的第一极(即节点S)连接；
数据写入子电路2，分别与相应行栅线GT、相应列数据线DA和所述驱动晶体管DT的第一极连接；
补偿子电路6，分别与相应行栅线GT、所述驱动晶体管DT的栅极和所述驱动晶体管DT的第二极连接；
第一复位子电路51，分别与复位控制端RE、所述第一控制端EM、所述驱动晶体管DT的栅极、公共节点N1、第一初始化电压输入端Vinit1和第二初始化电压输入端Vinit2连接；用于在所述复位控制端RE的控制下，控制导通或断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，以及控制导通或断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接；还用于在所述第一控制端EM的控制下，控制导通或断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接；
所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位，与发光时段所述驱动晶体管DT的栅极的电位之间的差值小于阈值。
具体的，所述像素驱动电路应用于显示装置，显示装置包括基底，阵列分布在所述基底上的多个像素驱动电路，以及位于所述多个像素驱动电路背向所述基底的一侧，且与所述多个像素驱动电路一一对应的发光元件EL。示例性的，所述发光元件EL具体包括沿远离所述基底的方向上依次层叠设置的阳极、发光功能层和阴极，发光元件EL的阳极能够与对应的所述像素驱动电路连接，接收对应的所述像素驱动电路提供的驱动信号，所述阴极能够与显示装置中的负电源信号线ELVSS连接，接收所述负电源信号线提供的负电源信号，发光功能层用于在所述阳极和所述阴极的共同作用下发光。
需要说明，所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位与发光时段所述驱动晶体管DT的栅极的电位大致相同，示例性的，所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位，与发光时段所述驱动晶体管DT的栅极的电位之间的差值小于阈值。值得注意，所述阈值可根据实际需要设置，示例性的，所述阈值的设置应满足的条件为：在一帧显示时间内，发光元件EL上的电流变化量小于7％。
请参阅图1、图2和图9所示，上述像素驱动电路在一个驱动周期的工 作过程为：
在复位时段P1，第一初始化电压输入端Vinit1输入的第一初始化信号的电位为V1，所述复位控制端RE输入的复位信号处于有效电平，使得在复位控制端RE的控制下，第一复位子电路51控制导通所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并导通所述公共节点N1与所述驱动晶体管DT的栅极之间的连接，使所述驱动晶体管DT的栅极的电位变为V1，实现对驱动晶体管DT的栅极复位，从而使得前一帧保持在驱动晶体管DT上的栅源电压Vgs被初始化；在该复位时段P1，所述第一控制端EM输入的第一控制信号处于非有效电平，使得在所述第一控制端EM的控制下，第一复位子电路51还控制断开第二初始化电压输入端Vinit2与所述公共节点N1之间的连接。
在写入补偿时段P2，所述复位控制端RE输入的复位信号处于非有效电平，使得在复位控制端RE的控制下，第一复位子电路51控制断开所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并控制断开所述公共节点N1与所述驱动晶体管DT的栅极之间的连接；在所述第一控制端EM的控制下，第一复位子电路51继续控制断开第二初始化电压输入端Vinit2与所述公共节点N1之间的连接；相应列数据线DA输入数据电压Vdata，相应行栅线GT输入的扫描信号处于有效电平，使得在相应行栅线GT的控制下，数据写入子电路2控制导通相应列数据线DA和所述驱动晶体管DT的第一极之间的连接，使驱动晶体管DT的第一极的电位变为Vdata；同时在相应行栅线GT的控制下，补偿子电路6控制导通所述驱动晶体管DT的栅极和所述驱动晶体管DT的第二极之间的连接，使所述驱动晶体管DT形成为二极管结构，因此通过数据写入子电路2、驱动晶体管DT和补偿子电路6配合工作，实现对驱动晶体管DT的阈值电压补偿，当补偿的时间足够长时，可控制驱动晶体管DT的栅极电位最终达到Vdata+Vth，Vth为驱动晶体管DT的阈值电压。
在发光时段P3，所述电源信号输入端ELVDD输入电源电压Vdd，所述第一控制端EM输入的第一控制信号处于有效电平，使得在所述第一控制端EM的控制下，所述电源控制子电路1控制导通所述电源信号输入端ELVDD 与所述驱动晶体管DT的第一极之间的连接，使所述驱动晶体管DT的第一极的电位由Vdata变为Vdd；同时第二初始化电压输入端Vinit2输入的第二初始化信号的电位为V2，在所述第一控制端EM的控制下，第一复位子电路51控制导通所述第二初始化电压输入端Vinit2与所述公共节点N1之间的连接，使得所述公共节点N1的电位变为V2；所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位V2，与发光时段P3所述驱动晶体管DT的栅极的电位之间的差值小于阈值。
在所述发光时段P3，驱动晶体管DT的栅极和驱动晶体管DT的第一极之间的电压Vgs为：
Vgs＝Vdata+Vth-Vdd，        公式(1)
驱动晶体管DT导通并工作在饱和状态时产生的驱动电流I为：
I＝k(Vgs-Vth) 2      公式(2)
将公式(1)代入公式(2)得到：
I＝k(Vdata+Vth-Vdd-Vth) 2＝k(Vdata-Vdd) 2      公式(3)
公式(3)中，k为常数。
由公式(3)可知驱动电流I只与电源电压Vdd和数据电压Vdata有关，而与驱动晶体管DT的阈值电压Vth没有关系；因此，即使向阈值电压Vth不同的多个驱动晶体管DT中输入相同的数据电压时，阈值电压Vth不同的驱动晶体管DT在饱和状态时所产生的驱动电流相同，从而使阈值电压Vth不同的驱动晶体管DT驱动对应的发光元件EL发光时，发光元件EL的发光亮度相同，避免了采用阈值电压Vth不同的驱动晶体管DT驱动发光元件EL发光时，由于阈值电压漂移而导致的发光元件EL发光不均匀的问题。
根据上述像素驱动电路的具体结构和工作过程可知，本公开实施例提供的像素驱动电路中，通过设置所述第一复位子电路51，使得在复位时段P1，所述第一复位子电路51能够导通所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，使所述驱动晶体管DT的栅极的电位变为由第一初始化电压输入端Vinit1输入的较低的电位V1，实现对驱动晶体管DT的栅极复位；同时在所述复位时段P1，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接。 在发光时段P3，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，并导通所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接，使得所述公共节点N1的电位与所述驱动晶体管DT的栅极的电位大致相同。
因此，本公开实施例提供的像素驱动电路，有效降低了在所述发光时段P3所述驱动晶体管DT的栅极通过所述第一复位子电路51漏电的电流，使得在低频驱动的情况下，也能够很好的保持所述驱动晶体管DT的栅极的电位，从而很好的改善了显示器件在显示时容易出现闪烁的问题。因此，本公开实施例提供的像素驱动电路在低频驱动的情况下，不仅保证了显示器件的显示质量还降低了显示器件的功耗。
另外，本公开实施例提供的像素驱动电路，在低灰阶显示情况和高灰阶显示情况下，均能够很好的保持所述驱动晶体管DT的栅极在发光时段的电位，改善显示器件在显示时容易出现闪烁的问题。
需要说明，图9中示出了两行像素驱动电路对应的驱动时序，其中EM2代表第二行像素驱动电路对应连接的第一控制端，RE2代第二行像素驱动电路对应连接的复位控制端，GT2代表第二行像素驱动电路对应连接的栅线，N1'代表第二行像素驱动电路中的公共节点。P1'代表第二行像素驱动电路对应的复位时段，P2'代表第二行像素驱动电路对应的写入补偿时段，P3'代表第二行像素驱动电路对应的发光时段。
如图3和图4所示，在一些实施例中，所述第一复位子电路51包括：
第一复位控制子电路511，分别与所述复位控制端RE、所述驱动晶体管DT的栅极和所述公共节点N1连接；用于在所述复位控制端RE的控制下，控制导通或断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接；
第二复位控制子电路512，分别与所述复位控制端RE、所述公共节点N1和所述第一初始化电压输入端Vinit1连接；用于在所述复位控制端RE的控制下，控制导通或断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接；
第三复位控制子电路513，分别与所述第一控制端EM、所述公共节点N1和所述第二初始化电压输入端Vinit2连接；用于在所述第一控制端EM的 控制下，控制导通或断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接。
具体的，所述第一复位子电路51的具体结构多种多样，示例性的，所述第一复位子电路51包括所述第一复位控制子电路511、所述第二复位控制子电路512和第三复位控制子电路513，所述第一复位控制子电路511连接在所述驱动晶体管DT的栅极与所述公共节点N1之间，所述第二复位控制子电路512连接在所述公共节点N1与所述第一初始化电压输入端Vinit1之间，所述第三复位控制子电路513连接在所述公共节点N1与所述第二初始化电压输入端Vinit2之间。
当所述第一复位子电路51采用上述结构时，所述第一复位子电路51的工作过程如下：
在复位时段P1，在所述复位控制端RE的控制下，所述第一复位控制子电路511控制导通所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512控制导通所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接，使所述驱动晶体管DT的栅极的电位变为V1，实现对驱动晶体管DT的栅极复位，从而使得前一帧保持在驱动晶体管DT上的栅源电压Vgs被初始化。同时在所述第一控制端EM的控制下，第三复位控制子电路513控制断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接。
在写入补偿时段P2，在所述复位控制端RE的控制下，所述第一复位控制子电路511控制断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512控制断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接。同时在所述第一控制端EM的控制下，第三复位控制子电路513继续控制断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接。
在发光时段P3，在所述复位控制端RE的控制下，所述第一复位控制子电路511继续控制断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512继续控制断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接。同时在所述第一控制端EM的控 制下，第三复位控制子电路513控制导通所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接，使得所述公共节点N1的电位变为与所述驱动晶体管DT的栅极电位大致相同的V2。
值得注意，所述驱动晶体管DT的栅极发生漏电的原因包括：在发光时段P3所述第一复位子电路51接入的初始化信号的电位较低，使得驱动晶体管DT的栅极电位与该初始化信号的电位之间产生较大的电位差，进而导致驱动晶体管DT的栅极通过所述第一复位子电路51向提供该初始化信号的初始化电压输入端漏电。
为了解决由上述原因导致的漏电问题，可以考虑将所述初始化电压输入端输入的初始化信号设置为交流信号，示例性的，在复位时段，设置所述初始化电压输入端输入的初始化信号的电位为在-1V至-3V之间的低电位；在发光时段，调节所述初始化电压输入端输入的初始化信号的电位为与所述驱动晶体管DT的栅极电位大致相同的高电位。
上述将所述初始化电压输入端输入的初始化信号设置为交流信号的方式虽然能够改善显示器件在显示时容易出现闪烁的问题，但是由于OLED驱动的架构为逐行发光，即所述初始化电压输入端输入的初始化信号的电位也需要逐行调节，这样就需要为每一行像素驱动电路对应的所述初始化电压输入端设置专门的GOA电路，即在显示器件中加入一列所述GOA电路，而一列所述GOA电路占用的空间较大，不利于显示器件的窄边框发展需求。
上述实施例提供的像素驱动电路中，由于所述第一初始化电压输入端Vinit1和所述第二初始化电压输入端Vinit2输入的均为直流信号，所述第一控制端EM除了能够控制所述第一复位子电路51，还能够同时控制所述电源控制子电路1，因此，第一复位子电路51和所述电源控制子电路1连接的第一控制端EM仅需要设置一个对应的GOA电路，同样的所述第一复位子电路51连接的所述复位控制端RE仅需要设置一个对应的GOA电路，因此，上述实施例提供的像素驱动电路采用现有的GOA方案即可实现在不同时段向所述公共节点N1提供具有合适电位的初始化信号，无需增加额外的专门用于实现初始化信号电位转换的GOA电路。
需要说明，现有的GOA方案中，包括一列EMGOA和一列GTGOA， EMGOA用于向其对应连接的第一控制端提供第一控制信号，GTGOA用于向其对应连接的栅线提供扫描信号。上述实施例提供的像素驱动电路采用现有的一列EMGOA和一列GTGOA即可，无需增加额外的专门用于实现初始化信号电位转换的GOA电路。
而且，上述实施例提供的像素驱动电路中，所述第一初始化电压输入端Vinit1和所述第二初始化电压输入端Vinit2输入的均为直流信号，避免了设置交流的初始化信号所导致的功耗增加。
在一些实施例中，所述第一复位控制子电路511包括第一晶体管T1，所述第一晶体管T1的栅极与所述复位控制端RE连接，所述第一晶体管T1的第一极与所述公共节点N1连接，所述第一晶体管T1的第二极与所述驱动晶体管DT的栅极连接；
所述第二复位控制子电路512包括第二晶体管T2，所述第二晶体管T2的栅极与所述复位控制端RE连接，所述第二晶体管T2的第一极与所述第一初始化电压输入端Vinit1连接，所述第二晶体管T2的第二极与所述公共节点N1连接；
所述第三复位控制子电路513包括第三晶体管T3，所述第三晶体管T3的栅极与所述第一控制端EM连接，所述第三晶体管T3的第一极与所述第二初始化电压输入端Vinit2连接，所述第三晶体管T3的第二极与所述公共节点N1连接。
具体地，所述第一复位控制子电路511、所述第二复位控制子电路512和所述第三复位控制子电路513的具体结构多种多样，示例性的，所述第一复位控制子电路511包括第一晶体管T1，所述第二复位控制子电路512包括第二晶体管T2，所述第三复位控制子电路513包括第三晶体管T3。
在所述复位时段P1，所述第一晶体管T1和所述第二晶体管T2导通，所述第三晶体管T3截止，从而控制导通所述第一初始化电压输入端Vinit1与所述驱动晶体管DT的栅极之间的连接，断开所述第二初始化电压输入端Vinit2与所述驱动晶体管DT的栅极之间的连接。
在所述数据写入时段，所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3均截止，从而控制断开所述驱动晶体管DT的栅极与所述第一 初始化电压输入端Vinit1之间的连接，同时控制断开所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接。
在所述发光时段P3，所述第一晶体管T1和所述第二晶体管T2截止，所述第三晶体管T3导通，从而控制断开所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，并控制导通所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接。
如图5和图6所示，在一些实施例中，所述像素驱动电路还包括：
第二复位子电路52，分别与所述复位控制端RE、所述发光元件EL和第三初始化电压输入端Vinit3连接；用于在所述复位控制端RE的控制下，控制导通或断开所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接。
具体地，在复位时段P1，在所述复位控制端RE提供的复位信号的控制下，第二复位子电路52控制导通所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接，利用所述第三初始化电压输入端Vinit3输入的第三初始化信号为所述发光元件EL的阳极复位。
在写入补偿时段P2和发光时段P3，在所述复位控制端RE提供的复位信号的控制下，第二复位子电路52控制断开所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接。
如图5和图6所示，在一些实施例中，所述第三初始化电压输入端Vinit3与所述第一初始化电压输入端Vinit1耦接。
具体地，所述第三初始化电压输入端Vinit3输入的第三初始化信号用于为所述发光元件EL的阳极进行复位，因此所述第三初始化信号的电位较低。所述第一初始化电压输入端Vinit1输入的第一初始化信号同样也是用于复位的信号，也具有较低的电位，因此，可以通过将所述第三初始化电压输入端Vinit3与所述第一初始化电压输入端Vinit1耦接，使得显示器件中仅需要设置一条能够同时为所述第一初始化电压输入端Vinit1和所述第三初始化电压输入端Vinit3，提供具有较低电位的初始化信号的初始化信号线，因此，上述实施例提供的像素驱动电路中，通过设置所述第三初始化电压输入端Vinit3与所述第一初始化电压输入端Vinit1耦接，有效减少了显示器件中初始化信 号线的设置数量，从而更有利于降低所述显示器件的布局难度。
如图5和图6所示，在一些实施例中，所述第二复位子电路52包括第四晶体管T4，所述第四晶体管T4的栅极与所述复位控制端RE连接，所述第四晶体管T4的第一极与所述第三初始化电压输入端Vinit3连接，所述第四晶体管T4的第二极与所述发光元件EL连接。
具体的，所述第二复位子电路52的具体结构多种多样，示例性的，所述第二复位子电路52包括所述第四晶体管T4。
在复位时段P1，在所述复位控制端RE的控制下，所述第四晶体管T4导通，从而导通所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接，实现对所述发光元件EL的阳极的复位。
在所述写入补偿时段P2和所述发光时段P3，在所述复位控制端RE的控制下，所述第四晶体管T4截止，从而断开所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接。
如图7和图8所示，在一些实施例中，所述像素驱动电路还包括发光控制子电路8，所述驱动晶体管DT的第二极通过所述发光控制子电路8与所述发光元件EL连接；
所述发光控制子电路8分别与所述第一控制端EM、所述驱动晶体管DT的第二极和所述发光元件EL连接，用于：在所述第一控制端EM的控制下，控制导通或断开所述驱动晶体管DT的第二极与所述发光元件EL之间的连接。
具体地，在发光时段P3，在第一控制端EM的控制下，发光控制子电路8控制导通驱动晶体管DT的第二极与发光元件EL的阳极之间的连接。
在复位时段P1和写入补偿时段P2，在第一控制端EM的控制下，发光控制子电路8控制断开驱动晶体管DT的第二极与发光元件EL的阳极之间的连接，从而很好的避免了在复位时段P1和写入补偿时段P2所述发光元件EL异常发光。
如图7和图8所示，在一些实施例中，所述发光控制子电路8包括第五晶体管T5，所述第五晶体管T5的栅极与所述第一控制端EM连接，所述第五晶体管T5的第一极与所述驱动晶体管DT的第二极连接，所述第五晶体管 T5的第二极与所述发光元件EL连接。
具体的，所述发光控制子电路8的具体结构多种多样，示例性的，所述发光控制子电路8包括所述第五晶体管T5。
在发光时段P3，在第一控制端EM的控制下，所述第五晶体管T5导通，从而控制导通驱动晶体管DT的第二极与发光元件EL的阳极之间的连接。
在复位时段P1和写入补偿时段P2，在第一控制端EM的控制下，所述第五晶体管T5截止，从而控制断开驱动晶体管DT的第二极与发光元件EL的阳极之间的连接，从而很好的避免了在复位时段P1和写入补偿时段P2所述发光元件EL异常发光。
如图7和图8所示，在一些实施例中，可设置所述电源控制子电路1包括第六晶体管T6，所述第六晶体管T6的栅极与所述第一控制端EM连接，所述第六晶体管T6的第一极与所述电源信号输入端连接，所述第六晶体管T6的第二极与所述驱动晶体管DT的第一极连接；
所述数据写入子电路2包括第七晶体管T7，所述第七晶体管T7的栅极与相应行栅线GT连接，所述第七晶体管T7的第一极与相应列数据线DA连接，所述第七晶体管T7的第二极与所述驱动晶体管DT的第一极连接；
所述补偿子电路6包括第八晶体管T8，所述第八晶体管T8的栅极与相应行栅线GT连接，所述第八晶体管T8的第一极与所述驱动晶体管DT的第二极连接，所述第八晶体管T8的第二极与所述驱动晶体管DT的栅极连接。
所述存储子电路4包括第一电容C1。
具体地，在复位时段P1，在所述第一控制端EM的控制下，所述第六晶体管T6截止，从而控制断开所述电源信号输入端ELVDD与所述驱动晶体管DT的第一极之间的连接；在相应行栅线GT的控制下，所述第七晶体管T7截止，从而控制断开所述相应列数据线DA与所述驱动晶体管DT的第一极之间的连接；在相应行栅线GT的控制下，所述第八晶体管T8截止，从而控制断开所述驱动晶体管DT的第二极与所述驱动晶体管DT的栅极之间的连接。
在写入补偿时段P2，在所述第一控制端EM的控制下，所述第六晶体管T6截止，继续控制断开所述电源信号输入端ELVDD与所述驱动晶体管DT 的第一极之间的连接；在相应行栅线GT的控制下，所述第七晶体管T7导通，从而控制导通所述相应列数据线DA与所述驱动晶体管DT的第一极之间的连接；在相应行栅线GT的控制下，所述第八晶体管T8导通，从而控制导通所述驱动晶体管DT的第二极与所述驱动晶体管DT的栅极之间的连接。
在发光时段P3，在所述第一控制端EM的控制下，所述第六晶体管T6导通，从而控制导通所述电源信号输入端ELVDD与所述驱动晶体管DT的第一极之间的连接；在相应行栅线GT的控制下，所述第七晶体管T7截止，从而控制断开所述相应列数据线DA与所述驱动晶体管DT的第一极之间的连接；在相应行栅线GT的控制下，所述第八晶体管T8截止，从而控制断开所述驱动晶体管DT的第二极与所述驱动晶体管DT的栅极之间的连接。
上述实施例提供的像素驱动电路中，采用的各晶体管均为PMOS晶体管，因此，所述像素驱动电路中包括的各晶体管均能够采用相同的工艺同时制备，避免了制作像素驱动电路时，需要通过复杂工艺同时制作PMOS晶体管和氧化物晶体管，导致的制作流程复杂、制作成本增加的问题。
本公开实施例还提供了一种显示装置，包括上述实施例提供的像素驱动电路。
上述像素驱动电路中，驱动电流I只与电源电压Vdd和数据电压Vdata有关，而与驱动晶体管DT的阈值电压Vth没有关系；因此，即使向阈值电压Vth不同的多个驱动晶体管DT中输入相同的数据电压时，阈值电压Vth不同的驱动晶体管DT在饱和状态时所产生的驱动电流相同，从而使阈值电压Vth不同的驱动晶体管DT驱动对应的发光元件EL发光时，发光元件EL的发光亮度相同，避免了采用阈值电压Vth不同的驱动晶体管DT驱动发光元件EL发光时，由于阈值电压漂移而导致的发光元件EL发光不均匀的问题。
上述实施例提供的像素驱动电路中，通过设置所述第一复位子电路51，使得在复位时段P1，所述第一复位子电路51能够导通所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，使所述驱动晶体管DT的栅极的电位变为由第一初始化电压输入端Vinit1输入的较低的电位V1，实现对驱动晶体管DT的栅极复位；同时在所述复位时段P1，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第二初始化电压输入端 Vinit2之间的连接。在发光时段P3，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，并导通所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接，使得所述公共节点N1的电位与所述驱动晶体管DT的栅极的电位大致相同。因此，上述实施例提供的像素驱动电路，有效降低了在所述发光时段P3所述驱动晶体管DT的栅极通过所述第一复位子电路51漏电的电流，使得在低频驱动的情况下，也能够很好的保持所述驱动晶体管DT的栅极的电位，从而很好的改善了显示器件在显示时容易出现闪烁的问题。因此，本公开实施例提供的像素驱动电路在低频驱动的情况下，不仅保证了显示器件的显示质量还降低了显示器件的功耗。
本公开实施例提供的显示装置在包括上述实施例提供的像素驱动电路时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
如图10所示，在一些实施例中，所述显示装置包括显示区域AA和围绕所述显示区域AA的周边区域，所述显示装置还包括位于所述周边区域的第一初始化信号线Init1和第二初始化信号线Init2，所述第一初始化信号线Init1和所述第二初始化信号线Init2均沿第一方向延伸；
所述显示装置包括阵列分布在所述显示区域AA的多个所述像素驱动电路，沿第二方向位于同一行的各像素驱动电路中，第一复位子电路51连接的第一初始化电压输入端Vinit1均通过同一条第一连接线91与所述第一初始化信号线Init1连接；
沿第二方向位于同一行的各像素驱动电路中，第一复位子电路51连接的第二初始化电压输入端Vinit2均通过同一条第二连接线92与所述第二初始化信号线Init2连接，所述第一方向与所述第二方向相交。
具体的，所述第一初始化信号线Init1和第二初始化信号线Init2的具体布局方式多种多样，示例性的，所述第一初始化信号线Init1和第二初始化信号线Init2均设置在周边区域，且沿第二方向相对的两侧均设置有所述第一初始化信号线Init1和第二初始化信号线Init2。
示例性的，所述第一方向与所述数据线的延伸方向相同，所述第二方向与所述栅线的延伸方向相同。
示例性的，所述第一初始化信号线Init1和第二初始化信号线Init2均采用相同的材料，同层制作，所述第一初始化信号线Init1和第二初始化信号线Init2沿第二方向依次排列。
示例性的，所述第一初始化信号线Init1和第二初始化信号线Init2异层设置，所述第一初始化信号线Init1在所述显示装置的基底上的正投影，与所述第二初始化信号线Init2在所述显示装置的基底上的正投影交叠。
示例性的，所述第一连接线91和所述第二连接线92异层设置。
按照上述方式在所述周边区域布局所述第一初始化信号线Init1和所述第二初始化信号线Init2时，更有利于缩小所述第一初始化信号线Init1和所述第二初始化信号线Init2占用的布局空间，在保证所述第一初始化信号线Init1和所述第二初始化信号线Init2为显示区域AA中的各像素驱动电路提供对应的初始化信号的情况下，更有利于显示装置的窄边框发展。
需要说明，图中还示出了第一扇出区F1，第二扇出区F2，弯折区BA，静电释放单元ESD，第一测试电路CT1、第二测试电路CT2，测试电路接触区ET，覆晶薄膜COF和多路调制器MUX。
本公开实施例还提供了一种像素驱动电路的驱动方法，应用于上述实施例提供的像素驱动电路，所述驱动方法包括：在每一工作周期，
在复位时段P1，第一初始化电压输入端Vinit1输入第一初始化电压Vinit1，在复位控制端RE的控制下，第一复位子电路51控制导通所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并导通所述公共节点N1与驱动子电路中驱动晶体管DT的栅极之间的连接；在所述第一控制端EM的控制下，第一复位子电路51控制断开第二初始化电压输入端Vinit2与所述公共节点N1之间的连接；
在写入补偿时段P2，在复位控制端RE的控制下，第一复位子电路51控制断开所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并控制断开所述公共节点N1与所述驱动晶体管DT的栅极之间的连接；相应列数据线DA输入数据电压Vdata，在相应行栅线GT的控制下，数据写入子 电路2控制导通相应列数据线DA和所述驱动晶体管DT的第一极之间的连接，补偿子电路6控制导通所述驱动晶体管DT的栅极和所述驱动晶体管DT的第二极之间的连接，使所述驱动晶体管DT形成为二极管结构，使所述驱动晶体管DT的栅极的电位变为Vdata+Vth，Vth为驱动晶体管DT的阈值电压；
在发光时段P3，所述电源信号输入端ELVDD输入电源电压Vdd，在所述第一控制端EM的控制下，所述电源控制子电路1控制导通所述电源信号输入端ELVDD与所述驱动晶体管DT的第一极之间的连接；在所述第一控制端EM的控制下，第一复位子电路51控制导通所述第二初始化电压输入端Vinit2与所述公共节点N1之间的连接；所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位，与发光时段P3所述驱动晶体管DT的栅极的电位之间的差值小于阈值。
采用上述驱动方法驱动像素驱动电路时，在一个驱动周期的工作过程为：
在复位时段P1，第一初始化电压输入端Vinit1输入的第一初始化信号的电位为V1，所述复位控制端RE输入的复位信号处于有效电平，使得在复位控制端RE的控制下，第一复位子电路51控制导通所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并导通所述公共节点N1与所述驱动晶体管DT的栅极之间的连接，使所述驱动晶体管DT的栅极的电位变为V1，实现对驱动晶体管DT的栅极复位，从而使得前一帧保持在驱动晶体管DT上的栅源电压Vgs被初始化；在该复位时段P1，所述第一控制端EM输入的第一控制信号处于非有效电平，使得在所述第一控制端EM的控制下，第一复位子电路51还控制断开第二初始化电压输入端Vinit2与所述公共节点N1之间的连接。
在写入补偿时段P2，所述复位控制端RE输入的复位信号处于非有效电平，使得在复位控制端RE的控制下，第一复位子电路51控制断开所述第一初始化电压输入端Vinit1与所述公共节点N1之间的连接，并控制断开所述公共节点N1与所述驱动晶体管DT的栅极之间的连接；在所述第一控制端EM的控制下，第一复位子电路51继续控制断开第二初始化电压输入端Vinit2与所述公共节点N1之间的连接；相应列数据线DA输入数据电压Vdata，相 应行栅线GT输入的扫描信号处于有效电平，使得在相应行栅线GT的控制下，数据写入子电路2控制导通相应列数据线DA和所述驱动晶体管DT的第一极之间的连接，使驱动晶体管DT的第一极的电位变为Vdata；同时在相应行栅线GT的控制下，补偿子电路6控制导通所述驱动晶体管DT的栅极和所述驱动晶体管DT的第二极之间的连接，使所述驱动晶体管DT形成为二极管结构，因此通过数据写入子电路2、驱动晶体管DT和补偿子电路6配合工作，实现对驱动晶体管DT的阈值电压补偿，当补偿的时间足够长时，可控制驱动晶体管DT的栅极电位最终达到Vdata+Vth，Vth为驱动晶体管DT的阈值电压。
在发光时段P3，所述电源信号输入端ELVDD输入电源电压Vdd，所述第一控制端EM输入的第一控制信号处于有效电平，使得在所述第一控制端EM的控制下，所述电源控制子电路1控制导通所述电源信号输入端ELVDD与所述驱动晶体管DT的第一极之间的连接，使所述驱动晶体管DT的第一极的电位由Vdata变为Vdd；同时第二初始化电压输入端Vinit2输入的第二初始化信号的电位为V2，在所述第一控制端EM的控制下，第一复位子电路51控制导通所述第二初始化电压输入端Vinit2与所述公共节点N1之间的连接，使得所述公共节点N1的电位变为V2；所述第二初始化电压输入端Vinit2输入的第二初始化信号的电位V2，与发光时段P3所述驱动晶体管DT的栅极的电位之间的差值小于阈值。
采用本公开实施例提供的驱动方法驱动上述实施例提供的像素驱动电路时，驱动电流I只与电源电压Vdd和数据电压Vdata有关，而与驱动晶体管DT的阈值电压Vth没有关系；因此，即使向阈值电压Vth不同的多个驱动晶体管DT中输入相同的数据电压时，阈值电压Vth不同的驱动晶体管DT在饱和状态时所产生的驱动电流相同，从而使阈值电压Vth不同的驱动晶体管DT驱动对应的发光元件EL发光时，发光元件EL的发光亮度相同，避免了采用阈值电压Vth不同的驱动晶体管DT驱动发光元件EL发光时，由于阈值电压漂移而导致的发光元件EL发光不均匀的问题。
采用本公开实施例提供的驱动方法驱动上述像素驱动电路时，在复位时段P1，所述第一复位子电路51能够导通所述驱动晶体管DT的栅极与所述第 一初始化电压输入端Vinit1之间的连接，使所述驱动晶体管DT的栅极的电位变为由第一初始化电压输入端Vinit1输入的较低的电位V1，实现对驱动晶体管DT的栅极复位；同时在所述复位时段P1，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接。在发光时段P3，所述第一复位子电路51能够断开所述驱动晶体管DT的栅极与所述第一初始化电压输入端Vinit1之间的连接，并导通所述驱动晶体管DT的栅极与所述第二初始化电压输入端Vinit2之间的连接，使得所述公共节点N1的电位与所述驱动晶体管DT的栅极的电位大致相同。
因此，采用本公开实施例提供的驱动方法驱动上述像素驱动电路，有效降低了在所述发光时段P3所述驱动晶体管DT的栅极通过所述第一复位子电路51漏电的电流，使得在低频驱动的情况下，也能够很好的保持所述驱动晶体管DT的栅极的电位，从而很好的改善了显示器件在显示时容易出现闪烁的问题。因此，本公开实施例提供的像素驱动电路在低频驱动的情况下，不仅保证了显示器件的显示质量还降低了显示器件的功耗。
在一些实施例中，当所述第一复位子电路包括第一复位控制子电路511、第二复位控制子电路512和第三复位控制子电路513时，
在所述复位时段P1，在所述复位控制端RE的控制下，所述第一复位控制子电路511控制导通所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，同时所述第二复位控制子电路512控制导通所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接；在所述第一控制端EM的控制下，所述第三复位控制子电路513控制断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接；
在写入补偿时段P2，在复位控制端RE的控制下，所述第一复位控制子电路511控制断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，同时所述第二复位控制子电路512控制断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接；
在发光时段P3，在所述第一控制端EM的控制下，所述第三复位控制子电路513控制导通所述第二初始化电压输入端Vinit2与所述公共节点N1之间的连接。
具体地，在复位时段P1，在所述复位控制端RE的控制下，所述第一复位控制子电路511控制导通所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512控制导通所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接，使所述驱动晶体管DT的栅极的电位变为V1，实现对驱动晶体管DT的栅极复位，从而使得前一帧保持在驱动晶体管DT上的栅源电压Vgs被初始化。同时在所述第一控制端EM的控制下，第三复位控制子电路513控制断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接。
在写入补偿时段P2，在所述复位控制端RE的控制下，所述第一复位控制子电路511控制断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512控制断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接。同时在所述第一控制端EM的控制下，第三复位控制子电路513继续控制断开所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接。
在发光时段P3，在所述复位控制端RE的控制下，所述第一复位控制子电路511继续控制断开所述驱动晶体管DT的栅极与所述公共节点N1之间的连接，所述第二复位控制子电路512继续控制断开所述公共节点N1与所述第一初始化电压输入端Vinit1之间的连接。同时在所述第一控制端EM的控制下，第三复位控制子电路513控制导通所述公共节点N1与所述第二初始化电压输入端Vinit2之间的连接，使得所述公共节点N1的电位变为与所述驱动晶体管DT的栅极电位大致相同的V2。
采用上述实施例提供的驱动方法驱动像素驱动电路时，由于所述第一初始化电压输入端Vinit1和所述第二初始化电压输入端Vinit2输入的均为直流信号，所述第一控制端EM除了能够控制所述第一复位子电路51，还能够同时控制所述电源控制子电路1，因此，第一复位子电路51和所述电源控制子电路1连接的第一控制端EM仅需要设置一个对应的GOA电路，同样的所述第一复位子电路51连接的所述复位控制端RE仅需要设置一个对应的GOA电路，因此，采用上述实施例提供的驱动方法驱动像素驱动电路时，采用现有的GOA方案即可实现在不同时段向所述公共节点N1提供具有合适电位的 初始化信号，无需增加额外的专门用于实现初始化信号电位转换的GOA电路。
而且，采用上述实施例提供的驱动方法驱动像素驱动电路时，所述第一初始化电压输入端Vinit1和所述第二初始化电压输入端Vinit2输入的均为直流信号，避免了设置交流的初始化信号所导致的功耗增加。
在一些实施例中，所述像素驱动电路还包括发光控制子电路8，所述驱动晶体管DT的第二极通过所述发光控制子电路8与所述发光元件EL连接；所述发光控制子电路8分别与所述第一控制端EM、所述驱动晶体管DT的第二极和所述发光元件EL连接；所述驱动方法还包括：在所述复位时段P1和所述写入补偿时段P2，在所述第一控制端EM的控制下，所述发光控制子电路8控制断开所述驱动晶体管DT的第二极与所述发光元件EL之间的连接，以使所述发光元件EL在所述复位时段P1和所述写入补偿时段P2不发光。
具体的，在发光时段P3，在第一控制端EM的控制下，发光控制子电路8控制导通驱动晶体管DT的第二极与发光元件EL的阳极之间的连接。
在复位时段P1和写入补偿时段P2，在第一控制端EM的控制下，发光控制子电路8控制断开驱动晶体管DT的第二极与发光元件EL的阳极之间的连接，从而很好的避免了在复位时段P1和写入补偿时段P2所述发光元件EL异常发光。
在一些实施例中，所述像素驱动电路还包括第二复位子电路52，所述第二复位子电路52分别与所述复位控制端RE、所述发光元件EL和第三初始化电压输入端Vinit3连接；在所述复位时段P1，在所述复位控制端RE的控制下，所述第二复位子电路52控制导通所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接。
具体地，在复位时段P1，在所述复位控制端RE提供的复位信号的控制下，第二复位子电路52控制导通所述第三初始化电压输入端Vinit3与所述发光元件EL之间的连接，利用所述第三初始化电压输入端Vinit3输入的第三初始化信号为所述发光元件EL的阳极复位。
在写入补偿时段P2和发光时段P3，在所述复位控制端RE提供的复位信号的控制下，第二复位子电路52控制断开所述第三初始化电压输入端Vinit3 与所述发光元件EL之间的连接。
在一些实施中，可设置所述第三初始化电压输入端Vinit3输入的第三初始化信号的电位，与所述第一初始化电压输入端Vinit1输入的第一初始化信号的电位相同。
具体地，所述第三初始化电压输入端Vinit3输入的第三初始化信号用于为所述发光元件EL的阳极进行复位，因此所述第三初始化信号的电位较低。所述第一初始化电压输入端Vinit1输入的第一初始化信号同样也是用于复位的信号，也具有较低的电位，因此，可以通过将所述第三初始化电压输入端Vinit3与所述第一初始化电压输入端Vinit1耦接，使得显示器件中仅需要设置一条能够同时为所述第一初始化电压输入端Vinit1和所述第三初始化电压输入端Vinit3，提供相同的具有较低电位的初始化信号的初始化信号线，因此，采用上述实施例提供的驱动方法驱动像素驱动电路时，能够有效减少显示器件中初始化信号线的设置数量，从而更有利于降低所述显示器件的布局难度。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在 中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种像素驱动电路，用于驱动发光元件，包括：
    驱动子电路，所述驱动子电路包括驱动晶体管，所述驱动晶体管的第二极与所述发光元件连接；
    存储子电路，所述存储子电路的第一端与所述驱动晶体管的栅极连接，所述存储子电路的第二端与电源信号输入端连接；
    电源控制子电路，分别与第一控制端、所述电源信号输入端和所述驱动晶体管的第一极连接；
    数据写入子电路，分别与相应行栅线、相应列数据线和所述驱动晶体管的第一极连接；
    补偿子电路，分别与相应行栅线、所述驱动晶体管的栅极和所述驱动晶体管的第二极连接；
    第一复位子电路，分别与复位控制端、所述第一控制端、所述驱动晶体管的栅极、公共节点、第一初始化电压输入端和第二初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述驱动晶体管的栅极与所述公共节点之间的连接，以及控制导通或断开所述公共节点与所述第一初始化电压输入端之间的连接；还用于在所述第一控制端的控制下，控制导通或断开所述公共节点与所述第二初始化电压输入端之间的连接；
    所述第二初始化电压输入端输入的第二初始化信号的电位，与发光时段所述驱动晶体管的栅极的电位之间的差值小于阈值。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一复位子电路包括：
    第一复位控制子电路，分别与所述复位控制端、所述驱动晶体管的栅极和所述公共节点连接；用于在所述复位控制端的控制下，控制导通或断开所述驱动晶体管的栅极与所述公共节点之间的连接；
    第二复位控制子电路，分别与所述复位控制端、所述公共节点和所述第一初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述公共节点与所述第一初始化电压输入端之间的连接；
    第三复位控制子电路，分别与所述第一控制端、所述公共节点和所述第二初始化电压输入端连接；用于在所述第一控制端的控制下，控制导通或断开所述公共节点与所述第二初始化电压输入端之间的连接。
  3. 根据权利要求2所述的像素驱动电路，其中，
    所述第一复位控制子电路包括第一晶体管，所述第一晶体管的栅极与所述复位控制端连接，所述第一晶体管的第一极与所述公共节点连接，所述第一晶体管的第二极与所述驱动晶体管的栅极连接；
    所述第二复位控制子电路包括第二晶体管，所述第二晶体管的栅极与所述复位控制端连接，所述第二晶体管的第一极与所述第一初始化电压输入端连接，所述第二晶体管的第二极与所述公共节点连接；
    所述第三复位控制子电路包括第三晶体管，所述第三晶体管的栅极与所述第一控制端连接，所述第三晶体管的第一极与所述第二初始化电压输入端连接，所述第三晶体管的第二极与所述公共节点连接。
  4. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二复位子电路，分别与所述复位控制端、所述发光元件和第三初始化电压输入端连接；用于在所述复位控制端的控制下，控制导通或断开所述第三初始化电压输入端与所述发光元件之间的连接。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第三初始化电压输入端与所述第一初始化电压输入端耦接。
  6. 根据权利要求4所述的像素驱动电路，其中，所述第二复位子电路包括第四晶体管，所述第四晶体管的栅极与所述复位控制端连接，所述第四晶体管的第一极与所述第三初始化电压输入端连接，所述第四晶体管的第二极与所述发光元件连接。
  7. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括发光控制子电路，所述驱动晶体管的第二极通过所述发光控制子电路与所述发光元件连接；
    所述发光控制子电路分别与所述第一控制端、所述驱动晶体管的第二极和所述发光元件连接，用于：在所述第一控制端的控制下，控制导通或断开 所述驱动晶体管的第二极与所述发光元件之间的连接。
  8. 根据权利要求7所述的像素驱动电路，其中，所述发光控制子电路包括第五晶体管，所述第五晶体管的栅极与所述第一控制端连接，所述第五晶体管的第一极与所述驱动晶体管的第二极连接，所述第五晶体管的第二极与所述发光元件连接。
  9. 根据权利要求1所述的像素驱动电路，其中，
    所述电源控制子电路包括第六晶体管，所述第六晶体管的栅极与所述第一控制端连接，所述第六晶体管的第一极与所述电源信号输入端连接，所述第六晶体管的第二极与所述驱动晶体管的第一极连接；
    所述数据写入子电路包括第七晶体管，所述第七晶体管的栅极与相应行栅线连接，所述第七晶体管的第一极与相应列数据线连接，所述第七晶体管的第二极与所述驱动晶体管的第一极连接；
    所述补偿子电路包括第八晶体管，所述第八晶体管的栅极与相应行栅线连接，所述第八晶体管的第一极与所述驱动晶体管的第二极连接，所述第八晶体管的第二极与所述驱动晶体管的栅极连接。
  10. 一种显示装置，包括权利要求1～9中任一项所述的像素驱动电路。
  11. 根据权利要求10所述的显示装置，其中，所述显示装置包括显示区域和围绕所述显示区域的周边区域，所述显示装置还包括位于所述周边区域的第一初始化信号线和第二初始化信号线，所述第一初始化信号线和所述第二初始化信号线均沿第一方向延伸；
    所述显示装置包括阵列分布在所述显示区域的多个所述像素驱动电路，沿第二方向位于同一行的各像素驱动电路中，第一复位子电路连接的第一初始化电压输入端均通过同一条第一连接线与所述第一初始化信号线连接；
    沿第二方向位于同一行的各像素驱动电路中，第一复位子电路连接的第二初始化电压输入端均通过同一条第二连接线与所述第二初始化信号线连接，所述第一方向与所述第二方向相交。
  12. 一种像素驱动电路的驱动方法，应用于如权利要求1～9中任一项所述的像素驱动电路，所述驱动方法包括：在每一工作周期，
    在复位时段，第一初始化电压输入端输入第一初始化电压Vinit1，在复 位控制端的控制下，第一复位子电路控制导通所述第一初始化电压输入端与所述公共节点之间的连接，并导通所述公共节点与驱动子电路中驱动晶体管的栅极之间的连接；在所述第一控制端的控制下，第一复位子电路控制断开第二初始化电压输入端与所述公共节点之间的连接；
    在写入补偿时段，在复位控制端的控制下，第一复位子电路控制断开所述第一初始化电压输入端与所述公共节点之间的连接，并控制断开所述公共节点与所述驱动晶体管的栅极之间的连接；相应列数据线输入数据电压Vdata，在相应行栅线的控制下，数据写入子电路控制导通相应列数据线和所述驱动晶体管的第一极之间的连接，补偿子电路控制导通所述驱动晶体管的栅极和所述驱动晶体管的第二极之间的连接，使所述驱动晶体管形成为二极管结构，使所述驱动晶体管的栅极的电位变为Vdata+Vth，Vth为驱动晶体管的阈值电压；
    在发光时段，所述电源信号输入端输入电源电压Vdd，在所述第一控制端的控制下，所述电源控制子电路控制导通所述电源信号输入端与所述驱动晶体管的第一极之间的连接；在所述第一控制端的控制下，第一复位子电路控制导通所述第二初始化电压输入端与所述公共节点之间的连接；所述第二初始化电压输入端输入的第二初始化信号的电位，与发光时段所述驱动晶体管的栅极的电位之间的差值小于阈值。
  13. 根据权利要求12所述的像素驱动电路的驱动方法，其中，当所述第一复位子电路包括第一复位控制子电路、第二复位控制子电路和第三复位控制子电路时，
    在所述复位时段，在所述复位控制端的控制下，所述第一复位控制子电路控制导通所述驱动晶体管的栅极与所述公共节点之间的连接，同时所述第二复位控制子电路控制导通所述公共节点与所述第一初始化电压输入端之间的连接；在所述第一控制端的控制下，所述第三复位控制子电路控制断开所述公共节点与所述第二初始化电压输入端之间的连接；
    在写入补偿时段，在复位控制端的控制下，所述第一复位控制子电路控制断开所述驱动晶体管的栅极与所述公共节点之间的连接，同时所述第二复位控制子电路控制断开所述公共节点与所述第一初始化电压输入端之间的连 接；
    在发光时段，在所述第一控制端的控制下，所述第三复位控制子电路控制导通所述第二初始化电压输入端与所述公共节点之间的连接。
  14. 根据权利要求12所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括发光控制子电路，所述驱动晶体管的第二极通过所述发光控制子电路与所述发光元件连接；所述发光控制子电路分别与所述第一控制端、所述驱动晶体管的第二极和所述发光元件连接；所述驱动方法还包括：
    在所述复位时段和所述写入补偿时段，在所述第一控制端的控制下，所述发光控制子电路控制断开所述驱动晶体管的第二极与所述发光元件之间的连接，以使所述发光元件在所述复位时段和所述写入补偿时段不发光。
  15. 根据权利要求12所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括第二复位子电路，所述第二复位子电路分别与所述复位控制端、所述发光元件和第三初始化电压输入端连接；
    在所述复位时段，在所述复位控制端的控制下，所述第二复位子电路控制导通所述第三初始化电压输入端与所述发光元件之间的连接。
  16. 根据权利要求15所述的像素驱动电路的驱动方法，其中，所述第三初始化电压输入端输入的第三初始化信号的电位，与所述第一初始化电压输入端输入的第一初始化信号的电位相同。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111445863B (zh) * 2020-05-14 2021-09-14 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111477179B (zh) * 2020-05-20 2021-10-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111951731B (zh) * 2020-08-21 2021-12-21 京东方科技集团股份有限公司 像素单元阵列及其驱动方法、显示面板和显示装置
CN111968581B (zh) * 2020-09-09 2021-11-23 京东方科技集团股份有限公司 像素电路的驱动方法
WO2022067487A1 (en) * 2020-09-29 2022-04-07 Boe Technology Group Co., Ltd. Pixel driving circuit, display apparatus, and pixel driving method
CN113012642A (zh) * 2021-03-04 2021-06-22 京东方科技集团股份有限公司 像素电路、显示面板以及驱动方法
CN113450715B (zh) * 2021-06-25 2022-10-28 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
KR20230143650A (ko) * 2022-04-05 2023-10-13 삼성디스플레이 주식회사 픽셀 회로 및 이를 포함하는 표시 장치
CN116168650B (zh) * 2023-04-21 2023-06-27 惠科股份有限公司 像素驱动电路和显示面板

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935198A (zh) * 2017-04-17 2017-07-07 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板
CN107342044A (zh) * 2017-08-15 2017-11-10 上海天马有机发光显示技术有限公司 像素电路、显示面板和像素电路的驱动方法
CN107665672A (zh) * 2016-07-27 2018-02-06 上海和辉光电有限公司 像素电路及其驱动方法
WO2018168174A1 (ja) * 2017-03-16 2018-09-20 株式会社ジャパンディスプレイ 表示装置および表示装置の駆動方法
CN108777131A (zh) * 2018-06-22 2018-11-09 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路及驱动方法
CN109036250A (zh) * 2018-08-22 2018-12-18 京东方科技集团股份有限公司 显示基板、显示面板及驱动方法、显示装置
US20190088689A1 (en) * 2011-05-13 2019-03-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN110047428A (zh) * 2018-01-15 2019-07-23 三星显示有限公司 像素和包括该像素的有机发光显示装置
CN110675822A (zh) * 2019-09-30 2020-01-10 昆山国显光电有限公司 像素驱动电路及像素驱动电路的控制方法
CN111276099A (zh) * 2020-03-24 2020-06-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示面板
CN111445863A (zh) * 2020-05-14 2020-07-24 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102218779B1 (ko) * 2014-07-04 2021-02-19 엘지디스플레이 주식회사 Oled 표시 장치
CN104575377A (zh) * 2014-12-22 2015-04-29 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN105590955A (zh) * 2015-12-25 2016-05-18 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN205541822U (zh) * 2016-04-06 2016-08-31 京东方科技集团股份有限公司 像素电路、阵列基板、显示面板和显示装置
CN106023898B (zh) * 2016-07-26 2018-07-24 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN107358917B (zh) * 2017-08-21 2020-04-28 上海天马微电子有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN107369410B (zh) * 2017-08-31 2023-11-21 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN113196486A (zh) * 2019-11-29 2021-07-30 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190088689A1 (en) * 2011-05-13 2019-03-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN107665672A (zh) * 2016-07-27 2018-02-06 上海和辉光电有限公司 像素电路及其驱动方法
WO2018168174A1 (ja) * 2017-03-16 2018-09-20 株式会社ジャパンディスプレイ 表示装置および表示装置の駆動方法
CN106935198A (zh) * 2017-04-17 2017-07-07 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板
CN107342044A (zh) * 2017-08-15 2017-11-10 上海天马有机发光显示技术有限公司 像素电路、显示面板和像素电路的驱动方法
CN110047428A (zh) * 2018-01-15 2019-07-23 三星显示有限公司 像素和包括该像素的有机发光显示装置
CN108777131A (zh) * 2018-06-22 2018-11-09 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路及驱动方法
CN109036250A (zh) * 2018-08-22 2018-12-18 京东方科技集团股份有限公司 显示基板、显示面板及驱动方法、显示装置
CN110675822A (zh) * 2019-09-30 2020-01-10 昆山国显光电有限公司 像素驱动电路及像素驱动电路的控制方法
CN111276099A (zh) * 2020-03-24 2020-06-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示面板
CN111445863A (zh) * 2020-05-14 2020-07-24 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

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