WO2023201468A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2023201468A1
WO2023201468A1 PCT/CN2022/087407 CN2022087407W WO2023201468A1 WO 2023201468 A1 WO2023201468 A1 WO 2023201468A1 CN 2022087407 W CN2022087407 W CN 2022087407W WO 2023201468 A1 WO2023201468 A1 WO 2023201468A1
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Prior art keywords
node
light
potential
gate
coupled
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PCT/CN2022/087407
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English (en)
French (fr)
Inventor
胥鑫
王仓鸿
黄星维
李春阳
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000781.7A priority Critical patent/CN117546225A/zh
Priority to PCT/CN2022/087407 priority patent/WO2023201468A1/zh
Publication of WO2023201468A1 publication Critical patent/WO2023201468A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display device.
  • a display device generally includes a plurality of pixels.
  • Each pixel includes a pixel circuit and a light-emitting element coupled to each other.
  • the pixel circuit can transmit a light-emitting driving signal to the light-emitting element to drive the light-emitting element to emit light.
  • pixel circuits generally include: data writing circuits and driving circuits.
  • the data writing circuit is respectively coupled to the two gate signal terminals, the data signal terminal, and the input terminal, control terminal and output terminal of the drive circuit.
  • the output terminal of the driving circuit is also coupled to the light-emitting element.
  • the data writing circuit can write the data signal from the data signal terminal to the input terminal and the control terminal of the driving circuit in response to the gate driving signal provided by each gate signal terminal.
  • the driving circuit can transmit a light-emitting driving signal to the light-emitting element through its output terminal based on the potential of its control terminal and the potential of its input terminal.
  • a parasitic capacitance is formed between one of the two gate signal terminals and the control terminal of the driving circuit.
  • the present disclosure provides a pixel circuit, a driving method thereof, and a display device, which can solve the problem of poor display effects of display devices in related technologies.
  • the technical solution is as follows:
  • a pixel circuit which includes:
  • the data writing circuit is respectively coupled to the first gate signal terminal, the second gate signal terminal, the third gate signal terminal, the data signal terminal, the first node, the second node and the third node.
  • the data writing circuit The input circuit is configured to respond to a first gate drive signal provided by the first gate signal terminal, a second gate drive signal provided by the second gate signal terminal, and a first gate drive signal provided by the third gate signal terminal.
  • the third gate drive signal controls the connection between the data signal terminal and the first node, and controls the connection between the second node and the third node.
  • the second gate signal terminal is connected to the first node.
  • a first parasitic capacitance is formed between the second nodes, and a second parasitic capacitance is formed between the third gate signal terminal and the second node;
  • a light-emitting control circuit respectively coupled to the light-emitting control terminal, the first power terminal, the first node, the third node and the light-emitting element.
  • the light-emitting control circuit is used to respond to the light-emitting control provided by the light-emitting control terminal.
  • a driving circuit, the input end, the control end and the output end of the driving circuit are respectively coupled to the first node, the second node and the third node, the driving circuit is used to operate based on the first node
  • the potential of the second node and the potential of the second node transmit a light-emitting driving signal to the third node.
  • the data writing circuit includes: a data writing sub-circuit and a compensation sub-circuit;
  • the data writing sub-circuit is coupled to the first gate signal terminal, the second gate signal terminal, the data signal terminal and the first node respectively, and the data writing sub-circuit is used to In response to the first gate drive signal and the second gate drive signal, controlling the connection between the data signal terminal and the first node;
  • the compensation subcircuit is coupled to the third gate signal terminal, the second node and the third node respectively, and the compensation subcircuit is used to control the The second node and the third node are connected and disconnected.
  • the data writing sub-circuit includes: a first data writing unit and a second data writing unit;
  • the first data writing unit is coupled to the first gate signal terminal, the data signal terminal and the first node respectively, and the first data writing unit is used to respond to the first gate signal terminal.
  • a pole drive signal to control the connection between the data signal terminal and the first node;
  • the second data writing unit is coupled to the second gate signal terminal, the data signal terminal and the first node respectively, and the second data writing unit is used to respond to the second gate signal terminal.
  • a pole driving signal controls the connection between the data signal terminal and the first node.
  • the first data writing unit includes: a first data writing transistor;
  • the second data writing unit includes: a second data writing transistor;
  • the gate of the first data writing transistor is coupled to the first gate signal terminal, the first pole of the first data writing transistor is coupled to the data signal terminal, and the first data writing transistor is coupled to the data signal terminal.
  • the second pole of the input transistor is coupled to the first node;
  • the gate of the second data writing transistor is coupled to the second gate signal terminal, the first pole of the second data writing transistor is coupled to the data signal terminal, and the second data writing transistor is coupled to the data signal terminal.
  • the second pole of the input transistor is coupled to the first node.
  • both the first data writing transistor and the second data writing transistor are P-type transistors.
  • the compensation subcircuit includes: a compensation transistor
  • the gate of the compensation transistor is coupled to the third gate signal terminal, the first pole of the compensation transistor is coupled to the third node, and the second pole of the compensation transistor is coupled to the second node. coupling.
  • the compensation transistor is an N-type transistor.
  • the driving circuit includes: a driving transistor, and the driving transistor is a P-type transistor;
  • the gate electrode of the driving transistor is coupled to the second node, the first electrode of the driving transistor is coupled to the first node, and the second electrode of the driving transistor is coupled to the third node.
  • the lighting control circuit includes: a first lighting control sub-circuit, a second lighting control sub-circuit and an adjustment sub-circuit;
  • the first lighting control sub-circuit is coupled to the lighting control terminal, the first power terminal and the first node respectively, and the first lighting control sub-circuit is used to control, in response to the lighting control signal, The connection between the first power terminal and the first node;
  • the second light-emitting control sub-circuit is coupled to the light-emitting control terminal, the third node and the first pole of the light-emitting element respectively, and the second pole of the light-emitting element is coupled to the second power terminal, so The second light-emitting control sub-circuit is used to control the connection between the third node and the first pole of the light-emitting element in response to the light-emitting control signal;
  • the adjustment subcircuit is coupled to the second node and the first power supply terminal respectively, and the adjustment subcircuit is used to adjust the potential of the second node based on the first power supply signal.
  • the first lighting control sub-circuit includes: a first lighting control transistor; the second lighting control sub-circuit includes: a second lighting control transistor; and the first lighting control transistor and the second lighting control transistor
  • the control transistors are all N-type transistors; the regulating subcircuit includes: a storage capacitor;
  • the gate of the first light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first power terminal, and the second terminal of the first light-emitting control transistor is coupled to the first light-emitting control transistor.
  • the pole is coupled to the first node;
  • the gate of the second light-emitting control transistor is coupled to the light-emitting control terminal, the first pole of the second light-emitting control transistor is coupled to the third node, and the second pole of the second light-emitting control transistor is coupled to the third node. coupled to the first pole of the light-emitting element;
  • One end of the storage capacitor is coupled to the first power terminal, and the other end of the storage capacitor is coupled to the second node.
  • the pixel circuit further includes: a first reset circuit and a second reset circuit;
  • the first reset circuit is coupled to the reset signal terminal, the first reset power terminal and the second node respectively, and the first reset circuit is used to control the first reset signal in response to the reset signal provided by the reset signal terminal.
  • the second reset circuit is respectively coupled to the first gate signal terminal, the second reset power terminal and the light-emitting element.
  • the second reset circuit is used to control, in response to the first gate drive signal,
  • the second reset power terminal is connected to the light-emitting element.
  • the first reset circuit includes: a first reset transistor; the second reset circuit includes: a second reset transistor; and, the first reset transistor is an N-type transistor, and the second reset transistor is P-type transistor;
  • the gate of the first reset transistor is coupled to the reset signal terminal, the first pole of the first reset transistor is coupled to the first reset power terminal, and the second pole of the first reset transistor is coupled to The second node is coupled;
  • the gate of the second reset transistor is coupled to the first gate signal terminal, the first electrode of the second reset transistor is coupled to the second reset power terminal, and the third terminal of the second reset transistor is coupled to the first gate signal terminal.
  • the diode is coupled to the light-emitting element.
  • a driving method of a pixel circuit for driving the pixel circuit as described in the above aspect.
  • the method includes: a first stage and a second stage performed sequentially in refresh frames in a multi-frame scan, And the third stage and the second stage are executed sequentially in the holding frames in the multi-frame scan;
  • the potential of the lighting control signal provided by the lighting control terminal, the potential of the second gate driving signal provided by the second gate signal terminal, and the potential of the third gate driving signal provided by the third gate signal terminal are The potentials are all the first potential, the potential of the first gate drive signal provided by the first gate signal terminal is the second potential, and the data writing circuit responds to the first gate drive signal to control the data signal terminal and the first gate drive signal.
  • the node is turned on, and in response to the third gate drive signal, the second node and the third node are controlled to be turned on;
  • the potential of the first gate drive signal and the potential of the second gate drive signal are both the first potential, and the potential of the light emission control signal and the third gate drive signal The potentials are all the second potential.
  • the light-emitting control circuit controls the first power terminal to be connected to the first node, and controls the third node to be connected to the light-emitting element.
  • the driving circuit is based on the The potential of the first node and the potential of the second node transmit a light-emitting driving signal to the third node;
  • the potential of the light emission control signal and the potential of the first gate drive signal are both the first potential, and the potential of the second gate drive signal and the third gate drive signal The potentials are all the second potential, and the data writing circuit controls the data signal terminal to be conductive with the first node in response to the second gate drive signal.
  • the method further includes: in the refresh frame, a fourth stage executed before the first stage;
  • the potential of the reset signal provided by the reset signal terminal, the potential of the lighting control signal, the potential of the first gate drive signal and the potential of the second gate drive signal are all the first potential
  • the potential of the third gate drive signal is the second potential
  • the first reset circuit responds to the reset signal and controls the first reset power terminal to be conductive with the second node
  • the second reset circuit responds to the first gate drive signal and controls the second reset power terminal to be connected to the light-emitting element.
  • a display device in another aspect, includes a display panel, a display driving circuit, and a plurality of pixels located on the display panel.
  • the pixels include a light-emitting element, and as described in the above aspect pixel circuit;
  • the display driving circuit is coupled to each signal terminal coupled to the pixel circuit, and the display driving circuit is used to provide signals to each signal terminal;
  • the pixel circuit is coupled to the light-emitting element, the pixel circuit is used to transmit a light-emitting driving signal to the light-emitting element, and the light-emitting element emits light based on the light-emitting driving signal.
  • the beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure may at least include:
  • a pixel circuit, a driving method thereof, and a display device are provided.
  • the data writing circuit is coupled to three gate signal terminals, and controls the first node, the second node and the third node under the control of gate drive signals provided by the three gate signal terminals. Potential.
  • the driving circuit may transmit the light-emitting driving signal to the third node based on the potentials of the first node and the second node.
  • the light-emitting control circuit can control the third node to be connected to the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby lighting the light-emitting element.
  • the potential of the second node can be kept stable by flexibly adjusting the gate drive signals provided by the two gate signal terminals. Furthermore, when the pixel circuit drives the light-emitting element in different frames, the brightness of the light-emitting element can be the same, and the display effect of the display device is better.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a flow chart of another driving method for a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a timing diagram of each signal terminal coupled to a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure can be field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, their source and drain are interchangeable.
  • the source electrode is called the first electrode and the drain electrode is called the second electrode.
  • the drain electrode is called the first electrode and the source electrode is called the second electrode.
  • the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain.
  • the switching transistor used in the embodiment of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level, and is turned off when the gate is at a low level.
  • multiple signals in various embodiments of the present disclosure correspond to effective potentials and ineffective potentials. The effective potentials and ineffective potentials only represent that the potential of the signal has two state quantities, and do not mean that the effective potential or the ineffective potential in the entire text has a specific state. numerical value.
  • the pixel circuit driving the light-emitting element to emit light can be divided into at least the following two stages: the data writing stage and the light-emitting stage.
  • the gate signal terminal can provide a gate drive signal of effective potential, so that the data write circuit responds to the gate drive signal of effective potential and writes to the input terminal and control terminal of the drive circuit.
  • the data signal provided by the data signal terminal.
  • the potential of the gate drive signal will jump from the effective potential to the inactive potential.
  • the driving circuit can transmit a light-emitting driving signal to the light-emitting element based on the potentials of its input terminal and control terminal to drive the light-emitting element to emit light.
  • the potential of the control terminal of the driving circuit will shift with the potential jump of the gate driving signal. For example, assuming that the effective potential is high and the ineffective potential is low, after the data signal is written, when the gate drive signal jumps from high to low, the potential of the control end of the drive circuit will be coupled by the parasitic capacitance. It was driven down under the influence, resulting in a negative bias. This negative bias will affect the difference in the luminous brightness of the light-emitting element driven by the pixel circuit during the scanning of two adjacent frames, resulting in a poor display effect of the display device.
  • the problem of poor display uniformity described in the above embodiments can be improved by adjusting the potential of the data signal. For example, if the potential of the control terminal of the driving circuit is pulled low in the current frame, the potential of the data signal can be increased in the next frame to compensate for the potential of the control terminal of the driving circuit, ensuring that the potential of the control terminal of the driving circuit can be relatively equal in the two frames. consistent.
  • increasing the potential of the data signal will undoubtedly cause a large difference in the potential of the data signal between the two frames, that is, the potential value range (data range) of the data signal is relatively high. In this way, the power consumption of the circuit (such as the source driving circuit) that provides the data signal for the data signal end will be higher, and the operating power consumption of the display panel (panel) in the display device will be increased.
  • panels in various display devices can support a higher refresh rate, such as 120 Hertz (Hz).
  • Hz Hertz
  • the high refresh rate improves the display effect of the display device, it also brings greater challenges to the working power consumption of the panel.
  • it is not always necessary to maintain a high refresh rate. For example, when entering reading mode, a low refresh rate can still meet the needs. Therefore, during the development process of the panel, it is necessary to reduce the operating power consumption of the panel from other aspects as much as possible.
  • a display device using the pixel circuit not only has better display effects, but also has lower power consumption.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. As shown in Figure 1, the pixel circuit includes: a data writing circuit 01, a light emission control circuit 02 and a driving circuit 03.
  • the data writing circuit 01 is respectively connected with the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1, the third gate signal terminal Gate_N, the data signal terminal Data, the first node N1, the second node N2 and the third Node N3 is coupled.
  • the data writing circuit 01 is configured to respond to a first gate drive signal provided by the first gate signal terminal Gate_P, a second gate drive signal provided by the second gate signal terminal Gate_P1, and a third gate signal terminal Gate_N.
  • the third gate driving signal controls the connection between the data signal terminal Data and the first node N1, and controls the connection between the second node N2 and the third node N3.
  • the data writing circuit 01 may provide the first gate drive signal at the first gate signal terminal Gate_P with an effective potential, and/or the second gate drive signal provided at the second gate signal terminal Gate_P1 with When the potential is an effective potential, the control data signal terminal Data is connected to the first node N1. At this time, the data signal provided by the data signal terminal Data can be transmitted to the first node N1.
  • the data writing circuit 01 can control the data signal terminal Data to be disconnected from the first node N1 when the potential of the first gate driving signal is an inactive potential and when the potential of the second gate driving signal is an inactive potential.
  • the data writing circuit 01 can control the second node N2 and the third node N3 to be conductive when the potential of the third gate driving signal provided by the third gate signal terminal Gate_N is an effective potential. At this time, the potential of the second node N2 and the potential of the third node N3 may influence each other. Furthermore, the data writing circuit 01 can control the second node N2 and the third node N3 to disconnect when the potential of the third gate driving signal is an invalid potential.
  • the data writing circuit 01 may include three transistors respectively coupled to the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1 and the third gate signal terminal Gate_N. And among the three transistors, the transistor coupled to the first gate signal terminal Gate_P and the transistor coupled to the second gate signal terminal Gate_P1 can both be P-type transistors, and the transistor coupled to the third gate signal terminal Gate_N can be N-type transistor.
  • the ineffective potential of the first gate drive signal and the ineffective potential of the second gate drive signal can be high potential, and the effective potential of the first gate drive signal and the effective potential of the second gate drive signal can be low potential.
  • the ineffective potential of the third gate driving signal may be low potential, and the effective potential of the third gate driving signal may be high potential.
  • the high potential may be called the first potential
  • the low potential may be called the second potential.
  • a second parasitic capacitance C2 be formed between the third gate signal terminal Gate_N and the second node N2, but also the second gate signal terminal Gate_P1 will be formed.
  • a first parasitic capacitance C1 is formed between the signal terminal Gate_P1 and the second node N2. In this way, under the coupling effect of the second parasitic capacitance C2, the potential of the second node N2 will shift with the potential jump of the third gate driving signal. And, under the coupling effect of the first parasitic capacitance C1, the potential of the second node N2 will shift with the potential jump of the second gate driving signal.
  • the potential of the second gate drive signal and the potential of the third gate drive signal can be flexibly adjusted, so that the potential of the second node N2 can be shifted forward (ie, the potential increases) and shifted in different stages respectively.
  • the negative shift ensures that the potential of the second node N2 is eventually maintained at a stable potential, thereby solving the display unevenness problem recorded in the above embodiment.
  • the potential range of the data signal required to be provided by the data signal terminal Data between the two frames can be relatively consistent, that is, the data range is reduced.
  • the power consumption of the source driver circuit that provides the data signal for the data signal terminal Data is effectively reduced, and the operating power consumption of the panel is reduced.
  • multi-frame scanning can be divided into refresh frames and hold frames. Refresh scanning is performed in the refresh frame, and refresh scanning is not performed in the hold frame and only display is performed.
  • the potential of the first gate driving signal can be controlled to be low potential
  • the potential of the third gate driving signal can be controlled to be high potential, so as to write data signals to the first node N1 and the second node N2.
  • the potential of the first gate driving signal can be controlled to jump to a high potential
  • the potential of the third gate driving signal can be controlled to jump to a low potential.
  • the potential of the second node N2 is pulled down.
  • the potential of the second gate driving signal can be controlled to be a low potential to write a data signal to the first node N1.
  • the potential of the second gate driving signal can be controlled to jump to a high potential.
  • the potential of the second node N2 is pulled up. In this way, it is ensured that the potential of the second node N2 remains stable. Furthermore, it ensures a better display effect and achieves the purpose of reducing the power consumption of the panel in the frame-holding stage in the low refresh rate mode.
  • the light-emitting control circuit 02 is coupled to the light-emitting control terminal EM, the first power terminal VDD, the first node N1, the third node N3 and the light-emitting element L1 respectively.
  • the lighting control circuit 02 is used to control the switching of the first power terminal VDD and the first node N1 in response to the lighting control signal provided by the lighting control terminal EM, and to control the switching of the third node N3 and the light-emitting element L1.
  • the light-emitting control circuit 02 can control the first power terminal VDD to be conductive to the first node N1, and control the third node N3 to be conductive to the light-emitting element L1 when the potential of the light-emitting control signal is the first potential.
  • the first power signal provided by the first power terminal VDD can be transmitted to the first node N1, and the potential of the third node N3 can be transmitted to the light-emitting element L1.
  • the light-emitting control circuit 02 may control the first power terminal VDD to be decoupled from the first node N1, and control the third node N3 to be decoupled from the light-emitting element L1 when the potential of the light-emitting control signal is the second potential.
  • the light-emitting control circuit 02 may be coupled to the first pole of the light-emitting element L1, and the second pole of the light-emitting element L1 may be coupled to the second power terminal VSS.
  • the first electrode of the light-emitting element L1 may be an anode
  • the second electrode of the light-emitting element L1 may be a cathode.
  • the first electrode of the light-emitting element L1 may be a cathode
  • the second electrode of the light-emitting element L1 may be an anode.
  • the input terminal, control terminal and output terminal of the driving circuit 03 are respectively coupled to the first node N1, the second node N2 and the third node N3. That is, the input terminal of the driving circuit 03 may be coupled to the first node N1, the control terminal of the driving circuit 03 may be coupled to the second node N2, and the output terminal of the driving circuit 03 may be coupled to the third node N3.
  • the driving circuit 03 is used to transmit a light-emitting driving signal (eg, driving current) to the third node N3 based on the potential of the first node N1 and the potential of the second node N2.
  • a light-emitting driving signal eg, driving current
  • the light-emitting control circuit 02 controls the third node N3 to be connected to the anode of the light-emitting element L1
  • the light-emitting driving signal can be transmitted to the anode of the light-emitting element L1 through the light-emitting control circuit 02.
  • the light-emitting element L1 can emit light under the action of the voltage difference between the light-emitting driving signal and the second power signal provided by the second power terminal VSS to which the cathode is coupled.
  • the potential of the light-emitting driving signal finally transmitted to the anode of the light-emitting element L1 is the same as the potential sum of the driving circuit 03 based on the first node N1.
  • the potential of the light emitting driving signal generated by the potential of the second node N2 may be different.
  • embodiments of the present disclosure provide a pixel circuit.
  • the data writing circuit is coupled to three gate signal terminals, and controls the first node, the second node and the third node under the control of gate drive signals provided by the three gate signal terminals. Potential.
  • the driving circuit may transmit the light-emitting driving signal to the third node based on the potentials of the first node and the second node.
  • the light-emitting control circuit can control the third node to be connected to the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby lighting the light-emitting element.
  • the potential of the second node can be kept stable by flexibly adjusting the gate drive signals provided by the two gate signal terminals. Furthermore, when the pixel circuit drives the light-emitting element in different frames, the brightness of the light-emitting element can be the same, and the display effect of the display device is better.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the data writing circuit 01 in the pixel circuit may include: a data writing sub-circuit 011 and a compensation sub-circuit 012.
  • the data writing sub-circuit 011 may be coupled to the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1, the data signal terminal Data and the first node N1 respectively.
  • the data writing sub-circuit 011 is used to control the connection between the data signal terminal Data and the first node N1 in response to the first gate driving signal and the second gate driving signal.
  • the data writing sub-circuit 011 can control the data signal terminal Data to be connected to the first node N1 when the potential of the first gate drive signal is an effective potential and/or when the potential of the second gate drive signal is an effective potential. pass, so that the data signal is transmitted to the first node N1. And, the data writing sub-circuit 011 can control the data signal terminal Data to be decoupled from the first node N1 when the potential of the first gate drive signal is an invalid potential and the potential of the second gate drive signal is an invalid potential. catch.
  • the compensation sub-circuit 012 is coupled to the third gate signal terminal Gate_N, the second node N2 and the third node N3 respectively.
  • the compensation subcircuit 012 is used to control the on/off of the second node N2 and the third node N3 in response to the third gate driving signal.
  • the compensation sub-circuit 012 can control the second node N2 and the third node N3 to be conductive when the potential of the third gate drive signal is an effective potential, so as to adjust the potential of the second node N2 based on the potential of the third node N3. compensate. Furthermore, the compensation subcircuit 012 can control the second node N2 and the third node N3 to disconnect when the potential of the third gate driving signal is an invalid potential.
  • FIG. 3 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • the data writing sub-circuit 011 in the data writing circuit 01 may include: a first data writing unit 0111 and a second data writing unit 0112.
  • the first data writing unit 0111 may be coupled to the first gate signal terminal Gate_P, the data signal terminal Data and the first node N1 respectively.
  • the first data writing unit 0111 may be used to control the connection between the data signal terminal Data and the first node N1 in response to the first gate driving signal.
  • the first data writing unit 0111 can control the data signal terminal Data to be conductive with the first node N1 when the potential of the first gate driving signal is an effective potential. And, the first data writing unit 0111 can control the data signal terminal Data to be disconnected from the first node N1 when the potential of the first gate driving signal is an invalid potential.
  • the second data writing unit 0112 may be coupled to the second gate signal terminal Gate_P1, the data signal terminal Data, and the first node N1 respectively.
  • the second data writing unit 0112 may be used to control the connection between the data signal terminal Data and the first node N1 in response to the second gate driving signal.
  • the second data writing unit 0112 may control the data signal terminal Data to be conductive with the first node N1 when the potential of the second gate driving signal is an effective potential. Furthermore, the second data writing unit 0112 may control the data signal terminal Data to disconnect from the first node N1 when the potential of the second gate driving signal is an invalid potential.
  • FIG. 4 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • the lighting control circuit 02 may include: a first lighting control sub-circuit 021 , a second lighting control sub-circuit 022 and an adjustment sub-circuit 023 .
  • the first lighting control sub-circuit 021 may be coupled to the lighting control terminal EM, the first power supply terminal VDD and the first node N1 respectively.
  • the first lighting control sub-circuit 021 may be used to control the connection between the first power terminal VDD and the first node N1 in response to the lighting control signal.
  • the first lighting control sub-circuit 021 can control the first power supply terminal VDD to conduct with the first node N1 when the potential of the lighting control signal is a valid potential, so that the first power signal provided by the first power supply terminal VDD can be transmitted. to the first node N1.
  • the first light-emitting control sub-circuit 021 can control the first power supply terminal VDD to disconnect from the first node N1 when the potential of the light-emitting control signal is an invalid potential.
  • the second light-emitting control sub-circuit 022 may be coupled to the light-emitting control terminal EM, the third node N3 and the first pole of the light-emitting element L1 respectively.
  • the second pole of the light-emitting element L1 is coupled to the second power terminal VSS.
  • the second light emission control sub-circuit 022 may be used to control the connection between the third node N3 and the first pole of the light emitting element L1 in response to the light emission control signal.
  • the first electrode of the light-emitting element L1 may be an anode
  • the second electrode of the light-emitting element L1 may be a cathode.
  • the second light-emitting control sub-circuit 022 can control the third node N3 to conduct with the first electrode of the light-emitting element L1 when the potential of the light-emitting control signal is an effective potential, so that the potential of the third node N3 is transmitted to the light-emitting element L1
  • the first pole drives the light-emitting element L1 to emit light.
  • the second light emission control sub-circuit 022 can control the third node N3 to disconnect from the first pole of the light emitting element L1 when the potential of the light emission control signal is an invalid potential.
  • the potential of the first power signal may be high potential, and the potential of the second power signal may be low potential.
  • the adjustment subcircuit 023 may be coupled to the second node N2 and the first power terminal VDD respectively.
  • the adjustment subcircuit 023 may be used to adjust the potential of the second node N2 based on the first power signal.
  • FIG. 5 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG. 5 , the pixel circuit may further include: a first reset circuit 04 and a second reset circuit 05 .
  • the first reset circuit 04 may be coupled to the reset signal terminal Rst, the first reset power terminal Vinit1 and the second node N2 respectively.
  • the first reset circuit 04 may be used to control the connection between the first reset power terminal Vinit1 and the second node N2 in response to the reset signal provided by the reset signal terminal Rst.
  • the first reset circuit 04 can control the first reset power terminal Vinit1 and the second node N2 to be conductive when the potential of the reset signal is a valid potential. At this time, the first reset power signal provided by the first reset power terminal Vinit1 can be transmitted to the second node N2 to realize the reset of the second node N2. Furthermore, the first reset circuit 04 can control the first reset power terminal Vinit1 to disconnect from the second node N2 when the potential of the reset signal is an invalid potential.
  • the second reset circuit 05 may be coupled to the first gate signal terminal Gate_P, the second reset power terminal Vinit2 and the light emitting element L1 respectively.
  • the second reset circuit 05 may be used to control the connection between the second reset power terminal Vinit2 and the light-emitting element L1 in response to the first gate drive signal.
  • the second reset circuit 05 may be coupled with the anode of the light emitting element L1.
  • the second reset circuit 05 can control the second reset power terminal Vinit2 to be conductive with the anode of the light-emitting element L1 when the potential of the first gate driving signal is an effective potential.
  • the second reset power signal provided by the second reset power terminal Vinit2 can be transmitted to the anode of the light-emitting element L1 to realize the reset of the anode of the light-emitting element L1.
  • the second reset circuit 05 can control the second reset power terminal Vinit2 to disconnect from the anode of the light-emitting element L1 when the potential of the first gate driving signal is an invalid potential.
  • the potential of the first reset power signal and the potential of the second reset power signal may both be low potential.
  • the potential of the first reset power signal may be less than or equal to the potential of the second reset power signal.
  • the potential of the first reset power signal may also be greater than the potential of the second reset power signal.
  • FIG. 6 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • the first data writing unit 0111 may include a first data writing transistor T1.
  • the second data writing unit 0112 may include a second data writing transistor T2.
  • Compensation sub-circuit 012 may include compensation transistor T3.
  • the driving circuit 03 may include a driving transistor T4.
  • the first lighting control sub-circuit 021 may include a first lighting control transistor T5, the second lighting control sub-circuit 022 may include a second lighting control transistor T6, and the adjustment sub-circuit 023 may include a storage capacitor Cst.
  • the first reset circuit 04 may include a first reset transistor T7.
  • the second reset circuit 05 may include a second reset transistor T8.
  • the gate of the first data writing transistor T1 may be coupled to the first gate signal terminal Gate_P
  • the first pole of the first data writing transistor T1 may be coupled to the data signal terminal Data
  • the first data writing transistor T1 may be coupled to the data signal terminal Data.
  • the second pole of T1 may be coupled with the first node N1.
  • the gate of the second data writing transistor T2 may be coupled to the second gate signal terminal Gate_P1.
  • the first electrode of the second data writing transistor T2 may be coupled to the data signal terminal Data.
  • the gate of the second data writing transistor T2 may be coupled to the second gate signal terminal Gate_P1.
  • the second pole may be coupled to the first node N1.
  • the potential of the first gate drive signal when refreshing the frame, can be controlled to be a low potential, and the potential of the second gate drive signal can be controlled to be a high potential, so that the first data is written into the transistor T1 is turned on, and the second data writing transistor T2 is turned off.
  • the data signal can be transmitted to the first node N1 through the turned-on first data writing transistor T1 to realize writing of the data signal.
  • the potential of the first gate drive signal can be controlled to be a high potential
  • the potential of the second gate drive signal can be controlled to be a low potential, so that the first data writing transistor T1 is turned off, and the second data writing transistor T1 is turned off.
  • Transistor T2 is on.
  • the data signal can be transmitted to the first node N1 via the turned-on second data writing transistor T2 to realize writing of the data signal.
  • the data signal terminal Data can be connected to the second data writing transistor T2 to be conductive with the first node N1.
  • the potential of the second gate drive signal can be controlled to a high potential, so that the potential of the second node N2 is pulled high under the coupling effect of the first parasitic capacitance C1 to match the third gate drive signal.
  • the potential jump of the gate drive signal causes the potential of the second node N2 to be pulled down and cancel each other out, ensuring the stability of the potential of the second node N2.
  • the gate of the compensation transistor T3 may be coupled to the third gate signal terminal Gate_N, the first electrode of the compensation transistor T3 may be coupled to the third node N3, and the second electrode of the compensation transistor T3 may be coupled to the second node N2.
  • the gate electrode of the driving transistor T4 may be coupled to the second node N2, the first electrode of the driving transistor T4 may be coupled to the first node N1, and the second electrode of the driving transistor T4 may be coupled to the third node N3.
  • the gate of the driving transistor T4 may be the control terminal of the driving circuit 03
  • the first pole of the driving transistor T4 may be the input terminal of the driving circuit 03
  • the second pole of the driving transistor T4 may be the output terminal of the driving circuit 03 .
  • the gate of the first light-emitting control transistor T5 is coupled to the light-emitting control terminal EM.
  • the first electrode of the first light-emitting control transistor T5 is coupled to the first power supply terminal VDD.
  • the second electrode of the first light-emitting control transistor T5 is coupled to the first node. N1 coupling.
  • the gate of the second light-emitting control transistor T6 is coupled to the light-emitting control terminal EM, the first electrode of the second light-emitting control transistor T6 is coupled to the third node N3, and the second electrode of the second light-emitting control transistor T6 is coupled to the light-emitting element L1.
  • the first pole is coupled.
  • One end of the storage capacitor Cst is coupled to the first power terminal VDD, and the other end of the storage capacitor Cst is coupled to the second node N2.
  • the gate of the first reset transistor T7 is coupled to the reset signal terminal Rst, the first pole T7 of the first reset transistor is coupled to the first reset power terminal Vinit1, and the second pole of the first reset transistor T7 is coupled to the second node N2. catch.
  • the gate of the second reset transistor T8 is coupled to the first gate signal terminal Gate_P, the first electrode of the second reset transistor T8 is coupled to the second reset power supply terminal Vinit2, and the second electrode of the second reset transistor T8 is coupled to the light-emitting element. L1 coupling.
  • the first data writing transistor T1 and the second data writing transistor T2 may both be P-type transistors.
  • the compensation transistor T3 may be an N-type transistor.
  • the first light emission control transistor T5 and the second light emission control transistor T6 may both be N-type transistors.
  • the driving transistor T4 may be a P-type transistor.
  • the first reset transistor T7 may be an N-type transistor, and the second reset transistor T8 may be a P-type transistor.
  • the P-type transistors included in the pixel circuit may all be transistors made of low temperature polysilicon (LTPS) material, and the N-type transistors may all be made of oxide (oxide) material. made transistors.
  • the pixel circuit may be a low-temperature polysilicon oxide LTPO pixel circuit.
  • the oxide material may include: indium gallium zinc oxide (IGZO) material.
  • IGZO indium gallium zinc oxide
  • the pixel circuit recorded in the embodiment of the present disclosure may have an 8T1C (ie, including 8 transistors and 1 capacitor) structure as shown in FIG. 6. Structures including other numbers of transistors are also possible. For example, it can be a 6T1C structure. The embodiments of the present disclosure do not limit this.
  • the types of each transistor included in the pixel circuit can be as described in the above embodiments.
  • the various transistor types included in the pixel circuit may also satisfy other choices.
  • the first reset transistor T7 may be a P-type transistor.
  • the effective potential is low relative to the ineffective potential; for N-type transistors, the effective potential is high relative to the ineffective potential.
  • embodiments of the present disclosure provide a pixel circuit.
  • the data writing circuit is coupled to three gate signal terminals, and controls the first node, the second node and the third node under the control of gate drive signals provided by the three gate signal terminals. Potential.
  • the driving circuit may transmit the light-emitting driving signal to the third node based on the potentials of the first node and the second node.
  • the light-emitting control circuit can control the third node to be connected to the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby lighting the light-emitting element.
  • the potential of the second node can be kept stable by flexibly adjusting the gate drive signals provided by the two gate signal terminals. Furthermore, when the pixel circuit drives the light-emitting element in different frames, the brightness of the light-emitting element can be the same, and the display effect of the display device is better.
  • FIG. 7 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure. This method can be used to drive the pixel circuit shown in any one of FIGS. 1 to 6 . As shown in FIG. 7 , the method includes: a first stage and a second stage in which refresh frames in a multi-frame scan are executed sequentially, and a third stage and a second stage in which the hold frames in a multi-frame scan are executed sequentially. For example, assuming a total of 60 frames, 30 frames can be divided into refresh frames and 30 frames as hold frames.
  • Step 701. In the first stage, the potential of the lighting control signal provided by the lighting control terminal, the potential of the second gate driving signal provided by the second gate signal terminal and the third gate driving signal provided by the third gate signal terminal The potentials of are all the first potential, the potential of the first gate drive signal provided by the first gate signal terminal is the second potential, the data writing circuit responds to the first gate drive signal, controls the data signal terminal and the first node is turned on, and in response to the third gate driving signal, the second node and the third node are controlled to be turned on.
  • Step 702. In the second stage, the potential of the first gate driving signal and the potential of the second gate driving signal are both the first potential, and the potential of the light emission control signal and the potential of the third gate driving signal are both the second potential.
  • the light-emitting control circuit responds to the light-emitting control signal, controls the first power supply terminal to be conductive to the first node, and controls the third node to be conductive to the light-emitting element, and the driving circuit, based on the potential of the first node and the potential of the second node, supplies the signal to the third node.
  • Three nodes transmit light-emitting driving signals.
  • the potential of the light emission control signal and the potential of the first gate drive signal are both the first potential
  • the potential of the second gate drive signal and the third gate drive signal are both the second potential.
  • the data writing circuit responds to the second gate driving signal and controls the data signal terminal to be connected to the first node.
  • the first potential may refer to a high potential
  • the second potential may refer to a low potential
  • embodiments of the present disclosure provide a driving method for a pixel circuit.
  • the potential of the third gate drive signal provided by the third gate signal terminal jumps from the first potential to the second potential, whereby the third gate Under the action of the parasitic capacitive coupling formed between the polar signal terminal and the second node, the potential of the second node will be driven to shift for the first time.
  • the potential of the second gate driving signal provided by the second gate signal terminal jumps from the second potential to the first potential, whereby the second gate signal terminal and Under the action of the parasitic capacitive coupling formed by the second node, the potential of the second node will be driven to shift for the first time. Since the first shift occurs when the first potential jumps to the second potential, and the second shift occurs when the second potential jumps to the first potential, it is ensured that the potential of the second node remains stable. . Furthermore, when the pixel circuit drives the light-emitting element in different frames, the brightness of the light-emitting element can be the same, and the display effect of the display device is better.
  • FIG. 8 is a flow chart of another driving method of a pixel circuit provided by an embodiment of the present disclosure. As shown in FIG. 8 , the method may further include: in the refresh frame, a fourth stage executed before the first stage, that is, the method may also include the following step 704 .
  • Step 704. the potential of the reset signal provided by the reset signal terminal, the potential of the lighting control signal, the potential of the first gate drive signal and the potential of the second gate drive signal are all the first potential, and the third gate The potential of the pole driving signal is the second potential, and the first reset circuit responds to the reset signal and controls the first reset power terminal to be connected to the second node.
  • the second reset circuit controls the second reset power terminal to be connected to the light-emitting element in response to the first gate drive signal.
  • FIG. 9 shows a timing diagram of each signal terminal coupled to a pixel circuit provided by an embodiment of the present disclosure.
  • the hold frame can be entered, and the refresh frame includes the fourth phase t4, the first phase t1, and the second phase t2 that are executed in sequence; the hold frame includes the third phase t3 and t2 that are executed in sequence.
  • the potential of the lighting control signal provided by the lighting control terminal EM, the potential of the reset signal provided by the reset signal terminal Rst, the potential of the first gate driving signal provided by the first gate signal terminal Gate_P, and The potential of the second gate drive signal provided by the second gate signal terminal Gate_P1 is all high potential (ie, the first potential), and only the potential of the third gate drive signal provided by the third gate signal terminal Gate_N is low potential. (i.e., the second potential).
  • the first reset transistor T7 is turned on, the first data writing transistor T1, the second data writing transistor T2, the compensation transistor T3, the first light emitting control transistor T5, the sixth light emitting control transistor T6 and the second reset transistor T8.
  • the low-level first reset power signal provided by the first reset power terminal Vinit1 can be transmitted to the second node N2 through the turned-on first reset transistor T7 to realize the reset of the second node N2 and thereby drive the transistor.
  • T4 is on.
  • This fourth phase t4 may also be called a reset phase for resetting the second node N2.
  • the potential of the light emission control signal, the potential of the second gate drive signal and the potential of the third gate drive signal are all high potential, and the potential of the reset signal and the potential of the first gate drive signal are low potential.
  • the first data writing transistor T1, the second reset transistor T8 and the compensation transistor T3 are all turned on
  • the second data writing transistor T2 the first light emitting control transistor T5, the sixth light emitting control transistor T6 and the first reset transistor T are turned on. are all turned off.
  • the potential of the second node N2 first remains at the low potential of the previous stage t4, and the driving transistor T4 remains on.
  • the low-potential second reset power signal provided by the second reset power terminal Vinit can be transmitted to the anode of the light-emitting element L1 through the turned-on second reset transistor T8 to realize the reset of the anode of the light-emitting element L1.
  • the data signal provided by the data signal terminal Data can be transmitted to the first node N1 through the turned-on first data writing transistor T1, and the potential of the first node N1 can then be transmitted to the third node N3 through the turned-on driving transistor T4. The potential of the third node N3 can then be transmitted to the second node N2 via the turned-on compensation transistor T3.
  • This first phase t1 may also be called a data writing phase and a reset phase for resetting the light emitting element L1.
  • the potential of the first gate drive signal and the second gate drive signal are both high, and the potential of the light emission control signal, the reset signal, and the third gate drive signal are all low. Potential.
  • the first light emitting control transistor T5 and the second light emitting control transistor T6 are both turned on, and the first data writing transistor T1, the second data writing transistor T2, the compensation transistor T3, the first reset transistor T7 and the second reset transistor T8 are all turned off.
  • the potential of the second node N2 first remains at the low potential of the previous stage t4, and the driving transistor T4 remains on.
  • the high-potential first power signal provided by the first power terminal VDD can be transmitted to the first node N1 through the turned-on first light-emitting control transistor T5, and the third node N3 is connected to the anode of the light-emitting element L1.
  • a path is formed between the first power terminal VDD and the second power terminal VSS.
  • the driving transistor T4 may transmit a light-emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2.
  • the light-emitting driving signal is then transmitted to the anode of the light-emitting element L1 through the turned-on second light-emitting control transistor T6, and the light-emitting element L1 emits light.
  • This second stage t2 can also be called the light-emitting stage.
  • the potential of the light-emitting control signal and the first gate drive signal are both high, and the potential of the reset signal, the second gate drive signal, and the third gate drive signal are all low. Potential.
  • the second data writing transistor T2 is turned on, the first data writing transistor T1, the compensation transistor T3, the first light emitting control transistor T5, the second light emitting control transistor T6, the first reset transistor T7 and the second reset transistor T8 are all turned on. Shut down.
  • the driving transistor T4 remains on.
  • the data signal provided by the data signal terminal Data can be transmitted to the first node N1 via the turned-on second data writing transistor T2.
  • This third phase t3 may also be called the data writing phase in the hold frame. and, a second phase t2 executed after the third phase t3.
  • the data signal terminal Data is connected to the first node N1 through the first data writing transistor T1 coupled to the first gate signal terminal Gate_P, and passes through the first data writing transistor T1.
  • the data writing transistor T1 transmits a data signal to the first node N1.
  • the data signal terminal Data is connected to the first node N1 through the second data writing transistor T2 coupled to the second gate signal terminal Gate_P1, and is connected to the first node N1 through the second data writing transistor T2.
  • N1 transmits data signals.
  • the potential of the third gate drive signal jumps from high potential to low potential, and then under the coupling effect of the second parasitic capacitance C2, the second node N2 The potential is pulled down.
  • the potential of the second gate drive signal jumps from low potential to high potential, and then under the coupling effect of the first parasitic capacitance C1, the potential of the second node N2 is Pull high. Thereby, the potential of the second node N2 remains stable.
  • the embodiment of the present disclosure uses the low refresh rate mode to refresh the frame to hold the frame and switch different data signal input transistors (that is, switch different data writing transistors) to reduce the data range and save power consumption.
  • the duration for which the third gate drive signal is at a high potential is longer than the duration for which the first gate drive signal is at a low potential (ie, effective potential) duration.
  • the duration that the third gate drive signal is at the effective potential determines the refresh rate. The longer the duration, the higher the refresh rate.
  • embodiments of the present disclosure provide a driving method for a pixel circuit.
  • the potential of the third gate drive signal provided by the third gate signal terminal jumps from the first potential to the second potential, whereby the third gate Under the action of the parasitic capacitive coupling formed between the polar signal terminal and the second node, the potential of the second node will be driven to shift for the first time.
  • the potential of the second gate driving signal provided by the second gate signal terminal jumps from the second potential to the first potential, whereby the second gate signal terminal and Under the action of the parasitic capacitive coupling formed by the second node, the potential of the second node will be driven to shift for the first time. Since the first shift occurs when the first potential jumps to the second potential, and the second shift occurs when the second potential jumps to the first potential, it is ensured that the potential of the second node remains stable. . Furthermore, when the pixel circuit drives the light-emitting element in different frames, the brightness of the light-emitting element can be the same, and the display effect of the display device is better.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device includes: a display panel 10, a display driving circuit 20, and a plurality of pixels P1 located on the display panel 10, and the pixels P1 can include: a light-emitting element L1, and any of the components shown in Figures 1 to 6 A pixel circuit 00 is shown.
  • the display driving circuit 10 may be coupled to each signal terminal of the pixel circuit 00 .
  • the display driving circuit 10 is used to provide signals to each signal terminal.
  • the pixel circuit 00 may be coupled with the light emitting element L1.
  • the pixel circuit 00 may be used to transmit a light-emitting driving signal to the light-emitting element L1 , and the light-emitting element L1 may be used to emit light based on the light-emitting driving signal.
  • the display driving circuit 10 may include a gate driving circuit and a source driving circuit.
  • the gate driving circuit may be coupled to the gate signal terminal and used to provide the gate driving signal to the gate signal terminal.
  • the source driver circuit can be coupled to the data signal terminal and used to provide the data signal to the data signal terminal.
  • the display device may be: an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a monitor, or any other device with A product or component that displays functionality.
  • AMOLED active-matrix organic light-emitting diode

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Abstract

提供了一种像素电路及其驱动方法、显示装置，属于显示技术领域。该像素电路中，数据写入电路与三个栅极信号端耦接，并在该三个栅极信号端提供的栅极驱动信号控制下，控制第一节点、第二节点和第三节点的电位。驱动电路可以基于第一节点和第二节点的电位，向第三节点传输发光驱动信号。发光控制电路可以控制第三节点与发光元件导通，以使得发光驱动信号进一步传输至发光元件，从而点亮发光元件。并且，存在两个栅极信号端与第二节点之间分别形成寄生电容。如此，可以通过灵活调节该两个栅极信号端提供的栅极驱动信号，以使得第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发光元件的亮度相同，显示装置的显示效果较好。

Description

像素电路及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示装置。
背景技术
显示装置一般包括多个像素，每个像素包括相互耦接的像素电路和发光元件，像素电路能够向发光元件传输发光驱动信号，以驱动发光元件发光。
目前，像素电路一般包括：数据写入电路和驱动电路。数据写入电路分别与两个栅极信号端，数据信号端，以及驱动电路的输入端、控制端和输出端耦接。驱动电路的输出端还与发光元件耦接。数据写入电路能够响应于每个栅极信号端提供的栅极驱动信号，将来自数据信号端的数据信号写入至驱动电路的输入端和控制端。驱动电路能够基于其控制端的电位和输入端的电位，经其输出端向发光元件传输发光驱动信号。且，两个栅极信号端中，一个栅极信号端与驱动电路的控制端之间还形成有寄生电容。
但是，受寄生电容的耦合作用影响，驱动电路的控制端的电位会随栅极驱动信号的电位跳变而发生偏移。如此，导致一个像素电路在不同帧驱动发光元件时，发光元件的亮度不同，显示装置的显示效果较差。
发明内容
本公开提供了一种像素电路及其驱动方法、显示装置，可以解决相关技术中显示装置的显示效果较差的问题，所述技术方案如下：
一方面，提供了一种像素电路，所述像素电路包括：
数据写入电路，分别与第一栅极信号端、第二栅极信号端、第三栅极信号端、数据信号端、第一节点、第二节点和第三节点耦接，所述数据写入电路用于响应于所述第一栅极信号端提供的第一栅极驱动信号、所述第二栅极信号端提供的第二栅极驱动信号和所述第三栅极信号端提供的第三栅极驱动信号，控 制所述数据信号端与所述第一节点的通断，且控制所述第二节点与所述第三节点的通断，所述第二栅极信号端与所述第二节点之间形成有第一寄生电容，且所述第三栅极信号端与所述第二节点之间形成有第二寄生电容；
发光控制电路，分别与发光控制端、第一电源端、所述第一节点、所述第三节点和发光元件耦接，所述发光控制电路用于响应于所述发光控制端提供的发光控制信号，控制所述第一电源端与所述第一节点的通断，且控制所述第三节点与所述发光元件的通断；
驱动电路，所述驱动电路的输入端、控制端和输出端分别与所述第一节点、所述第二节点和所述第三节点耦接，所述驱动电路用于基于所述第一节点的电位和所述第二节点的电位，向所述第三节点传输发光驱动信号。
可选的，所述数据写入电路包括：数据写入子电路和补偿子电路；
所述数据写入子电路分别与所述第一栅极信号端、所述第二栅极信号端、所述数据信号端和所述第一节点耦接，所述数据写入子电路用于响应于所述第一栅极驱动信号和所述第二栅极驱动信号，控制所述数据信号端与所述第一节点的通断；
所述补偿子电路分别与所述第三栅极信号端、所述第二节点和所述第三节点耦接，所述补偿子电路用于响应于所述第三栅极驱动信号，控制所述第二节点与所述第三节点的通断。
可选的，所述数据写入子电路包括：第一数据写入单元和第二数据写入单元；
所述第一数据写入单元分别与所述第一栅极信号端、所述数据信号端和所述第一节点耦接，所述第一数据写入单元用于响应于所述第一栅极驱动信号，控制所述数据信号端与所述第一节点的通断；
所述第二数据写入单元分别与所述第二栅极信号端、所述数据信号端和所述第一节点耦接，所述第二数据写入单元用于响应于所述第二栅极驱动信号，控制所述数据信号端与所述第一节点的通断。
可选的，所述第一数据写入单元包括：第一数据写入晶体管；所述第二数据写入单元包括：第二数据写入晶体管；
所述第一数据写入晶体管的栅极与所述第一栅极信号端耦接，所述第一数据写入晶体管的第一极与所述数据信号端耦接，所述第一数据写入晶体管的第 二极与所述第一节点耦接；
所述第二数据写入晶体管的栅极与所述第二栅极信号端耦接，所述第二数据写入晶体管的第一极与所述数据信号端耦接，所述第二数据写入晶体管的第二极与所述第一节点耦接。
可选的，所述第一数据写入晶体管和所述第二数据写入晶体管均为P型晶体管。
可选的，所述补偿子电路包括：补偿晶体管；
所述补偿晶体管的栅极与所述第三栅极信号端耦接，所述补偿晶体管的第一极与所述第三节点耦接，所述补偿晶体管的第二极与所述第二节点耦接。
可选的，所述补偿晶体管为N型晶体管。
可选的，所述驱动电路包括：驱动晶体管，且所述驱动晶体管为P型晶体管；
所述驱动晶体管的栅极与所述第二节点耦接，所述驱动晶体管的第一极与所述第一节点耦接，所述驱动晶体管的第二极与所述第三节点耦接。
可选的，所述发光控制电路包括：第一发光控制子电路、第二发光控制子电路和调节子电路；
所述第一发光控制子电路分别与所述发光控制端、所述第一电源端和所述第一节点耦接，所述第一发光控制子电路用于响应于所述发光控制信号，控制所述第一电源端与所述第一节点的通断；
所述第二发光控制子电路分别与所述发光控制端、所述第三节点和所述发光元件的第一极耦接，所述发光元件的第二极与第二电源端耦接，所述第二发光控制子电路用于响应于所述发光控制信号，控制所述第三节点与所述发光元件的第一极的通断；
所述调节子电路分别与所述第二节点和所述第一电源端耦接，所述调节子电路用于基于所述第一电源信号，调节所述第二节点的电位。
可选的，所述第一发光控制子电路包括：第一发光控制晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；且所述第一发光控制晶体管和所述第二发光控制晶体管均为N型晶体管；所述调节子电路包括：存储电容；
所述第一发光控制晶体管的栅极与所述发光控制端耦接，所述第一发光控制晶体管的第一极与所述第一电源端耦接，所述第一发光控制晶体管的第二极 与所述第一节点耦接；
所述第二发光控制晶体管的栅极与所述发光控制端耦接，所述第二发光控制晶体管的第一极与所述第三节点耦接，所述第二发光控制晶体管的第二极与所述发光元件的第一极耦接；
所述存储电容的一端与所述第一电源端耦接，所述存储电容的另一端与所述第二节点耦接。
可选的，所述像素电路还包括：第一复位电路和第二复位电路；
所述第一复位电路分别与复位信号端、第一复位电源端和所述第二节点耦接，所述第一复位电路用于响应于所述复位信号端提供的复位信号，控制所述第一复位电源端与所述第二节点的通断；
所述第二复位电路分别与所述第一栅极信号端、第二复位电源端和所述发光元件耦接，所述第二复位电路用于响应于所述第一栅极驱动信号，控制所述第二复位电源端与所述发光元件的通断。
可选的，所述第一复位电路包括：第一复位晶体管；所述第二复位电路包括：第二复位晶体管；且，所述第一复位晶体管为N型晶体管，所述第二复位晶体管为P型晶体管；
所述第一复位晶体管的栅极与所述复位信号端耦接，所述第一复位晶体管的第一极与所述第一复位电源端耦接，所述第一复位晶体管的第二极与所述第二节点耦接；
所述第二复位晶体管的栅极与所述第一栅极信号端耦接，所述第二复位晶体管的第一极与所述第二复位电源端耦接，所述第二复位晶体管的第二极与所述发光元件耦接。
另一方面，提供了一种像素电路的驱动方法，用于驱动如上述方面所述的像素电路，所述方法包括：在多帧扫描中的刷新帧依次执行的第一阶段和第二阶段，以及在所述多帧扫描中的保持帧依次执行的第三阶段和所述第二阶段；
在所述第一阶段，发光控制端提供的发光控制信号的电位、第二栅极信号端提供的第二栅极驱动信号的电位和第三栅极信号端提供的第三栅极驱动信号的电位均为第一电位，第一栅极信号端提供的第一栅极驱动信号的电位为第二电位，数据写入电路响应于所述第一栅极驱动信号，控制数据信号端与第一节点导通，且响应于所述第三栅极驱动信号，控制第二节点与第三节点导通；
在所述第二阶段，所述第一栅极驱动信号的电位和所述第二栅极驱动信号的电位均为第一电位，所述发光控制信号的电位和所述第三栅极驱动信号的电位均为第二电位，发光控制电路响应于所述发光控制信号，控制第一电源端与所述第一节点导通，且控制所述第三节点与发光元件导通，驱动电路基于所述第一节点的电位和所述第二节点的电位，向所述第三节点传输发光驱动信号；
在所述第三阶段，所述发光控制信号的电位和所述第一栅极驱动信号的电位均为第一电位，所述第二栅极驱动信号的电位和所述第三栅极驱动信号的电位均为第二电位，所述数据写入电路响应于所述第二栅极驱动信号，控制所述数据信号端与所述第一节点导通。
可选的，所述方法还包括：在所述刷新帧中，第一阶段之前执行的第四阶段；
在所述第四阶段，复位信号端提供的复位信号的电位、所述发光控制信号的电位、所述第一栅极驱动信号的电位和所述第二栅极驱动信号的电位均为第一电位，所述第三栅极驱动信号的电位为第二电位，第一复位电路响应于所述复位信号，控制第一复位电源端与所述第二节点导通；
以及，在所述第一阶段，第二复位电路响应于所述第一栅极驱动信号，控制第二复位电源端与所述发光元件导通。
又一方面，提供了一种显示装置，所述显示装置包括：显示面板，显示驱动电路，以及位于所述显示面板上的多个像素，所述像素包括：发光元件，以及如上述方面所述的像素电路；
其中，所述显示驱动电路与所述像素电路耦接的各个信号端耦接，所述显示驱动电路用于向所述各个信号端提供信号；
所述像素电路与所述发光元件耦接，所述像素电路用于向所述发光元件传输发光驱动信号，所述发光元件用于基于所述发光驱动信号发光。
综上所述，本公开实施例提供的技术方案带来的有益效果至少可以包括：
提供了一种像素电路及其驱动方法、显示装置。该像素电路中，数据写入电路与三个栅极信号端耦接，并在该三个栅极信号端提供的栅极驱动信号控制下，控制第一节点、第二节点和第三节点的电位。驱动电路可以基于第一节点和第二节点的电位，向第三节点传输发光驱动信号。发光控制电路可以控制第三节点与发光元件导通，以使得发光驱动信号进一步传输至发光元件，从而点 亮发光元件。并且，存在两个栅极信号端与第二节点之间分别形成寄生电容。如此，可以通过灵活调节该两个栅极信号端提供的栅极驱动信号，以使得第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发光元件的亮度相同，显示装置的显示效果较好。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素电路的结构示意图；
图2是本公开实施例提供的另一种像素电路的结构示意图；
图3是本公开实施例提供的又一种像素电路的结构示意图；
图4是本公开实施例提供的再一种像素电路的结构示意图；
图5是本公开实施例提供的再一种像素电路的结构示意图；
图6是本公开实施例提供的再一种像素电路的结构示意图；
图7是本公开实施例提供的一种像素电路的驱动方法流程图；
图8是本公开实施例提供的另一种像素电路的驱动方法流程图；
图9是本公开实施例提供的一种像素电路所耦接的各信号端时序图；
图10是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，或者，将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采 用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有有效电位和无效电位，有效电位和无效电位仅代表该信号的电位有2个状态量，不代表全文中有效电位或无效电位具有特定的数值。
目前，像素电路驱动发光元件发光至少可以划分为以下两个阶段：数据写入阶段和发光阶段。其中，在数据写入阶段，栅极信号端可以提供有效电位的栅极驱动信号，以使得数据写入电路响应于该有效电位的栅极驱动信号，向驱动电路的输入端和控制端写入数据信号端提供的数据信号。在发光阶段，栅极驱动信号的电位会由有效电位跳变为无效电位。此时，驱动电路可以基于其输入端和控制端的电位，向发光元件传输发光驱动信号，以驱动发光元件发光。
但是，受栅极信号端与驱动电路的控制端之间形成的寄生电容的耦合作用影响，驱动电路的控制端的电位会随栅极驱动信号的电位跳变而发生偏移。如，假设有效电位为高电位，无效电位为低电位，则在数据信号写入完成之后，栅极驱动信号由高电位跳变为低电位时，驱动电路的控制端的电位会在寄生电容的耦合作用下被带动拉低，发生负偏。该负偏会影响相邻两帧扫描时，像素电路驱动发光元件的发光亮度不同，造成显示装置的显示效果较差。
基于此，目前可以通过调整数据信号的电位，来改善上述实施例记载的显示均一性较差问题。如，若在当前帧驱动电路的控制端的电位被拉低，则可以通过在下一帧提高数据信号的电位，以补偿驱动电路的控制端的电位，确保两帧中，驱动电路的控制端的电位可以相对一致。但是，提高数据信号的电位无疑会造成两帧之间数据信号的电位差异较大，即数据信号的电位取值范围(data range)偏高。如此，会造成为数据信号端提供数据信号的电路(如，源极驱动电路)的功耗较高，并且增加了显示装置中显示面板(panel)的工作功耗。
并且，目前各类显示装置中的panel都可以支持一个较高的刷新率，如，120赫兹(Hz)。高刷新率虽然提高了显示装置的显示效果，但是同时也给panel的工作功耗带来了较大的挑战。以及，在panel的日常使用过程中，其实也不是一直需要保持高刷新率，比如进入阅读模式时，低刷新率一样可以满足需求。由此，在panel的开发过程中需要尽可能的从其他方面降低panel的工作功耗。
基于此，本公开实施例提供了一种像素电路，采用该像素电路的显示装置不仅显示效果较好，而且功耗较低。
图1是本公开实施例提供的一种像素电路的结构示意图。如图1所示，该像素电路包括：数据写入电路01、发光控制电路02和驱动电路03。
其中，数据写入电路01分别与第一栅极信号端Gate_P、第二栅极信号端Gate_P1、第三栅极信号端Gate_N、数据信号端Data、第一节点N1、第二节点N2和第三节点N3耦接。数据写入电路01用于响应于第一栅极信号端Gate_P提供的第一栅极驱动信号、第二栅极信号端Gate_P1提供的第二栅极驱动信号和第三栅极信号端Gate_N提供的第三栅极驱动信号，控制数据信号端Data与第一节点N1的通断，并控制第二节点N2与第三节点N3的通断。
例如，数据写入电路01可以在第一栅极信号端Gate_P提供的第一栅极驱动信号的电位为有效电位，和/或，第二栅极信号端Gate_P1提供的第二栅极驱动信号的电位为有效电位时，控制数据信号端Data与第一节点N1导通。此时，数据信号端Data提供的数据信号可以传输至第一节点N1。数据写入电路01可以在第一栅极驱动信号的电位为无效电位，和，第二栅极驱动信号的电位为无效电位时，控制数据信号端Data与第一节点N1断开耦接。
同理，数据写入电路01可以在第三栅极信号端Gate_N提供的第三栅极驱动信号的电位为有效电位时，控制第二节点N2与第三节点N3导通。此时，第二节点N2的电位和第三节点N3的电位可以相互影响。以及，数据写入电路01可以在第三栅极驱动信号的电位为无效电位时，控制第二节点N2与第三节点N3断开耦接。
可选的，数据写入电路01可以包括分别与第一栅极信号端Gate_P、第二栅极信号端Gate_P1和第三栅极信号端Gate_N耦接的三个晶体管。且该三个晶体管中，耦接第一栅极信号端Gate_P的晶体管和耦接第二栅极信号端Gate_P1的晶体管可以均为P型晶体管，耦接第三栅极信号端Gate_N的晶体管可以为N型晶体管。在此基础上，第一栅极驱动信号的无效电位和第二栅极驱动信号的无效电位可以为高电位，第一栅极驱动信号的有效电位和第二栅极驱动信号的有效电位可以为低电位。第三栅极驱动信号的无效电位可以为低电位，第三栅极驱动信号的有效电位可以为高电位。在本公开下述实施例中，高电位可以称为第一电位，低电位可以称为第二电位。
参考图1可知，在本公开实施例新增第二栅极信号端Gate_P1后，不仅第三栅极信号端Gate_N与第二节点N2之间会形成有第二寄生电容C2，且第二栅极信号端Gate_P1与第二节点N2之间形成有第一寄生电容C1。如此，在第二寄生电容C2的耦接作用下，第二节点N2的电位会随着第三栅极驱动信号的电位跳变发生偏移。以及，在第一寄生电容C1的耦接作用下，第二节点N2的电位会随着第二栅极驱动信号的电位跳变发生偏移。基于此，可以通过灵活调节第二栅极驱动信号的电位和第三栅极驱动信号的电位，使得第二节点N2的电位能够在不同阶段分别发生正向偏移(即，电位增大)和负向偏移(即，电位较小)，确保第二节点N2的电位最终保持在一个稳定的电位下，从而解决了上述实施例记载的显示不均一问题。并且，在第二节点N2的电位保持稳定基础上，两帧之间数据信号端Data所需提供的数据信号的电位范围可以相对保持一致，即减小了data range。进而，相对于相关技术，即有效降低了为数据信号端Data提供数据信号的源极驱动电路的功耗，并且降低了panel的工作功耗。
示例的，在本公开实施例中，在panel采用低频刷新模式时，可以将多帧扫描划分为刷新帧和保持帧，刷新帧中进行刷新扫描，保持帧中不进行刷新扫描，仅进行显示。在刷新帧中，可以控制第一栅极驱动信号的电位为低电位，且控制第三栅极驱动信号的电位为高电位，以向第一节点N1和第二节点N2写入数据信号。在数据信号写入完成之后，可以控制第一栅极驱动信号的电位跳变为高电位，且控制第三栅极驱动信号的电位跳变为低电位。此时，在第二寄生电容C2的耦合作用下，第二节点N2的电位被拉低。在保持帧中，可以控制第二栅极驱动信号的电位为低电位，以向第一节点N1写入数据信号。在数据信号写入完成之后，可以控制第二栅极驱动信号的电位跳变为高电位。此时，在第一寄生电容C1的耦合作用下，第二节点N2的电位被拉高。如此，即确保了第二节点N2的电位保持稳定。进而，确保了显示效果较好，且达到了在低刷新率模式下降低panel处于保持帧阶段的功耗的目的。
发光控制电路02分别与发光控制端EM、第一电源端VDD、第一节点N1、第三节点N3和发光元件L1耦接。发光控制电路02用于响应于发光控制端EM提供的发光控制信号，控制第一电源端VDD与第一节点N1的通断，且控制第三节点N3与发光元件L1的通断。
例如，发光控制电路02可以在发光控制信号的电位为第一电位时，控制第 一电源端VDD与第一节点N1导通，且控制第三节点N3与发光元件L1导通。此时，第一电源端VDD提供的第一电源信号可以传输至第一节点N1，且第三节点N3的电位可以传输至发光元件L1。以及，发光控制电路02可以在发光控制信号的电位为第二电位时，控制第一电源端VDD与第一节点N1断开耦接，且控制第三节点N3与发光元件L1断开耦接。
可选的，发光控制电路02可以是与发光元件L1的第一极耦接，发光元件L1的第二极可以与第二电源端VSS耦接。且，如图1所示，发光元件L1的第一极可以为阳极(Anode)，发光元件L1的第二极可以为阴极(Cathode)。当然，在一些其他实施例中，发光元件L1的第一极可以为阴极，相应的，发光元件L1的第二极可以为阳极。
驱动电路03的输入端、控制端和输出端分别与第一节点N1、第二节点N2和第三节点N3耦接。即，驱动电路03的输入端可以与第一节点N1耦接，驱动电路03的控制端可以与第二节点N2耦接，驱动电路03的输出端可以与第三节点N3耦接。驱动电路03用于基于第一节点N1的电位和第二节点N2的电位，向第三节点N3传输发光驱动信号(如，驱动电流)。
在发光控制电路02控制第三节点N3与发光元件L1的阳极导通后，该发光驱动信号即可以经发光控制电路02传输至发光元件L1的阳极。发光元件L1可以在该发光驱动信号和其阴极耦接的第二电源端VSS提供的第二电源信号的压差作用下发光。需要说明的是，因发光驱动信号是经发光控制电路02传输至发光元件L1的阳极，故最终传输至发光元件L1阳极的发光驱动信号的电位，与驱动电路03基于第一节点N1的电位和第二节点N2的电位生成的发光驱动信号的电位可以不同。
综上所述，本公开实施例提供了一种像素电路。该像素电路中，数据写入电路与三个栅极信号端耦接，并在该三个栅极信号端提供的栅极驱动信号控制下，控制第一节点、第二节点和第三节点的电位。驱动电路可以基于第一节点和第二节点的电位，向第三节点传输发光驱动信号。发光控制电路可以控制第三节点与发光元件导通，以使得发光驱动信号进一步传输至发光元件，从而点亮发光元件。并且，存在两个栅极信号端与第二节点之间分别形成寄生电容。如此，可以通过灵活调节该两个栅极信号端提供的栅极驱动信号，以使得第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发 光元件的亮度相同，显示装置的显示效果较好。
图2是本公开实施例提供的另一种像素电路的结构示意图。如图2所示，像素电路中的数据写入电路01可以包括：数据写入子电路011和补偿子电路012。
其中，数据写入子电路011可以分别与第一栅极信号端Gate_P、第二栅极信号端Gate_P1、数据信号端Data和第一节点N1耦接。数据写入子电路011用于响应于第一栅极驱动信号和第二栅极驱动信号，控制数据信号端Data与第一节点N1的通断。
例如，数据写入子电路011可以在第一栅极驱动信号的电位为有效电位，和/或，第二栅极驱动信号的电位为有效电位时，控制数据信号端Data与第一节点N1导通，以使数据信号传输至第一节点N1。以及，数据写入子电路011可以在第一栅极驱动信号的电位为无效电位，和，第二栅极驱动信号的电位为无效电位时，控制数据信号端Data与第一节点N1断开耦接。
补偿子电路012分别与第三栅极信号端Gate_N、第二节点N2和第三节点N3耦接。补偿子电路012用于响应于第三栅极驱动信号，控制第二节点N2与第三节点N3的通断。
例如，补偿子电路012可以在第三栅极驱动信号的电位为有效电位时，控制第二节点N2与第三节点N3导通，以基于第三节点N3的电位对第二节点N2的电位进行补偿。以及，补偿子电路012可以在第三栅极驱动信号的电位为无效电位时，控制第二节点N2与第三节点N3断开耦接。
图3是本公开实施例提供的又一种像素电路的结构示意图。如图3所示，数据写入电路01中的数据写入子电路011可以包括：第一数据写入单元0111和第二数据写入单元0112。
其中，第一数据写入单元0111可以分别与第一栅极信号端Gate_P、数据信号端Data和第一节点N1耦接。第一数据写入单元0111可以用于响应于第一栅极驱动信号，控制数据信号端Data与第一节点N1的通断。
例如，第一数据写入单元0111可以在第一栅极驱动信号的电位为有效电位时，控制数据信号端Data与第一节点N1导通。以及，第一数据写入单元0111可以在第一栅极驱动信号的电位为无效电位时，控制数据信号端Data与第一节 点N1断开耦接。
第二数据写入单元0112可以分别与第二栅极信号端Gate_P1、数据信号端Data和第一节点N1耦接。第二数据写入单元0112可以用于响应于第二栅极驱动信号，控制数据信号端Data与第一节点N1的通断。
例如，第二数据写入单元0112可以在第二栅极驱动信号的电位为有效电位时，控制数据信号端Data与第一节点N1导通。以及，第二数据写入单元0112可以在第二栅极驱动信号的电位为无效电位时，控制数据信号端Data与第一节点N1断开耦接。
图4是本公开实施例提供的再一种像素电路的结构示意图。如图4所示，该发光控制电路02可以包括：第一发光控制子电路021、第二发光控制子电路022和调节子电路023。
其中，第一发光控制子电路021可以分别与发光控制端EM、第一电源端VDD和第一节点N1耦接。第一发光控制子电路021可以用于响应于发光控制信号，控制第一电源端VDD与第一节点N1的通断。
例如，第一发光控制子电路021可以在发光控制信号的电位为有效电位时，控制第一电源端VDD与第一节点N1导通，以使第一电源端VDD提供的第一电源信号可以传输至第一节点N1。以及，第一发光控制子电路021可以在发光控制信号的电位为无效电位时，控制第一电源端VDD与第一节点N1断开耦接。
第二发光控制子电路022可以分别与发光控制端EM、第三节点N3和发光元件L1的第一极耦接，发光元件L1的第二极与第二电源端VSS耦接。第二发光控制子电路022可以用于响应于发光控制信号，控制第三节点N3与发光元件L1的第一极的通断。如上述实施例记载，发光元件L1的第一极可以为阳极，发光元件L1的第二极可以为阴极。
例如，第二发光控制子电路022可以在发光控制信号的电位为有效电位时，控制第三节点N3与发光元件L1的第一极导通，以使第三节点N3的电位传输至发光元件L1的第一极，驱动发光元件L1发光。以及，第二发光控制子电路022可以在发光控制信号的电位为无效电位时，控制第三节点N3与发光元件L1的第一极断开耦接。
可选的，在本公开实施例中，第一电源信号的电位可以为高电位，第二电源信号的电位可以为低电位。
调节子电路023可以分别与第二节点N2和第一电源端VDD耦接。调节子电路023可以用于基于第一电源信号，调节第二节点N2的电位。
图5是本公开实施例提供的再一种像素电路的结构示意图。如图5所示，像素电路还可以包括：第一复位电路04和第二复位电路05。
其中，第一复位电路04可以分别与复位信号端Rst、第一复位电源端Vinit1和第二节点N2耦接。第一复位电路04可以用于响应于复位信号端Rst提供的复位信号，控制第一复位电源端Vinit1与第二节点N2的通断。
例如，第一复位电路04可以在复位信号的电位为有效电位时，控制第一复位电源端Vinit1与第二节点N2导通。此时，第一复位电源端Vinit1提供的第一复位电源信号可以传输至第二节点N2，以实现对第二节点N2的复位。以及，第一复位电路04可以在复位信号的电位为无效电位时，控制第一复位电源端Vinit1与第二节点N2断开耦接。
第二复位电路05可以分别与第一栅极信号端Gate_P、第二复位电源端Vinit2和发光元件L1耦接。第二复位电路05可以用于响应于第一栅极驱动信号，控制第二复位电源端Vinit2与发光元件L1的通断。
例如，第二复位电路05可以与发光元件L1的阳极耦接。第二复位电路05可以在第一栅极驱动信号的电位为有效电位时，控制第二复位电源端Vinit2与发光元件L1的阳极导通。此时，第二复位电源端Vinit2提供的第二复位电源信号即可以传输至发光元件L1的阳极，以实现对发光元件L1的阳极的复位。以及，第二复位电路05可以在第一栅极驱动信号的电位为无效电位时，控制第二复位电源端Vinit2与发光元件L1的阳极断开耦接。
可选的，在本公开实施例中，第一复位电源信号的电位和第二复位电源信号的电位可以均为低电位。且，第一复位电源信号的电位可以小于等于第二复位电源信号的电位。当然，在一些其他实施例中，第一复位电源信号的电位也可以大于第二复位电源信号的电位。
图6是本公开实施例提供的再一种像素电路的结构示意图。如图6所示，第一数据写入单元0111可以包括：第一数据写入晶体管T1。第二数据写入单元0112可以包括：第二数据写入晶体管T2。补偿子电路012可以包括：补偿晶体管T3。驱动电路03可以包括：驱动晶体管T4。第一发光控制子电路021可以包括：第一发光控制晶体管T5，第二发光控制子电路022可以包括：第二发光 控制晶体管T6，调节子电路023可以包括：存储电容Cst。第一复位电路04可以包括：第一复位晶体管T7。第二复位电路05可以包括：第二复位晶体管T8。
其中，第一数据写入晶体管T1的栅极可以与第一栅极信号端Gate_P耦接，第一数据写入晶体管T1的第一极可以与数据信号端Data耦接，第一数据写入晶体管T1的第二极可以与第一节点N1耦接。
第二数据写入晶体管T2的栅极可以与第二栅极信号端Gate_P1耦接，第二数据写入晶体管T2的第一极可以与数据信号端Data耦接，第二数据写入晶体管T2的第二极可以与第一节点N1耦接。
基于此，结合上述实施例记载，在刷新帧时，可以控制第一栅极驱动信号的电位为低电位，且控制第二栅极驱动信号的电位为高电位，以使得第一数据写入晶体管T1开启，第二数据写入晶体管T2关断。此时，数据信号可以经开启的第一数据写入晶体管T1传输至第一节点N1，实现数据信号的写入。在保持帧时，可以控制第一栅极驱动信号的电位为高电位，且控制第二栅极驱动信号的电位为低电位，以使得第一数据写入晶体管T1关断，第二数据写入晶体管T2开启。此时，数据信号可以经开启的第二数据写入晶体管T2传输至第一节点N1，实现数据信号的写入。换言之，此时可以使得数据信号端Data转接第二数据写入晶体管T2，以与第一节点N1导通。随后，在数据写入完成后，可以控制第二栅极驱动信号的电位为高电位，从而使得第二节点N2的电位在第一寄生电容C1的耦合作用下被拉高，以与在第三栅极驱动信号的电位跳变带动下第二节点N2的电位被拉低相互抵消，确保第二节点N2的电位稳定性。
补偿晶体管T3的栅极可以与第三栅极信号端Gate_N耦接，补偿晶体管T3的第一极可以与第三节点N3耦接，补偿晶体管T3的第二极可以与第二节点N2耦接。
驱动晶体管T4的栅极可以与第二节点N2耦接，驱动晶体管T4的第一极可以与第一节点N1耦接，驱动晶体管T4的第二极可以与第三节点N3耦接。
即，驱动晶体管T4的栅极可以为驱动电路03的控制端，驱动晶体管T4的第一极可以为驱动电路03的输入端，驱动晶体管T4的第二极可以为驱动电路03的输出端。
第一发光控制晶体管T5的栅极与发光控制端EM耦接，第一发光控制晶体管T5的第一极与第一电源端VDD耦接，第一发光控制晶体管T5的第二极与第 一节点N1耦接。
第二发光控制晶体管T6的栅极与发光控制端EM耦接，第二发光控制晶体管T6的第一极与第三节点N3耦接，第二发光控制晶体管T6的第二极与发光元件L1的第一极耦接。
存储电容Cst的一端与第一电源端VDD耦接，存储电容Cst的另一端与第二节点N2耦接。
第一复位晶体管T7的栅极与复位信号端Rst耦接，第一复位晶体管的第一极T7与第一复位电源端Vinit1耦接，第一复位晶体管T7的第二极与第二节点N2耦接。
第二复位晶体管T8的栅极与第一栅极信号端Gate_P耦接，第二复位晶体管T8的第一极与第二复位电源端Vinit2耦接，第二复位晶体管T8的第二极与发光元件L1耦接。
并且，如上述实施例记载，第一数据写入晶体管T1和第二数据写入晶体管T2可以均为P型晶体管。补偿晶体管T3可以为N型晶体管。以及，在本公开实施例中，第一发光控制晶体管T5和第二发光控制晶体管T6可以均为N型晶体管。驱动晶体管T4可以为P型晶体管。第一复位晶体管T7可以为N型晶体管，第二复位晶体管T8为P型晶体管。在此基础上，发光控制信号的有效电位和复位信号的有效电位可以均为高电位，发光控制信号的无效电位和复位信号的无效电位可以均为低电位。
可选的，在本公开实施例中，像素电路包括的P型晶体管可以均为低温多晶硅(low temperature poly-silicon，LTPS)材料制成的晶体管，N型晶体管可以均为氧化物(oxide)材料制成的晶体管。相应的，像素电路可以为低温多晶硅氧化物LTPO像素电路。氧化物材料可以包括：铟镓锌氧化物(indium gallium zinc oxide，IGZO)材料。此处晶体管的材料是指晶体管包括的有源层的材料。
需要说明的是，在能够稳定第二节点N2的电位前提下，本公开实施例记载的像素电路除了可以为图6所示的8T1C(即，包括8个晶体管和1个电容)结构之外，还可以为包括其他数量的晶体管的结构。如可以为6T1C结构。本公开实施例对此不做限定。
还需要说明的是，像素电路包括的各个晶体管的类型可以如上述实施例记载。当然，在一些其他实施例中，像素电路包括的各个晶体管类型也可以满足 其他选择。如，第一复位晶体管T7可以为P型晶体管。但是，无论是满足何种选择，对于P型晶体管而言，有效电位相对于无效电位均为低电位；对于N型晶体管而言，有效电位相对于无效电位均为高电位。
综上所述，本公开实施例提供了一种像素电路。该像素电路中，数据写入电路与三个栅极信号端耦接，并在该三个栅极信号端提供的栅极驱动信号控制下，控制第一节点、第二节点和第三节点的电位。驱动电路可以基于第一节点和第二节点的电位，向第三节点传输发光驱动信号。发光控制电路可以控制第三节点与发光元件导通，以使得发光驱动信号进一步传输至发光元件，从而点亮发光元件。并且，存在两个栅极信号端与第二节点之间分别形成寄生电容。如此，可以通过灵活调节该两个栅极信号端提供的栅极驱动信号，以使得第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发光元件的亮度相同，显示装置的显示效果较好。
图7是本公开实施例提供的一种像素电路的驱动方法流程图，该方法可以用于驱动如图1至图6任一所示的像素电路。如图7所示，该方法包括：在多帧扫描中的刷新帧依次执行的第一阶段和第二阶段，以及在多帧扫描中的保持帧依次执行的第三阶段和第二阶段。如，假设共60帧，则可以划分30帧为刷新帧，30帧为保持帧。
步骤701、在第一阶段，发光控制端提供的发光控制信号的电位、第二栅极信号端提供的第二栅极驱动信号的电位和第三栅极信号端提供的第三栅极驱动信号的电位均为第一电位，第一栅极信号端提供的第一栅极驱动信号的电位为第二电位，数据写入电路响应于第一栅极驱动信号，控制数据信号端与第一节点导通，且响应于第三栅极驱动信号，控制第二节点与第三节点导通。
步骤702、在第二阶段，第一栅极驱动信号的电位和第二栅极驱动信号的电位均为第一电位，发光控制信号的电位和第三栅极驱动信号的电位均为第二电位，发光控制电路响应于发光控制信号，控制第一电源端与第一节点导通，且控制第三节点与发光元件导通，驱动电路基于第一节点的电位和第二节点的电位，向第三节点传输发光驱动信号。
步骤703、在第三阶段，发光控制信号的电位和第一栅极驱动信号的电位均为第一电位，第二栅极驱动信号的电位和第三栅极驱动信号的电位均为第二电 位，数据写入电路响应于第二栅极驱动信号，控制数据信号端与第一节点导通。
可选的，如上述实施例记载，方法中，第一电位可以是指高电位，第二电位可以是指低电位。
综上所述，本公开实施例提供了一种像素电路的驱动方法。该方法中，刷新帧包括的第一阶段至第二阶段中，第三栅极信号端提供的第三栅极驱动信号的电位由第一电位跳变为第二电位，由此在第三栅极信号端与第二节点形成的寄生电容耦合作用下，第二节点的电位会被带动发生第一次偏移。保持帧包括的第三阶段至第二阶段中，第二栅极信号端提供的第二栅极驱动信号的电位由第二电位跳变为第一电位，由此在第二栅极信号端与第二节点形成的寄生电容耦合作用下，第二节点的电位会被带动发生第一次偏移。因第一次偏移是在第一电位跳变为第二电位带动下发生，第二次偏移是在第二电位跳变为第一电位时发生，故可以确保第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发光元件的亮度相同，显示装置的显示效果较好。
图8是本公开实施例提供的另一种像素电路的驱动方法流程图。如图8所示，该方法还可以包括：在刷新帧中，第一阶段之前执行的第四阶段，即还包括下述步骤704。
步骤704、在第四阶段，复位信号端提供的复位信号的电位、发光控制信号的电位、第一栅极驱动信号的电位和第二栅极驱动信号的电位均为第一电位，第三栅极驱动信号的电位为第二电位，第一复位电路响应于复位信号，控制第一复位电源端与第二节点导通。
以及，在第一阶段(即，在步骤701中)，第二复位电路响应于第一栅极驱动信号，控制第二复位电源端与发光元件导通。
以图6所示像素电路，且第一电位为高电位，第二电位为低电位为例，对本公开实施例记载的像素电路的驱动原理进行如下说明。图9示出了本公开实施例提供的一种像素电路所耦接的各信号端的时序图。参考图9可以看出，刷新帧之后可以进入保持帧，且刷新帧共包括依次执行的第四阶段t4、第一阶段t1和第二阶段t2；保持帧共包括依次执行的第三阶段t3和第二阶段t2。
其中，在第四阶段t4，发光控制端EM提供的发光控制信号的电位，复位信号端Rst提供的复位信号的电位，第一栅极信号端Gate_P提供的第一栅极驱动信号的电位，以及第二栅极信号端Gate_P1提供的第二栅极驱动信号的电位 均为高电位(即，第一电位)，仅第三栅极信号端Gate_N提供的第三栅极驱动信号的电位为低电位(即，第二电位)。相应的，仅第一复位晶体管T7开启，第一数据写入晶体管T1、第二数据写入晶体管T2、补偿晶体管T3、第一发光控制晶体管T5、第六发光控制晶体管T6和第二复位晶体管T8均关断。在此基础上，第一复位电源端Vinit1提供的低电位的第一复位电源信号可以经开启的第一复位晶体管T7传输至第二节点N2，以实现对第二节点N2的复位，进而驱动晶体管T4开启。该第四阶段t4也可以称为对第二节点N2复位的复位阶段。
在第一阶段t1，发光控制信号的电位、第二栅极驱动信号的电位和第三栅极驱动信号的电位均为高电位，复位信号的电位和第一栅极驱动信号的电位为低电位。相应的，第一数据写入晶体管T1、第二复位晶体管T8和补偿晶体管T3均开启，第二数据写入晶体管T2、第一发光控制晶体管T5、第六发光控制晶体管T6和第一复位晶体管T均关断。且在存储电容Cst的存储作用下，第二节点N2的电位先保持为上一阶段t4的低电位，驱动晶体管T4保持开启。在此基础上，第二复位电源端Vinit提供的低电位的第二复位电源信号可以经开启的第二复位晶体管T8传输至发光元件L1的阳极，以实现对发光元件L1的阳极的复位。以及，数据信号端Data提供的数据信号可以经开启的第一数据写入晶体管T1传输至第一节点N1，第一节点N1的电位可以再经开启的驱动晶体管T4传输至第三节点N3，第三节点N3的电位可以再经开启的补偿晶体管T3传输至第二节点N2。由此，即达到了将数据信号写入至第二节点N2的目的。该第一阶段t1也可以称为数据写入阶段，以及对发光元件L1复位的复位阶段。
在第二阶段t2，第一栅极驱动信号的电位和第二栅极驱动信号的电位均为高电位，发光控制信号的电位、复位信号的电位和第三栅极驱动信号的电位均为低电位。相应的，第一发光控制晶体管T5和第二发光控制晶体管T6均开启，且第一数据写入晶体管T1、第二数据写入晶体管T2、补偿晶体管T3、第一复位晶体管T7和第二复位晶体管T8均关断。且在存储电容Cst的存储作用下，第二节点N2的电位先保持为上一阶段t4的低电位，驱动晶体管T4保持开启。在此基础上，第一电源端VDD提供的高电位的第一电源信号可以经开启的第一发光控制晶体管T5传输至第一节点N1，且第三节点N3与发光元件L1的阳极导通，第一电源端VDD和第二电源端VSS之间形成通路。驱动晶体管T4可以基于第一节点N1的电位和第二节点N2的电位，向第三节点N3传输发光驱动 信号。该发光驱动信号再经开启的第二发光控制晶体管T6传输至发光元件L1的阳极，发光元件L1发光。该第二阶段t2也可以称为发光阶段。
在第三阶段t3，发光控制信号的电位和第一栅极驱动信号的电位均为高电位，复位信号的电位、第二栅极驱动信号的电位和第三栅极驱动信号的电位均为低电位。相应的，第二数据写入晶体管T2开启，第一数据写入晶体管T1、补偿晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7和第二复位晶体管T8均关断。且，在存储电容Cst的存储作用下，驱动晶体管T4保持开启。数据信号端Data提供的数据信号可以经开启的第二数据写入晶体管T2传输至第一节点N1。该第三阶段t3也可以称为保持帧中的数据写入阶段。以及，在第三阶段t3之后执行的第二阶段t2。
参考上述针对各个阶段的记载可以进一步确定，刷新帧中，数据信号端Data是通过耦接第一栅极信号端Gate_P的第一数据写入晶体管T1与第一节点N1导通，并通过第一数据写入晶体管T1向第一节点N1传输数据信号。保持帧中，数据信号端Data转接至通过耦接第二栅极信号端Gate_P1的第二数据写入晶体管T2与第一节点N1导通，并通过第二数据写入晶体管T2向第一节点N1传输数据信号。以及，在刷新帧的第一阶段t1至第二阶段t2，第三栅极驱动信号的电位由高电位跳变为低电位，进而在第二寄生电容C2的耦合作用下，第二节点N2的电位被拉低。在保持帧的第三阶段t3至第二阶段t2，第二栅极驱动信号的电位由低电位跳变为高电位，进而在第一寄生电容C1的耦合作用下，第二节点N2的电位被拉高。由此，第二节点N2的电位保持稳定。本公开实施例是利用低刷新率模式下刷新帧至保持帧，切换不同的数据信号导入晶体管(即，切换不同的数据写入晶体管)，以降低data range，节省功耗。
需要说明的是，从图9还可以看出，在第一阶段t1，第三栅极驱动信号处于高电位(即，有效电位)的持续时长大于第一栅极驱动信号处于低电位(即，有效电位)的持续时长。第三栅极驱动信号处于有效电位的持续时长决定了刷新率，持续时长越长，刷新率越高。
综上所述，本公开实施例提供了一种像素电路的驱动方法。该方法中，刷新帧包括的第一阶段至第二阶段中，第三栅极信号端提供的第三栅极驱动信号的电位由第一电位跳变为第二电位，由此在第三栅极信号端与第二节点形成的寄生电容耦合作用下，第二节点的电位会被带动发生第一次偏移。保持帧包括 的第三阶段至第二阶段中，第二栅极信号端提供的第二栅极驱动信号的电位由第二电位跳变为第一电位，由此在第二栅极信号端与第二节点形成的寄生电容耦合作用下，第二节点的电位会被带动发生第一次偏移。因第一次偏移是在第一电位跳变为第二电位带动下发生，第二次偏移是在第二电位跳变为第一电位时发生，故可以确保第二节点的电位保持稳定。进而，可以使得像素电路在不同帧驱动发光元件时，发光元件的亮度相同，显示装置的显示效果较好。
图10是本公开实施例提供的一种显示装置的结构示意图。如图10所示，该显示装置包括：显示面板10，显示驱动电路20，以及位于显示面板10上的多个像素P1，且像素P1可以包括：发光元件L1，以及如图1至图6任一所示的像素电路00。
其中，显示驱动电路10可以与像素电路00耦接的各个信号端耦接。显示驱动电路10用于向各个信号端提供信号。
像素电路00可以与发光元件L1耦接。像素电路00可以用于向发光元件L1传输发光驱动信号，发光元件L1可以用于基于该发光驱动信号发光。
可选的，显示驱动电路10可以包括栅极驱动电路和源极驱动电路。栅极驱动电路可以与栅极信号端耦接，并用于向栅极信号端提供栅极驱动信号。源极驱动电路可以与数据信号端耦接，并用于向数据信号端提供数据信号。
可选的，显示装置可以为：OLED显示装置、有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、手机、平板电脑、柔性显示装置、电视机和显示器等任何具有显示功能的产品或部件。
本公开的实施方式部分使用的术语仅用于对本公开的实施例进行解释，而非旨在限定本公开。除非另作定义，本公开的实施方式使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
如，本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”或者“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。
同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。
“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前 面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。
“上”、“下”、“左”或者“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。“连接”或者“耦接”是指电连接。
“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的栅极驱动电路、移位寄存器单元、各电路和子电路的具体工作过程，可以参考方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种像素电路，所述像素电路包括：
    数据写入电路，分别与第一栅极信号端、第二栅极信号端、第三栅极信号端、数据信号端、第一节点、第二节点和第三节点耦接，所述数据写入电路用于响应于所述第一栅极信号端提供的第一栅极驱动信号、所述第二栅极信号端提供的第二栅极驱动信号和所述第三栅极信号端提供的第三栅极驱动信号，控制所述数据信号端与所述第一节点的通断，且控制所述第二节点与所述第三节点的通断，所述第二栅极信号端与所述第二节点之间形成有第一寄生电容，且所述第三栅极信号端与所述第二节点之间形成有第二寄生电容；
    发光控制电路，分别与发光控制端、第一电源端、所述第一节点、所述第三节点和发光元件耦接，所述发光控制电路用于响应于所述发光控制端提供的发光控制信号，控制所述第一电源端与所述第一节点的通断，且控制所述第三节点与所述发光元件的通断；
    驱动电路，所述驱动电路的输入端、控制端和输出端分别与所述第一节点、所述第二节点和所述第三节点耦接，所述驱动电路用于基于所述第一节点的电位和所述第二节点的电位，向所述第三节点传输发光驱动信号。
  2. 根据权利要求1所述的像素电路，其中，所述数据写入电路包括：数据写入子电路和补偿子电路；
    所述数据写入子电路分别与所述第一栅极信号端、所述第二栅极信号端、所述数据信号端和所述第一节点耦接，所述数据写入子电路用于响应于所述第一栅极驱动信号和所述第二栅极驱动信号，控制所述数据信号端与所述第一节点的通断；
    所述补偿子电路分别与所述第三栅极信号端、所述第二节点和所述第三节点耦接，所述补偿子电路用于响应于所述第三栅极驱动信号，控制所述第二节点与所述第三节点的通断。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入子电路包括：第一数据写入单元和第二数据写入单元；
    所述第一数据写入单元分别与所述第一栅极信号端、所述数据信号端和所述第一节点耦接，所述第一数据写入单元用于响应于所述第一栅极驱动信号，控制所述数据信号端与所述第一节点的通断；
    所述第二数据写入单元分别与所述第二栅极信号端、所述数据信号端和所述第一节点耦接，所述第二数据写入单元用于响应于所述第二栅极驱动信号，控制所述数据信号端与所述第一节点的通断。
  4. 根据权利要求3所述的像素电路，其中，所述第一数据写入单元包括：第一数据写入晶体管；所述第二数据写入单元包括：第二数据写入晶体管；
    所述第一数据写入晶体管的栅极与所述第一栅极信号端耦接，所述第一数据写入晶体管的第一极与所述数据信号端耦接，所述第一数据写入晶体管的第二极与所述第一节点耦接；
    所述第二数据写入晶体管的栅极与所述第二栅极信号端耦接，所述第二数据写入晶体管的第一极与所述数据信号端耦接，所述第二数据写入晶体管的第二极与所述第一节点耦接。
  5. 根据权利要求4所述的像素电路，其中，所述第一数据写入晶体管和所述第二数据写入晶体管均为P型晶体管。
  6. 根据权利要求2至5任一所述的像素电路，其中，所述补偿子电路包括：补偿晶体管；
    所述补偿晶体管的栅极与所述第三栅极信号端耦接，所述补偿晶体管的第一极与所述第三节点耦接，所述补偿晶体管的第二极与所述第二节点耦接。
  7. 根据权利要求6所述的像素电路，其中，所述补偿晶体管为N型晶体管。
  8. 根据权利要求1至7任一所述的像素电路，其中，所述驱动电路包括：驱动晶体管，且所述驱动晶体管为P型晶体管；
    所述驱动晶体管的栅极与所述第二节点耦接，所述驱动晶体管的第一极与所述第一节点耦接，所述驱动晶体管的第二极与所述第三节点耦接。
  9. 根据权利要求1至8任一所述的像素电路，其中，所述发光控制电路包括：第一发光控制子电路、第二发光控制子电路和调节子电路；
    所述第一发光控制子电路分别与所述发光控制端、所述第一电源端和所述第一节点耦接，所述第一发光控制子电路用于响应于所述发光控制信号，控制所述第一电源端与所述第一节点的通断；
    所述第二发光控制子电路分别与所述发光控制端、所述第三节点和所述发光元件的第一极耦接，所述发光元件的第二极与第二电源端耦接，所述第二发光控制子电路用于响应于所述发光控制信号，控制所述第三节点与所述发光元件的第一极的通断；
    所述调节子电路分别与所述第二节点和所述第一电源端耦接，所述调节子电路用于基于所述第一电源信号，调节所述第二节点的电位。
  10. 根据权利要求9所述的像素电路，其中，所述第一发光控制子电路包括：第一发光控制晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；且所述第一发光控制晶体管和所述第二发光控制晶体管均为N型晶体管；所述调节子电路包括：存储电容；
    所述第一发光控制晶体管的栅极与所述发光控制端耦接，所述第一发光控制晶体管的第一极与所述第一电源端耦接，所述第一发光控制晶体管的第二极与所述第一节点耦接；
    所述第二发光控制晶体管的栅极与所述发光控制端耦接，所述第二发光控制晶体管的第一极与所述第三节点耦接，所述第二发光控制晶体管的第二极与所述发光元件的第一极耦接；
    所述存储电容的一端与所述第一电源端耦接，所述存储电容的另一端与所述第二节点耦接。
  11. 根据权利要求1至10任一所述的像素电路，其中，所述像素电路还包括：第一复位电路和第二复位电路；
    所述第一复位电路分别与复位信号端、第一复位电源端和所述第二节点耦接，所述第一复位电路用于响应于所述复位信号端提供的复位信号，控制所述 第一复位电源端与所述第二节点的通断；
    所述第二复位电路分别与所述第一栅极信号端、第二复位电源端和所述发光元件耦接，所述第二复位电路用于响应于所述第一栅极驱动信号，控制所述第二复位电源端与所述发光元件的通断。
  12. 根据权利要求11所述的像素电路，其中，所述第一复位电路包括：第一复位晶体管；所述第二复位电路包括：第二复位晶体管；且，所述第一复位晶体管为N型晶体管，所述第二复位晶体管为P型晶体管；
    所述第一复位晶体管的栅极与所述复位信号端耦接，所述第一复位晶体管的第一极与所述第一复位电源端耦接，所述第一复位晶体管的第二极与所述第二节点耦接；
    所述第二复位晶体管的栅极与所述第一栅极信号端耦接，所述第二复位晶体管的第一极与所述第二复位电源端耦接，所述第二复位晶体管的第二极与所述发光元件耦接。
  13. 一种像素电路的驱动方法，用于驱动如权利要求1至12任一所述的像素电路，所述方法包括：在多帧扫描中的刷新帧依次执行的第一阶段和第二阶段，以及在所述多帧扫描中的保持帧依次执行的第三阶段和所述第二阶段；
    在所述第一阶段，发光控制端提供的发光控制信号的电位、第二栅极信号端提供的第二栅极驱动信号的电位和第三栅极信号端提供的第三栅极驱动信号的电位均为第一电位，第一栅极信号端提供的第一栅极驱动信号的电位为第二电位，数据写入电路响应于所述第一栅极驱动信号，控制数据信号端与第一节点导通，且响应于所述第三栅极驱动信号，控制第二节点与第三节点导通；
    在所述第二阶段，所述第一栅极驱动信号的电位和所述第二栅极驱动信号的电位均为第一电位，所述发光控制信号的电位和所述第三栅极驱动信号的电位均为第二电位，发光控制电路响应于所述发光控制信号，控制第一电源端与所述第一节点导通，且控制所述第三节点与发光元件导通，驱动电路基于所述第一节点的电位和所述第二节点的电位，向所述第三节点传输发光驱动信号；
    在所述第三阶段，所述发光控制信号的电位和所述第一栅极驱动信号的电位均为第一电位，所述第二栅极驱动信号的电位和所述第三栅极驱动信号的电 位均为第二电位，所述数据写入电路响应于所述第二栅极驱动信号，控制所述数据信号端与所述第一节点导通。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：在所述刷新帧中，第一阶段之前执行的第四阶段；
    在所述第四阶段，复位信号端提供的复位信号的电位、所述发光控制信号的电位、所述第一栅极驱动信号的电位和所述第二栅极驱动信号的电位均为第一电位，所述第三栅极驱动信号的电位为第二电位，第一复位电路响应于所述复位信号，控制第一复位电源端与所述第二节点导通；
    以及，在所述第一阶段，第二复位电路响应于所述第一栅极驱动信号，控制第二复位电源端与所述发光元件导通。
  15. 一种显示装置，所述显示装置包括：显示面板，显示驱动电路，以及位于所述显示面板上的多个像素，所述像素包括：发光元件，以及如权利要求1至12任一所述的像素电路；
    其中，所述显示驱动电路与所述像素电路耦接的各个信号端耦接，所述显示驱动电路用于向所述各个信号端提供信号；
    所述像素电路与所述发光元件耦接，所述像素电路用于向所述发光元件传输发光驱动信号，所述发光元件用于基于所述发光驱动信号发光。
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