WO2019205898A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2019205898A1
WO2019205898A1 PCT/CN2019/080831 CN2019080831W WO2019205898A1 WO 2019205898 A1 WO2019205898 A1 WO 2019205898A1 CN 2019080831 W CN2019080831 W CN 2019080831W WO 2019205898 A1 WO2019205898 A1 WO 2019205898A1
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Prior art keywords
circuit
transistor
voltage
driving
reset
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PCT/CN2019/080831
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English (en)
French (fr)
Inventor
徐映嵩
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/492,682 priority Critical patent/US11881164B2/en
Publication of WO2019205898A1 publication Critical patent/WO2019205898A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
  • Organic Light Emitting Diode (OLED) display devices are gradually gaining popularity due to their wide viewing angle, high contrast ratio, fast response speed, and higher brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, the organic light emitting diode (OLED) can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) driving and a passive matrix (PM) driving according to whether or not a switching component is introduced in each pixel unit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the driving of the thin film transistor and the storage capacitor, the current flowing through the OLED is controlled, so that the OLED is required according to the needs. Glowing.
  • AMOLED Compared with PMOLED, AMOLED requires less drive current, lower power consumption and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit including a data writing circuit, a driving circuit, a compensation circuit, and a light emitting element.
  • the driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current flowing through the first end and the second end for driving the light emitting element to emit light;
  • the data writing An input circuit is coupled to the control terminal of the drive circuit and configured to write a data signal to a control terminal of the drive circuit in response to a scan signal;
  • the first end, the second end of the driving circuit is connected and the first voltage end is connected, and is configured to store the data signal written by the data writing circuit and compensate the driving circuit and the coupling adjustment a voltage at a second end of the driving circuit;
  • the light emitting element includes a first end and a second end, the first end of the light emitting element is configured to receive the driving current, and the second end and the second end of
  • the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit.
  • the first compensation sub-circuit is coupled to the control terminal of the driving circuit and the second end of the driving circuit, and is configured to store the data signal written by the data writing circuit and to the driving circuit Performing compensation;
  • the second compensation sub-circuit is coupled to the first voltage terminal, the first end of the driving circuit, and the second end of the driving circuit, and is configured to be based on a voltage of a control terminal of the driving circuit The amount of variation coupling adjusts the voltage at the second end of the drive circuit.
  • the first compensation sub-circuit is further configured to couple a voltage of a control terminal of the driving circuit according to a voltage variation amount of the second end of the driving circuit.
  • the first compensation sub-circuit includes a first storage capacitor.
  • the first pole of the first storage capacitor is connected to the control end of the driving circuit, and the second pole of the first storage capacitor is connected to the second end of the driving circuit.
  • the second compensation sub-circuit includes a second storage capacitor.
  • the first pole of the second storage capacitor is connected to the first voltage terminal and the first end of the driving circuit, and the second pole of the second storage capacitor is connected to the second end of the driving circuit.
  • a pixel circuit provided by an embodiment of the present disclosure further includes an illumination control circuit.
  • the illumination control circuit is coupled to the second end of the drive circuit and the first end of the light emitting element, and is configured to apply the drive current to the light emitting element in response to an illumination control signal.
  • a pixel circuit provided by an embodiment of the present disclosure further includes a reset circuit.
  • the reset circuit is coupled to the reset voltage terminal and the first end of the light emitting element, and is configured to apply a reset voltage to the first end of the light emitting element in response to the reset signal; the reset signal and the scan signal Synchronize.
  • the driving circuit includes a first transistor. a gate of the first transistor as a control terminal of the driving circuit, a first pole of the first transistor as a first end of the driving circuit and configured to be connected to the first voltage terminal to receive a first And a second pole of the first transistor as a second end of the driving circuit.
  • the data writing circuit includes a second transistor.
  • a gate of the second transistor is configured to be coupled to a scan line to receive the scan signal
  • a first pole of the second transistor is configured to be coupled to a data line to receive the data signal
  • the second transistor The second pole is configured to be coupled to the control terminal of the drive circuit.
  • the light emission control circuit includes a third transistor.
  • a gate of the third transistor is configured to be coupled to an illumination control line to receive the illumination control signal, a first pole of the third transistor being configured to be coupled to a second end of the drive circuit, A second pole of the three transistor is configured to be coupled to the first end of the light emitting element.
  • the reset circuit includes a fourth transistor.
  • a gate of the fourth transistor is configured to be coupled to a reset control line to receive the reset signal, and a first pole of the fourth transistor is configured to be coupled to the reset voltage terminal to receive the reset voltage
  • the second pole of the fourth transistor is configured to be coupled to the first end of the light emitting element.
  • the reset circuit includes a fourth transistor; a gate of the fourth transistor is configured to be connected to a scan line to receive the scan signal and serve as the reset signal a first pole of the fourth transistor is configured to be coupled to the reset voltage terminal to receive the reset voltage, and a second pole of the fourth transistor is configured to be coupled to a first end of the light emitting element.
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units arranged in an array.
  • Each of the plurality of pixel units includes a pixel circuit as provided in any of the embodiments of the present disclosure.
  • a display panel further includes a plurality of scan lines corresponding to data write circuits connected to pixel circuits of each row of pixel units to provide the scan signals.
  • the plurality of scan lines are further corresponding to a reset circuit connected to a pixel circuit of each row of pixel units to provide a The scan signal is described, and the scan signal is used as the reset signal.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit for any of the pixel circuits provided by the embodiments of the present disclosure, the driving method including a compensation phase and a data writing phase.
  • the compensation phase the scan signal is input, the data writing circuit and the driving circuit are turned on, the compensation circuit compensates the driving circuit; and in the data writing phase, the scanning is input a signal and the data signal, the data writing circuit is turned on, the data writing circuit writes the data signal into the compensation circuit, and the compensation circuit is coupled according to a voltage variation of a control terminal of the driving circuit Adjusting the voltage at the second end of the drive circuit.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit, which is used in any pixel circuit provided by an embodiment of the present disclosure, where the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit
  • the driving method includes a compensation phase and a data writing phase; in the compensation phase, the scanning signal is input to turn on the data writing circuit and the driving circuit, and the first compensation sub-circuit pair
  • the drive circuit performs compensation; and in the data writing phase, the scan signal and the data signal are input to turn on the data write circuit, and the data write circuit writes the data signal into the a first compensation sub-circuit, and the second compensation sub-circuit is coupled to adjust a voltage of the second end of the driving circuit according to a voltage variation amount of a control terminal of the driving circuit.
  • the driving method further includes a light emitting phase.
  • the light emission control signal is input to turn on the light emission control circuit and the driving circuit, and the first compensation sub circuit couples the driving circuit according to a voltage variation amount of the second end of the driving circuit
  • the illumination control circuit applies the drive current to the light emitting element to cause the light emitting element to emit light.
  • 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • FIG. 2 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic block diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 4; FIG.
  • FIG. 6 is a timing diagram of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 7 to 10 are schematic circuit diagrams of the pixel circuit shown in FIG. 5 corresponding to the four stages in FIG. 6;
  • FIG. 11 is a circuit diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the basic pixel circuit used in the AMOLED display device is usually a 2T1C pixel circuit, that is, a basic function of driving the OLED to emit light by using two TFTs (Thin-film transistors) and one storage capacitor Cs.
  • 1A and 1B are schematic views showing two 2T1C pixel circuits, respectively.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to The first voltage terminal receives the first voltage Vdd (high voltage), and the drain of the driving transistor N0 is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and One end is connected to the source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the scan line to turn on the switching transistor T0
  • the data signal Vdata input by the data driving circuit through the data line charges the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs
  • the stored data signal Vdata controls the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor N0 to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, and the driving transistor The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the switching transistor T0 is not limited to the N-type transistor, and may be a P-type transistor, whereby the polarity of the scan signal Scan1 that controls its on or off is changed accordingly. can.
  • An OLED display device typically includes a plurality of pixel units arranged in an array, each of which may include, for example, the above-described pixel circuits.
  • the threshold voltage of a driving transistor in each pixel circuit may be different due to a manufacturing process, and the threshold voltage of the driving transistor may drift due to a change in operating time such as a temperature change. Therefore, the difference in threshold voltage of each driving transistor may cause display failure (for example, display unevenness), so it is necessary to compensate the threshold voltage of the driving transistor; on the other hand, the first voltage Vdd (for example, high voltage) is integrated in the slave.
  • the voltage on the first voltage line causes a voltage drop of the first voltage Vdd, thereby causing the screen brightness to exist near the IC end and the far IC end. Brightness deviation.
  • the pixel circuit includes a data writing circuit, a driving circuit, a compensation circuit, and a light emitting element.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current flowing through the first end and the second end for driving the light emitting element to emit light;
  • the data writing circuit is connected to the control end of the driving circuit and configured Writing a data signal to the control end of the driving circuit in response to the scan signal;
  • the compensation circuit and the control end of the driving circuit, the first end of the driving circuit, the second end of the driving circuit, and the first voltage end are connected, and configured to be stored
  • the data is written into the data signal written by the circuit and compensates for the driving circuit and coupled to adjust the voltage of the second end of the driving circuit;
  • the first end of the light emitting element is configured to receive the driving current, and the second end of the light emitting element is connected to the second voltage end .
  • At least one embodiment of the present disclosure also provides a driving method and a display panel corresponding to the above pixel circuit.
  • the pixel circuit and the driving method thereof and the display panel provided by at least one embodiment of the present disclosure can compensate the threshold voltage of the driving circuit of the pixel circuit on the one hand, thereby avoiding the phenomenon that the display device is unevenly displayed;
  • the problem of the difference in luminance due to the difference in voltage drop between the distal end and the near end of the integrated circuit can be solved, so that the display effect of the display panel using the pixel circuit can be improved.
  • the pixel circuit 10 includes a drive circuit 100, a data write circuit 200, a compensation circuit 300, and a light-emitting element 400.
  • the driving circuit 100 includes a first end 110, a second end 120, and a control end 130, and the driving circuit 100 is configured to control a driving current flowing through the first end 110 and the second end 120 for driving the light emitting element 400 to emit light.
  • the control terminal 130 of the driving circuit 100 is connected to the first node N1.
  • the first terminal 110 of the driving circuit 100 is connected to the fourth node N4.
  • the fourth node N4 is connected to the first voltage terminal VDD (for example, providing a high level).
  • the second end 120 of the driving circuit 100 is connected to the second node N2.
  • the driving circuit 100 may supply a driving current to the light emitting element 400 to drive the light emitting element 400 to emit light, and may emit light according to a desired "grayscale".
  • the light emitting element 400 may employ an OLED and be configured to be connected to the second node N2 and the second voltage terminal VSS (eg, providing a low level), for example, in the present disclosure.
  • the light emitting element 400 may also be connected to the second node N2 through the light emission control circuit 500.
  • Embodiments of the present disclosure include, but are not limited to, this scenario.
  • the data write circuit 200 is connected to the control terminal 130 (first node N1) of the drive circuit 100, and is configured to write a data signal to the control terminal 130 (first node N1) of the drive circuit 100 in response to the scan signal.
  • the data write circuit 200 is connected to a data line (for example, connected via a data signal terminal Vdata and a data line), a first node N1, and a scan line (for example, connected by a scan signal terminal Gate and a scan line).
  • a scan signal from the scan signal terminal Gate is applied to the data write circuit 200 to control whether the data write circuit 200 is turned on or not.
  • the data writing circuit 200 can be turned on in response to the scan signal, so that the data signal can be written to the control terminal 130 (first node N1) of the driving circuit 100, and the data signal is stored in the compensation.
  • a driving current for driving the light-emitting element 400 to emit light can be generated based on the data signal, for example, in an emission phase.
  • the compensation circuit 300 and the control terminal 130 (first node N1) of the driving circuit, the first terminal 110 (fourth node N4), the second terminal 120 (second node N2), and the first voltage terminal VDD (fourth node) N4) is connected and configured to store the data signal written by the data write circuit 200 and to compensate the drive circuit 100 and to couple the voltage of the second terminal 120 (second node N2) of the drive circuit 100.
  • the compensation circuit 300 may store relevant information of the threshold voltage of the drive circuit 100 in the storage capacitor, respectively.
  • the compensation circuit 300 can store the data signal written by the data writing circuit 200 in the storage capacitor, so that the stored voltage pair including the data signal Vdata and the threshold voltage can be utilized in, for example, the light emitting phase.
  • the drive circuit 100 performs control so that the output of the drive circuit 100 can be compensated.
  • the light emitting element 400 includes a first end 410 and a second end 420, the first end 410 of the light emitting element 400 being configured to receive a drive current from the second end 120 of the drive circuit 100, the second end 420 of the light emitting element 400
  • Two voltage terminals are connected to VSS.
  • the first end 410 of the light emitting element 400 is connected to the third node N3.
  • the third node N3 is connected to the second node N2, so the first end 410 of the light-emitting element 400 is connected to the second node N2.
  • the first end 410 (third node N3) of the light emitting element 400 may also pass through the light emission control circuit 500 and the second node. N2 connection.
  • the compensation circuit 300 includes a first compensation sub-circuit 310 and a second compensation sub-circuit 320.
  • the first compensation sub-circuit 310 is connected to the control terminal 130 (first node N1) of the driving circuit 100 and the second terminal 120 (second node N2) of the driving circuit 100, and is configured to store the data writing circuit 200 to write The data signal compensates for the drive circuit 100.
  • the first compensation sub-circuit 310 may cause information related to the threshold voltage of the drive circuit 100 to be stored in the storage capacitor, respectively.
  • the first compensation sub-circuit 310 can store the data signal written by the data writing circuit 200 in the storage capacitor, so that the stored data signal Vdata and the threshold voltage can be utilized in, for example, the light-emitting phase.
  • the voltage controls the drive circuit 100 such that the output of the drive circuit 100 can be compensated.
  • the second compensation sub-circuit 320 is connected to the first voltage terminal VDD, the first end 110 (fourth node N4) of the driving circuit 100, and the second end 120 (second node N2) of the driving circuit 100, and is configured according to The voltage change amount of the control terminal 130 (first node N1) of the drive circuit 100 is coupled to adjust the voltage of the second terminal 120 (second node N2) of the drive circuit 100.
  • the second compensation sub-circuit 320 includes a storage capacitor
  • the second compensating sub-circuit 320 can couple the second end 120 of the driving circuit 100 according to the voltage variation amount of the first node N1.
  • the voltage of the (second node N2) can thereby adjust the magnitude of the driving current for driving the light-emitting element 400 to emit light in the light-emitting phase.
  • the pixel circuit 10 may further include an illumination control circuit 500 and a reset circuit 600.
  • the illuminating control circuit 500 is coupled to the second end 120 of the driving circuit 100 (ie, the second node N2) and the first end 410 of the illuminating element 400 (ie, the third node N3), and is configured to be driven in response to the illuminating control signal.
  • a current is applied to the light emitting element 400.
  • the illumination control circuit 500 is respectively coupled to the illumination control line (eg, via the illumination control terminal Em and the illumination control line), the second end 120 (second node N2) of the drive circuit 100, and the first end 410 of the illumination element 400 ( That is, the third node N3) is connected.
  • the illumination control circuit 500 can be turned on in response to the illumination control signal, such that the reset voltage provided by the reset circuit 600 can be applied to the second terminal 120 of the drive circuit 100 (ie, the second node N2) through the illumination control circuit 500.
  • the light-emitting element 400 so that the light-emitting element 400, the driving circuit 100, the first compensation sub-circuit 310, and the second compensation sub-circuit 320 can be reset to eliminate the influence of the previous illumination phase.
  • the light emission control circuit 500 can be turned on in response to the light emission control signal, so that the drive current can be transmitted to the light emitting element 400 through the light emission control circuit 500, so that the light emitting element 400 emits light.
  • the reset circuit 600 is coupled to the reset voltage terminal Vinit and the first terminal 410 (third node N3) of the light emitting element 400, and is configured to apply a reset voltage to the first end 410 of the light emitting element 400 in response to the reset signal.
  • the reset circuit 600 is connected to the first terminal 410 (third node N3) of the light-emitting element 400, the reset voltage terminal Vinit, and the reset control line (for example, connected through the reset control terminal Reset and the reset control line).
  • the reset circuit 600 can be turned on in response to the reset signal, so that the reset voltage can be applied to the third node N3, at which stage, since the illumination control circuit 500 is turned on in response to the illumination control signal,
  • the first compensating sub-circuit 310, the second compensating sub-circuit 320, the driving circuit 100, and the light-emitting element 500 perform a reset operation to eliminate the influence of the previous lighting stage.
  • the reset voltage may be provided by a separate reset voltage terminal Vinit, and in other embodiments may also be provided by the first voltage terminal VSS, whereby accordingly, the reset circuit 600 is not connected to the reset voltage terminal Vinit but is connected to the first
  • the voltage terminal VSS is not limited by the embodiment of the present disclosure.
  • the reset signal may be a scan signal provided by the scan line (scan signal terminal Gate), and accordingly, the reset control terminal Reset of the reset circuit 600 may be directly connected to the scan signal terminal Gate, as opposed to In the conventional display panel, this method does not need to add a new signal, and the circuit structure is simple and easy to implement.
  • the reset signal may also be provided by an independent reset control terminal Reset, but the reset signal and the scan signal need to be synchronized, which is not limited by the embodiment of the present disclosure.
  • a plurality of scanning lines are correspondingly connected to the data writing circuit 200 of the pixel circuits of each row of pixel units to provide the scanning signals; for example, multiple scans
  • the line may also correspond to the reset circuit 600 connected to the pixel circuit of each row of pixel units to use the scan signal as a reset signal.
  • the display device may not separately set the reset control line, thereby saving wiring space and more. Easy to implement narrow borders.
  • the driving circuit 100 when the driving circuit 100 is implemented as a driving transistor, for example, the gate of the driving transistor may serve as the control terminal 130 of the driving circuit 100, and the first electrode (eg, the drain) may serve as the first terminal 110 of the driving circuit 100.
  • a diode eg, a source
  • the first voltage terminal VDD maintains an input DC high level
  • the DC high level is referred to as a first voltage
  • the second voltage terminal VSS maintains an input DC low level, for example.
  • the DC low level is referred to as a second voltage; and the second voltage is lower than the first voltage.
  • the symbol Vdata may represent both the data signal end and the data signal.
  • the symbol Reset can represent both the reset control terminal and the reset signal.
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage.
  • the symbol VDD can represent both the first voltage terminal and the first voltage
  • the symbol VSS can be both It can be said that the second voltage terminal can again represent the second voltage.
  • the pixel circuit 10 provided by the embodiment of the present disclosure can compensate the threshold voltage of the driving circuit of the pixel circuit on the one hand, thereby avoiding the phenomenon that the display device displays unevenness; on the other hand, it can also solve the problem due to the remote end of the integrated circuit.
  • the problem of the difference in luminance caused by the voltage drop of the near end is different, so that the display effect of the display device using the pixel circuit can be improved.
  • the pixel circuit 10 shown in FIG. 4 can be implemented as the pixel circuit structure shown in FIG.
  • the pixel circuit 10 includes first to fourth transistors T1, T2, T3, and T4 and includes a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element OLED.
  • the first transistor T1 is used as a driving transistor
  • the other second to fourth transistors are used as switching transistors.
  • the light-emitting element OLED may be of various types, such as top emission, bottom emission, double-sided emission, etc., and may emit red, green, blue, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • the first compensation sub-circuit 310 can be implemented as a first storage capacitor C1.
  • the first pole of the first storage capacitor C1 is connected to the control terminal 130 (first node N1) of the driving circuit 100, and the second pole of the first storage capacitor C1 is connected to the second terminal 120 (second node N2) of the driving circuit 100.
  • the embodiment of the present disclosure is not limited thereto, and the first compensation sub-circuit 310 may also be a circuit composed of other components to implement corresponding functions.
  • the second compensation sub-circuit 320 can be implemented as a second storage capacitor C2.
  • the first pole of the second storage capacitor C2 is connected to the first voltage terminal VDD and the first end 110 (fourth node N4) of the driving circuit 100, the second pole of the second storage capacitor C2 and the second end 120 of the driving circuit 100 (second node N2) is connected.
  • the embodiment of the present disclosure is not limited thereto, and the second compensation sub-circuit 320 may also be a circuit composed of other components to implement corresponding functions.
  • the driving circuit 100 can be implemented as the first transistor T1.
  • the gate of the first transistor T1 is connected to the first node N1 as the control terminal 130 of the driving circuit 100; the first electrode of the first transistor T1 serves as the first terminal 110 of the driving circuit 100, and is connected to the fourth node N4 to receive the first a voltage; the second pole of the first transistor T1 is coupled to the second node 120 as the second terminal 120 of the driving circuit 100.
  • the driving circuit 100 may also be a circuit composed of other components to implement corresponding functions.
  • the data write circuit 200 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be connected to a scan line (eg, connected by a scan signal terminal Gate) to receive a scan signal
  • the first pole of the second transistor T2 is configured to be a data line (eg, through a data signal end)
  • the Vdata connection is connected to receive a data signal
  • the second pole of the second transistor T2 is configured to be connected to the control terminal 130 (ie, the first node N1) of the drive circuit 100.
  • the data writing circuit 200 may also be a circuit composed of other components.
  • the light emitting element 400 can be implemented as an OLED.
  • a first end 410 (here an anode) of the light emitting element OLED is connected to the third node N3 and configured to receive a drive current, for example, in the example shown in FIG. 4, when the light emission control circuit 500 is turned on, the light emitting element OLED
  • the first end 410 can receive a drive current from the second end 120 of the drive circuit 100; for example, in the example shown in Figures 2 and 3, the first end 410 of the light emitting element OLED can be configured to directly drive from the drive circuit
  • the second end 120 of 100 receives the drive current.
  • a second end 420 (here a cathode) of the light emitting element OLED is configured to be coupled to the second voltage terminal VSS to receive the second voltage.
  • the second voltage terminal VSS can be grounded, that is, VSS can be 0V.
  • the cathodes of the light-emitting elements OLED can be electrically connected to the same voltage terminal, that is, the common cathode connection manner, and the following embodiments are the same, and will not be described again.
  • the illumination control circuit 500 can be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the light emission control line (for example, connected through the light emission control terminal Em) to receive the light emission control signal, and the first electrode of the third transistor T3 is configured to be the second end of the drive circuit 100 120 (second node N2) is connected, and the second pole of the third transistor T3 is configured to be connected to the first end 410 (third node N3) of the light emitting element OLED.
  • the reset circuit 600 can be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be connected to a reset control line (for example, connected via a reset control terminal Reset) to receive a reset signal, and the first electrode of the fourth transistor T4 is configured to be connected to the reset voltage terminal Vinit to receive a reset.
  • the voltage, the second pole of the fourth transistor T4 is configured to be coupled to the first end 410 (third node N3) of the light emitting element OLED.
  • the reset signal may be a scan signal provided by a scan line (scan signal terminal Gate).
  • the reset signal may also be provided by a separate reset control line, but need to satisfy the reset signal and
  • the scanning signal is synchronized, and embodiments of the present disclosure do not limit this.
  • the reset control terminal Reset is the scan signal terminal Gate, and therefore, the gate of the fourth transistor T4 is configured to be connected to the scan line to receive the scan signal and serve as a reset signal.
  • the embodiment of the present disclosure is not limited thereto, and the reset circuit 600 may also be a circuit composed of other components to implement corresponding functions.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual components, but represent convergence points of related electrical connections in the circuit diagram.
  • FIG. 6 is a timing diagram of signals of a pixel circuit according to an embodiment of the present disclosure.
  • the operation principle of the pixel circuit 10 shown in FIG. 5 will be described below with reference to the signal timing chart shown in FIG. 6.
  • the description will be made by taking an example in which each transistor is an N-type transistor, but the embodiment of the present disclosure is not limited thereto.
  • each frame image includes four stages, namely, a reset phase 1, a compensation phase 2, a data writing phase 3, and an illumination phase 4, and each signal in each phase is shown in FIG. Timing waveform.
  • FIG. 7 is a schematic diagram of the pixel circuit shown in FIG. 5 in the reset phase 1
  • FIG. 8 is a schematic diagram of the pixel circuit shown in FIG. 5 in the compensation phase 2
  • FIG. 9 is in FIG.
  • the illustrated pixel circuit is in a schematic view of the data writing phase 3
  • FIG. 10 is a schematic diagram of the pixel circuit shown in FIG. 5 in the light emitting phase 4.
  • the transistors identified by broken lines in FIGS. 7 to 10 are each shown to be in an off state in the corresponding phase, and the dotted line with arrows in FIGS. 7 to 10 indicates the current direction of the pixel circuit in the corresponding phase.
  • the reset phase 1 the reset signal, the scan signal, and the light emission control signal are input, the reset circuit 600, the data writing circuit 200, and the light emission control circuit 500 are turned on, and the first compensation sub circuit 310, the second compensation sub circuit 320, and the driving circuit 100 are turned on.
  • the light-emitting element 400 is reset.
  • the reset signal may be a scan signal provided by a scan line (for example, connected by a scan signal terminal Gate), and therefore, in the reset phase 1, only the scan signal and the light emission control signal need to be input.
  • the reset signal may also be provided by a separate reset control terminal Reset, but the reset signal and the scan signal need to be synchronized, which is not limited by the embodiment of the present disclosure. The following embodiments are the same as those described herein and will not be described again.
  • the fourth transistor T4 is turned on by the high level of the reset signal (scan signal), and the second transistor T2 is turned on by the high level of the scan signal;
  • the transistor T3 is turned on by the high level of the light emission control signal.
  • a reset path is formed (as indicated by the dotted line with an arrow in Fig. 7).
  • the light emitting element OLED is discharged through the fourth transistor T4, and since the third transistor T3 is turned on by the high level of the light emission control signal, the first storage capacitor C1 and the second storage capacitor C2 pass through the third transistor T3 and the fourth The transistor T4 is discharged, thereby resetting the second node N2 and the third node N3, so that after the reset phase 1, the potentials of the second node N2 and the third node N3 are the reset voltage Vinit, for example, the reset voltage Vinit is about -3V.
  • the data signal terminal Vdata inputs the low level of the data signal, that is, the reference voltage Vref
  • the potential of the first node N1 after the reset phase 1 is the reference voltage Vref, for example, the level of the reference voltage Vref is about 3V
  • the gate of the first transistor T1 is turned on due to the applied reference voltage.
  • the gate of the second transistor T2 of the Nth (N is an integer greater than zero) row pixel circuit is connected to the scan line of the Nth row to receive the scan.
  • the signal, the gate of the fourth transistor T4 of the Nth row pixel circuit is connected to the scan line of the Nth row to receive the scan signal of the Nth row as a reset signal.
  • this method can save signal lines, has a simple circuit structure, and is easy to implement a narrow border.
  • the second node N2 is reset, so the first storage capacitor C1 and the second storage capacitor C2 are reset, so that the charge stored in the first storage capacitor C1 is discharged, so that the data signal in the subsequent stage can be Stored more quickly and reliably in the first storage capacitor C1; the charge stored in the second storage capacitor C2 is also discharged, so that the second storage capacitor C2 can be better implemented in subsequent data writing stages, for example.
  • the third node N3 is also reset, that is, the light-emitting element OLED is reset, so that the light-emitting element OLED can be displayed as black state before the light-emitting phase 4, and the contrast of the display device using the pixel circuit can be improved. display effect.
  • the scan signal is input, the data write circuit 200 and the drive circuit 100 are turned on, and the first compensation sub-circuit 310 compensates the drive circuit 100.
  • the second transistor T2 is turned on by the high level of the scan signal. Since the second transistor T2 is turned on, the data signal terminal Vdata is input to the low level of the data signal, that is, the reference. The voltage Vref is to the first node N1, so the first transistor T1 is turned on by the level of the reference voltage Vref; at the same time, the third transistor T3 is turned off by the low level of the light emission control signal, and the fourth transistor T4 is reset (ie, scanned) The high level of the signal) is turned on, thereby ensuring that the light-emitting element OLED does not emit light at this stage.
  • a compensation path is formed (shown by a broken line with an arrow in FIG. 8), and the first voltage provided by the first voltage terminal VDD charges the second node N2 through the first transistor T1. (ie, charging the first storage capacitor C1).
  • Vref the reference voltage
  • Vth represents the threshold voltage of the first transistor T1. Since the first transistor T1 is described as an N-type transistor in the present embodiment, the threshold voltage Vth is a positive value here.
  • the pixel circuit 10 does not include the light emission control circuit 500 and the reset circuit 600, and in this example, the reference voltage Vref is determined according to the threshold voltage Vth of the first transistor T1 such that the first transistor T1 is
  • the compensation phase 2 has a shorter turn-on time and a smaller current flowing, thereby avoiding causing the light-emitting element OLED to emit light.
  • the potential of the first node N1 is maintained as the reference voltage Vref
  • the potential of the third node N3 is maintained at the reset voltage Vinit
  • the potential of the second node N2 is changed to Vref-Vth, that is, the threshold voltage will be
  • the voltage information of Vth is stored in the first storage capacitor C1 for subsequent compensation of the threshold voltage of the first transistor T1 itself during the illumination phase.
  • the scan signal and the data signal are input, the data writing circuit 200 is turned on, the data writing circuit 200 writes the data signal to the first compensation sub-circuit 310, and the second compensation sub-circuit 320 is based on the driving circuit 100.
  • the voltage variation amount of the control terminal 130 (first node N1) is coupled to adjust the voltage of the second terminal 120 (second node N2) of the drive circuit 100.
  • the second transistor T2 is turned on by the high level of the scan signal; meanwhile, the fourth transistor T4 is turned on by the high level of the reset signal (scanning signal).
  • the third transistor T3 is turned off by the low level of the light emission control signal.
  • a data writing path is formed (as indicated by a broken line with an arrow in FIG. 9), and the data signal Vdata is charged to the first node N1 via the second transistor T2 (ie, The first storage capacitor C1 is charged), so that the potential of the first node N1 is changed from the reference voltage Vref to the level Vdata of the data signal.
  • the potential of the second node N2 can be changed to Vref. -Vth+(Vdata-Vref)C1/(C1+C2).
  • the potential of the first node N1 becomes the level Vdata of the data signal
  • the potential of the third node N3 remains as the reset voltage Vinit
  • the potential of the second node N2 becomes Vref-Vth+(Vdata-Vref C1/(C1+C2), that is to say, the voltage information with the data signal Vdata is stored in the first storage capacitor C1 for subsequent gray level, and different gray levels can be performed according to different data signals. Display.
  • the illuminating control signal is input, the illuminating control circuit 500 and the driving circuit 100 are turned on, and the first compensating sub-circuit 310 is coupled to adjust the driving circuit 100 according to the voltage variation amount of the second end 120 (second node N2) of the driving circuit 100.
  • the voltage of the control terminal 130 (first node N1), the light emission control circuit 500 applies a driving current to the light emitting element OLED to cause it to emit light.
  • the third transistor T3 is turned on by the high level of the light-emission control signal, and the first transistor T1 is kept in the on-state due to the level of the first node N1 in the previous stage; At the same time, the second transistor T2 is turned off by the low level of the scan signal, and the fourth transistor T4 is turned off by the low level of the reset signal (scan signal).
  • a driving light-emitting path is formed (as indicated by a broken line with an arrow in FIG. 10).
  • the light emitting element OLED can emit light under the action of a driving current flowing through the first transistor T1.
  • the potential of the third node N3 is V OLED + VSS, and since the third transistor T3 is turned on by the high level of the light-emission control signal, the potential of the second node N2 is Vref-Vth+(Vdata-Vref) C1/(C1+C2) becomes equal to the potential of the third node N3.
  • the value of the driving current I OLED flowing through the light emitting element OLED can be obtained according to the following formula:
  • I OLED 1/2*K*(Vgs-Vth) 2
  • I OLED 1/2*K*((Vdata-Vref)C2/(C1+C2)) 2
  • Vth represents the threshold voltage of the first transistor T1
  • Vgs represents the voltage between the gate of the first transistor T1 and the second pole (for example, the source)
  • Vg represents the potential of the gate of the first transistor T1
  • Vs represents the potential of the second pole (for example, the source) of the first transistor T1
  • V N1 represents the potential of the first node N1
  • V N2 represents the potential of the second node N2
  • K is a constant value.
  • the driving current I OLED flowing through the light-emitting element OLED is no longer related to the threshold voltage Vth of the first transistor T1, thereby compensating the pixel circuit and solving the driving transistor (at In the embodiment of the present disclosure, the first transistor T1) has a problem of threshold voltage drift due to process process and long-time operation, and eliminates the influence of the threshold voltage on the driving current I OLED , thereby avoiding display unevenness and improving display effect.
  • the driving current I OLED flowing through the light emitting element OLED is no longer related to the first voltage VDD, thereby solving the difference in luminance due to the difference in voltage voltage drop of the first voltage VDD at the distal end and the near end of the integrated circuit. The problem is that the display effect of the display device using the pixel circuit can be improved.
  • charging a node indicates charging a capacitor electrically connected to the node; similarly, performing the node Discharging means discharging a capacitor electrically connected to the node.
  • the potential of the previous third node N3 is the reset voltage Vinit
  • the potential of the third node N3 becomes Voled+Vss when the light is emitted, so that in the light-emitting phase 4, the potential of the third node N3 is Voled+Vss.
  • -Vinit change when the third transistor T3 is turned on, since the second node N2 is connected to the third node N3, the change in the potential of the third node N3 affects the change of the potential of the second node N2, thereby affecting Vgs- The value of Vth.
  • the capacitance value of the second storage capacitor C2 can be avoided by increasing the capacitance value of the second storage capacitor C2, so that the capacitance value of the second storage capacitor C2 is much larger than the capacitance value of the parasitic capacitance of the light-emitting element OLED, so that the third node can be avoided to some extent. Display problems caused by potential changes in N3.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • transistors in the pixel circuit 10 shown in FIG. 5 are all described by taking an N-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • Embodiments of the present disclosure include, but are not limited to, the configuration of FIG. 5, for example, as shown in FIG. 11, in another embodiment of the present disclosure, transistors in the pixel circuit 10 may also be mixed with a P-type transistor and an N-type transistor. It is only necessary to simultaneously connect the polarities of the respective ends of the transistors of the selected type in accordance with the port polarities of the respective transistors in the embodiment of the present disclosure. For example, as shown in FIG.
  • the first transistor T1 uses an N-type transistor
  • the second transistor T2 the third transistor T3, and the fourth transistor T4 employ a P-type transistor. It should be noted that the second transistor T2 is provided at this time.
  • the signal levels of the third transistor T3 and the fourth transistor T4 need to be changed accordingly, for example, from a high level to a low level or from a low level to a high level.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS low temperature polysilicon
  • Silicon for example, hydrogenated amorphous silicon
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units arranged in an array, each of the plurality of pixel units including a pixel circuit provided by any of the embodiments of the present disclosure.
  • FIG. 12 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 11 is disposed in the display device 1 and is electrically connected to the gate driver 12, the timing controller 13, and the data driver 14.
  • the display panel 11 includes a pixel unit P defined according to a plurality of scan lines GL and a plurality of data lines DL; a gate driver 12 for driving a plurality of scan lines GL; and a data driver 14 for driving a plurality of data lines DL;
  • the controller 13 is for processing the image data RGB input from the outside of the display device 1, supplying the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, to The gate driver 12 and the data driver 14 are controlled.
  • the display panel 11 includes a plurality of pixel units P including any of the pixel circuits 10 provided in the embodiments of the present disclosure.
  • the pixel circuit 10 shown in FIG. 5 is included.
  • the display panel 11 further includes a plurality of scanning lines GL and a plurality of data lines DL.
  • the plurality of scan lines GL are correspondingly connected to the data write circuit 200 in the pixel circuit 10 of each row of pixel units P to provide a scan signal, and the plurality of scan lines GL may also be correspondingly connected to each row of pixel units P.
  • the reset circuit 600 in the pixel circuit 10 provides a reset signal, in which case the scan signal is used as a reset signal.
  • the pixel unit P is disposed at an intersection area of the scanning line GL and the data line DL.
  • each pixel unit P is connected to three scanning lines GL (providing a scan signal, a reset signal, and an illumination control signal, respectively), a data line DL, a first voltage line for supplying a first voltage, A second voltage line for providing a second voltage and a reset voltage line for providing a reset voltage.
  • the first voltage line or the second voltage line may be replaced with a corresponding plate-like common electrode (eg, a common anode or a common cathode). It should be noted that only a part of the pixel unit P, the scanning line GL, and the data line DL are shown in FIG.
  • each pixel unit P can be connected only to the two scan lines GL, that is, one scan line GL is used to provide The scan signal and the reset signal are used, and the other scan line GL is used to provide an illumination control signal.
  • the following embodiments are the same as those described herein and will not be described again.
  • the plurality of pixel units P are arranged in a plurality of rows, and the data writing circuit 200 and the reset circuit 600 of the pixel circuits of each row of the pixel units P are connected to the same scanning line GL, and the light emission control of the pixel circuits of each row of pixel units P
  • the circuit 500 is connected to another scan line GL to receive an illumination control signal.
  • the data line DL of each column is connected to the data write circuit 200 in the column of pixel circuits 10 to provide a data signal.
  • the gate driver 12 supplies a plurality of strobe signals to the plurality of scan lines GL in accordance with a plurality of scan control signals GCS derived from the timing controller 13.
  • the plurality of strobe signals include a scan signal, an illumination control signal, and a reset signal. These signals are supplied to each of the pixel units P through a plurality of scanning lines GL.
  • the data driver 14 converts the digital image data RGB input from the timing controller 13 into a data signal in accordance with a plurality of data control signals DCS derived from the timing controller 13 using the reference gamma voltage.
  • the data driver 14 supplies the converted data signals to the plurality of data lines DL.
  • the timing controller 13 processes the externally input image data RGB to match the size and resolution of the display panel 11, and then supplies the processed image data to the data driver 14.
  • the timing controller 13 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using a synchronization signal (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device.
  • the timing controller 13 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14, respectively, for controlling the gate driver 12 and the data driver 14.
  • the data driver 14 may be connected to the plurality of data lines DL to provide the data signal Vdata; and may also be connected to the plurality of first voltage lines, the plurality of second voltage lines, and the plurality of reset voltage lines to respectively provide the first voltage , the second voltage and the reset voltage.
  • the gate driver 12 and the data driver 14 can be implemented as a semiconductor chip.
  • the display device 1 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display panel 11 provided in this embodiment can be applied to any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure also provide a driving method that can be used to drive the pixel circuit 10 provided by an embodiment of the present disclosure.
  • the driving method includes the following operations:
  • the compensation phase a scan signal is input, the data write circuit 200 and the drive circuit 100 are turned on, and the compensation circuit 300 compensates the drive circuit 100;
  • the scan signal and the data signal are input, the data writing circuit 200 is turned on, the data writing circuit 200 writes the data signal to the compensation circuit 300, and the compensation circuit 300 varies according to the voltage of the control terminal 130 of the driving circuit 100.
  • the voltage of the second terminal 120 of the drive circuit 100 is coupled.
  • the driving method includes the following operations:
  • the scan signal is input, the data write circuit 200 and the drive circuit 100 are turned on, and the first compensation sub-circuit 310 compensates the drive circuit 100;
  • the scan signal and the data signal are input, the data writing circuit 200 is turned on, the data writing circuit 200 writes the data signal to the first compensation sub-circuit 310, and the second compensation sub-circuit 320 is controlled according to the driving circuit 100.
  • the amount of voltage change at terminal 130 couples to adjust the voltage at the second terminal 120 of drive circuit 100.
  • the driving method includes the following operations:
  • the driving method further includes a light emitting phase.
  • the illuminating phase the illuminating control signal is input, the illuminating control circuit 500 and the driving circuit 100 are turned on, and the first compensating sub-circuit 310 is coupled to adjust the voltage of the control terminal 130 of the driving circuit 100 according to the change of the voltage of the second end 120 of the driving circuit 100.
  • the light emission control circuit 500 applies a drive current to the light emitting element OLED to cause it to emit light.
  • the driving method further includes a reset phase.
  • the reset phase the reset signal, the scan signal, and the illumination control signal are input, the reset circuit 600, the data write circuit 200, and the illumination control circuit 500 are turned on, and the first compensation sub-circuit 310, the second compensation sub-circuit 320, and the light-emitting element OLED are performed.
  • the reset for example, the reset signal is synchronized with the scan signal, and for example, the scan signal can be used as a reset signal.
  • the driving method provided by the embodiment of the present disclosure can compensate the threshold voltage of the driving circuit of the pixel circuit, so that the display device can be prevented from being unevenly displayed; on the other hand, the remote end of the integrated circuit can also be solved.
  • the problem of the difference in luminance caused by the difference in voltage drop at the near end can improve the display effect of the display device using the pixel circuit.

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Abstract

一种像素电路及其驱动方法、显示面板。该像素电路(10)包括数据写入电路(200)、驱动电路(100)、补偿电路(300)和发光元件(400)。驱动电路(100)包括控制端(130)、第一端(110)和第二端(120)，且被配置为控制流经第一端(110)和第二端(120)的用于驱动发光元件(400)发光的驱动电流；数据写入电路(200)被配置为响应于扫描信号将数据信号写入驱动电路(100)的控制端(130)；补偿电路(300)和驱动电路(100)的控制端(130)、驱动电路(100)的第一端(110)、驱动电路(100)的第二端(120)以及第一电压端(VDD)连接，且被配置为存储数据写入电路(200)写入的数据信号并对驱动电路(100)进行补偿以及耦合调整驱动电路(100)的第二端(120)的电压；发光元件(400)的第一端(410)被配置为接收驱动电流，发光元件(400)的第二端(420)与第二电压端(VSS)连接。该像素电路(10)可以对驱动电路(100)的阈值电压进行补偿，提高显示面板的显示质量。

Description

像素电路及其驱动方法、显示面板
本申请要求于2018年4月26日递交的中国专利申请第201810388273.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种像素电路，包括数据写入电路、驱动电路、补偿电路和发光元件。所述驱动电路包括控制端、第一端和第二端， 且被配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；所述数据写入电路连接到所述驱动电路的控制端且被配置为响应于扫描信号将数据信号写入所述驱动电路的控制端；所述补偿电路和所述驱动电路的控制端、所述驱动电路的第一端、所述驱动电路的第二端连接以及第一电压端连接，且被配置为存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿以及耦合调整所述驱动电路的第二端的电压；所述发光元件包括第一端和第二端，所述发光元件的第一端被配置为接收所述驱动电流，所述发光元件的第二端与第二电压端连接。
例如，在本公开一实施例提供的像素电路中，所述补偿电路包括第一补偿子电路和第二补偿子电路。所述第一补偿子电路和所述驱动电路的控制端以及所述驱动电路的第二端连接，且被配置为存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿；所述第二补偿子电路和所述第一电压端、所述驱动电路的第一端以及所述驱动电路的第二端连接，且被配置为根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
例如，在本公开一实施例提供的像素电路中，所述第一补偿子电路还被配置为根据所述驱动电路的第二端的电压变化量耦合调整所述驱动电路的控制端的电压。
例如，在本公开一实施例提供的像素电路中，所述第一补偿子电路包括第一存储电容。所述第一存储电容的第一极和所述驱动电路的控制端连接，所述第一存储电容的第二极和所述驱动电路的第二端连接。
例如，在本公开一实施例提供的像素电路中，所述第二补偿子电路包括第二存储电容。所述第二存储电容的第一极和所述第一电压端以及所述驱动电路的第一端连接，所述第二存储电容的第二极和所述驱动电路的第二端连接。
例如，本公开一实施例提供的像素电路还包括发光控制电路。所述发光控制电路和所述驱动电路的第二端以及所述发光元件的第一端连接，且被配置为响应于发光控制信号将所述驱动电流施加至所述发光元件。
例如，本公开一实施例提供的像素电路还包括复位电路。所述复位电路与复位电压端以及所述发光元件的第一端连接，且被配置为响应于复位信号将复位电压施加至所述发光元件的第一端；所述复位信号和所述扫描 信号同步。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括第一晶体管。述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端且被配置为和所述第一电压端连接以接收第一电压，所述第一晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一实施例提供的像素电路中，所述数据写入电路包括第二晶体管。所述第二晶体管的栅极被配置为和扫描线连接以接收所述扫描信号，所述第二晶体管的第一极被配置为和数据线连接以接收所述数据信号，所述第二晶体管的第二极被配置为和所述驱动电路的控制端连接。
例如，在本公开一实施例提供的像素电路中，所述发光控制电路包括第三晶体管。所述第三晶体管的栅极被配置为和发光控制线连接以接收所述发光控制信号，所述第三晶体管的第一极被配置为和所述驱动电路的第二端连接，所述第三晶体管的第二极被配置为和所述发光元件的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述复位电路包括第四晶体管。所述第四晶体管的栅极被配置为和复位控制线连接以接收所述复位信号，所述第四晶体管的第一极被配置为和所述复位电压端连接以接收所述复位电压，所述第四晶体管的第二极被配置为和所述发光元件的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述复位电路包括第四晶体管；所述第四晶体管的栅极被配置为和扫描线连接以接收所述扫描信号并作为所述复位信号，所述第四晶体管的第一极被配置为和所述复位电压端连接以接收所述复位电压，所述第四晶体管的第二极被配置为和所述发光元件的第一端连接。
本公开至少一实施例还提供一种显示面板，包括阵列布置的多个像素单元。所述多个像素单元中的每个包括如本公开任一实施例提供的像素电路。
例如，本公开一实施例提供的显示面板还包括多条扫描线，该多条扫描线对应连接到每行像素单元的像素电路的数据写入电路以提供所述扫描信号。
例如，在本公开一实施例提供的显示面板中，在所述像素电路包括复 位电路的情形下，所述多条扫描线还对应连接到每行像素单元的像素电路中的复位电路以提供所述扫描信号，并将所述扫描信号作为所述复位信号。
本公开至少一实施例还提供一种像素电路的驱动方法，该驱动方法用于本公开的实施例提供的任一像素电路，该驱动方法包括补偿阶段和数据写入阶段。在所述补偿阶段，输入所述扫描信号，开启所述数据写入电路和所述驱动电路，所述补偿电路对所述驱动电路进行补偿；以及在所述数据写入阶段，输入所述扫描信号和所述数据信号，开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述补偿电路，且所述补偿电路根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
本公开至少一实施例还提供一种像素电路的驱动方法，该驱动方法用于本公开的实施例提供的任一像素电路，在所述补偿电路包括第一补偿子电路和第二补偿子电路的情形下，所述驱动方法包括补偿阶段和数据写入阶段；在所述补偿阶段，输入所述扫描信号，开启所述数据写入电路和所述驱动电路，所述第一补偿子电路对所述驱动电路进行补偿；以及在所述数据写入阶段，输入所述扫描信号和所述数据信号，开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述第一补偿子电路，且所述第二补偿子电路根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
例如，在本公开一实施例提供的驱动方法中，在所述像素电路包括发光控制电路的情形下，所述驱动方法还包括发光阶段。在所述发光阶段，输入所述发光控制信号，开启所述发光控制电路和所述驱动电路，所述第一补偿子电路根据所述驱动电路的第二端的电压变化量耦合调整所述驱动电路的控制端的电压，所述发光控制电路将所述驱动电流施加至所述发光元件以使得所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2为本公开一实施例提供的一种像素电路的示意框图；
图3为本公开一实施例提供的另一种像素电路的示意框图；
图4为本公开一实施例提供的又一种像素电路的示意框图；
图5为图4中所示的像素电路的一种具体实现示例的电路图；
图6为本公开一实施例提供的一种像素电路的驱动方法的时序图；
图7至图10分别为图5中所示的像素电路对应于图6中四个阶段的电路示意图；
图11为本公开一实施例提供的另一种像素电路的电路图；以及
图12为本公开一实施例提供的一种显示面板的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，驱动晶体管N0的漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线输入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管N0以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电压端以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号Scan1的极性进行相应地改变即可。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元例如可以包括上述像素电路。在OLED显示装置中，一方面，各个像素电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且随着工作时间的变化例如温度变化的影响使得驱动晶体管的阈值电压可能会发生漂移现象， 因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对驱动晶体管的阈值电压进行补偿；另一方面，第一电压Vdd(例如高电压)在从集成电路(Integrated Circuit，IC)输出并传送至像素单元的过程中，由于第一电压线上有电阻，从而引起第一电压Vdd的电压压降，从而导致屏幕亮度在近IC端和远IC端存在亮度偏差。
本公开至少一实施例提供一种像素电路。该像素电路包括数据写入电路、驱动电路、补偿电路和发光元件。驱动电路包括控制端、第一端和第二端，且配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；数据写入电路连接到驱动电路的控制端且配置为响应于扫描信号将数据信号写入驱动电路的控制端；补偿电路和驱动电路的控制端、驱动电路的第一端、驱动电路的第二端连接以及第一电压端连接，且配置为存储数据写入电路写入的数据信号并对驱动电路进行补偿以及耦合调整驱动电路的第二端的电压；发光元件的第一端配置为接收驱动电流，发光元件的第二端与第二电压端连接。
本公开至少一实施例还提供对应于上述像素电路的驱动方法和显示面板。
本公开至少一实施例提供的像素电路及其驱动方法、显示面板，一方面，可以对像素电路的驱动电路的阈值电压进行补偿，从而可以避免显示装置显示不均匀的现象；另一方面，还可以解决由于集成电路远端和近端的电压压降不同引起的亮度差异的问题，从而可以改善采用该像素电路的显示面板的显示效果。
下面结合附图对本公开的实施例及其示例进行详细说明。需要注意的是，不同的附图中相同的附图标记用于指代已描述的相同的元件。
本公开实施例的一个示例提供一种像素电路10，该像素电路10例如用于OLED显示面板的子像素。如图2所示，该像素电路10包括驱动电路100、数据写入电路200、补偿电路300和发光元件400。
例如，驱动电路100包括第一端110、第二端120和控制端130，驱动电路100被配置为控制流经第一端110和第二端120的用于驱动发光元件400发光的驱动电流。驱动电路100的控制端130和第一节点N1连接，驱动电路100的第一端110和第四节点N4连接，例如，第四节点N4与第一电压端VDD(例如，提供高电平)连接，驱动电路100的第二端120和第二节点 N2连接。例如，在发光阶段，驱动电路100可以向发光元件400提供驱动电流以驱动发光元件400进行发光，且可以根据需要的“灰度”发光。例如，在图2和图3所示的示例中，发光元件400可以采用OLED，且配置为和第二节点N2以及第二电压端VSS(例如，提供低电平)连接，例如，在本公开的其他示例中，如图4所示的示例中，在像素电路10包括发光控制电路500的情形下，发光元件400还可以通过发光控制电路500与第二节点N2连接。本公开的实施例包括但不限于此情形。
例如，数据写入电路200与驱动电路100的控制端130(第一节点N1)连接，且被配置为响应于扫描信号将数据信号写入驱动电路100的控制端130(第一节点N1)。例如，数据写入电路200分别和数据线(例如，通过数据信号端Vdata和数据线连接)、第一节点N1以及扫描线(例如，通过扫描信号端Gate和扫描线连接)连接。例如，来自扫描信号端Gate的扫描信号被施加至数据写入电路200以控制数据写入电路200开启与否。例如，在数据写入阶段，数据写入电路200可以响应于扫描信号而开启，从而可以将数据信号写入驱动电路100的控制端130(第一节点N1)，并将该数据信号存储在补偿电路300中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件400发光的驱动电流。
例如，补偿电路300与驱动电路的控制端130(第一节点N1)、第一端110(第四节点N4)、第二端120(第二节点N2)以及第一电压端VDD(第四节点N4)连接，且被配置为存储数据写入电路200写入的数据信号并对驱动电路100进行补偿以及耦合调整驱动电路100的第二端120(第二节点N2)的电压。例如，在补偿电路300包括存储电容的情形下，例如在补偿阶段，补偿电路300可以将驱动电路100的阈值电压的相关信息相应地存储在存储电容中。又例如，在数据写入阶段，补偿电路300可以将数据写入电路200写入的数据信号存储在存储电容中，从而在例如发光阶段时可以利用存储的包括数据信号Vdata以及阈值电压的电压对驱动电路100进行控制，使得驱动电路100的输出可以得到补偿。
例如，发光元件400包括第一端410和第二端420，发光元件400的第一端410被配置为从驱动电路100的第二端120接收驱动电流，发光元件400的第二端420与第二电压端VSS连接。例如，发光元件400的第一端410与第三节点N3连接。例如，在图2或图3所示的示例中，第三节点N3与 第二节点N2连接，所以发光元件400的第一端410与第二节点N2连接。又例如，在图4所示的示例中，在像素电路10包括发光控制电路500的情形下，发光元件400的第一端410(第三节点N3)还可以通过发光控制电路500与第二节点N2连接。
如图3所示，在图2所示的示例的基础上，例如补偿电路300包括第一补偿子电路310和第二补偿子电路320。
该第一补偿子电路310和驱动电路100的控制端130(第一节点N1)以及驱动电路100的第二端120(第二节点N2)连接，且被配置为存储数据写入电路200写入的数据信号并对驱动电路100进行补偿。例如，在第一补偿子电路310包括存储电容的情形下，例如在补偿阶段，第一补偿子电路310可以使驱动电路100的阈值电压的相关信息相应地存储在存储电容中。又例如，在数据写入阶段，第一补偿子电路310可以将数据写入电路200写入的数据信号存储在存储电容中，从而在例如发光阶段时可以利用存储的包括数据信号Vdata以及阈值电压的电压对驱动电路100进行控制，使得驱动电路100的输出可以得到补偿。
该第二补偿子电路320和第一电压端VDD、驱动电路100的第一端110(第四节点N4)以及驱动电路100的第二端120(第二节点N2)连接，且被配置为根据驱动电路100的控制端130(第一节点N1)的电压变化量耦合调整驱动电路100的第二端120(第二节点N2)的电压。例如，在第二补偿子电路320包括存储电容的情形下，在数据写入阶段和发光阶段，当驱动电路100的控制端130(即第一节点N1)的电压变化时，根据该第二补偿子电路320中的存储电容自身的特性(例如存储电容两极的电压差不能突变的特性)，第二补偿子电路320可以根据第一节点N1的电压变化量耦合调整驱动电路100的第二端120(第二节点N2)的电压，从而可以调整在发光阶段时用于驱动发光元件400进行发光的驱动电流的大小。
例如，如图4所示，在图3所示的示例的基础上，像素电路10还可以包括发光控制电路500和复位电路600。
该发光控制电路500和驱动电路100的第二端120(即第二节点N2)以及发光元件400的第一端410(即第三节点N3)连接，且被配置为响应于发光控制信号将驱动电流施加至发光元件400。例如，发光控制电路500分别和发光控制线(例如，通过发光控制端Em和发光控制线连接)、驱动电路 100的第二端120(第二节点N2)以及发光元件400的第一端410(即第三节点N3)连接。例如，在复位阶段，发光控制电路500可以响应于发光控制信号而开启，从而复位电路600提供的复位电压可以通过发光控制电路500施加至驱动电路100的第二端120(即第二节点N2)以及发光元件400，从而可以对发光元件400、驱动电路100、第一补偿子电路310以及第二补偿子电路320进行复位操作，以消除之前的发光阶段的影响。又例如，在发光阶段，发光控制电路500可以响应于发光控制信号而开启，从而驱动电流可以通过发光控制电路500传输至发光元件400，以使得发光元件400发光。
该复位电路600与复位电压端Vinit以及发光元件400的第一端410(第三节点N3)连接，且被配置为响应于复位信号将复位电压施加至发光元件400的第一端410。例如，复位电路600分别和发光元件400的第一端410(第三节点N3)、复位电压端Vinit和复位控制线(例如，通过复位控制端Reset和复位控制线连接)连接。例如，在复位阶段，复位电路600可以响应于复位信号而开启，从而可以将复位电压施加至第三节点N3，在此阶段，由于发光控制电路500响应于发光控制信号而导通，从而可以对第一补偿子电路310、第二补偿子电路320、驱动电路100以及发光元件500进行复位操作，以消除之前的发光阶段的影响。
例如，复位电压可以由独立的复位电压端Vinit提供，在其他实施例中也可以由第一电压端VSS提供，由此相应地，复位电路600不是连接到复位电压端Vinit而是连接到第一电压端VSS，本公开的实施例对此不作限制。
例如，在本公开的实施例中，复位信号可以是扫描线(扫描信号端Gate)提供的扫描信号，由此相应地，复位电路600的复位控制端Reset可以直接连接到扫描信号端Gate，相对于传统显示面板而言，这种方式无需增加新的信号，电路结构简单，易于实现。在其他实施例中，复位信号也可以由独立的复位控制端Reset提供，但需要满足复位信号和扫描信号同步，本公开的实施例对此不作限制。
例如，在一个显示装置中，当像素电路10呈阵列排布时，多条扫描线对应连接到每行像素单元的像素电路的数据写入电路200以提供所述扫描信号；例如，多条扫描线还可以对应连接到每行像素单元的像素电路中的复位电路600以将扫描信号作为复位信号，在这种情形中，该显示装置可以不单独设置复位控制线，从而可以节省布线空间，更易于实现窄边框。
例如，在驱动电路100实现为驱动晶体管的情形时，例如驱动晶体管的栅极可以作为驱动电路100的控制端130，第一极(例如漏极)可以作为驱动电路100的第一端110，第二极(例如源极)可以作为驱动电路100的第二端120。
需要说明的是，本公开的各实施例中的第一电压端VDD例如保持输入直流高电平，将该直流高电平称为第一电压，第二电压端VSS例如保持输入直流低电平，将该直流低电平称为第二电压；且第二电压低于第一电压。以下各实施例与此相同，不再赘述。
另外，需要说明的是，在本公开的各实施例的描述中，符号Vdata既可以表示数据信号端又可以表示数据信号。同样地，符号Reset既可以表示复位控制端又可以表示复位信号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电压，符号VSS既可以表示第二电压端又可以表示第二电压。以下各实施例与此相同，不再赘述。
本公开的实施例提供的像素电路10，一方面，可以对像素电路的驱动电路的阈值电压进行补偿，从而可以避免显示装置显示不均匀的现象；另一方面，还可以解决由于集成电路远端和近端的电压压降不同引起的亮度差异的问题，从而可以改善采用该像素电路的显示装置的显示效果。
例如，图4所示的像素电路10可以实现为图5所示的像素电路结构。如图5所示，该像素电路10包括：第一至第四晶体管T1、T2、T3、T4以及包括第一存储电容C1、第二存储电容C2和发光元件OLED。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第四晶体管被用作开关晶体管。例如，发光元件OLED可以为各种类型，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图5所示，更详细地，第一补偿子电路310可以实现为第一存储电容C1。第一存储电容C1的第一极和驱动电路100的控制端130(第一节点N1)连接，第一存储电容C1的第二极和驱动电路100的第二端120(第二节点N2)连接。需要注意的是，本公开的实施例不限于此，第一补偿子电路310也可以是由其他的组件组成的电路，以实现相应的功能。
第二补偿子电路320可以实现为第二存储电容C2。第二存储电容C2的第一极和第一电压端VDD以及驱动电路100的第一端110(第四节点N4) 连接，第二存储电容C2的第二极和驱动电路100的第二端120(第二节点N2)连接。需要注意的是，本公开的实施例不限于此，第二补偿子电路320也可以是由其他的组件组成的电路，以实现相应的功能。
驱动电路100可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路100的控制端130，和第一节点N1连接；第一晶体管T1的第一极作为驱动电路100的第一端110，和第四节点N4连接以接收第一电压；第一晶体管T1的第二极作为驱动电路100的第二端120，和第二节点N2连接。需要注意的是，本公开的实施例不限于此，驱动电路100也可以是由其他的组件组成的电路，以实现相应的功能。
数据写入电路200可以实现为第二晶体管T2。第二晶体管T2的栅极被配置为和扫描线(例如，通过扫描信号端Gate连接)连接以接收扫描信号，第二晶体管T2的第一极被配置为和数据线(例如，通过数据信号端Vdata连接)连接以接收数据信号，第二晶体管T2的第二极被配置为和驱动电路100的控制端130(即第一节点N1)连接。需要注意的是，本公开的实施例不限于此，数据写入电路200也可以是由其他的组件组成的电路。
发光元件400可以实现为OLED。发光元件OLED的第一端410(这里为阳极)和第三节点N3连接且被配置为接收驱动电流，例如，在图4所示的示例中，当发光控制电路500导通时，发光元件OLED的第一端410可以从驱动电路100的第二端120接收驱动电流；又例如，在图2和图3所示的示例中，发光元件OLED的第一端410可以被配置为直接从驱动电路100的第二端120接收驱动电流。发光元件OLED的第二端420(这里为阴极)配置为和第二电压端VSS连接以接收第二电压。例如第二电压端VSS可以接地，即VSS可以为0V。例如，在一个显示面板中，当像素电路10呈阵列排布时，发光元件OLED的阴极可以电连接到同一个电压端，即采用共阴极连接方式，以下实施例与此相同，不再赘述。
发光控制电路500可以实现为第三晶体管T3。第三晶体管T3的栅极被配置为和发光控制线(例如，通过发光控制端Em连接)连接以接收发光控制信号，第三晶体管T3的第一极被配置为和驱动电路100的第二端120(第二节点N2)连接，第三晶体管T3的第二极被配置为和发光元件OLED的第一端410(第三节点N3)连接。
复位电路600可以实现为第四晶体管T4。第四晶体管T4的栅极被配置 为和复位控制线(例如，通过复位控制端Reset连接)连接以接收复位信号，第四晶体管T4的第一极被配置为和复位电压端Vinit连接以接收复位电压，第四晶体管T4的第二极被配置为和发光元件OLED的第一端410(第三节点N3)连接。例如，在本公开的实施例中，复位信号可以是扫描线(扫描信号端Gate)提供的扫描信号，在其他实施例中复位信号也可以由单独的复位控制线提供，但需要满足复位信号和扫描信号同步，本公开的实施例对此不作限制。例如，在该示例中，复位控制端Reset为扫描信号端Gate，因此，第四晶体管T4的栅极被配置为和扫描线连接以接收扫描信号并作为复位信号。需要注意的是，本公开的实施例不限于此，复位电路600也可以是由其他的组件组成的电路，以实现相应的功能。
在本公开的实施例中，第一节点N1、第二节点N2、第三节点N3、第四节点N4并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
图6为本公开一实施例提供的一种像素电路的信号时序图。下面结合图6所示的信号时序图，对图5所示的像素电路10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
如图6所示，每一帧图像的显示过程包括四个阶段，分别为复位阶段1、补偿阶段2、数据写入阶段3以及发光阶段4，图6中示出了每个阶段中各个信号的时序波形。
需要说明的是，图7为图5中所示的像素电路处于复位阶段1时的示意图，图8为图5中所示的像素电路处于补偿阶段2时的示意图，图9为图5中所示的像素电路处于数据写入阶段3时的示意图，图10为图5中所示的像素电路处于发光阶段4时的示意图。另外图7至图10中用虚线标识的晶体管均表示在对应阶段内处于截止状态，图7至图10中带箭头的虚线表示像素电路在对应阶段内的电流方向。图7至图10中所示的晶体管均以N型晶体管为例进行说明，即各个晶体管的栅极在接入高电平时导通，而在接入低电平时截止。以下实施例与此相同，不再赘述。
在复位阶段1，输入复位信号、扫描信号和发光控制信号，开启复位电路600、数据写入电路200和发光控制电路500，对第一补偿子电路310、第二补偿子电路320、驱动电路100和发光元件400进行复位。
例如，在本公开的实施例中，复位信号可以是扫描线(例如，通过扫描 信号端Gate连接)提供的扫描信号，因此，在复位阶段1，只须输入扫描信号和发光控制信号即可。在其他实施例中复位信号也可以由单独的复位控制端Reset提供，但需要满足复位信号和扫描信号同步，本公开的实施例对此不作限制。以下实施例与此相同，不再赘述。
如图6和图7所示，在复位阶段1，第四晶体管T4被复位信号(扫描信号)的高电平导通，第二晶体管T2被扫描信号的高电平导通；同时，第三晶体管T3被发光控制信号的高电平导通。
如图7所示，在复位阶段1，形成一条复位路径(如图7中带箭头的虚线所示)。在此阶段，发光元件OLED通过第四晶体管T4放电，由于第三晶体管T3被发光控制信号的高电平导通，所以第一存储电容C1和第二存储电容C2通过第三晶体管T3以及第四晶体管T4放电，从而将第二节点N2和第三节点N3复位，所以经过复位阶段1后，第二节点N2和第三节点N3的电位为复位电压Vinit，例如复位电压Vinit为约-3V。由于在此阶段，数据信号端Vdata输入数据信号的低电平，即参考电压Vref，因此经过复位阶段1后第一节点N1的电位为参考电压Vref，例如参考电压Vref的电平为约3V，此时第一晶体管T1的栅极由于施加的参考电压而导通。例如，在一个显示装置中，当像素电路10呈阵列排布时，第N(N为大于零的整数)行像素电路的第二晶体管T2的栅极与第N行的扫描线连接以接收扫描信号，第N行像素电路的第四晶体管T4的栅极与第N行的扫描线连接以接收第N行的扫描信号作为复位信号。相对于传统显示面板而言，这种方式可以节省信号线，电路结构简单，易于实现窄边框。
在复位阶段1，第二节点N2被复位，所以第一存储电容C1和第二存储电容C2被复位，使得存储在第一存储电容C1中的电荷放电，从而使后续阶段中的数据信号可以被更迅速、更可靠地存储在第一存储电容C1中；存储在第二存储电容C2中的电荷也被放电，从而使得第二存储电容C2在后续的例如数据写入阶段中可以更好的实现耦合调整的作用；同时，第三节点N3也被复位，即将发光元件OLED复位，从而可以使发光元件OLED在发光阶段4之前显示为黑态不发光，改善采用上述像素电路的显示装置的对比度等显示效果。
在补偿阶段2，输入扫描信号，开启数据写入电路200和驱动电路100，第一补偿子电路310对驱动电路100进行补偿。
如图6和图8所示，在补偿阶段2，第二晶体管T2被扫描信号的高电平导通，由于第二晶体管T2导通，数据信号端Vdata输入数据信号的低电平，即参考电压Vref，至第一节点N1，因此第一晶体管T1被参考电压Vref的电平导通；同时，第三晶体管T3被发光控制信号的低电平截止，第四晶体管T4被复位信号(即扫描信号)的高电平导通，从而保证在此阶段发光元件OLED不发光。
如图8所示，在补偿阶段2，形成一条补偿路径(如图8中带箭头的虚线所示)，第一电压端VDD提供的第一电压通过第一晶体管T1对第二节点N2进行充电(即对第一存储电容C1充电)。容易理解，在此阶段，第一节点N1的电位保持为参考电压Vref，同时根据第一晶体管T1的自身特性，当第二节点N2的电位被充电至Vref-Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vth表示第一晶体管T1的阈值电压，由于在本实施例中，第一晶体管T1是以N型晶体管为例进行说明的，所以此处阈值电压Vth为正值。
在图3所示的示例中，例如，像素电路10不包括发光控制电路500和复位电路600，在该示例中，根据第一晶体管T1的阈值电压Vth确定参考电压Vref，使得第一晶体管T1在该补偿阶段2开启时间较短且流过的电流较小，从而避免导致发光元件OLED发光。
经过补偿阶段2后，第一节点N1的电位保持为参考电压Vref，第三节点N3的电位保持为复位电压Vinit，第二节点N2的电位变为Vref-Vth，也就是说将带有阈值电压Vth的电压信息存储在了第一存储电容C1中，以用于后续在发光阶段时，可以对第一晶体管T1自身的阈值电压进行补偿。
在数据写入阶段3，输入扫描信号和数据信号，开启数据写入电路200，数据写入电路200将数据信号写入第一补偿子电路310，且第二补偿子电路320根据驱动电路100的控制端130(第一节点N1)的电压变化量耦合调整驱动电路100的第二端120(第二节点N2)的电压。
如图6和图9所示，在数据写入阶段3，第二晶体管T2被扫描信号的高电平导通；同时，第四晶体管T4被复位信号(扫描信号)的高电平导通，第三晶体管T3被发光控制信号的低电平截止。
如图9所示，在数据写入阶段3，形成一条数据写入路径(如图9中带箭头的虚线所示)，数据信号Vdata经过第二晶体管T2对第一节点N1进行充 电(即对第一存储电容C1进行充电)，从而第一节点N1的电位由参考电压Vref变为数据信号的电平Vdata。由于电容本身的特性(例如电容的两极的电压差不能突变的特性)，第一存储电容C1的一极即第一节点N1的电位的变化会导致另一极即第二节点N2的变化，同时又根据第一存储电容C1和第二存储电容C2串联连接，第二存储电容C2的一极即第四节点N4的电位保持不变，根据电荷守恒原理可以得到第二节点N2的电位变为Vref-Vth+(Vdata-Vref)C1/(C1+C2)。
经过数据写入阶段3后，第一节点N1的电位变为数据信号的电平Vdata，第三节点N3的电位保持为复位电压Vinit，第二节点N2的电位变为Vref-Vth+(Vdata-Vref)C1/(C1+C2)，也就是说将带有数据信号Vdata的电压信息存储在了第一存储电容C1中，以用于后续在发光阶段时，可以根据不同的数据信号进行不同灰度的显示。
在发光阶段4，输入发光控制信号，开启发光控制电路500和驱动电路100，第一补偿子电路310根据驱动电路100的第二端120(第二节点N2)的电压变化量耦合调整驱动电路100的控制端130(第一节点N1)的电压，发光控制电路500将驱动电流施加至发光元件OLED以使其发光。
如图6和图10所示，在发光阶段4，第三晶体管T3被发光控制信号的高电平导通，第一晶体管T1由于上一阶段第一节点N1的电平也保持导通状态；同时，第二晶体管T2被扫描信号的低电平截止，第四晶体管T4被复位信号(扫描信号)的低电平截止。
如图10所示，在发光阶段4，形成一条驱动发光路径(如图10中带箭头的虚线所示)。发光元件OLED可以在流经第一晶体管T1的驱动电流的作用下发光。在发光阶段4中，第三节点N3的电位为V OLED+VSS，由于第三晶体管T3被发光控制信号的高电平导通，所以第二节点N2的电位由Vref-Vth+(Vdata-Vref)C1/(C1+C2)变为和第三节点N3的电位相等，由上述可知，当电容的一极的电位改变时，该电容的另一极也会相应的改变，因此，在此阶段，第一节点N1的电位变为V OLED+VSS-(Vdata-Vref)C1/(C1+C2)-Vref+Vth+Vdata。
具体地，流经发光元件OLED的驱动电流I OLED的值可以根据下述公式得出：
I OLED＝1/2*K*(Vgs-Vth) 2
将如下值：
Vg＝V N1＝V OLED+VSS-(Vdata-Vref)C1/(C1+C2)-Vref+Vth+Vdata，
Vs＝V N2＝V OLED+VSS
代入上述公式可以得到：
I OLED＝1/2*K*((Vdata-Vref)C2/(C1+C2)) 2
在上述公式中，Vth表示第一晶体管T1的阈值电压，Vgs表示第一晶体管T1的栅极和第二极(例如源极)之间的电压，Vg表示第一晶体管T1的栅极的电位，Vs表示第一晶体管T1的第二极(例如源极)的电位，V N1表示第一节点N1的电位，V N2表示第二节点N2的电位，K为一常数值。
从上述公式可以看出，一方面，流经发光元件OLED的驱动电流I OLED不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除阈值电压对驱动电流I OLED的影响，从而可以避免显示不均匀的现象，改善显示效果；另一方面，流经发光元件OLED的驱动电流I OLED也不再与第一电压VDD有关，从而解决了由于集成电路远端和近端的第一电压VDD的电压压降不同引起的亮度差异的问题，从而可以改善采用该像素电路的显示装置的显示效果。
需要说明的是，在本公开的实施例中，对一个节点(例如第一节点N1、第二节点N2等)进行充电表示对与该节点电连接的电容进行充电；类似地，对该节点进行放电即表示对与该节点电连接的电容进行放电。
需要注意的是，由于之前的第三节点N3的电位为复位电压Vinit，发光时第三节点N3的电位变为Voled+Vss，从而在发光阶段4，第三节点N3的电位会有Voled+Vss-Vinit的变化，在第三晶体管T3导通时，由于第二节点N2与第三节点N3连接，从而第三节点N3的电位的变化会影响第二节点N2的电位的变化，从而影响Vgs-Vth的值。对于这种现象，可以通过增大第二存储电容C2的电容值来避免，使得第二存储电容C2的电容值远大于发光元件OLED的寄生电容的电容值，从而可以一定程度上避免第三节点N3的电位变化导致的显示问题。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的， 所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，图5所示的像素电路10中的晶体管均是以N型晶体管为例进行说明的，此时，第一极可以是漏极，第二极可以是源极。本公开的实施例包括但不限于图5的配置方式，例如如图11所示，在本公开的另一个实施例中，像素电路10中的晶体管也可以混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的各端的极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。例如，如图11所示，第一晶体管T1采用N型晶体管，第二晶体管T2、第三晶体管T3和第四晶体管T4采用P型晶体管，需要注意的是，此时提供给第二晶体管T2、第三晶体管T3和第四晶体管T4的信号电平需要进行相应的改变，例如由高电平变更为低电平或者由低电平变为高电平。
需要说明的是，当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及避免漏电流的产生。
本公开至少一个实施例还提供一种显示面板，该显示面板包括阵列布置的多个像素单元，该多个像素单元中的每个包括本公开任一实施例提供的像素电路。
图12为本公开一实施例提供的一种显示面板的示意框图。如图12所示，显示面板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该显示面板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条扫描线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括多个像素单元P，该像素单元P包括本公开的实施例中提供的任一像素电路10。例如，包括图5所示的像素电路10。如 图12所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线GL对应连接到每行像素单元P的像素电路10中的数据写入电路200以提供扫描信号，并且该多条扫描线GL还可以对应连接到每行像素单元P的像素电路10中的复位电路600以提供复位信号，在这种情形下，将扫描信号作为复位信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图12所示，每个像素单元P连接到三条扫描线GL(分别提供扫描信号、复位信号以及发光控制信号)、一条数据线DL、用于提供第一电压的第一电压线、用于提供第二电压的第二电压线以及用于提供复位电压的复位电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图12中仅示出了部分的像素单元P、扫描线GL、数据线DL。需要注意的是，在本公开实施例中，由于扫描线提供的扫描信号还可以用作复位信号，所以每个像素单元P可以仅连接到两条扫描线GL，即一条扫描线GL用于提供扫描信号和复位信号，另一条扫描线GL用于提供发光控制信号。以下实施例与此相同，不再赘述。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的数据写入电路200和复位电路600连接到同一条扫描线GL，每一行像素单元P的像素电路的发光控制电路500连接到另一条扫描线GL以接收发光控制信号。例如，每一列的数据线DL和本列像素电路10中的数据写入电路200连接以提供数据信号。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括扫描信号、发光控制信号以及复位信号。这些信号通过多条扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动 器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于控制栅极驱动器12和数据驱动器14。
例如，数据驱动器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电压线、多条第二电压线和多条复位电压线连接以分别提供第一电压、第二电压和复位电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的显示面板11可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
关于显示面板11的技术效果可以参考本公开的实施例中提供的像素电路10的技术效果，这里不再赘述。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的像素电路10。例如，在图2所示的示例中，该驱动方法包括如下操作：
在补偿阶段，输入扫描信号，开启数据写入电路200和驱动电路100，补偿电路300对驱动电路100进行补偿；以及
在数据写入阶段，输入扫描信号和数据信号，开启数据写入电路200，数据写入电路200将数据信号写入补偿电路300，且补偿电路300根据驱动电路100的控制端130的电压变化量耦合调整驱动电路100的第二端120的电压。
例如，在图3所示的示例中，在补偿电路300包括第一补偿子电路310和第二补偿子电路320的情况下，该驱动方法包括如下操作：
在补偿阶段，输入扫描信号，开启数据写入电路200和驱动电路100，第一补偿子电路310对驱动电路100进行补偿；以及
在数据写入阶段，输入扫描信号和数据信号，开启数据写入电路200，数据写入电路200将数据信号写入第一补偿子电路310，且第二补偿子电路320根据驱动电路100的控制端130的电压变化量耦合调整驱动电路100的第二端120的电压。
例如，在图4或图5所示的示例中，该驱动方法包括如下操作：
例如，在像素电路10还包括发光控制电路500的情况下，该驱动方法 还包括发光阶段。在发光阶段，输入发光控制信号，开启发光控制电路500和驱动电路100，第一补偿子电路310根据驱动电路100的第二端120的电压的变化耦合调整驱动电路100的控制端130的电压，发光控制电路500将驱动电流施加至发光元件OLED以使其发光。
例如，在像素电路10还包括复位电路600的情况下，该驱动方法还包括复位阶段。在复位阶段，输入复位信号、扫描信号和发光控制信号，开启复位电路600、数据写入电路200和发光控制电路500，对第一补偿子电路310、第二补偿子电路320和发光元件OLED进行复位，例如该复位信号和该扫描信号同步，又例如，该扫描信号可以作为复位信号。
本公开的实施例提供的驱动方法，一方面，可以对像素电路的驱动电路的阈值电压进行补偿，从而可以避免显示装置显示不均匀的现象；另一方面，还可以解决由于集成电路远端和近端的电压压降不同引起的亮度差异的问题，从而可以改善采用该像素电路的显示装置的显示效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种像素电路，包括：数据写入电路、驱动电路、补偿电路和发光元件；其中，
    所述驱动电路包括控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；
    所述数据写入电路连接到所述驱动电路的控制端且被配置为响应于扫描信号将数据信号写入所述驱动电路的控制端；
    所述补偿电路和所述驱动电路的控制端、所述驱动电路的第一端、所述驱动电路的第二端以及第一电压端连接，且被配置为存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿以及耦合调整所述驱动电路的第二端的电压；
    所述发光元件包括第一端和第二端，所述发光元件的第一端被配置为接收所述驱动电流，所述发光元件的第二端与第二电压端连接。
  2. 根据权利要求1所述的像素电路，其中，所述补偿电路包括第一补偿子电路和第二补偿子电路；其中，
    所述第一补偿子电路和所述驱动电路的控制端以及所述驱动电路的第二端连接，且被配置为存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿；
    所述第二补偿子电路和所述第一电压端、所述驱动电路的第一端以及所述驱动电路的第二端连接，且被配置为根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
  3. 根据权利要求2所述的像素电路，其中，所述第一补偿子电路还被配置为根据所述驱动电路的第二端的电压变化量耦合调整所述驱动电路的控制端的电压。
  4. 根据权利要求2或3所述的像素电路，其中，所述第一补偿子电路包括第一存储电容；
    所述第一存储电容的第一极和所述驱动电路的控制端连接，所述第一存储电容的第二极和所述驱动电路的第二端连接。
  5. 根据权利要求2-4任一所述的像素电路，其中，所述第二补偿子电路包括第二存储电容；
    所述第二存储电容的第一极和所述第一电压端以及所述驱动电路的第一端连接，所述第二存储电容的第二极和所述驱动电路的第二端连接。
  6. 根据权利要求1-5任一所述的像素电路，还包括发光控制电路，其中，
    所述发光控制电路和所述驱动电路的第二端以及所述发光元件的第一端连接，且被配置为响应于发光控制信号将所述驱动电流施加至所述发光元件。
  7. 根据权利要求6所述的像素电路，还包括复位电路，其中，
    所述复位电路与复位电压端以及所述发光元件的第一端连接，且被配置为响应于复位信号将复位电压施加至所述发光元件的第一端；
    其中，所述复位信号和所述扫描信号同步。
  8. 根据权利要求1-7任一所述的像素电路，其中，所述驱动电路包括第一晶体管；
    所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端且被配置为和所述第一电压端连接以接收第一电压，所述第一晶体管的第二极作为所述驱动电路的第二端。
  9. 根据权利要求1-8任一所述的像素电路，其中，所述数据写入电路包括第二晶体管；
    所述第二晶体管的栅极被配置为和扫描线连接以接收所述扫描信号，所述第二晶体管的第一极被配置为和数据线连接以接收所述数据信号，所述第二晶体管的第二极被配置为和所述驱动电路的控制端连接。
  10. 根据权利要求6或7所述的像素电路，其中，所述发光控制电路包括第三晶体管；
    所述第三晶体管的栅极被配置为和发光控制线连接以接收所述发光控制信号，所述第三晶体管的第一极被配置为和所述驱动电路的第二端连接，所述第三晶体管的第二极被配置为和所述发光元件的第一端连接。
  11. 根据权利要求7所述的像素电路，其中，所述复位电路包括第四晶体管；
    所述第四晶体管的栅极被配置为和复位控制线连接以接收所述复位信号，所述第四晶体管的第一极被配置为和所述复位电压端连接以接收所述复位电压，所述第四晶体管的第二极被配置为和所述发光元件的第一端 连接。
  12. 根据权利要求7所述的像素电路，其中，所述复位电路包括第四晶体管；
    所述第四晶体管的栅极被配置为和扫描线连接以接收所述扫描信号并作为所述复位信号，所述第四晶体管的第一极被配置为和所述复位电压端连接以接收所述复位电压，所述第四晶体管的第二极被配置为和所述发光元件的第一端连接。
  13. 一种显示面板，包括阵列布置的多个像素单元，其中，所述多个像素单元中的每个包括如权利要求1-12任一所述的像素电路。
  14. 根据权利要求13所述的显示面板，还包括多条扫描线，其中，所述多条扫描线对应连接到每行像素单元的像素电路的数据写入电路以提供所述扫描信号。
  15. 根据权利要求14所述的显示面板，其中，在所述像素电路包括复位电路的情形下，所述多条扫描线还对应连接到每行像素单元的像素电路中的复位电路以提供所述扫描信号，并将所述扫描信号作为所述复位信号。
  16. 一种如权利要求1-12任一所述的像素电路的驱动方法，包括补偿阶段和数据写入阶段；其中，
    在所述补偿阶段，输入所述扫描信号，开启所述数据写入电路和所述驱动电路，所述补偿电路对所述驱动电路进行补偿；以及
    在所述数据写入阶段，输入所述扫描信号和所述数据信号，开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述补偿电路，且所述补偿电路根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
  17. 一种如权利要求1-12任一所述的像素电路的驱动方法，在所述补偿电路包括第一补偿子电路和第二补偿子电路的情形下，所述驱动方法包括补偿阶段和数据写入阶段；其中，
    在所述补偿阶段，输入所述扫描信号，开启所述数据写入电路和所述驱动电路，所述第一补偿子电路对所述驱动电路进行补偿；以及
    在所述数据写入阶段，输入所述扫描信号和所述数据信号，开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述第一补偿子电 路，且所述第二补偿子电路根据所述驱动电路的控制端的电压变化量耦合调整所述驱动电路的第二端的电压。
  18. 根据权利要求17所述的像素电路的驱动方法，在所述像素电路包括发光控制电路的情形下，所述驱动方法还包括发光阶段；其中，
    在所述发光阶段，输入所述发光控制信号，开启所述发光控制电路和所述驱动电路，所述第一补偿子电路根据所述驱动电路的第二端的电压变化量耦合调整所述驱动电路的控制端的电压，所述发光控制电路将所述驱动电流施加至所述发光元件以使得所述发光元件发光。
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