WO2019174228A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2019174228A1
WO2019174228A1 PCT/CN2018/110673 CN2018110673W WO2019174228A1 WO 2019174228 A1 WO2019174228 A1 WO 2019174228A1 CN 2018110673 W CN2018110673 W CN 2018110673W WO 2019174228 A1 WO2019174228 A1 WO 2019174228A1
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Prior art keywords
circuit
signal
bias
transistor
emitting element
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PCT/CN2018/110673
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English (en)
French (fr)
Inventor
陈鹏
王梓轩
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/478,419 priority Critical patent/US11328668B2/en
Publication of WO2019174228A1 publication Critical patent/WO2019174228A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, and a display panel.
  • Organic Light Emitting Diode (OLED) display devices are gradually gaining popularity due to their wide viewing angle, high contrast ratio, fast response speed, and higher brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, the organic light emitting diode (OLED) can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) driving and a passive matrix (PM) driving according to whether or not a switching component is introduced in each pixel unit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the driving of the thin film transistor and the storage capacitor, the current flowing through the OLED is controlled, so that the OLED is required according to the needs. Glowing.
  • AMOLED Compared with PMOLED, AMOLED requires less drive current, lower power consumption and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving circuit, a data writing circuit, a memory circuit, a light emitting element, and a bias circuit; wherein the driving circuit includes a control end, a first end, and a second end, And configured to control a driving current for driving the light emitting element to emit light, the second end of the driving circuit receives the first voltage signal of the first voltage end; the data writing circuit is connected to the control end of the driving circuit, and is configured Writing a data signal to a control end of the driving circuit in response to the scan signal; a first end of the memory circuit is coupled to a control terminal of the driving circuit, a second end of the memory circuit and the driving circuit The first end is connected to be configured to store the data signal written by the data writing circuit; the first end of the light emitting element receives a second voltage signal of the second voltage end, and the second end of the light emitting element The first end of the driving circuit is connected to be configured to emit light according to the driving current; the biasing circuit is
  • the bias circuit includes a first capacitor and a first transistor; and a first pole of the first capacitor is configured to be connected to a second end of the light emitting element, a second pole of the first capacitor is configured to be coupled to a first pole of the first transistor; a gate of the first transistor is configured to be coupled to a bias enable end to receive the bias enable signal, A second pole of the first transistor is configured to be coupled to the bias amplitude terminal to receive the bias amplitude signal.
  • the driving circuit includes a second transistor; a gate of the second transistor serves as a control terminal of the driving circuit, and a first pole of the second transistor serves as a first end of the driving circuit, and a second end of the second transistor serves as a second end of the driving circuit.
  • the data writing circuit includes a third transistor; a gate of the third transistor is configured to be connected to the scan end to receive the scan signal, and the third A first pole of the transistor is configured to be coupled to the data terminal to receive the data signal, and a second pole of the third transistor is configured to be coupled to the control terminal of the driver circuit.
  • the memory circuit includes a second capacitor; a first pole of the second capacitor serves as a first end of the memory circuit, and a second capacitor The pole acts as the second end of the storage circuit.
  • a pixel circuit provided in an embodiment of the present disclosure includes a reset circuit, wherein the reset circuit is connected to a control end of the driving circuit, and configured to apply a reset voltage to a control end of the driving circuit in response to a reset signal .
  • the reset circuit includes a fourth transistor; a gate of the fourth transistor is configured to be connected to a reset terminal to receive the reset signal, and the fourth transistor
  • the first pole is configured to be coupled to the control terminal of the drive circuit, and the second pole of the fourth transistor is configured to be coupled to the first voltage terminal to receive the reset voltage.
  • a pixel circuit provided in an embodiment of the present disclosure includes a light emission control circuit, wherein the light emission control circuit is connected to a first end of the light emitting element, and configured to be in a second voltage end in response to a light emission control signal A second voltage signal is applied to the first end of the light emitting element.
  • the light emission control circuit includes a fifth transistor; a gate of the fifth transistor is configured to be connected to the light emission control end to receive the light emission control signal, A first pole of the five transistor is configured to be coupled to the second voltage terminal to receive the second voltage signal, and a second pole of the fifth transistor is configured to be coupled to the first end of the light emitting element.
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units distributed in an array, the pixel unit including the pixel circuit of any of the embodiments of the present disclosure.
  • a display panel provided in an embodiment of the present disclosure includes a plurality of scan lines, wherein a data write circuit in a pixel circuit of the Nth row is connected to a scan line of the Nth row to receive the scan signal, the Nth row a bias circuit in the pixel circuit is connected to the scan line of the N-1th row to receive the scan signal of the N-1th row as the bias enable signal and/or the bias amplitude signal, where N is greater than 1. Integer.
  • the reset circuit in the pixel circuit of the Nth row is connected to the scan line of the N-2th row to receive the scan signal of the N-2th row as the reset signal.
  • N is an integer greater than 2.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit according to any one of the embodiments of the present disclosure, including: an offset phase and a data writing phase; wherein, in the biasing phase, the bias is input Activating a signal to turn on the bias circuit, the bias circuit applying the bias voltage to a second end of the light emitting element according to the bias amplitude signal to reverse bias the light emitting element;
  • the scan signal and the data signal are input to turn on the data writing circuit and the driving circuit, and the data writing circuit writes the data signal into the driving circuit
  • the memory circuit stores the data signal, and the light emitting element emits light according to the driving current.
  • the driving method further includes a reset phase; wherein, in the reset phase, a reset signal is input.
  • the reset circuit applies a reset voltage to the control terminal of the drive circuit and the first end of the memory circuit to reset the drive circuit and the memory circuit.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit according to any one of the embodiments of the present disclosure, including: a bias phase, a data writing phase, and an illumination phase; wherein, in the bias phase, the input Deriving a bias enable signal to turn on the bias circuit, the bias circuit applying the bias voltage to a second end of the light emitting element according to the bias amplitude signal to reverse the light emitting element Offseting; in the data writing phase, inputting the scan signal and the data signal to turn on the data write circuit, the data write circuit writing the data signal to the drive circuit, a storage circuit storing the data signal; in the light emitting phase, inputting the light emission control signal to turn on the light emission control circuit, the light emission control circuit and the drive circuit applying the drive current to the light emitting element Make it glow.
  • FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 1;
  • FIG. 4 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2;
  • FIG. 5 is a timing diagram of signals of a pixel circuit according to an embodiment of the present disclosure.
  • 6A to 6C are circuit diagrams respectively showing the pixel circuit shown in FIG. 3 corresponding to the three stages in FIG. 5;
  • FIG. 7 is a timing diagram of signals of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a circuit diagram of the pixel circuit shown in FIG. 4 corresponding to the fourth stage of FIG. 7;
  • FIG. 9 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of another display panel according to an embodiment of the present disclosure.
  • OLED In the field of display and lighting, the service life of OLED devices has always been the focus of major manufacturers. Since the OLED is a self-luminous device, the OLED may age during the illuminating process, resulting in a decrease in brightness. The aging mechanism of OLEDs includes various factors such as device inherent defects, OLED device degradation, and the like.
  • pixel circuits for driving OLEDs such as a 2T1C circuit composed of two Thin Film Transistors (TFTs) and one capacitor (Capacitor, C), or with threshold voltage compensation. Functional 4T1C, 4T2C circuit, etc. These pixel circuits cannot improve the aging of the OLED device itself, and cannot effectively extend the service life of the OLED device.
  • At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display panel.
  • the pixel circuit can apply a reverse voltage difference after the OLED emits light, and promotes elimination of defects accumulated in the positive pressure stage of the OLED, thereby improving the aging problem of the OLED device itself, thereby extending the service life of the OLED device.
  • the pixel circuit is used for a display panel, it is not necessary to add a new signal to the display panel, which is easy to implement, and the life of the display panel can be extended.
  • At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a data writing circuit, a memory circuit, a light emitting element, and a bias circuit.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current for driving the light emitting element to emit light, and the second end of the driving circuit receives the first voltage signal of the first voltage end; a data write circuit coupled to the control terminal of the drive circuit and configured to write a data signal to a control terminal of the drive circuit in response to the scan signal; a first end of the memory circuit and a control terminal of the drive circuit Connected, the second end of the storage circuit is connected to the first end of the driving circuit, configured to store the data signal written by the data writing circuit; the first end of the light emitting element receives the second voltage a second voltage signal of the terminal, the second end of the light emitting element is coupled to the first end of the driving circuit, configured to emit light according to the driving current; and the bias circuit is coupled
  • FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 10 includes a drive circuit 100, a data write circuit 200, a memory circuit 300, a reset circuit 400, a light emitting element 500, and a bias circuit 600.
  • the pixel circuit 10 is used, for example, for a sub-pixel of an OLED display device.
  • the driving circuit 100 includes a first end 110, a second end 120, and a control end 130, and is configured to control a driving current for driving the light emitting element 500 to emit light, and the second end 120 of the driving circuit 100 receives the first of the first voltage end VSS. Voltage signal.
  • the control terminal 130 of the driving circuit 100 is connected to the first node N1, the first end 110 of the driving circuit 100 is connected to the second node N2, and the second end 120 of the driving circuit 100 is connected to the first voltage terminal VSS (third node N3) To receive the first voltage signal.
  • the driving circuit 100 may supply a driving current to the light emitting element 500 to drive the light emitting element 500 to emit light, and may emit light according to a desired "grayscale".
  • the light emitting element 500 can employ an OLED and is configured to be coupled to the second node N2 and the second voltage terminal VDD (eg, a high level), and embodiments of the present disclosure include, but are not limited to, the case.
  • the data write circuit 200 is coupled to the control terminal 130 (first node N1) of the drive circuit 100 and is configured to write a data signal to the control terminal 130 of the drive circuit 100 in response to the scan signal.
  • the data write circuit 200 is connected to the data signal terminal Vdata, the first node N1, and the scan signal terminal Vscan(n), respectively.
  • a scan signal from the scan signal terminal Vscan(n) is applied to the data write circuit 200 to control whether the data write circuit 200 is turned on or not.
  • the data writing circuit 200 can be turned on in response to the scan signal, so that the data signal can be written to the control terminal 130 (first node N1) of the driving circuit 100, and then the data signal can be stored in the memory.
  • a drive current for driving the light-emitting element 500 to emit light is generated based on the data signal.
  • the first end 310 of the memory circuit 300 is connected to the control terminal 130 (first node N1) of the driving circuit 100, and the second end 320 of the memory circuit 300 is connected to the first terminal 110 (second node N2) of the driving circuit 100.
  • the memory circuit 300 can store the data signal and control the drive circuit 100 using the stored data signal.
  • the reset circuit 400 is coupled to the control terminal 130 (first node N1) of the drive circuit 100 and is configured to apply a reset voltage to the control terminal 130 of the drive circuit 100 and the first terminal 310 of the memory circuit 300 in response to the reset signal.
  • the reset circuit 400 is connected to the first node N1, the first voltage terminal VSS (third node N3), and the reset terminal Rst, respectively.
  • the reset circuit 400 can be turned on in response to the reset signal, so that the reset voltage (here, the voltage for resetting is the first voltage signal) can be applied to the first node N1, the first end 310 of the memory circuit 300, and the driving circuit 100.
  • the control terminal 130 can thereby perform a reset operation on the memory circuit 300 and the drive circuit 100 to eliminate the influence of the previous illumination phase.
  • the reset voltage may be provided by the first voltage terminal VSS, and in other embodiments may also be provided by a reset voltage terminal independent of the first voltage terminal VSS, whereby accordingly, the reset circuit 400 is not connected to the first voltage terminal VSS.
  • the third node N3 is connected to the reset voltage terminal, which is not limited in the embodiment of the present disclosure.
  • the first voltage terminal VSS is a low voltage terminal, for example, a ground terminal.
  • the reset circuit 400 can also be omitted or integrated into other circuits depending on the particular circuit configuration.
  • the Nth (N is an integer greater than 2) row of the data writing circuit 200 and the Nth row of scanning lines (or the scanning signal terminal Vscan(n) )) is connected to receive the scan signal
  • the reset circuit 400 of the Nth row is connected to the scan line of the N-2th row (or the scan signal terminal Vscan(n-2)) to receive the scan signal of the N-2th row as the reset signal .
  • this method does not need to add a new signal, and the circuit structure is simple and easy to implement.
  • the embodiment of the present disclosure is not limited thereto, and the reset circuit 400 may also be connected to a reset signal line that is separately provided to receive a reset signal that is separately provided.
  • the light emitting element 500 includes a first end 510 and a second end 520 configured to emit light according to a driving current provided by the driving circuit 100.
  • the first end 510 of the light emitting element 500 is configured to receive a second voltage signal of the second voltage terminal VDD, and the second end 520 of the light emitting element 500 is configured to be coupled to the first end 110 (second node N2) of the driving circuit 100.
  • the bias circuit 600 is coupled to the second terminal 520 (second node N2) of the light emitting element 500, configured to apply a bias voltage to the second end 520 of the light emitting element 500 in response to the bias enable signal and in accordance with the bias amplitude signal.
  • the light emitting element 500 is reverse biased.
  • the bias circuit 600 is coupled to the second node N2, the bias enable terminal Vb, and the bias amplitude terminal Vamp, respectively.
  • the bias circuit 600 can be turned on in response to a bias enable signal provided by the bias enable terminal Vb to apply a bias voltage to the second terminal 520 of the light emitting element 500 in accordance with the bias amplitude signal provided by the bias amplitude terminal Vamp.
  • the bias voltage may not be equal to the bias amplitude signal.
  • the light-emitting element 500 for example, OLED
  • the light-emitting element 500 emits light
  • it is biased to be reverse-biased, which can promote the elimination of defects accumulated in the positive voltage phase (for example, the light-emitting phase) of the light-emitting element 500, thereby improving the light-emitting element.
  • the problem of aging of the 500 itself serves to extend the life of the light-emitting element 500.
  • the bias enable terminal Vb and the bias amplitude terminal Vamp can be connected to the same signal line, so that the bias enable signal and the bias amplitude signal are the same signal, which simplifies the circuit design.
  • the Nth N is an integer greater than 1 row of the data writing circuit 200 and the Nth row of scanning lines (or the scanning signal terminal Vscan(n) )) is connected to receive the scan signal
  • the bias circuit 600 of the Nth row is connected to the scan line of the N-1th row (or the scan signal terminal Vscan(n-1)) to receive the scan signal of the N-1th row as a bias Set the start signal and / or bias amplitude signal.
  • the scanning signal of the pixel circuit 10 can be utilized, and it is not necessary to add a new signal with respect to the conventional display panel, and the circuit structure is simple and easy to implement.
  • the bias circuit 600 may also be connected to a separately provided bias enable signal line and/or bias amplitude signal line to receive a separately provided bias enable signal and/or bias amplitude. signal.
  • FIG. 2 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 10 may further include an illumination control circuit 700, the other structure being substantially the same as the pixel circuit 10 shown in FIG.
  • the illumination control circuit 700 is coupled to the first end 510 of the light emitting element 500 and is configured to apply a second voltage signal of the second voltage terminal VDD to the first end 510 of the light emitting element 500 in response to the illumination control signal.
  • the light emission control circuit 700 is connected to the second voltage terminal VDD, the light emission control terminal Em, and the first end 510 of the light emitting element 500, respectively.
  • the light emission control circuit 700 is turned on in response to the light emission control signal provided by the light emission control terminal Em, so that the driving circuit 100 can apply a driving current to the light emitting element 500 through the light emission control circuit 700 to cause it to emit light;
  • the illuminating control circuit 700 is turned off in response to the illuminating control signal, thereby preventing current from flowing through the illuminating element 500 to cause it to illuminate, and the contrast of the corresponding display device can be improved.
  • the driving circuit 100 is implemented as a driving transistor
  • the gate of the driving transistor may serve as the control terminal 130 of the driving circuit 100 (connected to the first node N1), and the first pole (eg, source) may function as a driving circuit
  • the first end 110 of the 100 connected to the second node N2), the second pole (eg, the drain) can serve as the second end 120 of the drive circuit 100 (connected to the third node N3).
  • the first voltage terminal VSS in each embodiment of the present disclosure keeps, for example, an input DC low level signal, and the DC low level is referred to as a first voltage (which can be used as a reset voltage); the second voltage terminal VDD For example, the input DC high level signal is maintained, and the DC high level is referred to as a second voltage and is higher than the first voltage.
  • the following embodiments are the same as those described herein and will not be described again.
  • the symbol Vdata may represent both the data signal end and the level of the data signal.
  • the symbol Rst can represent both the reset terminal and the level of the reset signal
  • the symbol VSS can represent both the first voltage terminal and the first voltage
  • the symbol VDD can represent both the second voltage terminal and the second voltage.
  • the symbol Vb can represent both the bias start and the level of the bias enable signal
  • the symbol Vamp can represent both the bias amplitude terminal and the level of the bias amplitude signal.
  • the pixel circuit 10 provided by the embodiments of the present disclosure may further include other circuit structures having a compensation function.
  • the compensation function can be implemented by voltage compensation, current compensation or hybrid compensation, and the pixel circuit 10 having the compensation function can be, for example, a combination of a circuit such as 4T1C or 4T2C and a bias circuit 600.
  • the data write circuit 200 and the compensation circuit cooperate to write the voltage value carrying the data signal and the threshold voltage information of the drive transistor in the drive circuit 100 to the control terminal of the drive circuit 100. 130 is stored by the storage circuit 300.
  • An example of a specific compensation circuit is not described in detail herein.
  • the pixel circuit 10 provided by the embodiment of the present disclosure can apply a reverse voltage difference to the light-emitting element 500 after it emits light, and promote the elimination of the defects accumulated by the light-emitting element 500 during the positive pressure phase, thereby improving the problem of aging of the light-emitting element 500 itself. This has the effect of extending the life of the light-emitting element 500, and in the case where the pixel circuit 10 is used for a display panel, it is not necessary to add a new signal to the display panel, and it is easy to implement.
  • FIG. 3 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG.
  • the pixel circuit 10 includes first to fourth transistors T1, T2, T3, and T4 and includes a first capacitor C1, a second capacitor C2, and a light-emitting element L1.
  • the second transistor T2 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element L1 may be various types of OLEDs, such as top emission, bottom emission, double-sided emission, etc., and may emit red, green, blue, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • the bias circuit 600 can be implemented as a first capacitor C1 and a first transistor T1.
  • the first pole of the first capacitor C1 is configured to be connected to the second end 520 (second node N2) of the light emitting element L1, and the second pole of the first capacitor C1 is configured to be connected to the first pole of the first transistor T1.
  • the gate of the first transistor T1 is configured to be coupled to the bias enable terminal Vb to receive a bias enable signal
  • the second electrode of the first transistor T1 is configured to be coupled to the bias amplitude terminal Vamp to receive the bias amplitude signal.
  • the bias circuit 600 may also be a circuit composed of other components.
  • the drive circuit 100 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected as the control terminal 130 of the driving circuit 100 to the first node N1; the first electrode of the second transistor T2 is connected as the first terminal 110 of the driving circuit 100 and the second node N2; the second transistor T2 The second pole is connected as the second end 120 of the driving circuit 100 and the third node N3.
  • the driving circuit 100 may also be a circuit composed of other components.
  • the driving circuit 100 may have two sets of driving transistors.
  • the two sets of driving transistors may be switched according to specific conditions.
  • the data write circuit 200 can be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the scan signal terminal Vscan(n) to receive the scan signal
  • the first pole of the third transistor T3 is configured to be connected to the data signal terminal Vdata to receive the data signal
  • the third transistor T3 The two poles are configured to be connected to the first node N1.
  • the data writing circuit 200 may be a circuit composed of other components.
  • the memory circuit 300 can be implemented as a second capacitor C2.
  • the first pole of the second capacitor C2 is configured to be connected to the first node N1 as the first end 310 of the storage circuit 300, and the second pole 320 of the second capacitor C2 is configured as the second end 320 of the storage circuit 300 and the second node N2. connection.
  • the memory circuit 300 may also be a circuit composed of other components.
  • the memory circuit 300 may include two capacitors connected in parallel/series in parallel with each other.
  • the reset circuit 400 can be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be connected to the reset terminal Rst to receive the reset signal
  • the first electrode of the fourth transistor T4 is connected to the control terminal 130 (first node N1) of the driving circuit 100
  • the second transistor T4 is connected to the second transistor T4.
  • the pole is configured to be coupled to the first voltage terminal VSS (third node N3) to receive the first voltage signal (which can be used as a reset voltage).
  • the reset circuit 400 may also be a circuit composed of other components.
  • the reset circuit 400 may also be connected to the second end 520 of the light emitting element 500 for further use of the light emitting element 500. The second end 520 is reset (but not biased).
  • the light emitting element 500 can be implemented as a light emitting element L1 (eg, an OLED).
  • a first end (here an anode) of the light-emitting element L1 is configured as a first end 510 of the light-emitting element 500 to be coupled to the second voltage terminal VDD for receiving a second voltage signal, the second end of the light-emitting element L1 (here, a cathode) being The second end 520 of the light emitting element 500 is coupled to the second node N2 and configured to receive a drive current from the first end 110 of the drive circuit 100.
  • the second voltage terminal VDD maintains an input DC high level signal, that is, VDD can be a high level.
  • the anodes of the light-emitting elements L1 can be electrically connected to the same voltage terminal, that is, by a common anode connection.
  • the first node N1, the second node N2, and the third node N3 do not represent actual components, but represent convergence points of related electrical connections in the circuit diagram.
  • FIG. 4 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2.
  • the pixel circuit 10 shown in FIG. 4 is substantially the same as the pixel circuit 10 shown in FIG. 3, except that the pixel circuit 10 shown in FIG. 4 further includes a fifth transistor T5 to implement the light emission control circuit 700.
  • the illumination control circuit 700 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the light emission control terminal Em to receive the light emission control signal
  • the first electrode of the fifth transistor T5 is configured to be connected to the second voltage terminal VDD to receive the second voltage signal
  • the fifth transistor T5 The second pole is configured to be coupled to the first end of the light emitting element L1.
  • the illumination control circuit 700 may also be a circuit composed of other components.
  • FIG. 5 is a timing diagram of signals of a pixel circuit according to an embodiment of the present disclosure.
  • the operation principle of the pixel circuit 10 shown in FIG. 3 will be described below with reference to the signal timing chart shown in FIG. 5.
  • the description will be made by taking an example in which each transistor is an N-type transistor, but the embodiment of the present disclosure is not limited thereto.
  • the display process of each frame image includes three phases, namely, a reset phase 1, a bias phase 2, and a data writing phase 3, which show timing waveforms of respective signals in each phase.
  • FIG. 6A to FIG. 6C are schematic diagrams of the pixel circuit 10 shown in FIG. 3 in the above three stages, respectively.
  • 6A is a schematic diagram of the pixel circuit 10 shown in FIG. 3 in the reset phase 1
  • FIG. 6B is a schematic diagram of the pixel circuit 10 shown in FIG. 3 in the bias phase 2
  • FIG. 6C is a diagram shown in FIG. A schematic diagram of the pixel circuit 10 at the time of data writing phase 3.
  • the transistors identified by broken lines in FIGS. 6A to 6C each indicate that they are in an off state in the corresponding phase, and the dotted line with arrows in FIGS. 6A to 6C indicates the current direction of the pixel circuit in the corresponding phase.
  • the transistors shown in FIGS. 6A to 6C are each exemplified by an N-type transistor, that is, the gates of the respective transistors are turned on when they are connected to a high level, and are turned off when they are connected to a low level.
  • the following embodiments are the same as those described herein and will not be described again.
  • a reset signal (provided by the reset terminal Rst) is input to turn on the reset circuit 400, and the reset circuit 400 applies a reset voltage (provided by the first voltage terminal VSS) to the control terminal 130 of the drive circuit 100 and the memory circuit 300.
  • the first terminal 310 is configured to reset the driving circuit 100 and the memory circuit 300.
  • the fourth transistor T4 is turned on by the high level of the reset signal; meanwhile, the first transistor T1 is turned off by the low level of the bias enable signal, and the third transistor T3 is turned off.
  • the low level of the scan signal is turned off, and the second transistor T2 is turned off by the low level of the first node N1.
  • a reset path is formed (as indicated by a broken line with an arrow in FIG. 6A), and since the fourth transistor T4 is turned on, a reset voltage can be applied to the gate of the second transistor T2 ( The first node N1) and the first pole of the second capacitor C2. Since the reset voltage is a low level signal (eg, grounded or other low level signal), the second capacitor C2 is discharged through the reset path, thereby resetting the second transistor T2 and the second capacitor C2.
  • the gate of the third transistor T3 of the Nth (N is an integer greater than 2) and the scanning line of the Nth row (or the scanning signal terminal Vscan) (n)) connected to receive the scan signal
  • the gate of the fourth transistor T4 of the Nth row is connected to the scan line of the N-2th row (or the scan signal terminal Vscan(n-2)) to receive the N-2th row
  • the scan signal is used as a reset signal.
  • the potential of the first node N1 is the reset voltage.
  • the second capacitor C2 is reset, discharging the charge stored in the second capacitor C2, so that the data signal in the subsequent stage can be stored in the second capacitor C2 more quickly and reliably.
  • the second transistor T2 since the second transistor T2 is turned off, the light-emitting element L1 is also reset, so that the light-emitting element L1 can be displayed in a black state, that is, not illuminated, before the data writing phase 3, to improve the display device using the pixel circuit 10 described above.
  • the contrast ratio and other display effects are examples of the first node N1 .
  • bias circuit 600 In bias phase 2, an input bias enable signal (provided by bias enable terminal Vb) is applied to turn on bias circuit 600, which applies a bias voltage based on the bias amplitude signal (provided by bias amplitude terminal Vamp) To the second end (second node N2) of the light-emitting element L1 to reverse-bias the light-emitting element L1.
  • the first transistor T1 is turned on by the high level of the bias enable signal; meanwhile, the second transistor T2 is turned off by the low level of the first node N1, and the third The transistor T3 is turned off by the low level of the scan signal, and the fourth transistor T4 is turned off by the low level of the reset signal.
  • a bias path is formed (as indicated by the dashed line with an arrow in FIG. 6B), and the bias voltage signal can be applied to the first capacitor C1 because the first transistor T1 is turned on.
  • the second pole The first capacitor C1 is charged during the display phase of the previous frame image, and the first pole (second node N2) of the first capacitor C1 and the second pole of the first capacitor C1 reach a potential balance.
  • the bias amplitude signal is applied to the second pole of the first capacitor C1
  • the potential of the first pole (second node N2) of the first capacitor C1 is raised due to the bootstrap effect of the first capacitor C1, thereby making The potential of the two nodes N2 is greater than VDD.
  • a bias voltage is applied to the light-emitting element L1, which can facilitate the elimination of defects accumulated in the light-emitting phase (positive voltage phase) of the image of the previous frame of the light-emitting element L1, thereby improving the problem of aging of the light-emitting element L1 itself and extending the light emission.
  • the gate of the third transistor T3 of the Nth (N is an integer greater than 1) and the scanning line of the Nth row (or the scanning signal terminal Vscan) (n)) connected to receive the scan signal, the gate and/or the second pole of the first transistor T1 of the Nth row being connected to the scan line of the N-1th row (or the scan signal terminal Vscan(n-1))
  • the scan signal of the N-1th row is received as a bias enable signal and/or a bias amplitude signal.
  • this method does not need to add a new signal, and the circuit structure is simple and easy to implement.
  • the potential of the second node N2 is a bias voltage.
  • the light-emitting element L1 is reversely biased, so that defects accumulated in the positive pressure phase can be eliminated, and the life of the light-emitting element L1 is effectively extended. Moreover, since the high-level time of the bias enable signal is short and is smaller than the resolution of the human eye, the display effect of the display device using the pixel circuit 10 described above is not affected.
  • an input scan signal (provided by the scan signal terminal Vscan(n)) and a data signal (provided by the data signal terminal Vdata) are turned on to turn on the data write circuit 200 and the drive circuit 100, and the data write circuit 200
  • the data signal is written to the drive circuit 100, the memory circuit 300 stores the data signal, and the light-emitting element L1 emits light according to the drive current.
  • the third transistor T3 is turned on by the high level of the scan signal, and the second transistor T2 is turned on by the high level of the first node N1;
  • the transistor T1 is turned off by the low level of the bias enable signal, and the fourth transistor T4 is turned off by the low level of the reset signal.
  • a data writing path is formed (shown by a broken line with an arrow in FIG. 6C), and the data signal passes through the third transistor T3 to charge the second capacitor C2.
  • Vth represents the threshold voltage of the second transistor T2. Since the second transistor T2 is described as an N-type transistor in the present embodiment, the threshold voltage Vth may be a positive value. In other embodiments, if the second transistor T2 is a P-type transistor, the threshold voltage Vth may be a negative value.
  • the value of the drive current I L1 flowing through the light-emitting element L1 can be obtained according to the following formula:
  • I L1 K(V GS –Vth) 2 ,
  • Vth represents the threshold voltage of the second transistor T2
  • V GS represents the voltage between the gate and the source of the second transistor T2 (here, the first pole)
  • K is associated with the second transistor T2 itself. Constant value. It can be seen that the driving current I L1 flowing through the light-emitting element L1 is related to V GS , that is, the light-emitting element L1 can emit light according to the data signal stored in the second capacitor C2.
  • the voltage information with the data signal is stored in the second capacitor C2, and the second transistor T2 provides the light-emitting element L1 under the control of the voltage difference between the first node N1 and the second node N2.
  • the current is driven to cause the light-emitting element L1 to emit light.
  • the pixel circuit 10 writes both the data signal and the light.
  • data writing and illuminating can also be implemented in two stages, respectively, in combination with a specific circuit structure, which is not limited by the embodiments of the present disclosure.
  • FIG. 7 is a timing diagram of signals of another pixel circuit according to an embodiment of the present disclosure.
  • the signal timing is substantially the same as the signal timing shown in FIG. 5 except that the illuminating phase 4 is also included.
  • the operation principle of the pixel circuit 10 shown in FIG. 4 will be described below with reference to the signal timing chart shown in FIG. 7.
  • the description will be made by taking an example in which each transistor is an N-type transistor, but the embodiment of the present disclosure is not limited thereto.
  • FIG. 8 is a circuit diagram of the pixel circuit 10 shown in FIG. 4 corresponding to the illumination stage 4 of FIG.
  • the transistors identified by dashed lines in Figure 8 are all shown in an off state during the corresponding phase, and the dashed arrows in Figure 8 indicate the direction of current flow of the pixel circuit 10 in the corresponding phase.
  • the reset phase 1, the offset phase 2, and the data write phase 3 are substantially the same as those of the pixel circuit 10 shown in FIGS. 5 and 6A to 6C, and are not described herein again.
  • an illumination control signal (provided by the illumination control terminal Em) is input to turn on the illumination control circuit 700, and the illumination control circuit 700 and the drive circuit 100 apply a drive current to the light-emitting element L1 to cause it to emit light.
  • the fifth transistor T5 is turned on by the high level of the light-emission control signal, and the second transistor T2 is turned on by the high level of the first node N1; meanwhile, the first transistor T1 is turned off by the low level of the bias enable signal, the third transistor T3 is turned off by the low level of the scan signal, and the fourth transistor T4 is turned off by the low level of the reset signal.
  • a driving light-emitting path is formed (as indicated by a broken line with an arrow in FIG. 8), and since the fifth transistor T5 and the second transistor T2 are turned on, a driving current can be supplied to the light-emitting element L1.
  • the light-emitting element L1 emits light under the action of a driving current.
  • the light-emitting element L1 emits light only in the light-emitting phase 4, and does not emit light in the data writing phase 3.
  • Data writing and illumination are respectively implemented in two stages, which is advantageous for ensuring the integrity of data writing and improving the contrast of the corresponding display device.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • one of the first poles and the other pole are directly described.
  • the transistors in the pixel circuit 10 shown in FIG. 3 and FIG. 4 are all described by taking an N-type transistor as an example.
  • the first pole may be the source, and the second pole may be Drain.
  • the transistors in the pixel circuit 10 may also use only P-type transistors or a mixture of P-type transistors and N-type transistors, and only need to simultaneously select the port polarity of the selected type of transistor according to the port pole of the corresponding transistor in the embodiment of the present disclosure.
  • the corresponding voltage terminal and signal terminal are provided with corresponding high level signals or low level signals.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS low temperature polysilicon
  • amorphous silicon for example, hydrogenation non-hydrogenation
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units distributed in an array, the pixel unit including the pixel circuit of any of the embodiments of the present disclosure.
  • the pixel circuit in the display panel can apply a reverse voltage difference after the OLED is illuminated, thereby facilitating elimination of defects accumulated in the positive pressure stage of the OLED, thereby improving the aging problem of the OLED device itself, thereby extending the OLED device.
  • the effect of the service life, and the display panel does not need to add a new signal, and is easy to implement.
  • FIG. 9 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 2000 is disposed in the display device 20 and is electrically connected to the gate driver 2010 and the data driver 2030.
  • Display device 20 also includes a timing controller 2020.
  • the display panel 2000 includes a pixel unit P defined according to a plurality of scan lines GL and a plurality of data lines DL; a gate driver 2010 for driving a plurality of scan lines GL; a data driver 2030 for driving a plurality of data lines DL; timing control
  • the processor 2020 is for processing the image data RGB input from the outside of the display device 20, supplying the processed image data RGB to the data driver 2030, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 2010 and the data driver 2030 to The pole driver 2010 and the data driver 2030 are controlled.
  • the display panel 2000 includes a plurality of pixel units P including the pixel circuits 10 provided in any of the above embodiments.
  • a pixel circuit 10 as shown in FIG. 3 is included.
  • a pixel circuit as shown in FIG. 4 may also be included.
  • the display panel 2000 further includes a plurality of scanning lines GL and a plurality of data lines DL.
  • the pixel unit P is disposed at an intersection area of the scanning line GL and the data line DL.
  • each pixel unit P is connected to two scan lines GL (providing a scan signal and an illumination control signal, respectively), a data line DL, a first voltage line for providing a first voltage signal, and a second voltage signal for providing The second voltage line.
  • the first voltage line or the second voltage line may be replaced with a corresponding plate-like common electrode (eg, a common anode or a common cathode). It should be noted that only a part of the pixel unit P, the scanning line GL, and the data line DL are shown in FIG.
  • the gate driver 2010 supplies a plurality of strobe signals to the plurality of scan lines GL according to the plurality of scan control signals GCS derived from the timing controller 2020.
  • the plurality of strobe signals include a scan signal, an illumination control signal, and the like. These signals are supplied to each of the pixel units P through a plurality of scanning lines GL.
  • the data driver 2030 converts the digital image data RGB input from the timing controller 2020 into a data signal according to a plurality of data control signals DCS derived from the timing controller 2020 using the reference gamma voltage.
  • the data driver 2030 supplies the converted data signals to the plurality of data lines DL.
  • the timing controller 2020 processes the externally input image data RGB to match the size and resolution of the display panel 2000, and then supplies the processed image data to the data driver 2030.
  • the timing controller 2020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 20. .
  • the timing controller 2020 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 2010 and the data driver 2030, respectively, for control of the gate driver 2010 and the data driver 2030.
  • the data driver 2030 may be coupled to the plurality of data lines DL to provide a data signal; and may also be coupled to the plurality of first voltage lines and the plurality of second voltage lines to provide the first voltage signal and the second voltage signal, respectively.
  • the gate driver 2010 and the data driver 2030 can be implemented as a semiconductor chip.
  • the display device 20 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display panel 2000 can be applied to any product or component having an display function such as an e-book, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • an e-book a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 10 is a schematic block diagram of another display panel according to an embodiment of the present disclosure.
  • a plurality of pixel units P are arranged in a plurality of rows, and only the specific connection relationship of the pixel cells P in the example region 3000 is shown in the drawing, and the other pixel cells P have similar connection relationships.
  • the data writing circuit 200 in the pixel circuit 10 of the Nth (N is an integer greater than 2) row pixel unit P (the pixel unit P in the example region 3000) is connected to one scanning line S N , and the Nth row of pixels
  • the reset circuit 400 in the pixel circuit 10 of the unit P is connected to the other scan line S N-2 .
  • the other scan line S N-2 is also connected to the data write circuit 200 in the pixel circuit 10 of the pixel unit P of the N-2th row.
  • the data writing circuit 200 is not specifically shown in the drawing. By means of signal multiplexing, there is no need to add new signals, and the circuit structure is simple and easy to implement.
  • the data writing circuit 200 in the pixel circuit 10 of the Nth (N is an integer greater than 1) row pixel unit P is connected to one scanning line S N , and the Nth row pixel unit P
  • the bias circuit 600 in the pixel circuit 10 is connected to another scan line S N-1 .
  • the other scan line S N-1 is also connected to the data write circuit 200 in the pixel circuit 10 of the pixel unit P of the N-1th row.
  • the data lines D M , D M-1 , D M-2 of each column and the data write circuit 200 in the column pixel circuit 10 of the present column are connected to provide a data signal.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, which can be used to drive the pixel circuit 10 provided by an embodiment of the present disclosure.
  • the driving method can apply a reverse voltage difference after the OLED emits light, and promote elimination of defects accumulated in the positive pressure stage of the OLED, thereby improving the aging problem of the OLED device itself, thereby extending the service life of the OLED device. And it is easy to implement without adding a new signal to the display panel.
  • the driving method includes the following operations:
  • a bias enable signal is input to turn on the bias circuit 600, and the bias circuit 600 applies a bias voltage to the second terminal 520 of the light emitting element 500 according to the bias amplitude signal to reverse bias the light emitting element 500.
  • the scan signal and the data signal are input to turn on the data write circuit 200 and the drive circuit 100, the data write circuit 200 writes the data signal to the drive circuit 100, the memory circuit 300 stores the data signal, and the light-emitting element 500 is driven according to the drive. The current illuminates.
  • the driving method further includes a reset phase.
  • a reset signal is input to turn on the reset circuit 400, and the reset circuit 400 applies a reset voltage to the control terminal 130 of the driving circuit 100 and the first terminal 310 of the memory circuit 300 to reset the driving circuit 100 and the memory circuit 300.
  • the driving method includes the following operations:
  • a bias enable signal is input to turn on the bias circuit 600, and the bias circuit 600 applies a bias voltage to the second terminal 520 of the light emitting element 500 according to the bias amplitude signal to reverse bias the light emitting element 500.
  • the scan signal and the data signal are input to turn on the data writing circuit 200, the data writing circuit 200 writes the data signal to the driving circuit 100, and the storage circuit 300 stores the data signal;
  • a light emission control signal is input to turn on the light emission control circuit 700, and the light emission control circuit 700 and the drive circuit 100 apply a drive current to the light emitting element 500 to cause it to emit light.
  • the light-emitting element 500 does not emit light during the data writing phase.
  • the driving method may further include a reset phase, and the operation of the reset phase may refer to the above content, and details are not described herein again.

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Abstract

一种像素电路及其驱动方法、显示面板，该像素电路（10）包括驱动电路(100）、数据写入电路（200）、存储电路（300）、发光元件（500）和偏置电路（600）。驱动电路（100）控制驱动发光元件（500）发光的驱动电流；数据写入电路（200）响应于扫描信号将数据信号写入驱动电路（100）的控制端（130）；存储电路（300）存储数据写入电路（200）写入的数据信号；发光元件（500）根据驱动电流发光；偏置电路（600）响应于偏置启动信号并根据偏压幅度信号对发光元件（500）的第二端（520）施加偏置电压以将发光元件（500）反向偏置。该像素电路（10）可延长OLED器件的使用寿命，且在将该像素电路（10）用于显示面板的情况下，对于显示面板而言无需增加新的信号，易于实现。

Description

像素电路及其驱动方法、显示面板
本申请要求于2018年3月12日递交的中国专利申请第201810201169.1号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一个实施例提供一种像素电路，包括：驱动电路、数据写入电路、存储电路、发光元件和偏置电路；其中，所述驱动电路包括控制端、 第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第二端接收第一电压端的第一电压信号；所述数据写入电路与所述驱动电路的控制端连接，且配置为响应于扫描信号将数据信号写入所述驱动电路的控制端；所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述驱动电路的第一端连接，配置为存储所述数据写入电路写入的所述数据信号；所述发光元件的第一端接收第二电压端的第二电压信号，所述发光元件的第二端与所述驱动电路的第一端连接，配置为根据所述驱动电流发光；所述偏置电路与所述发光元件的第二端连接，配置为响应于偏置启动信号并根据偏压幅度信号对所述发光元件的第二端施加偏置电压以将所述发光元件反向偏置。
例如，在本公开一实施例提供的像素电路中，所述偏置电路包括第一电容和第一晶体管；所述第一电容的第一极配置为与所述发光元件的第二端连接，所述第一电容的第二极配置为与所述第一晶体管的第一极连接；所述第一晶体管的栅极配置为与偏置启动端连接以接收所述偏置启动信号，所述第一晶体管的第二极配置为与偏压幅度端连接以接收所述偏压幅度信号。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括第二晶体管；所述第二晶体管的栅极作为所述驱动电路的控制端，所述第二晶体管的第一极作为所述驱动电路的第一端，所述第二晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一实施例提供的像素电路中，所述数据写入电路包括第三晶体管；所述第三晶体管的栅极配置为与扫描端连接以接收所述扫描信号，所述第三晶体管的第一极配置为与数据端连接以接收所述数据信号，所述第三晶体管的第二极配置为与所述驱动电路的控制端连接。
例如，在本公开一实施例提供的像素电路中，所述存储电路包括第二电容；所述第二电容的第一极作为所述存储电路的第一端，所述第二电容的第二极作为所述存储电路的第二端。
例如，在本公开一实施例提供的像素电路包括复位电路，其中，所述复位电路与所述驱动电路的控制端连接，配置为响应于复位信号将复位电压施加至所述驱动电路的控制端。
例如，在本公开一实施例提供的像素电路中，所述复位电路包括第四晶 体管；所述第四晶体管的栅极配置为与复位端连接以接收所述复位信号，所述第四晶体管的第一极配置为与所述驱动电路的控制端连接，所述第四晶体管的第二极配置为与所述第一电压端连接以接收所述复位电压。
例如，在本公开一实施例提供的像素电路包括发光控制电路，其中，所述发光控制电路与所述发光元件的第一端连接，配置为响应于发光控制信号将所述第二电压端的第二电压信号施加至所述发光元件的第一端。
例如，在本公开一实施例提供的像素电路中，所述发光控制电路包括第五晶体管；所述第五晶体管的栅极配置为与发光控制端连接以接收所述发光控制信号，所述第五晶体管的第一极配置为与所述第二电压端连接以接收所述第二电压信号，所述第五晶体管的第二极配置为与所述发光元件的第一端连接。
本公开至少一个实施例还提供一种显示面板，包括呈阵列分布的多个像素单元，所述像素单元包括本公开任一实施例所述的像素电路。
例如，在本公开一实施例提供的显示面板包括多条扫描线，其中，第N行的像素电路中的数据写入电路与第N行的扫描线连接以接收所述扫描信号，第N行的像素电路中的偏置电路与第N-1行的扫描线连接以接收第N-1行的扫描信号作为所述偏置启动信号和/或所述偏压幅度信号，N为大于1的整数。
例如，在本公开一实施例提供的显示面板中，第N行的像素电路中的复位电路与第N-2行的扫描线连接以接收第N-2行的扫描信号作为所述复位信号，N为大于2的整数。
本公开至少一个实施例还提供一种本公开任一实施例所述的像素电路的驱动方法，包括：偏置阶段和数据写入阶段；其中，在所述偏置阶段，输入所述偏置启动信号以开启所述偏置电路，所述偏置电路根据所述偏压幅度信号将所述偏置电压施加至所述发光元件的第二端，以将所述发光元件反向偏置；在所述数据写入阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路和所述驱动电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述存储电路存储所述数据信号，所述发光元件根据所述驱动电流发光。
例如，在本公开一实施例提供的像素电路的驱动方法中，在所述像素电 路还包括复位电路的情况下，所述驱动方法还包括复位阶段；其中，在所述复位阶段，输入复位信号以开启所述复位电路，所述复位电路将复位电压施加至所述驱动电路的控制端以及所述存储电路的第一端，以对所述驱动电路和所述存储电路进行复位。
本公开至少一个实施例还提供一种本公开任一实施例所述的像素电路的驱动方法，包括：偏置阶段、数据写入阶段和发光阶段；其中，在所述偏置阶段，输入所述偏置启动信号以开启所述偏置电路，所述偏置电路根据所述偏压幅度信号将所述偏置电压施加至所述发光元件的第二端，以将所述发光元件反向偏置；在所述数据写入阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述存储电路存储所述数据信号；在所述发光阶段，输入所述发光控制信号以开启所述发光控制电路，所述发光控制电路和所述驱动电路将所述驱动电流施加至所述发光元件以使其发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种像素电路的示意框图；
图2为本公开一实施例提供的另一种像素电路的示意框图；
图3为图1中所示的像素电路的一种具体实现示例的电路图；
图4为图2中所示的像素电路的一种具体实现示例的电路图；
图5为本公开一实施例提供的一种像素电路的信号时序图；
图6A至图6C分别为图3中所示的像素电路对应于图5中三个阶段的电路示意图；
图7为本公开一实施例提供的另一种像素电路的信号时序图；
图8为图4中所示的像素电路对应于图7中第四阶段的电路示意图；
图9为本公开一实施例提供的一种显示面板的示意框图；以及
图10为本公开一实施例提供的另一种显示面板的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示领域以及照明领域，OLED器件的使用寿命一直是各大厂商关注的重点。由于OLED为自发光器件，OLED在发光过程中会发生老化，导致亮度降低。OLED的老化机理包括多种因素，例如器件固有缺陷、OLED器件劣化等。在AMOLED显示领域，用于驱动OLED的像素电路有多种类型，例如由2个薄膜晶体管(Thin-Film Transistor,TFT)和1个电容(Capacitor,C)组成的2T1C电路，或者具有阈值电压补偿功能的4T1C、4T2C电路等。这些像素电路无法改善OLED器件本身老化的问题，不能有效延长OLED器件的使用寿命。
本公开至少一个实施例提供一种像素电路及其驱动方法、显示面板。该像素电路可在OLED发光后，对其加载反向压差，促进消除OLED在正压阶段积累的缺陷，从而可改善OLED器件本身老化的问题，由此起到延长OLED器件的使用寿命的效果，且在将该像素电路用于显示面板的情况下，对于显示面板而言无需增加新的信号，易于实现，可以延长显示面板的使用寿命。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一个实施例提供一种像素电路，该像素电路包括驱动电路、数据写入电路、存储电路、发光元件和偏置电路。所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第二端接收第一电压端的第一电压信号；所述数据写入电路与所述驱动电路的控制端连接，且配置为响应于扫描信号将数据信号写入所述驱动电路的控制端；所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述驱动电路的第一端连接，配置为存储所述数据写入电路写入的所述数据信号；所述发光元件的第一端接收第二电压端的第二电压信号，所述发光元件的第二端与所述驱动电路的第一端连接，配置为根据所述驱动电流发光；所述偏置电路与所述发光元件的第二端连接，配置为响应于偏置启动信号并根据偏压幅度信号对所述发光元件的第二端施加偏置电压以将所述发光元件反向偏置。
图1为本公开一实施例提供的一种像素电路的示意框图。参考图1，像素电路10包括驱动电路100、数据写入电路200、存储电路300、复位电路400、发光元件500和偏置电路600。像素电路10例如用于OLED显示装置的子像素。
例如，驱动电路100包括第一端110、第二端120和控制端130，且配置为控制驱动发光元件500发光的驱动电流，驱动电路100的第二端120接收第一电压端VSS的第一电压信号。驱动电路100的控制端130和第一节点N1连接，驱动电路100的第一端110和第二节点N2连接，驱动电路100的第二端120连接到第一电压端VSS(第三节点N3)以接收第一电压信号。例如，驱动电路100可以向发光元件500提供驱动电流以驱动发光元件500进行发光，且可以根据需要的“灰度”发光。例如，发光元件500可以采用OLED，且配置为和第二节点N2以及第二电压端VDD(例如，高电平)连接，本公开的实施例包括但不限于此情形。
例如，数据写入电路200与驱动电路100的控制端130(第一节点N1)连接，且配置为响应于扫描信号将数据信号写入驱动电路100的控制端130。例如，数据写入电路200分别和数据信号端Vdata、第一节点N1以及扫描信号端Vscan(n)连接。例如，来自扫描信号端Vscan(n)的扫描信号被施加至数据写入电路200以控制数据写入电路200开启与否。例如，在数据写入阶段， 数据写入电路200可以响应于扫描信号而开启，从而可以将数据信号写入驱动电路100的控制端130(第一节点N1)，然后可将数据信号存储在存储电路300中，以根据该数据信号生成驱动发光元件500发光的驱动电流。
例如，存储电路300的第一端310与驱动电路100的控制端130(第一节点N1)连接，存储电路300的第二端320与驱动电路100的第一端110(第二节点N2)连接，配置为存储数据写入电路200写入的数据信号。例如，存储电路300可以存储该数据信号并利用存储的数据信号对驱动电路100进行控制。
例如，复位电路400与驱动电路100的控制端130(第一节点N1)连接，配置为响应于复位信号将复位电压施加至驱动电路100的控制端130以及存储电路300的第一端310。例如，复位电路400分别和第一节点N1、第一电压端VSS(第三节点N3)和复位端Rst连接。例如，复位电路400可以响应于复位信号而开启，从而可以将复位电压(这里用于复位的电压为第一电压信号)施加至第一节点N1、存储电路300的第一端310以及驱动电路100的控制端130，从而可以对存储电路300和驱动电路100进行复位操作，消除之前的发光阶段的影响。例如，复位电压可以由第一电压端VSS提供，在其他实施例中也可以由独立于第一电压端VSS的复位电压端提供，由此相应地，复位电路400不是连接到第一电压端VSS(第三节点N3)而是连接到该复位电压端，本公开的实施例对此不作限制。例如，第一电压端VSS为低压端，例如为接地端。例如，根据具体的电路结构，复位电路400也可以省略或者集成到其他电路中。
例如，在一个显示装置中，当像素电路10呈阵列排布时，第N(N为大于2的整数)行的数据写入电路200与第N行的扫描线(或扫描信号端Vscan(n))连接以接收扫描信号，第N行的复位电路400与第N-2行的扫描线(或扫描信号端Vscan(n-2))连接以接收第N-2行的扫描信号作为复位信号。这种方式相对于传统显示面板而言无需增加新的信号，电路结构简单，易于实现。当然，本公开的实施例不限于此，复位电路400也可以和另行设置的复位信号线连接以接收另行提供的复位信号。
例如，发光元件500包括第一端510和第二端520，配置为根据驱动电路100提供的驱动电流发光。发光元件500的第一端510配置为接收第二电 压端VDD的第二电压信号，发光元件500的第二端520配置为与驱动电路100的第一端110(第二节点N2)连接。
例如，偏置电路600与发光元件500的第二端520(第二节点N2)连接，配置为响应于偏置启动信号并根据偏压幅度信号对发光元件500的第二端520施加偏置电压以将发光元件500反向偏置。例如，偏置电路600分别和第二节点N2、偏置启动端Vb和偏压幅度端Vamp连接。例如，偏置电路600可以响应于偏置启动端Vb提供的偏置启动信号而开启，从而根据偏压幅度端Vamp提供的偏压幅度信号对发光元件500的第二端520施加偏置电压。例如，偏置电压可以不等于偏压幅度信号。在发光元件500(例如，OLED)发光后，对其加载偏置电压使其反向偏置，可以促进消除发光元件500在正压阶段(例如，发光阶段)积累的缺陷，从而可改善发光元件500本身老化的问题，起到延长发光元件500使用寿命的效果。
例如，偏置启动端Vb和偏压幅度端Vamp可以连接到同一根信号线，从而使偏置启动信号和偏压幅度信号为同一信号，这样可以简化电路设计。例如，在一个显示装置中，当像素电路10呈阵列排布时，第N(N为大于1的整数)行的数据写入电路200与第N行的扫描线(或扫描信号端Vscan(n))连接以接收扫描信号，第N行的偏置电路600与第N-1行的扫描线(或扫描信号端Vscan(n-1))连接以接收第N-1行的扫描信号作为偏置启动信号和/或偏压幅度信号。这样可以利用像素电路10的扫描信号，相对于传统显示面板而言无需增加新的信号，电路结构简单，易于实现。当然，本公开的实施例不限于此，偏置电路600也可以和另行设置的偏置启动信号线和/或偏压幅度信号线连接以接收另行提供的偏置启动信号和/或偏压幅度信号。
图2为本公开一实施例提供的另一种像素电路的示意框图。参考图2，像素电路10还可以包括发光控制电路700，其他结构与图1中所示的像素电路10基本相同。发光控制电路700与发光元件500的第一端510连接，配置为响应于发光控制信号将第二电压端VDD的第二电压信号施加至发光元件500的第一端510。例如，发光控制电路700分别和第二电压端VDD、发光控制端Em、发光元件500的第一端510连接。例如，在发光阶段，发光控制电路700响应于发光控制端Em提供的发光控制信号而开启，从而驱动电路100可以通过发光控制电路700将驱动电流施加至发光元件500以使其发 光；而在非发光阶段，发光控制电路700响应于发光控制信号而截止，从而避免有电流流过发光元件500而使其发光，可以提高相应的显示装置的对比度。
例如，在驱动电路100实现为驱动晶体管的情形时，例如驱动晶体管的栅极可以作为驱动电路100的控制端130(连接到第一节点N1)，第一极(例如源极)可以作为驱动电路100的第一端110(连接到第二节点N2)，第二极(例如漏极)可以作为驱动电路100的第二端120(连接到第三节点N3)。
需要说明的是，本公开的各实施例中的第一电压端VSS例如保持输入直流低电平信号，将该直流低电平称为第一电压(可作为复位电压)；第二电压端VDD例如保持输入直流高电平信号，将该直流高电平称为第二电压，且高于第一电压。以下各实施例与此相同，不再赘述。
需要说明的是，在本公开的各实施例的描述中，符号Vdata既可以表示数据信号端又可以表示数据信号的电平。同样地，符号Rst既可以表示复位端又可以表示复位信号的电平，符号VSS既可以表示第一电压端又可以表示第一电压，符号VDD既可以表示第二电压端又可以表示第二电压，符号Vb既可以表示偏置启动端又可以表示偏置启动信号的电平，符号Vamp既可以表示偏压幅度端又可以表示偏压幅度信号的电平。以下各实施例与此相同，不再赘述。
需要说明的是，本公开各实施例提供的像素电路10还可以包括其他具有补偿功能的电路结构。补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路10例如可以为4T1C或4T2C等电路与偏置电路600的结合。例如，在具有补偿功能的像素电路10中，数据写入电路200和补偿电路配合将携带有数据信号以及驱动电路100中的驱动晶体管的阈值电压信息的电压值写入到驱动电路100的控制端130且通过存储电路300存储。具体的补偿电路的示例，这里不再详述。
本公开的实施例提供的像素电路10可在发光元件500发光后，对其加载反向压差，促进消除发光元件500在正压阶段积累的缺陷，从而可改善发光元件500本身老化的问题，由此起到延长发光元件500的使用寿命的效果，且在将该像素电路10用于显示面板的情况下，对于显示面板而言无需增加新的信号，易于实现。
图3为图1中所示的像素电路的一种具体实现示例的电路图。参考图3，像素电路10包括第一至第四晶体管T1、T2、T3、T4以及包括第一电容C1、第二电容C2和发光元件L1。例如，第二晶体管T2被用作驱动晶体管，其他的晶体管被用作开关晶体管。例如，发光元件L1可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图3所示，偏置电路600可以实现为第一电容C1和第一晶体管T1。第一电容C1的第一极配置为和发光元件L1的第二端520(第二节点N2)连接，第一电容C1的第二极配置为和第一晶体管T1的第一极连接。第一晶体管T1的栅极配置为和偏置启动端Vb连接以接收偏置启动信号，第一晶体管T1的第二极配置为和偏压幅度端Vamp连接以接收偏压幅度信号。需要注意的是，不限于此，偏置电路600也可以是由其他的组件组成的电路。
驱动电路100可以实现为第二晶体管T2。第二晶体管T2的栅极作为驱动电路100的控制端130和第一节点N1连接；第二晶体管T2的第一极作为驱动电路100的第一端110和第二节点N2连接；第二晶体管T2的第二极作为驱动电路100的第二端120和第三节点N3连接。需要注意的是，不限于此，驱动电路100也可以是由其他的组件组成的电路，例如，驱动电路100可以具有两组驱动晶体管，例如，该两组驱动晶体管可以根据具体情况进行切换。
数据写入电路200可以实现为第三晶体管T3。第三晶体管T3的栅极配置为与扫描信号端Vscan(n)连接以接收扫描信号，第三晶体管T3的第一极配置为与数据信号端Vdata连接以接收数据信号，第三晶体管T3的第二极配置为与第一节点N1连接。需要注意的是，不限于此，数据写入电路200也可以是由其他的组件组成的电路。
存储电路300可以实现为第二电容C2。第二电容C2的第一极作为存储电路300的第一端310配置为和第一节点N1连接，第二电容C2的第二极作为存储电路300的第二端320配置为和第二节点N2连接。需要注意的是，不限于此，存储电路300也可以是由其他的组件组成的电路，例如，存储电路300可以包括两个彼此并联/串联的电容。
复位电路400可以实现为第四晶体管T4。第四晶体管T4的栅极配置为 和复位端Rst连接以接收复位信号，第四晶体管T4的第一极和驱动电路100的控制端130(第一节点N1)连接，第四晶体管T4的第二极配置为和第一电压端VSS(第三节点N3)连接以接收第一电压信号(可作为复位电压)。需要注意的是，不限于此，复位电路400也可以是由其他的组件组成的电路，例如，复位电路400还可以连接到发光元件500的第二端520，以用于进一步对发光元件500的第二端520进行复位(但未偏置)。
发光元件500可以实现为发光元件L1(例如，OLED)。发光元件L1的第一端(这里为阳极)作为发光元件500的第一端510配置为和第二电压端VDD连接以接收第二电压信号，发光元件L1的第二端(这里为阴极)作为发光元件500的第二端520和第二节点N2连接且配置为从驱动电路100的第一端110接收驱动电流。例如，第二电压端VDD保持输入直流高电平信号，即VDD可以为高电平。例如，在一个显示面板中，当像素电路10呈阵列排布时，发光元件L1的阳极可以电连接到同一个电压端，即采用共阳极连接方式。
请注意，在本公开的说明中，第一节点N1、第二节点N2和第三节点N3并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
图4为图2中所示的像素电路的一种具体实现示例的电路图。图4所示的像素电路10与图3所示的像素电路10基本相同，区别在于图4所示的像素电路10还包括第五晶体管T5以实现发光控制电路700。
例如，如图4所示，发光控制电路700可以实现为第五晶体管T5。第五晶体管T5的栅极配置为和发光控制端Em连接以接收发光控制信号，第五晶体管T5的第一极配置为和第二电压端VDD连接以接收第二电压信号，第五晶体管T5的第二极配置为和发光元件L1的第一端连接。需要注意的是，不限于此，发光控制电路700也可以是由其他的组件组成的电路。
图5为本公开一实施例提供的一种像素电路的信号时序图。下面结合图5所示的信号时序图，对图3所示的像素电路10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
如图5所示，每一帧图像的显示过程包括三个阶段，分别为复位阶段1、偏置阶段2和数据写入阶段3，图中示出了每个阶段中各个信号的时序波形。
需要说明的是，图6A至图6C分别为图3中所示的像素电路10处于上述三个阶段的示意图。图6A为图3中所示的像素电路10处于复位阶段1时的示意图，图6B为图3中所示的像素电路10处于偏置阶段2时的示意图，图6C为图3中所示的像素电路10处于数据写入阶段3时的示意图。
另外，图6A至图6C中用虚线标识的晶体管均表示在对应阶段内处于截止状态，图6A至图6C中带箭头的虚线表示像素电路在对应阶段内的电流方向。图6A至图6C中所示的晶体管均以N型晶体管为例进行说明，即各个晶体管的栅极在接入高电平时导通，而在接入低电平时截止。以下实施例与此相同，不再赘述。
在复位阶段1，输入复位信号(由复位端Rst提供)以开启复位电路400，复位电路400将复位电压(由第一电压端VSS提供)施加至驱动电路100的控制端130以及存储电路300的第一端310，以对驱动电路100和存储电路300进行复位。
如图5和图6A所示，在复位阶段1，第四晶体管T4被复位信号的高电平导通；同时，第一晶体管T1被偏置启动信号的低电平截止，第三晶体管T3被扫描信号的低电平截止，第二晶体管T2被第一节点N1的低电平截止。
如图6A所示，在复位阶段1，形成一条复位路径(如图6A中带箭头的虚线所示)，由于第四晶体管T4导通，可以将复位电压施加至第二晶体管T2的栅极(第一节点N1)和第二电容C2的第一极。由于复位电压为低电平信号(例如可以接地或为其他低电平信号)，第二电容C2通过复位路径放电，从而将第二晶体管T2和第二电容C2复位。例如，在一个显示装置中，当像素电路10呈阵列排布时，第N(N为大于2的整数)行的第三晶体管T3的栅极与第N行的扫描线(或扫描信号端Vscan(n))连接以接收扫描信号，第N行的第四晶体管T4的栅极与第N-2行的扫描线(或扫描信号端Vscan(n-2))连接以接收第N-2行的扫描信号作为复位信号。相对于传统显示面板而言，这种方式无需增加新的信号，电路结构简单，易于实现。
经过复位阶段1后，第一节点N1的电位为复位电压。第二电容C2被复位，使存储在第二电容C2中的电荷放电，从而使后续阶段中的数据信号可以被更迅速、更可靠地存储在第二电容C2中。同时，由于第二晶体管T2被截止，使得发光元件L1也被复位，从而可以使发光元件L1在数据写入阶段 3之前显示为黑态，即不发光，以改善采用上述像素电路10的显示装置的对比度等显示效果。
在偏置阶段2，输入偏置启动信号(由偏置启动端Vb提供)以开启偏置电路600，偏置电路600根据偏压幅度信号(由偏压幅度端Vamp提供)将偏置电压施加至发光元件L1的第二端(第二节点N2)，以将发光元件L1反向偏置。
如图5和图6B所示，在偏置阶段2，第一晶体管T1被偏置启动信号的高电平导通；同时，第二晶体管T2被第一节点N1的低电平截止，第三晶体管T3被扫描信号的低电平截止，第四晶体管T4被复位信号的低电平截止。
如图6B所示，在偏置阶段2，形成一条偏置路径(如图6B中带箭头的虚线所示)，由于第一晶体管T1导通，可以将偏压幅度信号施加至第一电容C1的第二极。第一电容C1在上一帧图像的显示阶段进行了充电，第一电容C1的第一极(第二节点N2)和第一电容C1的第二极达到电位平衡。当将偏压幅度信号施加至第一电容C1的第二极时，由于第一电容C1的自举效应，第一电容C1的第一极(第二节点N2)的电位得到抬升，从而使得第二节点N2的电位大于VDD。由此对发光元件L1施加了偏置电压，可以促进消除发光元件L1在上一帧图像的发光阶段(正压阶段)积累的缺陷，从而可改善发光元件L1本身老化的问题，起到延长发光元件L1的使用寿命的效果。例如，在一个显示装置中，当像素电路10呈阵列排布时，第N(N为大于1的整数)行的第三晶体管T3的栅极与第N行的扫描线(或扫描信号端Vscan(n))连接以接收扫描信号，第N行的第一晶体管T1的栅极和/或第二极与第N-1行的扫描线(或扫描信号端Vscan(n-1))连接以接收第N-1行的扫描信号作为偏置启动信号和/或偏压幅度信号。相对于传统显示面板而言，这种方式无需增加新的信号，电路结构简单，易于实现。
经过偏置阶段2后，第二节点N2的电位为偏置电压。发光元件L1被反向偏置，从而可以消除在正压阶段积累的缺陷，有效延长发光元件L1的使用寿命。并且，由于偏置启动信号的高电平时间很短，小于人眼的分辨能力，因此不会影响采用上述像素电路10的显示装置的显示效果。
在数据写入阶段3，输入扫描信号(由扫描信号端Vscan(n)提供)和数据信号(由数据信号端Vdata提供)以开启数据写入电路200和驱动电路100， 数据写入电路200将数据信号写入驱动电路100，存储电路300存储数据信号，发光元件L1根据驱动电流发光。
如图5和图6C所示，在数据写入阶段3，第三晶体管T3被扫描信号的高电平导通，第二晶体管T2被第一节点N1的高电平导通；同时，第一晶体管T1被偏置启动信号的低电平截止，第四晶体管T4被复位信号的低电平截止。
如图6C所示，在数据写入阶段3，形成一条数据写入路径(如图6C中带箭头的虚线所示)，数据信号经过第三晶体管T3后对第二电容C2进行充电。当第一节点N1与第二节点N2之间的电压差大于Vth时，第二晶体管T2导通，从而使发光元件L1在驱动电流的作用下发光。需要说明的是，Vth表示第二晶体管T2的阈值电压，由于在本实施例中，第二晶体管T2是以N型晶体管为例进行说明的，所以此处阈值电压Vth可以是个正值。在其他实施例中，若第二晶体管T2是P型晶体管，则阈值电压Vth可以是个负值。
例如，流经发光元件L1的驱动电流I L1的值可以根据下述公式得出：
I L1＝K(V GS–Vth) 2，
在上述公式中，Vth表示第二晶体管T2的阈值电压，V GS表示第二晶体管T2的栅极和源极(这里为第一极)之间的电压，K为与第二晶体管T2本身相关的常数值。由此可知，流经发光元件L1的驱动电流I L1与V GS有关，即发光元件L1可根据存储在第二电容C2中的数据信号进行发光。
经过数据写入阶段3后，带有数据信号的电压信息储存在了第二电容C2中，并且第二晶体管T2在第一节点N1和第二节点N2的电压差的控制下为发光元件L1提供驱动电流，以使发光元件L1发光。需要说明的是，在本实施例中，在数据写入阶段3，像素电路10既将数据信号写入，又进行发光。在其他实施例中，结合具体的电路结构，数据写入和发光也可以分别在两个阶段中实现，本公开的实施例对此不作限制。
图7为本公开一实施例提供的另一种像素电路的信号时序图。参考图7，除了还包括发光阶段4外，该信号时序与图5中所示的信号时序基本相同。下面结合图7所示的信号时序图，对图4所示的像素电路10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
图8为图4中所示的像素电路10对应于图7中发光阶段4的电路示意图。图8中用虚线标识的晶体管均表示在对应阶段内处于截止状态，图8中带箭头的虚线表示像素电路10在对应阶段内的电流方向。复位阶段1、偏置阶段2和数据写入阶段3与图5和图6A至图6C中所示的像素电路10的工作原理基本相同，此处不再赘述。
在发光阶段4，输入发光控制信号(由发光控制端Em提供)以开启发光控制电路700，发光控制电路700和驱动电路100将驱动电流施加至发光元件L1以使其发光。
如图7和图8所示，在发光阶段4，第五晶体管T5被发光控制信号的高电平导通，第二晶体管T2被第一节点N1的高电平导通；同时，第一晶体管T1被偏置启动信号的低电平截止，第三晶体管T3被扫描信号的低电平截止，第四晶体管T4被复位信号的低电平截止。
如图8所示，在发光阶段4，形成一条驱动发光路径(如图8中带箭头的虚线所示)，由于第五晶体管T5和第二晶体管T2导通，可以向发光元件L1提供驱动电流，发光元件L1在驱动电流的作用下发光。
需要说明的是，在本实施例中，发光元件L1仅在发光阶段4发光，而在数据写入阶段3不发光。数据写入和发光分别在两个阶段中实现，有利于保证数据写入的完整性，并且可以提高相应的显示装置的对比度。
需要说明的是，本公开的各实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的各实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的各实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，图3和图4中所示的像素电路10中的晶体管均是以N型晶体管为例进行说明的，此时，第一极可以是源极，第二极可以是漏极。像素电路10中的晶体管也可以仅采用P型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性相应连接，并且使相应的电压端和信号端提供对应的高电平信号或低电平信号即可。当采用N型晶体管时，可以采用氧 化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开至少一个实施例还提供一种显示面板，包括呈阵列分布的多个像素单元，所述像素单元包括本公开任一实施例所述的像素电路。该显示面板中的像素电路可在OLED发光后，对其加载反向压差，促进消除OLED在正压阶段积累的缺陷，从而可改善OLED器件本身老化的问题，由此起到延长OLED器件的使用寿命的效果，且该显示面板无需增加新的信号，易于实现。
图9为本公开一实施例提供的一种显示面板的示意框图。参考图9，显示面板2000设置在显示装置20中，并与栅极驱动器2010和数据驱动器2030电连接。显示装置20还包括定时控制器2020。显示面板2000包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器2010用于驱动多条扫描线GL；数据驱动器2030用于驱动多条数据线DL；定时控制器2020用于处理从显示装置20外部输入的图像数据RGB，向数据驱动器2030提供处理的图像数据RGB以及向栅极驱动器2010和数据驱动器2030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器2010和数据驱动器2030进行控制。
例如，显示面板2000包括多个像素单元P，像素单元P包括上述任一实施例中提供的像素电路10。例如，包括如图3所示的像素电路10。例如，也可以包括如图4所示的像素电路。如图9所示，显示面板2000还包括多条扫描线GL和多条数据线DL。例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，每个像素单元P连接到两条扫描线GL(分别提供扫描信号和发光控制信号)、一条数据线DL、用于提供第一电压信号的第一电压线、用于提供第二电压信号的第二电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图9中仅示出了部分的像素单元P、扫描线GL和数据线DL。
例如，栅极驱动器2010根据源自定时控制器2020的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括扫描信号、发光控制信号等。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器2030使用参考伽玛电压根据源自定时控制器2020的多个数据控制信号DCS将从定时控制器2020输入的数字图像数据RGB转换成数据信号。数据驱动器2030向多条数据线DL提供转换的数据信号。
例如，定时控制器2020对外部输入的图像数据RGB进行处理以匹配显示面板2000的大小和分辨率，然后向数据驱动器2030提供处理的图像数据。定时控制器2020使用从显示装置20外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器2020分别向栅极驱动器2010和数据驱动器2030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器2010和数据驱动器2030的控制。
例如，数据驱动器2030可以与多条数据线DL连接，以提供数据信号；同时还可以与多条第一电压线和多条第二电压线连接以分别提供第一电压信号和第二电压信号。
例如，栅极驱动器2010和数据驱动器2030可以实现为半导体芯片。该显示装置20还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示面板2000可以应用于电子书、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
图10为本公开一实施例提供的另一种显示面板的示意框图。参考图10，多个像素单元P排列为多行，图中仅示出示例区域3000内的像素单元P的具体连接关系，其他像素单元P具有类似的连接关系。
例如，第N(N为大于2的整数)行像素单元P(示例区域3000内的像素单元P)的像素电路10中的数据写入电路200连接到一条扫描线S N，且第N行像素单元P的像素电路10中的复位电路400连接到另一条扫描线S N-2。例如，该另一条扫描线S N-2还与第N-2行的像素单元P的像素电路10中的数据写入电路200连接。这里，数据写入电路200未在图中具体表示。通过信号复用的方式，无需增加新的信号，电路结构简单，易于实现。
又例如，如图10所示，第N(N为大于1的整数)行像素单元P的像素电路10中的数据写入电路200连接到一条扫描线S N，且第N行像素单元P的像素电路10中的偏置电路600连接到另一条扫描线S N-1。例如，该另一 条扫描线S N-1还与第N-1行的像素单元P的像素电路10中的数据写入电路200连接。
例如，每一列的数据线D M、D M-1、D M-2和本列像素电路10中的数据写入电路200连接以提供数据信号。
本公开至少一个实施例还提供一种像素电路的驱动方法，可以用于驱动本公开的实施例提供的像素电路10。该驱动方法可以在OLED发光后，对其加载反向压差，促进消除OLED在正压阶段积累的缺陷，从而可改善OLED器件本身老化的问题，由此起到延长OLED器件的使用寿命的效果，且对于显示面板而言无需增加新的信号，易于实现。
例如，在一个示例中，该驱动方法包括如下操作：
在偏置阶段，输入偏置启动信号以开启偏置电路600，偏置电路600根据偏压幅度信号将偏置电压施加至发光元件500的第二端520，以将发光元件500反向偏置；
在数据写入阶段，输入扫描信号和数据信号以开启数据写入电路200和驱动电路100，数据写入电路200将数据信号写入驱动电路100，存储电路300存储数据信号，发光元件500根据驱动电流发光。
例如，在像素电路10还包括复位电路400的情况下，该驱动方法还包括复位阶段。在复位阶段，输入复位信号以开启复位电路400，复位电路400将复位电压施加至驱动电路100的控制端130以及存储电路300的第一端310，以对驱动电路100和存储电路300进行复位。
例如，在另一个示例中，该驱动方法包括如下操作：
在偏置阶段，输入偏置启动信号以开启偏置电路600，偏置电路600根据偏压幅度信号将偏置电压施加至发光元件500的第二端520，以将发光元件500反向偏置；
在数据写入阶段，输入扫描信号和数据信号以开启数据写入电路200，数据写入电路200将数据信号写入驱动电路100，存储电路300存储数据信号；
在发光阶段，输入发光控制信号以开启发光控制电路700，发光控制电路700和驱动电路100将驱动电流施加至发光元件500以使其发光。
需要注意的是，在该示例中，发光元件500在数据写入阶段不发光。例 如，在该示例中，该驱动方法还可以包括复位阶段，复位阶段的操作可以参考上文内容，此处不再赘述。
需要说明的是，关于该驱动方法的详细描述可以参考本公开的实施例中对于像素电路10的工作原理的描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素电路，包括：驱动电路、数据写入电路、存储电路、发光元件和偏置电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第二端接收第一电压端的第一电压信号；
    所述数据写入电路与所述驱动电路的控制端连接，且配置为响应于扫描信号将数据信号写入所述驱动电路的控制端；
    所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述驱动电路的第一端连接，配置为存储所述数据写入电路写入的所述数据信号；
    所述发光元件的第一端接收第二电压端的第二电压信号，所述发光元件的第二端与所述驱动电路的第一端连接，配置为根据所述驱动电流发光；
    所述偏置电路与所述发光元件的第二端连接，配置为响应于偏置启动信号并根据偏压幅度信号对所述发光元件的第二端施加偏置电压以将所述发光元件反向偏置。
  2. 根据权利要求1所述的像素电路，其中，所述偏置电路包括第一电容和第一晶体管；
    所述第一电容的第一极配置为与所述发光元件的第二端连接，所述第一电容的第二极配置为与所述第一晶体管的第一极连接；
    所述第一晶体管的栅极配置为与偏置启动端连接以接收所述偏置启动信号，所述第一晶体管的第二极配置为与偏压幅度端连接以接收所述偏压幅度信号。
  3. 根据权利要求1或2所述的像素电路，其中，所述驱动电路包括第二晶体管；
    所述第二晶体管的栅极作为所述驱动电路的控制端，所述第二晶体管的第一极作为所述驱动电路的第一端，所述第二晶体管的第二极作为所述驱动电路的第二端。
  4. 根据权利要求1-3任一所述的像素电路，其中，所述数据写入电路包 括第三晶体管；
    所述第三晶体管的栅极配置为与扫描信号端连接以接收所述扫描信号，所述第三晶体管的第一极配置为与数据信号端连接以接收所述数据信号，所述第三晶体管的第二极配置为与所述驱动电路的控制端连接。
  5. 根据权利要求1-4任一所述的像素电路，其中，所述存储电路包括第二电容；
    所述第二电容的第一极作为所述存储电路的第一端，所述第二电容的第二极作为所述存储电路的第二端。
  6. 根据权利要求1-5任一所述的像素电路，还包括复位电路，其中，
    所述复位电路与所述驱动电路的控制端连接，配置为响应于复位信号将复位电压施加至所述驱动电路的控制端。
  7. 根据权利要求6所述的像素电路，其中，所述复位电路包括第四晶体管；
    所述第四晶体管的栅极配置为与复位端连接以接收所述复位信号，所述第四晶体管的第一极配置为与所述驱动电路的控制端连接，所述第四晶体管的第二极配置为与所述第一电压端连接以接收所述复位电压。
  8. 根据权利要求1-7任一所述的像素电路，还包括发光控制电路，其中，所述发光控制电路与所述发光元件的第一端连接，配置为响应于发光控制信号将所述第二电压端的第二电压信号施加至所述发光元件的第一端。
  9. 根据权利要求8所述的像素电路，其中，所述发光控制电路包括第五晶体管；
    所述第五晶体管的栅极配置为与发光控制端连接以接收所述发光控制信号，所述第五晶体管的第一极配置为与所述第二电压端连接以接收所述第二电压信号，所述第五晶体管的第二极配置为与所述发光元件的第一端连接。
  10. 一种显示面板，包括呈阵列分布的多个像素单元，所述像素单元包括权利要求1-9任一所述的像素电路。
  11. 根据权利要求10所述的显示面板，还包括多条扫描线，其中，第N行的像素电路中的数据写入电路与第N行的扫描线连接以接收所述扫描信号，第N行的像素电路中的偏置电路与第N-1行的扫描线连接以接收第N-1行的扫描信号作为所述偏置启动信号和/或所述偏压幅度信号，N为大于1的 整数。
  12. 根据权利要求11所述的显示面板，其中，第N行的像素电路中的复位电路与第N-2行的扫描线连接以接收第N-2行的扫描信号作为所述复位信号，N为大于2的整数。
  13. 一种如权利要求1-9任一所述的像素电路的驱动方法，包括：偏置阶段和数据写入阶段；其中，
    在所述偏置阶段，输入所述偏置启动信号以开启所述偏置电路，所述偏置电路根据所述偏压幅度信号将所述偏置电压施加至所述发光元件的第二端，以将所述发光元件反向偏置；
    在所述数据写入阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路和所述驱动电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述存储电路存储所述数据信号，所述发光元件根据所述驱动电流发光。
  14. 根据权利要求13所述的像素电路的驱动方法，在所述像素电路还包括复位电路的情况下，所述驱动方法还包括复位阶段；其中，
    在所述复位阶段，输入复位信号以开启所述复位电路，所述复位电路将复位电压施加至所述驱动电路的控制端以及所述存储电路的第一端，以对所述驱动电路和所述存储电路进行复位。
  15. 一种如权利要求8或9所述的像素电路的驱动方法，包括：偏置阶段、数据写入阶段和发光阶段；其中，
    在所述偏置阶段，输入所述偏置启动信号以开启所述偏置电路，所述偏置电路根据所述偏压幅度信号将所述偏置电压施加至所述发光元件的第二端，以将所述发光元件反向偏置；
    在所述数据写入阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述存储电路存储所述数据信号；
    在所述发光阶段，输入所述发光控制信号以开启所述发光控制电路，所述发光控制电路和所述驱动电路将所述驱动电流施加至所述发光元件以使其发光。
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