WO2020113372A1 - 显示装置和电子装置 - Google Patents

显示装置和电子装置 Download PDF

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Publication number
WO2020113372A1
WO2020113372A1 PCT/CN2018/118926 CN2018118926W WO2020113372A1 WO 2020113372 A1 WO2020113372 A1 WO 2020113372A1 CN 2018118926 W CN2018118926 W CN 2018118926W WO 2020113372 A1 WO2020113372 A1 WO 2020113372A1
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Prior art keywords
signal
transistor
display device
pixel unit
electrically connected
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PCT/CN2018/118926
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English (en)
French (fr)
Inventor
黄强灿
金志河
邱昌明
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深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201880097610.4A priority Critical patent/CN113196367A/zh
Priority to PCT/CN2018/118926 priority patent/WO2020113372A1/zh
Publication of WO2020113372A1 publication Critical patent/WO2020113372A1/zh
Priority to US17/336,624 priority patent/US20210287612A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes

Definitions

  • the present application relates to the field of display technology, in particular to a display device and an electronic device.
  • GOA Gate Driver On Array
  • two GOA circuits are generally used to provide scan pulse signals for a plurality of rows of pixel units Pixel of a pixel array, one provides a scan signal Gn for the pixel unit Pixel, and the other provides a reset signal Rn for the pixel unit Pixel.
  • Gn scan signal
  • Rn reset signal
  • the embodiments of the present application provide a display device and an electronic device.
  • a pixel array the pixel array including M rows of pixel units
  • N and M are both positive integers;
  • a first driving module and a second driving module one of the first driving module and the second driving module is connected to the scanning line connecting the odd-numbered rows of the pixel units and used for the odd-numbered rows through the scanning line
  • the pixel unit provides a scan signal and a reset signal
  • the other of the first drive module and the second drive module is connected to the scan line connecting the even-numbered rows of the pixel units and used to pass the scan line to an even number
  • the pixel unit of the row provides a scan signal and a reset signal.
  • the Nth scanning line may provide a reset signal for the pixel unit of the N+2th row while providing the scan signal for the pixel unit of the Nth row.
  • the number of circuit stages required for the two driving modules can be reduced, so that the frame of the display device can be narrower.
  • the electronic device includes the display device described in the above embodiment.
  • the Nth scan line may provide a reset signal to the N+2th row pixel unit while supplying the scan signal to the Nth row pixel unit. In this way, it is not necessary to provide two separate scan lines for each row of pixel units to provide scan signals and reset signals for each row of pixel units. In this way, the number of circuit stages required for the two driving modules can be reduced, so that the frame of the display device can be narrower.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a module frame of an electronic device according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a pixel unit of a display device according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the operation timing of the pixel unit of the display device according to the embodiment of the present application.
  • FIG. 5 is an operation state diagram of a pixel unit of a display device according to an embodiment of the present application.
  • FIG. 6 is another operational state diagram of the pixel unit of the display device according to the embodiment of the present application.
  • FIG. 7 is another operational state diagram of the pixel unit of the display device according to the embodiment of the present application.
  • FIG. 8 is another operational state diagram of the pixel unit of the display device according to the embodiment of the present application.
  • Electronic device 1000 display device 100, pixel array 10, pixel unit 11, scan line 20, first drive module 30, second drive module 40, scan signal Gn, reset signal GSn, first transistor T1, second transistor T2, Third transistor T3, fourth transistor T4, first capacitor C1, second capacitor C2, light emitting element DOLED, power supply positive voltage VDD, power supply negative voltage VSS, first node N1, second node N2, gate G, drain D, source level S, data signal DATA, initialization signal INT, enable signal En, reference potential Vref, data potential Vdata.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connect, or connect integrally. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the connection between two elements or the interaction between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.
  • the display device 100 according to the embodiment of the present application may be used in the electronic device 1000 according to the embodiment of the present application.
  • the electronic device 1000 in the embodiment of the present application includes the display device 100 in the embodiment of the present application.
  • the display device 100 according to the embodiment of the present application may be a display device 1000 such as an LCD (Liquid Crystal Display) or an OLED (Organic Light-Emitting Display).
  • the electronic device 1000 includes but is not limited to a mobile phone, a tablet computer, a wearable smart device, a display, a car terminal, a music player, a video player, a television, etc.
  • the electronic device 1000 100 is a mobile phone.
  • the display device 100 of the embodiment of the present application includes a pixel array 10, a scanning line 20, a first driving module 30 and a second driving module 40.
  • the pixel array 10 includes M rows of pixel units 11, and the number of scanning lines 20 corresponds to the number of rows of pixel units 11, that is, the number of scanning lines 20 is M, and the Nth scanning line 20 is connected to the Nth
  • the row pixel unit 11 and the N+2th row pixel unit 11 are used to provide the scan signal Gn for the Nth row pixel unit 11 and the reset signal GSn for the N+2 row pixel unit 11, where 1 ⁇ N, N+2 ⁇ M, N and M are positive integers. That is to say, the scan signal Gn of the pixel unit 11 of the Nth row can be used as the reset signal GSn of the pixel unit 11 of the N+2th row.
  • the scan signal Gn and the reset signal GSn are both pulse signals, and the scan signal Gn of the pixel unit 11 in the Nth row and the reset signal GSn of the pixel unit 11 in the N+2 row are the same pulse
  • the signal for example, in the example shown in FIG. 1, the scan signal Gn of the pixel unit 11 in the first row and the reset signal GSn of the pixel unit 11 in the third row are the same pulse signal, and are both provided by the first scan line 20.
  • the first driving module 30 and the second driving module 40 may be GOA (Gate driver on array, array substrate gate drive) modules, the first driving module 30 and the second driving The modules 40 are disposed on opposite sides of the pixel array 10 respectively.
  • the two are respectively on the left and right sides of the pixel array 10.
  • the first driving module 30 is connected to the scanning line 20 connected to the pixel units 11 in odd rows
  • the second driving module 40 is connected to the scanning line 20 connected to the pixel units 11 in even rows.
  • M is an even number, and the scan line 20 connecting the pixel units 11 in the M-th row is connected to the second driving module 40. It can be understood that in other examples, M may also be an odd number, which is not specifically limited.
  • the first driving module 30 and the second driving module 40 are used to emit pulse signals, and the pulse signals emitted by the two are sent to the pixel array 10 through the scan line 20 as the scan signal Gn and the reset signal GSn of the pixel unit 11.
  • the first driving module 30 is connected to the scan line 20 connected to the odd-line pixel units 11, and the scan line Gn and the reset signal are provided to the odd-line pixel units 11 through the scan line 20 GSn.
  • the second driving module 40 is connected to the scan line 20 connected to the pixel units 11 in even rows, and provides the scan unit Gn and the reset signal GSn for the pixel units 11 in even rows through the scan lines 20.
  • the first driving module 30 and the scanning line 20 connecting the even-row pixel units 11 may be used, and the second driving module 40 and the scanning line 20 may be connected to the odd-row pixel units 11.
  • the scanning signal Gn and the reset signal GSn are provided to the pixel array 10.
  • the pixel array 10 may be driven continuously row by row, that is, from the first row to the Mth row.
  • the scanning signal Gn of the pixel unit 11 of the N-th row is advanced by one pulse width before the scanning signal Gn of the N+2th.
  • the pulse widths of the scan signal Gn and the reset signal GSn of the pixel units 11 of each row are equal. That is to say, the scanning signal Gn sent by the Nth scanning line 20 is one pulse width earlier than the scanning signal Gn sent by the N+2th scanning line 20.
  • the scan signal Gn sent by the Nth scan line 20 is the reset signal GSn of the pixel unit 11 in the N+2th row
  • the scan signal Gn sent by the N+2 scan line 20 is the pixel in the N+2th row Scan signal Gn of unit 11.
  • the pulse widths of the reset signal GSn and the scan signal Gn of the pixel unit 11 in the N+2th row are equal and the reset signal GSn of the pixel unit 11 in the N+2 row is one pulse width earlier than the scan signal Gn in the N+2th row.
  • the scanning signal Gn of the pixel unit 11 of the Nth row is earlier than the scanning signal Gn of the pixel unit 11 of the N+1th row by half a pulse signal, and the scanning signal Gn of the pixel unit 11 of the N+1th row is lower than that of the The scanning signal Gn of the pixel unit 11 of the N+2 row is advanced by half a pulse signal. That is to say, the scanning signal Gn sent by the Nth scanning line 20 is earlier than the scanning signal Gn sent by the N+1th scanning line 20 by half a pulse width, and the scanning signal Gn sent by the N+1th scanning line 20 is faster than the scanning signal Gn sent by the N+1th scanning line 20.
  • the scanning signal Gn sent by the N+2th scanning line 20 is advanced by half a pulse width.
  • both the first driving module 30 and the second driving module 40 include a pulse output terminal (not shown in the figure), and the pulse output terminal of the first driving module 30 is the pixel unit 11 in the first row
  • the reset signal GSn is provided, and the pulse output terminal of the second driving module 40 provides the reset signal GSn for the pixel unit 11 in the second row.
  • the pulse output terminal of the first driving module 30 may also be used to provide the reset signal GSn for the pixel unit 11 in the second row, and the pulse output terminal of the second driving module 40 may provide the pixel unit 11 in the first row.
  • the reset signal GSn is not specifically limited.
  • each pixel unit 11 of the pixel array 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and light emission Element D OLED .
  • the transistors used in the embodiments of the present application may all be thin-film transistors (Thin-film transistors, TFTs).
  • the transistors (T1-T4) all include a gate G, a source S, and a drain D.
  • each transistor (T1 to T4) is an N-type thin film transistor.
  • the thin film transistor includes a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
  • Each transistor of this embodiment ( T1 ⁇ T4) can use one or more of them.
  • the light emitting element D OLED is an organic light emitting diode (OLED). It can be understood that in other embodiments, each transistor (T1 to T4) may also use a P-type thin film transistor, and only the voltage polarity of the input signal needs to be reversed, that is, the high level turns to the low level, and the low level turns It can be high level. In addition, in some embodiments, the light-emitting element D OLED may also be an inorganic light-emitting diode, which is not specifically limited.
  • the gate G of the first transistor T1 is connected to the reset signal GSn, the source S of the first transistor T1 is connected to the initialization signal INT, and the drain D of the first transistor T1 is electrically connected to the first node N1.
  • the gate G of the second transistor T2 is connected to the scan signal Gn, the source S of the second transistor T2 is connected to the data signal DATA, and the drain D of the second transistor T2 is electrically connected to the second node N2.
  • the gate G of the third transistor T3 is connected to the enable signal En, the source S of the third transistor T3 is electrically connected to the drain D of the fourth transistor T4, and the drain D of the third transistor T3 is electrically connected to the positive power supply voltage VDD .
  • the gate G of the fourth transistor T4 is electrically connected to the second node N2, the source S of the fourth transistor T4 is electrically connected to the first node N1, and the drain D of the fourth transistor T4 is electrically connected to the source of the third transistor T3 S.
  • One end of the first capacitor C1 is electrically connected to the first node N1, and the other end is electrically connected to the second node N2.
  • One end of the second capacitor C2 is electrically connected to the power supply positive voltage VDD, and the other end is electrically connected to the first node N1.
  • the anode of the light emitting element D OLED is electrically connected to the first node N1, and the cathode of the light emitting element D OLED is electrically connected to the power supply negative voltage VSS.
  • the reset signal GSn is used to control the on and off of the first transistor T1.
  • the first transistor T1 is turned on, and when the reset signal GSn is at a low potential, the first transistor T1 is turned off.
  • the scan signal Gn is used to control the turning on and off of the second transistor T2.
  • the second transistor T2 is turned on, and when the scan signal Gn is at a low potential, the second transistor T2 is turned off.
  • the enable signal En is used to control the turning on and off of the third transistor T3.
  • the third transistor T3 When the enable signal En is at a high potential, the third transistor T3 is turned on, and when the enable signal En is at a low potential, the third transistor T3 is turned off.
  • the initialization signal INT is a constant low potential
  • the data signal DATA is a high potential single pulse.
  • the working process of the display device 100 includes a reset phase, a compensation phase, a writing phase, and a light-emitting phase of the pixel unit 11.
  • the scan signal Gn, the reset signal GSn, the initialization signal INT, and the enable signal En operate according to the timing diagram shown in FIG. 4 to correspond to the reset phase, the compensation phase, the writing phase, and the light-emitting phase.
  • the reset phase The specific operation in the reset phase is shown in Figure 5. Specifically, in the reset phase, the reset signal GSn and the enable signal En are at a high potential, the first transistor T1 and the third transistor T3 are turned on, the scan signal Gn and the data signal DATA are at a low potential, and the second transistor T2 and the fourth transistor T4 Turned off, the initialization signal INT resets the first node N1 and simultaneously charges the first capacitor C1 and the second capacitor C2. In the reset phase, the light-emitting element D OLED does not emit light.
  • the compensation stage The specific operation of the compensation stage is shown in Figure 6. Specifically, in the compensation stage, the scan signal Gn and the enable signal En are at a high potential, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, the reset signal GSn and the data signal DATA are at a low potential, and the first transistor T1 Off, the second node N2 of the data signal DATA transmits the reference potential Vref (ie, the low potential of the data signal DATA), and the potential of the first node N1 at this time is the difference between the reference potential Verf and the threshold voltage of the fourth transistor T4, the fourth transistor T4
  • the threshold voltage of is the voltage difference between the gate G and the source S of the fourth transistor T4.
  • the first capacitor C1 and the second capacitor C2 may be used to maintain the voltage of the first node N1.
  • the specific operation of the writing stage is shown in Figure 7. Specifically, in the writing stage, the scan signal Gn and the data signal DATA are at a high potential, the second transistor T2 and the fourth transistor T4 are turned on, the reset signal GSn and the enable signal En are at a low potential, and the first transistor T1 and the third transistor T3 is turned off, and the data signal DATA transmits the data potential Vdata (that is, the high potential of the data signal DATA) to the second node N2.
  • the first capacitor C1 and the second capacitor C2 can also be used to maintain the voltage of the first node N1.
  • the enable signal En is at a high potential
  • the scan signal Gn the reset signal GSn
  • the data signal DATA are at a low potential
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the first transistor T1 and the second transistor T2 is turned off
  • the power supply positive voltage VDD charges the first node N1
  • the light emitting element D OLED emits light.
  • the Nth scanning line 20 may be the N+2th row pixel unit while providing the Nth row of pixel units 11 with the scanning signal Gn 11 Provide a reset signal GSn.
  • the Nth scanning line 20 may be the N+2th row pixel unit while providing the Nth row of pixel units 11 with the scanning signal Gn 11 Provide a reset signal GSn.
  • the first feature “above” or “below” the second feature may include the direct contact of the first and second features, or may include the first and second features Contact not directly but through another feature between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.
  • the disclosure herein provides many different implementations or examples for implementing different structures of the present application.
  • the components and settings of specific examples are described herein. Of course, they are only examples, and the purpose is not to limit this application.
  • the present application may repeat reference numerals and/or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or settings discussed.
  • the present application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and/or the use of other materials.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示装置(100)和电子装置(1000)。显示装置(100)，包括像素阵列(10)、扫描线(20)、第一驱动模块(30)和第二驱动模块(40)。像素阵列(10)包括M行像素单元(11)，扫描线(20)的条数为M条扫描线(20)，第N条扫描线(20)连接第N行像素单元(11)和第N+2行像素单元(11)。第一驱动模块(30)和第二驱动模块(40)的其中一个与连接奇数行像素单元(11)的扫描线(20)连接并用于通过扫描线(20)为奇数行像素单元(11)提供扫描信号(Gn)和复位信号(GSn)，另外一个与连接偶数行像素单元(11)的扫描线(20)连接并用于通过扫描线(20)为偶数行像素单元(11)提供扫描信号(Gn)和复位信号(GSn)。

Description

显示装置和电子装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示装置和电子装置。
背景技术
在现有技术中，GOA(Gate driver on array，阵列基板栅极驱动)电路广泛应用于LCD和AMOLED等电子显示器中。它是显示装置的关键部分，用于向像素阵列提供扫描脉冲信号。
现有技术的显示装置中，一般采用两个GOA电路为像素阵列的多行像素单元Pixel提供扫描脉冲信号，一个为像素单元Pixel提供扫描信号Gn，另一个为像素单元Pixel提供复位信号Rn。然而，随着人们对显示装置的分辨率要求越来越高，像素阵列的行数增加，每一个GOA电路的级数也会相应的增加，例如，针对1920分辨率的面板，两个GOA都要分别需要1920级电路，一个GOA提供扫描信号Gn，另一个GOA提供复位信号Rn。这样，使得显示装置的边框较宽，无法满足目前更窄边框的需求。
发明内容
有鉴于此，本申请实施方式提供一种显示装置和电子装置。
本申请的实施方式的显示装置包括：
像素阵列，所述像素阵列包括M行像素单元；
M条扫描线，第N条扫描线连接第N行像素单元和第N+2行像素单元，1<＝N，(N+2)≦M，N和M均为正整数；和
第一驱动模块和第二驱动模块，所述第一驱动模块和所述第二驱动模块的其中一个与连接奇数行所述像素单元的所述扫描线连接并用于通过所述扫描线为奇数行所述像素单元提供扫描信号和复位信号，所述第一驱动模块和所述第二驱动模块的另外一个与连接偶数行所述像素单元的所述扫描线连接并用于通过所述扫描线为偶数行所述像素单元提供扫描信号和复位信号。
本申请实施方式的显示装置中，第N条扫描线在为第N行像素单元提供扫描信号的同时也可以为第N+2行像素单元提供复位信号。如此，可以无须每一行像素单元都需要设置2条单独的扫描线以分别为每一行像素单元提供扫描信号和复位信号。这样，可以减少两个驱动模块需要的设置的电路级数，使得显示装置的边框能够做到更窄。
本申请实施方式的电子装置包括上述实施方式所述的显示装置。
本申请实施方式的电子装置中，第N条扫描线在为第N行像素单元提供扫描信号的同时也可以为第N+2行像素单元提供复位信号。如此，可以无须每一行像素单元都需要设置2条单独的扫描线以分别为每一行像素单元提供扫描信号和复位信号。这样，可以减少两个驱动模块需要的设置的电路级数，使得显示装置的边框能够做到更窄。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本申请的实施方式的显示装置的结构示意图；
图2是本申请的实施方式的电子装置的模块框架示意图；
图3是本申请的实施方式的显示装置的像素单元的结构示意图；
图4是本申请的实施方式的显示装置的像素单元的工作时序示意图；
图5是本申请的实施方式的显示装置的像素单元的运行状态图；
图6是本申请的实施方式的显示装置的像素单元的又一运行状态图；
图7是本申请的实施方式的显示装置的像素单元的再一运行状态图；
图8是本申请的实施方式的显示装置的像素单元的又一运行状态图。
主要元件符号说明：
电子装置1000、显示装置100、像素阵列10、像素单元11、扫描线20、第一驱动模块30、第二驱动模块40、扫描信号Gn、复位信号GSn、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容C1、第二电容C2、发光元件DOLED、电源正电压VDD、电源负电压VSS、第一节点N1、第二节点N2、栅极G、漏极D、源级S、数据信号DATA、初始化信号INT、使能信号En、参考电位Vref、数据电位Vdata。
具体实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、 “厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接。可以是机械连接，也可以是电连接。可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
请参阅图1和图2，本申请实施方式的显示装置100可以用于本申请实施方式的电子装置1000。或者说，本申请实施方式的电子装置1000包括本申请实施方式显示装置100。本申请实施方式的显示装置100可以为LCD(Liquid Crystal Display，液晶显示屏)或OLED(Organic Light-Emitting Display，有机发光显示屏)等显示装置1000。
本申请实施方式的电子装置1000包括但不限于手机、平板电脑、可穿戴智能设备、显示器、车载终端、音乐播放器、视频播放器、电视机等，在图2所示的示例中，电子装置100为手机。
本申请实施方式的显示装置100包括像素阵列10、扫描线20、第一驱动模块30和第二驱动模块40。
请参阅图1，像素阵列10包括M行像素单元11，扫描线20的条数与像素单元11的行数相对应，即扫描线20的数量为M条，第N条扫描线20连接第N行像素单元11和第N+2行像素单元11并用于为第N行像素单元11提供扫描信号Gn和为第N+2行像素单元11提供复位信号GSn，其中，1≦N，N+2≦M，N和M均为正整数。也即是说，第N行像素单元11的扫描信号Gn可以作为第N+2行像素单元11的复位信号GSn。
可以理解的是，在本实施方式中，扫描信号Gn和复位信号GSn都为脉冲信号，第N行像素单元11的扫描信号Gn和第N+2行像素单元11的复位信号GSn为同一个脉冲信号，例如，如图1所示的示例中，第1行像素单元11的扫描信号Gn和第3行像素单元11的复位信号GSn为同一脉冲信号，且均由第1条扫描线20提供。
请继续参阅图1，在本申请实施方式中，第一驱动模块30和第二驱动模块40可以 为GOA(Gate driver on array，阵列基板栅极驱动)模块，第一驱动模块30和第二驱动模块40分别设置于像素阵列10的相背两侧，例如，在图1的示例中，两者分别为与像素阵列10的左右两侧。第一驱动模块30与连接奇数行像素单元11的扫描线20连接，第二驱动模块40与连接偶数行像素单元11的扫描线20连接。
需要说明的是，在图1的示例中，M为偶数，连接第M行像素单元11的扫描线20与第二驱动模块40连接。可以理解，在其他例子中，M也可以为奇数，具体不作限制。
第一驱动模块30和第二驱动模块40用于发出脉冲信号，两者发出的脉冲信号通过扫描线20输送给像素阵列10以作为像素单元11的扫描信号Gn和复位信号GSn。
具体地，如图1所示，在本实施方式中，第一驱动模块30与奇数行像素单元11连接的扫描线20连接，通过扫描线20为奇数行像素单元11提供扫描信号Gn和复位信号GSn。第二驱动模块40与偶数行像素单元11连接的扫描线20连接，通过扫描线20为偶数行像素单元11提供扫描信号Gn和复位信号GSn。
可以理解的是，在其他实施方式中，也可以采用第一驱动模块30与连接偶数行像素单元11的扫描线20，第二驱动模块40与连接奇数行像素单元11的扫描线20的方式来实现为像素阵列10提供扫描信号Gn和复位信号GSn。
在本实施方式中，像素阵列10可以采用逐行连续驱动的形式，即从第1行开始以此驱动，直至第M行。在本实施方式中，第N行像素单元11的扫描信号Gn比第N+2的扫描信号Gn提前一个脉冲宽度。同时，每一行像素单元11的扫描信号Gn和复位信号GSn的脉冲宽度相等。也即是说，第N条扫描线20输送的扫描信号Gn比第N+2条扫描线20输送的扫描信号Gn提前一个脉冲宽度。可以理解，第N条扫描线20输送的扫描信号Gn即为第N+2行像素单元11的复位信号GSn，第N+2条扫描线20输送的扫描信号Gn即为第N+2行像素单元11的扫描信号Gn。显然，第N+2行像素单元11的复位信号GSn和扫描信号Gn的脉冲宽度相等且第N+2行像素单元11的复位信号GSn比第N+2行的扫描信号Gn提前一个脉冲宽度。
同时，可以理解的是，第N行像素单元11的扫描信号Gn比第N+1行像素单元11的扫描信号Gn提前半个脉冲信号，第N+1行像素单元11的扫描信号Gn比第N+2行像素单元11的扫描信号Gn提前半个脉冲信号。也即是说，第N条扫描线20输送的扫描信号Gn比第N+1条扫描线20输送的扫描信号Gn提前半个脉冲宽度，第N+1条扫描线20输送的扫描信号Gn比第N+2条扫描线20输送的扫描信号Gn提前半个脉冲宽度。
需要说明的是，在本实施方式中，第一驱动模块30和第二驱动模块40均包括脉冲输出端(图未示出)，第一驱动模块30的脉冲输出端为第1行像素单元11提供复位信 号GSn，第二驱动模块40的脉冲输出端为第2行像素单元11提供复位信号GSn。可以理解，在其他实施方式中，也可以采用第一驱动模块30的脉冲输出端为第2行像素单元11提供复位信号GSn，第二驱动模块40的脉冲输出端为第1行像素单元11提供复位信号GSn，具体不作限制。
请参阅图3和图4，像素阵列10的每一个像素单元11都包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容C1、第二电容C2以及发光元件D OLED。
本申请实施方式中采用的晶体管均可以为薄膜晶体管(Thin-film transistor，TFT)。晶体管(T1～T4)均包括栅极G、源级S和漏极D。在图示的实施方式中，各个晶体管(T1～T4)均为N型薄膜晶体管，薄膜晶体管包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管，本实施实施方式的各个晶体管(T1～T4)可采用其中的一种或多种。
发光元件D OLED为有机发光二极管(OLED)。可以理解，在其他实施方式中，各个晶体管(T1～T4)也可以采用P型薄膜晶体管，仅需将输入信号的电压极性反转，即高电平转成低电平，低电平转为高电平即可。此外，在某些实施方式中，发光元件D OLED也可以是无机发光二极管，具体不作限制。
第一晶体管T1的栅极G接入复位信号GSn，第一晶体管T1的源极S接入初始化信号INT，第一晶体管T1的漏极D电性连接第一节点N1。第二晶体管T2的栅极G接入扫描信号Gn，第二晶体管T2的源极S接入数据信号DATA，第二晶体管T2的漏极D电性连接第二节点N2。第三晶体管T3的栅极G接入使能信号En，第三晶体管T3的源极S电性连接第四晶体管T4的漏极D，第三晶体管T3的漏极D电性连接电源正电压VDD。第四晶体管T4的栅极G电性连接第二节点N2，第四晶体管T4的源极S电性连接第一节点N1，第四晶体管T4的漏极D电性连接第三晶体管T3的源极S。第一电容C1的一端电性连接第一节点N1，另一端电性连接第二节点N2。第二电容C2的一端电性连接电源正电压VDD，另一端电性连接第一节点N1。发光元件D OLED的阳极电性连接第一节点N1，发光元件D OLED的阴极电性连接电源负电压VSS。
具体地，复位信号GSn用于控制第一晶体管T1的开启和关闭，在复位信号GSn为高电位时，第一晶体管T1开启，在复位信号GSn为低电位时，第一晶体管T1关闭。扫描信号Gn用于控制第二晶体管T2的开启和关闭，在扫描信号Gn为高电位时，第二晶体管T2开启，在扫描信号Gn为低电位时，第二晶体管T2关闭。使能信号En用于控制第三晶体管T3的开启和关闭，在使能信号En为高电位时，第三晶体管T3开启，在使能信号En为低电位时，第三晶体管T3关闭。此外，请结合图4，初始化信号INT 为一恒定低电位，数据信号DATA为一高电位单脉冲。
请参阅图4，显示装置100的工作过程包括像素单元11的复位阶段、补偿阶段、写入阶段和发光阶段。扫描信号Gn、复位信号GSn、初始化信号INT和使能信号En根据图4所示的的时序图运行以对应复位阶段、补偿阶段、写入阶段和发光阶段。
复位阶段的具体运行情况如图5所示。具体地，在复位阶段，复位信号GSn和使能信号En为高电位，第一晶体管T1和第三晶体管T3打开，扫描信号Gn和数据信号DATA为低电位，第二晶体管T2和第四晶体管T4关闭，初始化信号INT对第一节点N1进行复位并同时对第一电容C1和第二电容C2进行充电。在复位阶段，发光元件D OLED不发光。
补偿阶段的具体运行情况如图6所示。具体地，在补偿阶段，扫描信号Gn和使能信号En为高电位，第二晶体管T2、第三晶体管T3和第四晶体管T4打开，复位信号GSn和数据信号DATA为低电位，第一晶体管T1关闭，数据信号DATA第二节点N2传输参考电位Vref(即数据信号DATA的低电位)，此时第一节点N1的电位为参考电位Verf和第四晶体管T4的阈值电压之差，第四晶体管T4的阈值电压为第四晶体管T4栅极G与源极S之间的压差。在补偿阶段，第一电容C1和第二电容C2可用于维持第一节点N1的电压。
写入阶段的具体运行情况如图7所示。具体地，在写入阶段，扫描信号Gn和数据信号DATA为高电位，第二晶体管T2、第四晶体管T4打开，复位信号GSn和使能信号En为低电位，第一晶体管T1和第三晶体管T3关闭，数据信号DATA对第二节点N2传输数据电位Vdata(即数据信号DATA的高电位)。在写入阶段，第一电容C1和第二电容C2也可用为维持第一节点N1的电压。
发光阶段的具体运行情况如图8所示。具体地，在发光阶段，使能信号En为高电位，扫描信号Gn、复位信号GSn和数据信号DATA均为低电位，第三晶体管T3和第四晶体管T4打开，第一晶体管T1和第二晶体管T2关闭，电源正电压VDD对第一节点N1充电，发光元件D OLED发光。
综上所述，在本申请实施方式的显示装置100和电子装置1000中，第N条扫描线20在为第N行像素单元11提供扫描信号Gn的同时也可以为第N+2行像素单元11提供复位信号GSn。如此，可以无须每一行像素单元11都需要设置2条单独的扫描线20以分别为每一行像素单元11提供扫描信号Gn和复位信号GSn。这样，可以减少两个驱动模块需要的设置的电路级数，使得显示装置100的边框能够做到更窄。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它 们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
本文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，本文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。尽管已经示出和描述了本申请的实施方式，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施方式进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (12)

  1. 一种显示装置，其特征在于，包括：
    像素阵列，所述像素阵列包括M行像素单元；
    M条扫描线，第N条扫描线连接第N行像素单元和第N+2行像素单元，1≦N，(N+2)≦M，N和M均为正整数；和
    第一驱动模块和第二驱动模块，所述第一驱动模块和所述第二驱动模块的其中一个与连接奇数行所述像素单元的所述扫描线连接并用于通过所述扫描线为奇数行所述像素单元提供扫描信号和复位信号，所述第一驱动模块和所述第二驱动模块的另外一个与连接偶数行所述像素单元的所述扫描线连接并用于通过所述扫描线为偶数行所述像素单元提供扫描信号和复位信号。
  2. 如权利要求1所述的显示装置，其特征在于，提供给第N行所述像素单元的扫描信号比提供给第N+2行所述像素单元的扫描信号提前一个脉冲宽度。
  3. 如权利要求1所述的显示装置，其特征在于，提供给所述像素单元的扫描信号和复位信号的脉冲宽度相等。
  4. 如权利要求1所述的显示装置，其特征在于，所述像素单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容以及发光元件；
    所述第一晶体管的栅极接入所述复位信号，源极接入初始化信号，漏极电性连接第一节点；
    所述第二晶体管的栅极接入所述扫描信号，源极接入数据信号，漏极电性连接第二节点；
    所述第三晶体管的栅极接入使能信号，源极电性连接第四晶体管的漏极，漏极电性连接电源正电压；
    所述第四晶体管的栅极电性连接所述第二节点，源极电性连接所述第一节点，漏极电性连接所述第三晶体管的源极；
    所述第一电容的一端电性连接所述第一节点，另一端电性连接所述第二节点；
    所述第二电容的一端电性连接电源正电压，另一端电性连接所述第一节点；
    所述发光元件的阳极电性连接第一节点，所述发光元件的阴极电性连接电源负电压。
  5. 如权利要求4所述的显示装置，其特征在于，所述显示装置的工作过程包括所述像素单元的复位阶段，在所述复位阶段，所述复位信号和所述使能信号为高电位，所述扫描信号和所述数据信号为低电位。
  6. 如权利要求4所述的显示装置，其特征在于，所述显示装置的工作过程包括所述像素单元的补偿阶段，在所述补偿阶段，所述扫描信号和所述使能信号为高电位，所述复位信号和所述数据信号为低电位。
  7. 如权利要求4所述的显示装置，其特征在于，所述显示装置的工作过程包括所述像素单元的写入阶段，在所述写入阶段，所述扫描信号和所述数据信号为高电位，所述复位信号和所述使能信号为低电位。
  8. 如权利要求4所述的显示装置，其特征在于，所述显示装置的工作过程包括所述像素单元的发光阶段，在所述发光阶段，所述使能信号为高电位，所述扫描信号、复位信号和所述数据信号均为低电位。
  9. 如权利要求4所述的显示装置，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管中的至少一个为薄膜晶体管。
  10. 如权利要求4所述的显示装置，其特征在于，所述初始化信号为一恒定低电位，所述数据信号为一高电位单脉冲。
  11. 如权利要求1所述的显示装置，其特征在于，所述第一驱动模块与第二驱动模块分别设于所述像素阵列相背的两侧。
  12. 一种电子装置，其特征在于，包括权利要求1-11任意一项所述的显示装置。
PCT/CN2018/118926 2018-12-03 2018-12-03 显示装置和电子装置 WO2020113372A1 (zh)

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