WO2019200901A1 - 信号处理电路及其驱动方法、显示面板及其驱动方法及显示装置 - Google Patents

信号处理电路及其驱动方法、显示面板及其驱动方法及显示装置 Download PDF

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Publication number
WO2019200901A1
WO2019200901A1 PCT/CN2018/115253 CN2018115253W WO2019200901A1 WO 2019200901 A1 WO2019200901 A1 WO 2019200901A1 CN 2018115253 W CN2018115253 W CN 2018115253W WO 2019200901 A1 WO2019200901 A1 WO 2019200901A1
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Prior art keywords
circuit
signal
display panel
reset
input
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PCT/CN2018/115253
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English (en)
French (fr)
Inventor
钟杰兴
Original Assignee
京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
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Priority to US16/470,659 priority Critical patent/US11302260B2/en
Priority to EP18887201.4A priority patent/EP3783598A4/en
Publication of WO2019200901A1 publication Critical patent/WO2019200901A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • Embodiments of the present disclosure relate to a signal processing circuit and a driving method thereof, a display panel, a driving method thereof, and a display device.
  • the display mainly includes a liquid crystal display (LCD) screen and an Organic Light-Emitting Diode (OLED) screen, which can be applied to mobile phones, televisions, notebook computers, digital cameras, instrumentation, virtual reality ( Virtual Reality, VR) devices, Augmented Reality (AR) devices and other electronic devices with display functions.
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure provides a signal processing circuit including: a shunt circuit including N output nodes; N buffer circuits respectively connected to the N output nodes; wherein the shunt circuit is configured to respond The control signal outputs the input signal to the N output nodes at N different times respectively; each of the N buffer circuits is configured to buffer and output the input signal received by the corresponding output node; N is greater than An integer equal to 2.
  • a first end of each of the N cache circuits is configured to be connected to the output node corresponding thereto, and each of the N cache circuits The second end is configured to be coupled to the first voltage terminal to receive the first voltage.
  • each of the N cache circuits includes a capacitor, a first pole of the capacitor serves as a first end of the buffer circuit, and a second capacitor The pole acts as the second end of the buffer circuit.
  • the signal processing circuit provided in an embodiment of the present disclosure includes N reset circuits, wherein the N reset circuits are respectively connected to the N output nodes, and configured to respond to the reset signal to the N output nodes. Reset.
  • a control terminal of each of the N reset circuits is configured to be connected to a reset signal line to receive the reset signal, and each of the N reset circuits The first end is configured to be connected to the corresponding output node, and the second end of each of the N reset circuits is configured to be connected to the second voltage terminal to receive the second voltage.
  • each of the N reset circuits includes a reset transistor, a gate of the reset transistor serves as a control terminal of the reset circuit, and a One pole serves as a first end of the reset circuit, and a second pole of the reset transistor serves as a second end of the reset circuit.
  • the shunt circuit further includes an input end, N input control ends, and N switch circuits, wherein the N switch circuits are connected to the input end, and Each of the N output nodes and the N input control terminals are respectively connected in one-to-one correspondence, and each of the N switch circuits is configured to respond to the control signal received from the corresponding input control terminal, The input signal received from the input is output to a corresponding one of the output nodes.
  • each of the N switching circuits includes a switching transistor, and a gate of the switching transistor is connected to a corresponding input control terminal, where the switching transistor is A first pole is coupled to the input, and a second pole of the switching transistor is coupled to the corresponding one of the output nodes.
  • N is equal to 2
  • the N input control terminals are connected to each other to be connected to the same input control line.
  • the N switch circuits include a first switch circuit and a second switch circuit
  • the shunt circuit further includes an inverter circuit, the first switch circuit and One of the second switching circuits is connected to the N input control terminals through the inverter circuit.
  • At least one embodiment of the present disclosure further provides a display panel comprising the signal processing circuit and the plurality of data lines according to any one of the embodiments of the present disclosure, wherein the N data lines of the plurality of data lines are respectively connected to the The N buffer circuits of the signal processing circuit, wherein the input signal is a display data signal.
  • a display panel provided in an embodiment of the present disclosure includes a plurality of pixel units distributed in an array, wherein N data lines connected to the signal processing circuit are connected to the same column of pixel units, and the same column of pixel units includes N pixel unit groups, each of which is connected to the same data line.
  • N is equal to 2
  • the N pixel unit groups include a first pixel unit group and a second pixel unit group, and the first pixel unit group includes an odd number of rows.
  • a pixel unit, the second pixel unit group including pixel units located in even rows.
  • a display panel provided in an embodiment of the present disclosure includes an array substrate, wherein the signal processing circuit is disposed on the array substrate.
  • N data lines connected to the same signal processing circuit are located at different layers of the array substrate.
  • a display panel provided in an embodiment of the present disclosure includes at least one gate driving circuit, wherein the gate driving circuit is configured to provide a plurality of gate scanning signals to perform line scanning on pixel units of the display panel,
  • the pulse duration of the gate scan signal of the M+1th row partially overlaps with the pulse duration of the gate scan signal of the Mth row, and M is an integer greater than zero.
  • At least one embodiment of the present disclosure further provides a display device including the signal processing circuit according to any embodiment of the present disclosure or the display panel according to any of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a signal processing circuit, comprising: providing the control signal and the input signal such that the shunt circuit sequentially sets the input signal to N in response to the control signal The different timings are respectively output to the N output nodes, and the input signals are buffered and output by each of the N buffer circuits.
  • At least one embodiment of the present disclosure also provides a driving method of a display panel, comprising: providing the control signal and the display data signal such that the shunt circuit sequentially sequentially displays the display data signal in response to the control signal N different timings are respectively output to the N output nodes, and the display data signals are buffered and output to the corresponding N data lines by each of the N buffer circuits.
  • a driving method of a display panel includes: providing a gate scan signal to perform line scanning on the display panel, and pulse durations of adjacent gate scan signals partially overlap each other.
  • FIG. 1 is a schematic block diagram of a signal processing circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic block diagram of a shunt circuit of a signal processing circuit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic block diagram of a shunt circuit of another signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram showing a specific implementation example of the signal processing circuit shown in FIG. 2;
  • FIG. 8 is a circuit diagram of a specific implementation example of a buffer circuit of a signal processing circuit according to an embodiment of the present disclosure
  • FIG. 9 is a circuit diagram showing a specific implementation example of the signal processing circuit shown in FIG. 4;
  • 10A is a circuit diagram showing a specific implementation example of a shunt circuit of the signal processing circuit shown in FIG. 6;
  • 10B is a circuit diagram showing another specific implementation example of the shunt circuit of the signal processing circuit shown in FIG. 6;
  • FIG. 11 is a timing diagram of signals of a signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of signals of another signal processing circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 14 is a timing diagram of signals of a display panel according to an embodiment of the present disclosure.
  • Figure 15A is a schematic diagram of a pixel circuit
  • Fig. 15B is a driving timing chart of the pixel circuit shown in Fig. 15A.
  • a pixel array of a display screen typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the gate driving circuit in the display screen provides a switching state voltage signal for the plurality of rows of gate lines of the pixel array, thereby, for example, controlling the plurality of rows of gate lines to be sequentially turned on, and simultaneously providing data signals from the data lines to the pixel units of the corresponding rows in the pixel array.
  • the pixel circuit in the pixel unit is compensated or charged by the data signal) to form a gray voltage required for each gray scale of the display image in each pixel unit, thereby displaying one frame of image.
  • the update rate refers to the number of times the display screen repeatedly scans the displayed image at a certain time.
  • the high update rate display can be applied to the fields of movie playback, AR display, VR display, e-sports, etc. It can improve the smear phenomenon caused by the influence of display delay on the dynamic picture, and the stability of the display picture is good.
  • a high update rate may result in insufficient compensation time (charging time) of the pixel circuits in the display, resulting in a severe deterioration in picture quality, for example, generation of display mura.
  • the charging time available for the pixel circuit is 3.3 ⁇ s, charging only the 60Hz AMOLED display.
  • the compensation time of its pixel circuit is insufficient.
  • the inventors of the present disclosure have noticed that insufficient compensation time of the pixel circuit may result in insufficient data voltage writing, which affects display quality.
  • Figure 15A shows a pixel circuit with threshold compensation capability.
  • the pixel circuit is a 7T1C type pixel circuit, that is, a pixel circuit having seven transistors and one storage capacitor Cst.
  • the pixel circuit includes a first transistor Tt1, a second transistor Tt2, a third transistor Tt3, a fourth transistor Tt4, a fifth transistor Tt5, a sixth transistor Tt6, a seventh transistor Tt7, a storage capacitor Cst, and a light-emitting element ( For example, oled), the first node N1, and the second node N2.
  • the control terminals of the second transistor Tt2 and the fourth transistor Tt4 are configured as a gate control terminal GAT of the pixel circuit, connected to the gate line to receive the scan signal; and the control terminals of the fifth transistor Tt5 and the sixth transistor Tt6 are configured as pixel circuits
  • the illumination control terminal EM is connected to the illumination control line to receive the illumination control signal; the control terminals of the first transistor Tt1 and the seventh transistor Tt7 are configured as a reset control terminal RESE of the pixel circuit, and are connected to the reset line to connect the reset signal.
  • the control terminal of the third transistor Tt3 is connected to the second node N2 and the first end of the storage capacitor Cst, the first node N1 is connected to the first power terminal ELVDD, and the second end of the light emitting element is connected to the second power terminal ELVSS;
  • the first power supply terminal ELVDD and the second power supply terminal ELVSS are configured as a constant voltage source, and the voltage Vt1 output by the first power supply terminal ELVDD is, for example, greater than the voltage Vt2 output by the second power supply terminal ELVSS, and the voltage Vt2 output by the ELVSS is, for example, zero (for example, Ground).
  • each transistor is a P-type transistor as an example, but the embodiment of the present disclosure is not limited to such a case, for example, at least one transistor in the pixel circuit may be an N-type transistor.
  • the P-type transistor is turned on when the gate of the P-type transistor receives a low level signal below a threshold voltage, and the P-type transistor is turned off when receiving a high level signal above a threshold voltage.
  • Fig. 15B shows a driving timing chart of the pixel circuit shown in Fig. 15A. As shown in FIG. 15B, each driving period of the pixel circuit includes a reset phase Tre, a compensation phase Tc, and an emission phase Tem.
  • the reset control terminal RSE of the pixel circuit receives the low level signal, whereby the first transistor Tt1 and the seventh transistor Tt7 are turned on, whereby the initial voltage Vinit is turned on via the first transistor Tt1 and the seventh transistor Tt7, respectively.
  • the initial voltage Vinit can cause the third transistor Tt3 (drive transistor ) is in the on state.
  • the voltage of the first node N1 is V1.
  • the gate control terminal GAT of the pixel circuit receives the low level signal, whereby the second transistor Tt2 and the fourth transistor Tt4 are turned on, thus causing the data voltage Vdata to be applied to the source of the third transistor Tt3, and The drain and the gate of the third transistor Tt3 are electrically connected. Since the third transistor Tt3 is in an on state, the storage capacitor Cst can be charged by the drain and the gate of the third transistor Tt3, and the charging process ends as the voltage of the gate of the third transistor Tt3 rises.
  • the voltage Vt1 of the source (first end) of the third transistor Tt3 is Vdata
  • the voltage Vt2 of the drain (second terminal) and the gate (control terminal) is changed to Vdata+Vth, that is, the second node N2.
  • the voltage is also Vdata+Vth, and is stored at the first end of the storage capacitor Cst (that is, the end connected to the second node N2), where Vth is the threshold voltage of the third transistor Tt3, and the first node N1 at this time
  • the voltage is still V1.
  • the light emitting control terminal EM receives the low level signal, whereby the fifth transistor Tt5 and the sixth transistor Tt6 are turned on, and the first end of the third transistor Tt3 is connected to the first through the turned-on fifth transistor Tt5.
  • the current Ids outputted by the third transistor Tt3 in a saturated state can be obtained by the following formula:
  • K W / L ⁇ C ⁇ ⁇
  • W / L is the width to length ratio (i.e., the ratio of the width to the length) of the channel of the third transistor Tt3
  • ⁇ is the electron mobility
  • C is the capacitance per unit area.
  • the current Ids outputted by the third transistor Tt3 in the saturated state is independent of the threshold voltage of the third transistor Tt3, whereby the pixel circuit shown in FIG. 15A has a threshold compensation function.
  • the inventors of the present disclosure have noted in the study that when the refresh rate of the display panel is increased (for example, from 60 Hz to 120 Hz), since the scan signal output from the gate drive circuit and the (pulse) time of the reset signal are reduced, reset The lengths of the phase Tre, the compensation phase Tc, and the illumination phase Tem are all reduced (eg, halved). At this time, since the time of the compensation phase Tc is short, that is, the data writing time is short, the storage capacitor Cst cannot be sufficiently charged, resulting in insufficient threshold voltage compensation capability of the pixel circuit.
  • the pixel circuit shown in FIG. 15A is exemplarily described below. As shown in FIG.
  • At least one embodiment of the present disclosure provides a signal processing circuit and a driving method thereof, a display panel, a driving method thereof, and a display device.
  • the signal processing circuit can extend the compensation time of a pixel circuit in a display panel, and is compatible with existing pixel circuits and drivers.
  • the chip can solve the problem of insufficient compensation time of the pixel circuit in the high update rate screen, and helps to improve the display quality.
  • At least one embodiment of the present disclosure provides a signal processing circuit including a shunt circuit and N cache circuits.
  • the shunt circuit includes N output nodes, and the N cache circuits are respectively connected to the N output nodes.
  • the shunt circuit is configured to output an input signal to the N output nodes at N different times in response to a control signal.
  • the buffer circuit is configured to buffer and output the input signal received by the corresponding output node.
  • N is an integer greater than or equal to 2.
  • FIG. 1 is a schematic block diagram of a signal processing circuit according to an embodiment of the present disclosure.
  • the signal processing circuit 10 includes a shunt circuit (Demux circuit) 100 and N buffer circuits 200, N being an integer greater than or equal to two.
  • the shunt circuit 100 includes N output nodes, such as Q1, Q2, . . . , QN.
  • the shunt circuit 100 is configured to output the received input signal to the N output nodes at N different times in response to the received control signal.
  • the shunt circuit 100 is connected to the input control terminal Mx and the input terminal Input, and is configured to output the input signal provided by the input terminal to the Q1 and Q2 at different N times under the control of the control signal provided by the input control terminal Mx.
  • ⁇ , QN the data information represented by the input signals at these N different times may be different from each other.
  • the input terminal Input may be connected to the data driving circuit 400 disposed outside the signal processing circuit 10 to receive the display data signal supplied from the data driving circuit 400 as an input signal.
  • the data driving circuit 400 may be a data driver or a driving chip disposed in the display device, and configured to provide a display data signal to the plurality of pixel units, the display data signal being the input signal.
  • the number of output nodes is not limited, for example, it may be 2, 3, 4, or any number, and only needs to ensure that the number of output nodes is greater than or equal to 2.
  • the number of control signals is not limited, and may be any number as needed. Accordingly, the number of input control terminals Mx is also not limited, and is equal to the number of control signals.
  • the N cache circuits 200 are respectively connected to the N output nodes, and are configured to buffer and output the input signals received by the corresponding output nodes.
  • the buffer circuit 200_1 is connected to the first output node Q1 and the first output terminal Out1, configured to buffer and output the input signal received by the first output node Q1 to the first output terminal Out1, and maintain the output for a predetermined time;
  • the buffer circuit 200_2 is connected to the second output node Q2 and the second output terminal Out2, configured to buffer and output the input signal received by the second output node Q2 to the second output terminal Out2, and maintain the output for a predetermined time.
  • N output terminals Out1, Out2, . . . , OutN may be respectively connected to N data lines to provide an input data signal to the pixel unit.
  • the number of cache circuits 200 is equal to the number of output nodes, thereby ensuring that the two are connected one-to-one.
  • FIG. 2 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • the signal processing circuit 10 includes a shunt circuit 100, a first buffer circuit 210, and a second buffer circuit 220.
  • the shunt circuit 100 includes a first output node Q1 and a second output node Q2.
  • the first end 211 of the first buffer circuit 210 is configured to be connected with an output node corresponding thereto (ie, the first output node Q1), and the second end 212 of the first buffer circuit 210 is configured to be connected to the first voltage terminal VDC for receiving The first voltage.
  • the first end 221 of the second buffer circuit 220 is configured to be connected to an output node corresponding thereto (ie, the second output node Q2), and the second end 222 of the second buffer circuit 220 is configured to be connected to the first voltage terminal VDC for receiving The first voltage.
  • the first voltage terminal VDC is a DC voltage terminal, and can provide a DC high level signal (for example, VDD), and can also provide a DC low level signal (for example, VSS), which is not limited by the embodiment of the present disclosure.
  • the shunt circuit 100 is similar to the shunt circuit 100 depicted in FIG. 1, and will not be described again herein.
  • the shunt circuit 100 When the control signal supplied from the input control terminal Mx is an active level, the shunt circuit 100 outputs the input signals supplied from the input terminal Input to the first output node Q1 and the second output node Q2, respectively, at different timings. For example, at a first time, the shunt circuit 100 outputs an input signal to the first output node Q1 in response to the control signal and maintains the output for a predetermined time; thereafter, at a second time, the shunt circuit 100 is responsive to the control signal Outputting the input signal to the second output node Q2 and maintaining the output for a predetermined time; thereafter, at the third time, the shunt circuit 100 outputs the input signal to the first output node Q1 in response to the control signal, and is scheduled This output is maintained for a while.
  • the shunt circuit 100 cyclically outputs the input signal to the first output node Q1 and the second output node Q2 in this manner.
  • the first buffer circuit 210 buffers and outputs the input signal received by the first output node Q1 to the first output terminal Out1
  • the second buffer circuit 220 buffers and outputs the input signal received by the second output node Q2 to the second output terminal Out2.
  • the input signal is decomposed into two sub-signals, and the frequency of the sub-signal is half the frequency of the input signal, i.e., the period of the sub-signal is twice the period of the input signal.
  • the sub-signal is supplied to the pixel unit of the display panel as a display data signal, and the pixel circuit in the pixel unit is compensated or charged in response to the gate scan signal and under the action of the display data signal, so that the pixel circuit can be compensated
  • the time is extended to twice the original compensation time, which makes the data voltage writing more complete, thereby improving the display quality.
  • the amount of extension of the compensation time is related to the frequency of the input signal and the number of output nodes and buffer circuits.
  • the number of output nodes and buffer circuits can be set according to actual needs, so that the amount of compensation time is extended to meet the demand.
  • FIG. 3 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • the signal processing circuit 10 is substantially identical to the signal processing circuit 10 depicted in FIG. 1 except that it further includes N reset circuits 300.
  • the N reset circuits 300 are respectively connected to the N output nodes, and are configured to reset the N output nodes in response to the reset signal provided by the reset signal line (the reset signal terminal RST) (that is, to N caches) Circuit 200 is reset).
  • the reset circuit 300_1 is connected to the reset signal terminal RST and the first output node Q1
  • the reset circuit 300_2 is connected to the reset signal terminal RST and the second output node Q2, and so on.
  • the number of reset circuits 300 is not limited and may be determined according to the number of output nodes and cache circuits 200.
  • the number of reset circuits 300 is equal to the number of output nodes and buffer circuits 200, and each reset circuit 300 resets the buffer circuit 200 connected thereto.
  • the scanning timing of each frame of image includes blank time and effective time.
  • the pixel circuit of the pixel unit scans line by line to display an image; during the blank time, the pixel circuit does not perform a scanning operation.
  • the reset circuit 300 resets each of the buffer circuits 200 at blank time so that the display data signals of the next frame image are more accurately and faster buffered into the respective buffer circuits 200, thereby improving display quality.
  • the reset circuit 300 may reset each buffer circuit 200 before or after the start of scanning of each frame image, and the reset circuit 300 may also correspond to a specific time (for example, before data writing of each row of pixel units).
  • the cache circuit 200 performs a reset.
  • FIG. 4 is a schematic block diagram of another signal processing circuit according to an embodiment of the present disclosure.
  • the signal processing circuit 10 of this embodiment is substantially identical to the signal processing circuit 10 depicted in FIG. 2 except that the first reset circuit 310 and the second reset circuit 320 are further included.
  • the first reset circuit 310 is coupled to the first output node Q1 and is configured to reset the first buffer circuit 210 in response to a reset signal provided by the reset signal line (reset signal terminal RST).
  • the second reset circuit 320 is connected to the second output node Q2 and configured to reset the second buffer circuit 220 in response to a reset signal provided by the reset signal line (the reset signal terminal RST).
  • the first end 311 of the first reset circuit 310 is configured to be connected to the first output node Q1
  • the second end 312 of the first reset circuit 310 is configured to be connected to the second voltage terminal VSS to receive the second voltage
  • the first reset The control terminal 313 of the circuit 310 is configured to be connected to a reset signal line (reset signal terminal RST) to receive a reset signal.
  • the first end 321 of the second reset circuit 320 is configured to be connected to the second output node Q2, and the second end 322 of the second reset circuit 320 is configured to be connected to the second voltage terminal VSS to receive the second voltage, and the second reset circuit 320
  • the control terminal 323 is configured to be connected to a reset signal line (reset signal terminal RST) to receive a reset signal.
  • the second voltage terminal VSS provides a DC low level signal (eg, ground), the DC low level signal is referred to as a second voltage and acts as a reset voltage; or the second voltage terminal VSS can also provide a DC high level signal
  • the second voltage terminal VSS is equal to the first voltage terminal VDC.
  • the first reset circuit 310 electrically connects the second voltage terminal VSS and the first output node Q1
  • the second reset circuit 320 electrically connects the second voltage terminal VSS and the second output node Q2, thereby
  • the first output node Q1, the first buffer circuit 210, the second output node Q2, and the second buffer circuit 220 are reset.
  • resetting can be performed before or after the start of scanning of each frame of image.
  • the embodiments of the present disclosure are not limited thereto, and may be reset at a specific time according to actual needs, for example, before the corresponding cache circuit caches data.
  • the input signal e.g., display data signal
  • the input signal can be more accurately and quickly buffered into the first buffer circuit 210 and the second buffer circuit 220, thereby improving display quality.
  • FIG. 5 is a schematic block diagram of a shunt circuit of a signal processing circuit according to an embodiment of the present disclosure.
  • the shunt circuit 100 includes an input terminal Input, a first input control terminal MxO, a second input control terminal MxE, a first switching circuit 110, and a second switching circuit 120.
  • the first switch circuit 110 is connected to the input terminal Input, the first output node Q1 and the first input control terminal MxO, and configured to receive the input from the input terminal Input in response to the first control signal received from the first input control terminal MxO.
  • the signal is output to the first output node Q1.
  • the second switch circuit 120 is coupled to the input terminal Input, the second output node Q2, and the second input control terminal MxE, and configured to receive an input from the input terminal Input in response to the second control signal received from the second input control terminal MxE. The signal is output to the second output node Q2.
  • the first switching circuit 110 When the first control signal is at an active level (ie, a level at which the first switching circuit 110 can be turned on), the first switching circuit 110 electrically connects the first output node Q1 and the input terminal Input, thereby outputting the input signal to The first output node Q1.
  • the second control signal When the second control signal is at an active level (ie, a level at which the second switch circuit 120 can be turned on), the second switch circuit 120 electrically connects the second output node Q2 and the input terminal Input, thereby outputting the input signal to The second output node Q2.
  • the first control signal and the second control signal alternate to an active level such that the input signal is alternately output to the first output node Q1 and the second output node Q2.
  • the number of switch circuits is not limited and may be determined according to actual needs.
  • two switching circuits (the first switching circuit 110 and the second switching circuit 120) will be described as an example.
  • the shunt circuit 100 includes N switch circuits, and correspondingly, the input control terminal and the output node are also N, respectively, and N switch circuits are connected to the input terminal Input, and respectively, and N output nodes.
  • N input control terminals are connected one by one.
  • N is an integer greater than or equal to 2.
  • FIG. 6 is a schematic block diagram of a shunt circuit of another signal processing circuit according to an embodiment of the present disclosure.
  • the shunt circuit 100 of this embodiment is substantially identical to the shunt circuit 100 depicted in FIG. 5 except that the input control terminals are connected differently and further include the inverter circuit 130.
  • the first input control terminal MxO and the second input control terminal MxE are connected to each other and to the same input control line (input control terminal Mx) to receive the same control signal.
  • the second switching circuit 120 is connected to the second input control terminal MxE through the inverter circuit 130. That is, the control signal received by the second switching circuit 120 and the control signal received by the first switching circuit 110 are inverted from each other, thereby achieving alternate control of the first switching circuit 110 and the second switching circuit 120.
  • the first switching circuit 110 when the control signals of the first input control terminal MxO and the second input control terminal MxE are active levels (even if the first switching circuit 110 is turned on), the first switching circuit 110 will be the first output node Q1 and The input terminal is electrically connected, and at this time, the control signal received by the second switch circuit 120 is an inactive level (even if the second switch circuit 120 is turned off) by the action of the inverter circuit 130, thereby making the second output node Q2 is disconnected from the input Input.
  • the control signals of the first input control terminal MxO and the second input control terminal MxE are inactive levels, the first switching circuit 110 turns off the first output node Q1 and the input terminal Input, and at this time, through the function of the inverter circuit 130.
  • the control signal received by the second switch circuit 120 is an active level, thereby electrically connecting the second output node Q2 and the input terminal Input.
  • the alternate control of the first switching circuit 110 and the second switching circuit 120 is realized by using one control signal, which can simplify the control mode of the circuit, reduce the number of signals, and avoid mutual interference between signals, thereby enhancing Signal isolation of the first output node Q1 and the second output node Q2.
  • the manner of setting the inverter circuit 130 is not limited, and the inverter circuit 130 may be connected to any one of the first switch circuit 110 and the second switch circuit 120. Depending on the actual needs, for example, depending on the matching relationship between the control signal and the switching circuit.
  • Fig. 7 is a circuit diagram showing a specific implementation example of the signal processing circuit shown in Fig. 2.
  • each transistor is a P-type transistor as an example, but this does not constitute a limitation on the embodiment of the present disclosure.
  • the signal processing circuit 10 includes a first transistor T1, a second transistor T2, a first capacitor C1, and a second capacitor C2.
  • the shunt circuit 100 includes a first switching circuit 110 and a second switching circuit 120.
  • the first switching circuit 110 can be implemented as a first transistor T1
  • the first transistor T1 functions as a switching transistor.
  • the gate of the first transistor T1 is connected to the first input control terminal MxO
  • the first electrode of the first transistor T1 is connected to the input terminal Input
  • the second electrode of the first transistor T1 is connected to the first output node Q1.
  • the second switching circuit 120 can be implemented as a second transistor T2 as a switching transistor.
  • the gate of the second transistor T2 is connected to the second input control terminal MxE, the first electrode of the second transistor T2 is connected to the input terminal Input, and the second electrode of the second transistor T2 is connected to the second output node Q2.
  • the first control signal provided by the first input control terminal MxO and the second control signal provided by the second input control terminal MxE alternate to an active level, the first transistor T1 and the second transistor T2 are alternately turned on, thereby making the input terminal Input
  • the input signals are alternately output to the first output node Q1 and the second output node Q2.
  • the first buffer circuit 210 can be implemented as a first capacitor C1.
  • the first pole of the first capacitor C1 is connected to the first output node Q1 as the first end 211 of the first buffer circuit 210, and the second pole 212 of the first capacitor C1 is connected to the first end 212 of the first buffer circuit 210. Voltage terminal VDC.
  • the first capacitor C1 can buffer the input signal received by the first output node Q1 and output the input signal to the first output terminal Out1.
  • the second buffer circuit 220 can be implemented as a second capacitor C2.
  • the first pole of the second capacitor C2 is connected to the second output node Q2 as the first end 221 of the second buffer circuit 220, and the second pole 222 of the second capacitor C2 is connected to the first terminal 222 of the second buffer circuit 220. Voltage terminal VDC.
  • the second capacitor C2 can buffer the input signal received by the second output node Q2 and output the input signal to the second output terminal Out2.
  • the buffer circuit 200 can be implemented as a circuit structure as shown in FIG. 8 due to the influence of the wiring.
  • the first cache circuit 210 is taken as an example for description.
  • the first buffer circuit 210 includes a first sub-capacitor C11, a second sub-capacitor C12, and a resistor R.
  • the first pole of the first sub-capacitor C11 is connected to the first sub-node Q11, and the second pole of the first sub-capacitor C11 is connected to the first voltage terminal VDC.
  • the first pole of the second sub-capacitor C12 is connected to the second sub-node Q12, and the second pole of the second sub-capacitor C12 is connected to the first voltage terminal VDC.
  • the first pole of the resistor R is connected to the first sub-node Q11, and the second pole of the resistor R is connected to the second sub-node Q12.
  • the shunt circuit 100 outputs an input signal to the first sub-node Q11 in response to the control signal, and the first buffer circuit 210 buffers the input signal and outputs it to the first output terminal Out1 through the second sub-node Q12.
  • the first sub-capacitor C11 is a capacitor device fabricated on a display panel by a process, for example, by fabricating a special capacitor electrode, which can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like.
  • the second sub-capacitor C12 is a parasitic capacitance between data lines in the display panel, and can be realized by the data line itself and other devices and lines.
  • the resistance R is the resistance of the data line itself in the display panel, and is not the actual resistance device.
  • the capacitance values of the parasitic capacitances (second sub-capacitors C12) in the respective buffer circuits 200 may be the same or different, which is related to the wiring manner of the data lines in the display panel. Therefore, in order to ensure that the reference signals of the output signals of the respective buffer circuits 200 are consistent, the capacitance values of the first sub-capacitors C11 in the respective buffer circuits 200 are adjusted according to the capacitance values of the corresponding parasitic capacitances, that is, the first in each of the buffer circuits 200.
  • the capacitance value of the sub-capacitor C11 may be the same or different.
  • the parasitic capacitance in the buffer circuit 200 satisfies the requirement of the capacitance value, so the first sub-capacitor C11 can be omitted, and the input signal can be cached only by the parasitic capacitance.
  • there is no specially fabricated capacitor device in the buffer circuit 200 which does not need to be fabricated by a process, thereby reducing costs and improving production efficiency.
  • FIG. 9 is a circuit diagram showing a specific implementation example of the signal processing circuit shown in FIG.
  • the signal processing circuit 10 of this embodiment is substantially the same as the signal processing circuit 10 described in FIG. 7, except that the third transistor T3 and the fourth transistor T4 are further included.
  • the first reset circuit 310 can be implemented as a third transistor T3, and the third transistor T3 acts as a reset transistor.
  • the first pole of the third transistor T3 is connected as a first end 311 of the first reset circuit 310 to the first output node Q1, and the second pole of the third transistor T3 is connected as a second end 312 of the first reset circuit 310 to the second The voltage terminal VSS, the gate of the third transistor T3 is connected as a control terminal 313 of the first reset circuit 310 to the reset signal line (reset signal terminal RST).
  • the third transistor T3 is turned on when the reset signal is at an active level, and electrically connects the first output node Q1 and the second voltage terminal VSS, so that the first buffer circuit 210 (first capacitor C1) can be reset.
  • the second reset circuit 320 can be implemented as a fourth transistor T4, which functions as a reset transistor.
  • the first pole of the fourth transistor T4 is connected as a first end 321 of the second reset circuit 320 to the second output node Q2, and the second pole of the fourth transistor T4 is connected as a second end 322 of the second reset circuit 320 to the second The voltage terminal VSS, the gate of the fourth transistor T4 is connected as a control terminal 323 of the second reset circuit 320 to the reset signal line (reset signal terminal RST).
  • the fourth transistor T4 is turned on when the reset signal is at an active level, and electrically connects the second output node Q2 and the second voltage terminal VSS, so that the second buffer circuit 220 (second capacitor C2) can be reset.
  • Fig. 10A is a circuit diagram showing a specific implementation example of the shunt circuit of the signal processing circuit shown in Fig. 6.
  • the first shunt circuit 110 and the second shunt circuit 120 in the shunt circuit 100 are substantially the same as those described in FIG. 7, and are not described herein again.
  • the inverter circuit 130 may be implemented as a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is connected to the gate of the sixth transistor T6 and is connected to the second input control terminal MxE, and the first electrode of the fifth transistor T5 is connected to the third voltage terminal VDD to receive the third voltage, the fifth transistor
  • the second pole of T5 is connected to the first pole of the sixth transistor T6 and is connected to the gate of the second transistor T2, and the second pole of the sixth transistor T6 is connected to the second voltage terminal VSS.
  • the first input control terminal MxO and the second input control terminal MxE are connected to each other and to the same input control line (input control terminal Mx) to receive the same control signal.
  • the third voltage terminal VDD provides a DC high level signal
  • the DC high level signal is referred to as a third voltage.
  • the first transistor T1 when the control signals of the first input control terminal MxO and the second input control terminal MxE are at a low level, the first transistor T1 is turned on. At this time, the fifth transistor T5 is also turned on to electrically connect the third voltage terminal VDD and the gate of the second transistor T2, so that the gate of the second transistor T2 receives the high level signal, and the second transistor T2 is turned off. It should be noted that the sixth transistor T6 is an N-type transistor, and at this time, the sixth transistor T6 is turned off.
  • the first transistor T1 When the control signals of the first input control terminal MxO and the second input control terminal MxE are at a high level, the first transistor T1 is turned off. At this time, the sixth transistor T6 is turned on to electrically connect the second voltage terminal VSS and the gate of the second transistor T2, so that the gate of the second transistor T2 receives the low level signal, and the second transistor T2 is turned on. At this time, the fifth transistor T5 is turned off.
  • Fig. 10B is a circuit diagram showing another specific implementation example of the shunt circuit of the signal processing circuit shown in Fig. 6.
  • the first shunt circuit 110 and the second shunt circuit 120 in the shunt circuit 100 are respectively different types of transistors.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type. Transistor.
  • the first input control terminal MxO and the second input control terminal MxE are connected to each other and to the same input control line (input control terminal Mx) to receive the same control signal.
  • the control signal is low level
  • the first transistor T1 is turned on, and the second transistor T2 is turned off; when the control signal is high level, the first transistor T1 is turned off, and the second transistor T2 is turned on.
  • the control signals of the first input control terminal MxO and the second input control terminal MxE can be inversely transformed, and the control of the first transistor T1 and the second transistor T2 can be realized by using only one control signal.
  • the control mode of the circuit is simplified, the number of signals is reduced, the mutual interference between the signals is avoided, and the signal isolation of the first output node Q1 and the second output node Q2 is enhanced.
  • the N output nodes (Q1, Q2, . . . , QN) do not represent actual components, but represent the convergence points of the relevant electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor, a field effect transistor, or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking a P-type transistor as an example.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the signal processing circuit 10 provided by the embodiments of the present disclosure may also adopt an N-type transistor.
  • the first pole of the transistor is a drain and the second pole is a source, and only needs to be selected.
  • the respective poles of the transistor of the type may be connected in accordance with the respective poles of the respective transistors in the embodiment of the present disclosure.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS low temperature polysilicon
  • amorphous silicon for example, hydrogenation non-hydrogenation
  • FIG. 11 is a timing diagram of signals of a signal processing circuit according to an embodiment of the present disclosure.
  • the working principle of the signal processing circuit 10 shown in FIG. 7 will be described below with reference to the signal timing diagram shown in FIG. 11.
  • the description will be made by taking each transistor as a P-type transistor as an example, but the embodiment of the present disclosure is not limited thereto. .
  • a control signal (provided by the first input control terminal MxO and the second input control terminal MxE) and an input signal (provided by the input terminal Input) are provided, so that the shunt circuit 100 sequentially inputs the input signal in response to the control signal.
  • the signals are output to the two output nodes (the first output node Q1 and the second output node Q2) at two different times, and the input signal received by the first output node Q1 is buffered and output to the first by the first buffer circuit 210.
  • the output terminal Out1 buffers the input signal received by the second output node Q2 by the second buffer circuit 220 and outputs it to the second output terminal Out2.
  • the signal processing circuit 10 can perform the following operations, respectively.
  • the first input control terminal MxO provides a low level signal, and the first transistor T1 is turned on, so that the input signal at the moment is output to the first output node Q1.
  • the input signal at this moment is the first data data1.
  • the first capacitor C1 buffers the first data data1 and can output the first data data1 within a predetermined time.
  • the second input control terminal MxE provides a high level signal, the second transistor T2 is turned off, and the second output node Q2 holds the signal of the previous stage or the signal after the reset.
  • the second input control terminal MxE provides a low level signal, and the second transistor T2 is turned on, so that the input signal at that moment is output to the second output node Q2.
  • the input signal at this moment is the second data data2.
  • the second capacitor C2 buffers the second data data2 and can output the second data data2 within a predetermined time.
  • the first input control terminal MxO provides a high level signal, the first transistor T1 is turned off, and the first output node Q1 holds the signal of the previous stage (ie, the first data data1) or the signal after being reset.
  • the first transistor T1 and the second transistor T2 alternately output the input signals to the first output node Q1 and the second output.
  • Node Q2 thereby decomposing the input signal into 2-way sub-signals, and the signal frequencies of the first output node Q1 and the second output node Q2 are half of the frequency of the input signal, that is, the signals of the first output node Q1 and the second output node Q2 The period is twice the period of the input signal.
  • the signals of the first output node Q1 and the second output node Q2 are supplied to the pixel unit of the display panel as a display data signal, and the pixel circuit in the pixel unit is responsive to the gate scan signal and compensated according to the display data signal or Charging, so that the compensation time of the pixel circuit can be extended to twice the original compensation time, so that the data voltage is written more fully, thereby improving the display quality.
  • the signals of the first output node Q1 and the second output node Q2 are 60 Hz, respectively.
  • the compensation time of the conventional pixel circuit is 3.3 ⁇ s.
  • the frequency of the display data signal supplied from the signal processing circuit 10 to the pixel unit is 60 Hz, so the compensation time is 6.5 ⁇ s, and the compensation time is prolonged.
  • an input signal eg, a display data signal
  • the input signal can be 120 Hz, 90 Hz, 60 Hz, or other suitable frequency to accommodate conventional high update rate screens, AR/VR displays, and the like.
  • the amount of compensation time can be adjusted according to the demand.
  • the input signal is 120 Hz and the output node is three, and the signal frequency of each output node is 40 Hz to further extend the compensation time.
  • FIG. 12 is a timing diagram of signals of another signal processing circuit according to an embodiment of the present disclosure. Next, the operation principle of the signal processing circuit 10 shown in FIG. 9 in the reset phase 0 will be described with reference to the signal timing chart shown in FIG.
  • the reset signal terminal RST provides a low level signal
  • the third transistor T3 and the fourth transistor T4 are both turned on, so that the first output node Q1 and the second output node Q2 are electrically connected to the second voltage terminal VSS, respectively.
  • the first capacitor C1 and the second capacitor C2 are reset, so that the signals of the first output node Q1 and the second output node Q2 are at a low level.
  • both the first input control terminal MxO and the second input control terminal MxE provide a high level signal to turn off both the first transistor T1 and the second transistor T2.
  • an input signal for example, a display data signal
  • it may be reset before or after the start of scanning of each frame of image, or may be reset at a specific time according to actual needs.
  • an input signal for example, a display data signal
  • an input signal can be more accurately buffered into the first capacitor C1 and the second capacitor C2, thereby improving display quality.
  • At least one embodiment of the present disclosure further provides a display panel including the signal processing circuit and the plurality of data lines according to any of the embodiments of the present disclosure.
  • N of the plurality of data lines are respectively connected to N buffer circuits of the signal processing circuit, and the input signal is a display data signal.
  • the display panel can extend the compensation time of the pixel circuit and is compatible with the existing pixel circuit and the driving chip, and can solve the problem that the compensation time of the pixel circuit in the high update rate screen is insufficient, and the display quality is improved.
  • FIG. 13 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 20 includes an array substrate 500, a plurality of signal processing circuits 10, a plurality of data lines 510, and a plurality of pixel units P distributed in an array.
  • the signal processing circuit 10, the data line 510, and the pixel unit P are all disposed on the array substrate 500.
  • the signal processing circuit 10 is a signal processing circuit according to any of the embodiments of the present disclosure.
  • the array substrate 500 includes a display area and a peripheral area, a plurality of pixel units P are disposed in the display area, and a plurality of signal processing circuits 10 are disposed in the peripheral area.
  • the N data lines of the plurality of data lines 510 are respectively connected to the N cache circuits of the signal processing circuit 10.
  • the N data lines 510 connected to the signal processing circuit 10 are connected to the same column of pixel units P.
  • the same column of pixel units P includes N pixel unit groups, each of which is connected to the same data line 510.
  • the pixel units P in the N pixel unit groups are alternately arranged in the column direction.
  • the number of signal processing circuits 10 is equal to the number of columns of pixel units P
  • the number of data lines 510 is equal to N times the number of signal processing circuits 10.
  • the same column of pixel units P refers to a plurality of pixel units of the same signal processing circuit 10, and does not limit the center of the same column of pixel units P on the same straight line (a straight line extending in the column direction).
  • the centers of the pixel units of different pixel unit groups of the same column of pixel units P may be staggered in the row direction (for example, the line of the center of the pixel unit of the different pixel unit group of the same column of pixel units P) Set apart from each other).
  • the centers of the pixel units P of the same column may also be on the same straight line.
  • N is equal to 2
  • the two data lines 510 connected to the same signal processing circuit 10 include a first data line 511 and a second data line 512.
  • the first data line 511 is connected to the first buffer circuit 210
  • the second data line 512 is connected to the second buffer circuit 220.
  • the first data line 511 and the second data line 512 are connected to the same column of pixel units P.
  • the same column of pixel units P includes two pixel unit groups, that is, a first pixel unit group and a second pixel unit group.
  • the first pixel unit group includes pixel units P located in odd rows
  • the second pixel unit group includes pixel units P located in even rows.
  • the signal processing circuit 10 is also connected to the data driving circuit 400 and the control circuit (for example, the timing controller T-CON) 600 disposed outside the array substrate 500 through the lead D1 or the like to receive the input signals from the data driving circuit 400, respectively.
  • a control signal is received from control circuit 600.
  • the above input signal is a display data signal.
  • the data driving circuit 400 is configured to provide a display data signal to each column of pixel units P.
  • the data driving circuit 400 can be a driver chip or a data driver.
  • the data driving circuit 400 supplies the display data signals supplied to the respective column pixel units P to the signal processing circuits 10 correspondingly connected to the respective column pixel units P, respectively.
  • the control circuit 600 is configured to provide a control signal to the signal processing circuit 10, for example, to provide two control signals to the first input control terminal MxO and the second input control terminal MxE, respectively.
  • the first input control terminals MxO of the plurality of signal processing circuits 10 are connected to the same signal line to receive the same first control signal
  • the second input control terminals MxE of the plurality of signal processing circuits 10 are connected to the same signal line. Receiving the same second control signal.
  • the control circuit 600 can also be disposed on the array substrate 500 or integrated into the data driving circuit 400.
  • the number of output ports of the data driving circuit 400 may be equal to the number of the signal processing circuits 10 and the number of columns of the pixel units P, that is, the number of output ports of the data driving circuit 400 of the display panel provided by the embodiment of the present disclosure.
  • the number of ports of the data driving circuit is kept constant compared to the conventional display panel. Therefore, the display panel provided by the embodiment of the present disclosure can adopt an existing data driving circuit (for example, a driving chip), thereby reducing the design cost and the manufacturing cost of the panel.
  • the signal processing circuit 10 may also be disposed outside the array substrate 500 according to actual application requirements.
  • the signal processing circuit 10 may be integrated in the data driving circuit 400, for example, to increase the number of output ports of the data driving circuit 400.
  • the N data lines 510 connected to the same signal processing circuit 10 are located at different layers of the array substrate 500.
  • N is equal to 2
  • the first data line 511 and the second data line 512 are located at different layers of the array substrate 500.
  • This arrangement reduces signal interference between data lines and does not increase the process difficulty of the array substrate, helping to achieve high pixel density (Pixels Per Inch, PPI).
  • a first data line 511 is formed on a data line layer of a conventional array substrate, and an insulating layer and a metal layer are added, and a second data line 512 is formed in the metal layer. In this way, the signal interference between the first data line 511 and the second data line 512 can be effectively reduced, and the original data line layer manufacturing process is not affected.
  • the relative positional relationship of the N data lines 510 is not limited, and the N data lines 510 may be located in different layers, or some of the N data lines 510 may be located. Located on different floors.
  • the upper and lower stacking relationships of the N data lines 510 are not limited and may be determined according to the actual wiring manner of the display panel.
  • the N data lines 510 can also be disposed on the same layer, which can simplify the manufacturing process and reduce the thickness of the panel.
  • the display panel 20 further includes a gate driving circuit 700, and the plurality of pixel units P are connected to the gate driving circuit 700.
  • the gate drive circuit 700 is configured to provide a plurality of gate scan signals to perform line scan on the pixel cells P of the display panel 20.
  • the number of gate drive circuits 700 is not limited and may be determined according to actual needs.
  • the display panel 20 includes two gate drive circuits 700 that are respectively disposed on both sides of the display panel 20 to achieve bilateral driving.
  • the gate driving circuit 700 disposed on one side of the display panel 20 is configured to drive odd-numbered gate lines
  • the gate driving circuit 700 disposed on the other side of the display panel 20 is configured to drive even-numbered gate lines.
  • the manner of setting the gate driving circuit 700 is not limited, and may be determined according to actual needs.
  • the gate driving circuit 700 may be a gate driver disposed outside the array substrate 500.
  • the gate driving circuit 700 may also be disposed on the array substrate 500 to constitute a Gate-driver On Array, thereby reducing the number of leads of the display panel 20 and other components.
  • the pulse times (ie, pulse durations) of the gate scan signals of adjacent rows partially overlap, that is, the M+1th row
  • the pulse time of the gate scan signal partially overlaps with the pulse time of the gate scan signal of the Mth row, and M is an integer greater than zero.
  • the pixel unit P includes a pixel circuit
  • the pixel circuit can be implemented, for example, as a 7T1C type pixel circuit, a 6T1C type pixel circuit, a 5T2C type pixel circuit, or other pixel circuit having a threshold compensation function illustrated in FIG. 15A.
  • the gate control terminal GAT of the pixel circuit shown in FIG. 15A may be connected to the gate driving circuit 700 via a gate line
  • the data signal receiving terminal DAT of the pixel circuit may be connected to the signal processing circuit 10 and the data driving circuit 400 via the data line.
  • FIG. 14 is a timing diagram of signals of a display panel according to an embodiment of the present disclosure.
  • the operation principle of the display panel 20 shown in FIG. 13 will be described with reference to the signal timing chart shown in FIG.
  • the operation principle of the signal processing circuit 10 in the display panel 20 is similar to that of the signal processing circuit 10 shown in FIG. 7, and will not be described herein.
  • the signal processing circuit 10 outputs the display data signals from the data driving circuit 400 to the first output node Q1 and the second output node Q2, respectively, under the control of the control signal, the first buffer The circuit 210 and the second buffer circuit 220 respectively buffer the display data signals received from the lead D1 and output them to the first data line 511 (DO1) and the second data line 512 (DE1).
  • the first data line 511 supplies the signal of the first output node Q1 to the first pixel unit group (the pixel unit P located in the odd row), and the second data line 512 provides the signal of the second output node Q2 to the second pixel unit group. (Pixel unit P in even rows).
  • the display data signals are alternately supplied to the first pixel unit group and the second pixel unit group in this manner.
  • the gate driving circuit 700 provides a plurality of gate scan signals (G1, G2, G3, etc.) to perform line scanning on the plurality of pixel cells P.
  • the first row of gate scan signals G1 eg, the gate scan signals supplied to the first row of pixel cells
  • the first row of gate scan signals G1 is at a low level, causing the first row of pixel cells P to be turned on, and Compensation or charging is performed by the display data signal supplied from the first data line 511 (DO1).
  • the second row of gate scan signals G2 (eg, the gate scan signals supplied to the second row of pixel cells) is at a low level, causing the second row of pixel cells P to be turned on, and Compensation or charging is performed by the display data signal provided by the second data line 512 (DE1).
  • the pixel unit P located in the odd rows and the pixel unit P located in the even rows are compensated or charged in this manner, respectively.
  • the pulse time t1 of the gate scan signal is equal to twice the period t2 of the display data signal to maximize the compensation time or charging time.
  • the pulse time of the gate scan signal of the M+1th row partially overlaps with the pulse time of the gate scan signal of the Mth row, and the overlap time is t3.
  • the overlap time t3 is equal to the display data signal period t2, that is, the overlap time t3 is equal to 1/2 of the pulse time t1. In this manner, the compensation time of the pixel circuit in the pixel unit P is extended to twice the original compensation time.
  • the overlap time t3 is (N-1)/N of the pulse time t1, thereby prolonging the compensation time of the pixel circuit in the pixel unit P to N times the original compensation time.
  • the pulse time of the gate scan signal is equal to N times of the period of the display data signal provided by the data driving circuit 400; due to the signal buffer function of the buffer circuit, the pixel unit can continuously receive the display data signal during the pulse time of the gate scan signal, That is, the compensation time available for the pixel unit is N times the period of the display data signal, whereby the compensation effect of the pixel circuit of the pixel unit P can be improved, and the brightness uniformity of the display panel can be improved.
  • At least one embodiment of the present disclosure further provides a display device including the signal processing circuit 10 of any of the embodiments of the present disclosure or the display panel 20 of any of the embodiments of the present disclosure.
  • the display device can extend the compensation time of the pixel circuit and is compatible with the existing pixel circuit and the driving chip, and can solve the problem that the compensation time of the pixel circuit in the high update rate screen is insufficient, and the display quality is improved.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure also provides a driving method of a signal processing circuit, which can be used to drive the signal processing circuit 10 of any of the embodiments of the present disclosure.
  • the driving method By using the driving method, the compensation time of the pixel circuit can be prolonged, and the existing pixel circuit and the driving chip are compatible, which can solve the problem that the compensation time of the pixel circuit in the high update rate screen is insufficient, and the display quality is improved.
  • the driving method of the signal processing circuit includes the operation of providing a control signal and an input signal such that the shunt circuit 100 sequentially outputs the input signal to the N output nodes at N different times in response to the control signal. And the input signal is buffered and output by the buffer circuit 200, and N is an integer greater than or equal to 2.
  • At least one embodiment of the present disclosure further provides a driving method of a display panel, which can be used to drive the display panel 20 according to any embodiment of the present disclosure.
  • the driving method By using the driving method, the compensation time of the pixel circuit can be prolonged, and the existing pixel circuit and the driving chip are compatible, which can solve the problem that the compensation time of the pixel circuit in the high update rate screen is insufficient, and the display quality is improved.
  • the driving method of the display panel includes the following operations:
  • the control signal and the display data signal are provided, so that the shunt circuit 100 sequentially outputs the display data signal to the N output nodes at N different times in response to the control signal, and the display data signal is buffered and outputted by the buffer circuit 200 to the corresponding N data lines 510, N is an integer greater than or equal to 2.
  • the driving method of the display panel further includes: providing a gate scan signal to perform line scan on the display panel 20, and pulse times of adjacent gate scan signals partially overlap each other.

Abstract

一种信号处理电路(10)及其驱动方法、显示面板(20)及其驱动方法及显示装置，该信号处理电路(10)包括分路电路(100)和N个缓存电路(200)，分路电路(100)包括N个输出节点(Q1, Q2 … QN)，N个缓存电路(200)与N个输出节点(Q1, Q2 … QN)分别连接，分路电路(100)配置为响应于控制信号将输入信号在N个不同时刻分别输出到N个输出节点(Q1, Q2 … QN)，N个缓存电路(200)的每个配置为将对应的输出节点(Q1, Q2 … QN)接收的输入信号缓存并输出，N为大于等于2的整数，信号处理电路(10)可以延长显示面板(20)中像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。

Description

信号处理电路及其驱动方法、显示面板及其驱动方法及显示装置
本申请要求于2018年4月16日递交的中国专利申请第201810338993.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种信号处理电路及其驱动方法、显示面板及其驱动方法及显示装置。
背景技术
随着显示技术的发展，各种显示屏得到了越来越广泛的应用。这些显示屏能为用户提供丰富多彩的画面和良好的视觉体验。显示屏主要包括液晶显示(Liquid Crystal Display,LCD)屏和有机发光二极管显示(Organic Light-Emitting Diode,OLED)屏，可以应用于手机、电视机、笔记本电脑、数码相机、仪器仪表、虚拟现实(Virtual Reality,VR)设备、增强现实(Augmented Reality,AR)设备等具有显示功能的电子装置中。
发明内容
本公开至少一个实施例提供一种信号处理电路，包括：分路电路，包括N个输出节点；N个缓存电路，与所述N个输出节点分别连接；其中，所述分路电路配置为响应于控制信号将输入信号在N个不同时刻分别输出到所述N个输出节点；所述N个缓存电路的每个配置为将对应的输出节点接收的所述输入信号缓存并输出；N为大于等于2的整数。
例如，在本公开一实施例提供的信号处理电路中，所述N个缓存电路的每个的第一端配置为和与之对应的所述输出节点连接，所述N个缓存电路的每个的第二端配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的信号处理电路中，所述N个缓存电路的每个包括电容，所述电容的第一极作为所述缓存电路的第一端，所述电容的 第二极作为所述缓存电路的第二端。
例如，在本公开一实施例提供的信号处理电路包括N个复位电路，其中，所述N个复位电路与所述N个输出节点分别连接，配置为响应于复位信号对所述N个输出节点复位。
例如，在本公开一实施例提供的信号处理电路中，所述N个复位电路的每个的控制端配置为和复位信号线连接以接收所述复位信号，所述N个复位电路的每个的第一端配置为和对应的所述输出节点连接，所述N个复位电路的每个的第二端配置为和第二电压端连接以接收第二电压。
例如，在本公开一实施例提供的信号处理电路中，所述N个复位电路的每个包括复位晶体管，所述复位晶体管的栅极作为所述复位电路的控制端，所述复位晶体管的第一极作为所述复位电路的第一端，所述复位晶体管的第二极作为所述复位电路的第二端。
例如，在本公开一实施例提供的信号处理电路中，所述分路电路还包括输入端、N个输入控制端以及N个开关电路，所述N个开关电路与所述输入端连接，且分别与所述N个输出节点以及所述N个输入控制端一一对应连接，所述N个开关电路的每个配置为响应于从对应的所述输入控制端接收的所述控制信号，将从所述输入端接收的所述输入信号输出到对应的所述输出节点。
例如，在本公开一实施例提供的信号处理电路中，所述N个开关电路的每个包括开关晶体管，所述开关晶体管的栅极连接到对应的所述输入控制端，所述开关晶体管的第一极连接到所述输入端，所述开关晶体管的第二极连接到对应的所述输出节点。
例如，在本公开一实施例提供的信号处理电路中，N等于2，且所述N个输入控制端彼此连接以连接到相同的输入控制线。
例如，在本公开一实施例提供的信号处理电路中，所述N个开关电路包括第一开关电路和第二开关电路，所述分路电路还包括反相电路，所述第一开关电路和所述第二开关电路其中之一通过所述反相电路与所述N个输入控制端连接。
本公开至少一个实施例还提供一种显示面板，包括本公开任一实施例所述的信号处理电路和多条数据线，其中，所述多条数据线中的N条数据线分别连接到所述信号处理电路的N个缓存电路，所述输入信号为显示数据信号。
例如，在本公开一实施例提供的显示面板包括呈阵列分布的多个像素单元，其中，与所述信号处理电路连接的N条数据线连接到同一列像素单元，所述同一列像素单元包括N个像素单元组，每个像素单元组连接到同一条数据线。
例如，在本公开一实施例提供的显示面板中，N等于2，所述N个像素单元组包括第一像素单元组和第二像素单元组，所述第一像素单元组包括位于奇数行的像素单元，所述第二像素单元组包括位于偶数行的像素单元。
例如，在本公开一实施例提供的显示面板包括阵列基板，其中，所述信号处理电路设置在所述阵列基板上。
例如，在本公开一实施例提供的显示面板中，连接到同一个信号处理电路的N条数据线位于所述阵列基板的不同层。
例如，在本公开一实施例提供的显示面板包括至少一个栅极驱动电路，其中，所述栅极驱动电路配置为提供多个栅极扫描信号以对所述显示面板的像素单元进行行扫描，第M+1行的栅极扫描信号的脉冲持续时间与第M行的栅极扫描信号的脉冲持续时间部分重叠，M为大于0的整数。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的信号处理电路或本公开任一实施例所述的显示面板。
本公开至少一个实施例还提供一种信号处理电路的驱动方法，包括：提供所述控制信号和所述输入信号，使得所述分路电路响应于所述控制信号依次将所述输入信号在N个不同时刻分别输出到所述N个输出节点，并由所述N个缓存电路的每个将所述输入信号缓存并输出。
本公开至少一个实施例还提供一种显示面板的驱动方法，包括：提供所述控制信号和所述显示数据信号，使得所述分路电路响应于所述控制信号依次将所述显示数据信号在N个不同时刻分别输出到所述N个输出节点，并由所述N个缓存电路的每个将所述显示数据信号缓存并输出至对应的N条数据线。
例如，在本公开一实施例提供的显示面板的驱动方法包括：提供栅极扫描信号以对所述显示面板进行行扫描，相邻的栅极扫描信号的脉冲持续时间彼此部分重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种信号处理电路的示意框图；
图2为本公开一实施例提供的另一种信号处理电路的示意框图；
图3为本公开一实施例提供的另一种信号处理电路的示意框图；
图4为本公开一实施例提供的另一种信号处理电路的示意框图；
图5为本公开一实施例提供的一种信号处理电路的分路电路的示意框图；
图6为本公开一实施例提供的另一种信号处理电路的分路电路的示意框图；
图7为图2中所示的信号处理电路的一种具体实现示例的电路图；
图8为本公开一实施例提供的一种信号处理电路的缓存电路的一种具体实现示例的电路图；
图9为图4中所示的信号处理电路的一种具体实现示例的电路图；
图10A为图6中所示的信号处理电路的分路电路的一种具体实现示例的电路图；
图10B为图6中所示的信号处理电路的分路电路的另一种具体实现示例的电路图；
图11为本公开一实施例提供的一种信号处理电路的信号时序图；
图12为本公开一实施例提供的另一种信号处理电路的信号时序图；
图13为本公开一实施例提供的一种显示面板的示意框图；
图14为本公开一实施例提供的一种显示面板的信号时序图；
图15A是一种像素电路的示意图；以及
图15B是图15A示出的像素电路的驱动时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
例如，显示屏的像素阵列通常包括多行栅线和与之交错的多列数据线。显示屏中的栅极驱动电路为像素阵列的多行栅线提供开关态电压信号，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号(例如，像素单元中的像素电路在该数据信号的作用下进行补偿或充电)，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
近年来，高更新率(刷新率)的显示屏得到了越来越多的关注和应用。更新率是指显示屏在一定时间下对显示图像的重复扫描的次数。高更新率的显示屏可应用于电影播放、AR显示、VR显示、电子竞技等领域，能够改善动态画面因显示延迟的影响而造成的拖影现象，显示画面的稳定性好。
但是，高更新率会导致显示屏中的像素电路的补偿时间(充电时间)不足，造成画面品质严重下降，例如，产生显示波纹(mura)。以120Hz的有源矩阵有机发光二极管(Active-Matrix Organic Light Emitting Diode,AMOLED)显示屏为例，在该更新率下，像素电路可用的充电时间为3.3μs，仅为60Hz的AMOLED显示屏的充电时间的一半，其像素电路的补偿时间不足。本公开的发明人注意到像素电路的补偿时间不足会导致数据电压写入不充分，影响显示质量。
下面结合图15A和图15B对像素电路的补偿时间不足对显示质量的影响进行示例性说明。
图15A示出了一种具有阈值补偿能力的像素电路。如图15所示，该像素 电路为7T1C型像素电路，也即，具有七个晶体管和一个存储电容Cst的像素电路。具体而言，该像素电路包括第一晶体管Tt1、第二晶体管Tt2、第三晶体管Tt3、第四晶体管Tt4、第五晶体管Tt5、第六晶体管Tt6、第七晶体管Tt7、存储电容Cst、发光元件(例如oled)、第一节点N1以及第二节点N2。第二晶体管Tt2和第四晶体管Tt4的控制端配置为像素电路的选通控制端GAT，与栅线连接，以接收扫描信号；第五晶体管Tt5和第六晶体管Tt6的控制端配置为像素电路的发光控制端EM，与发光控制线连接，以接收发光控制信号；第一晶体管Tt1和第七晶体管Tt7的控制端配置为像素电路的复位控制端RESE，与复位线连接，以连接复位信号。第三晶体管Tt3的控制端连接至第二节点N2以及存储电容Cst的第一端，第一节点N1连接至第一电源端ELVDD，发光元件的第二端连接至第二电源端ELVSS；此处，第一电源端ELVDD和第二电源端ELVSS配置为恒压源，且第一电源端ELVDD输出的电压Vt1例如大于第二电源端ELVSS输出的电压Vt2，ELVSS输出的电压Vt2例如为零(例如接地)。第一晶体管Tt1的第二端和第七晶体管Tt7的第一端配置为接收初始电压Vinit，第四晶体管Tt4的第一端配置像素电路的数据信号接收端DAT，与数据线连接以接收数据信号(例如，数据电压Vdata)。该像素电路中以各个晶体管为P型晶体管为例进行说明，但是本公开实施例不限于这种情形，例如像素电路中至少一个晶体管可以为N型晶体管。当P型晶体管的栅极接收低于阈值电压的低电平信号时，该P型晶体管导通，而当接收高于阈值电压的高电平信号时，该P型晶体管截止。
图15B示出了图15A所示的像素电路的驱动时序图。如图15B所示，像素电路的每个驱动周期包括复位阶段Tre、补偿阶段Tc以及发光阶段Tem。
在复位阶段Tre，像素电路的复位控制端RESE接收低电平信号，由此第一晶体管Tt1和第七晶体管Tt7导通，由此初始电压Vinit分别经第一晶体管Tt1和第七晶体管Tt7导通被施加至发光元件的阳极以及第二节点N2，由此发光元件的阳极和第二节点N2的电压被设置为初始电压Vinit并因此被复位，该初始电压Vinit可使得第三晶体管Tt3(驱动晶体管)处于导通状态。此时第一节点N1的电压为V1。
在补偿阶段Tc，像素电路的选通控制端GAT接收低电平信号，由此第二晶体管Tt2和第四晶体管Tt4导通，因此使得数据电压Vdata被施加至第三晶体管Tt3的源极，且使得第三晶体管Tt3的漏极和栅极电连接。由于第三晶 体管Tt3处于导通状态，因此可通过第三晶体管Tt3的漏极和栅极进行存储电容Cst进行充电，随着第三晶体管Tt3的栅极的电压升高，充电过程结束。此时，第三晶体管Tt3的源极(第一端)的电压Vt1为Vdata，漏极(第二端)以及栅极(控制端)的电压Vt2变化至Vdata+Vth，也即第二节点N2的电压也为Vdata+Vth，并存储在存储电容Cst第一端(也即，与第二节点N2相连的一端)，此处，Vth为第三晶体管Tt3的阈值电压，此时第一节点N1的电压仍为V1。
在发光阶段Tem，发光控制端EM接收低电平信号，由此第五晶体管Tt5和第六晶体管Tt6导通，进而第三晶体管Tt3的第一端经由导通的第五晶体管Tt5连接至第一电源端ELVDD，并且第三晶体管Tt3的第一端的电压Vt1改变为V1；此时，在存储电容Cst的作用下，第三晶体管Tt3的控制端的电压Vtg即第二节点N2的电压仍为Vdata+Vth。第三晶体管Tt3处于饱和状态下输出的电流Ids可如下计算公式得到：
Ids＝1/2×K(Vgs-Vth) 2
＝1/2×K(Vtg-Vt1-Vth) 2
＝1/2×K(Vdata+Vth-V1-Vth) 2
＝1/2×K(Vdata-V1) 2。
这里，K＝W/L×C×μ，W/L为第三晶体管Tt3的沟道的宽长比(即，宽度与长度的比值)，μ为电子迁移率，C为单位面积的电容。
由上述公式可知，第三晶体管Tt3处于饱和状态下输出的电流Ids与第三晶体管Tt3的阈值电压无关，由此图15A所示的像素电路具有阈值补偿功能。
本公开的发明人在研究中注意到，在显示面板的刷新频率提升时(例如，从60Hz提升至120Hz)，由于栅极驱动电路输出的扫描信号以及复位信号的(脉冲)时间减小，复位阶段Tre、补偿阶段Tc以及发光阶段Tem的时间长度均减小(例如，减半)。此时，由于补偿阶段Tc的时间较短，即数据写入时间较短，从而不能对存储电容Cst充分充电，导致像素电路的阈值电压补偿能力不足。下面以图15A示出的像素电路做示例性说明。如图15A所示，在补偿阶段Tc的时间较短的情况下，第三晶体管Tt3的控制端的电压Vt2难以充分变化至Vdata+Vth，并使得存储在存储电容Cst与第二节点相连的一端的电压并非Vdata+Vth(例如小于Vdata+Vth)。这种情况下，电流Ids与第三晶体管Tt3的阈值电压Vth依然有一定的关系，由此导致像素电路的阈值电 压补偿能力不足并降低了显示面板的补偿效果以及亮度均匀度。本公开至少一实施例提供一种信号处理电路及其驱动方法、显示面板及其驱动方法及显示装置，该信号处理电路可以延长显示面板中像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一实施例提供一种信号处理电路，该信号处理电路包括分路电路和N个缓存电路。所述分路电路包括N个输出节点，所述N个缓存电路与所述N个输出节点分别连接。所述分路电路配置为响应于控制信号将输入信号在N个不同时刻分别输出到所述N个输出节点。所述缓存电路配置为将对应的输出节点接收的所述输入信号缓存并输出。这里，N为大于等于2的整数。
图1为本公开一实施例提供的一种信号处理电路的示意框图。参考图1，该信号处理电路10包括分路电路(Demux电路)100和N个缓存电路200，N为大于等于2的整数。
如图1所示，分路电路100包括N个输出节点，例如Q1、Q2、···、QN。分路电路100配置为响应于接收的控制信号，将接收的输入信号在N个不同时刻分别输出到N个输出节点。例如，分路电路100与输入控制端Mx和输入端Input连接，配置为在输入控制端Mx提供的控制信号的控制下使输入端Input提供的输入信号在N个不同时刻分别输出到Q1、Q2、···、QN，在这N个不同时刻输入信号所代表的数据信息可以彼此不同。例如，输入端Input可以和设置在该信号处理电路10之外的数据驱动电路400连接，以接收数据驱动电路400提供的显示数据信号并作为输入信号。例如，数据驱动电路400可以是设置在显示装置中的数据驱动器或驱动芯片，配置为向多个像素单元提供显示数据信号，该显示数据信号即为上述输入信号。
需要说明的是，本公开的各实施例中，输出节点的数量不受限制，例如，可以为2个、3个、4个或任意个数，只需保证输出节点的数量大于等于2即可。例如，控制信号的数量不受限制，根据需要，可以为任意个数。相应地，输入控制端Mx的数量也不受限制，与控制信号的数量相等即可。
N个缓存电路200与N个输出节点分别连接，配置为将对应的输出节点 接收的输入信号缓存并输出。例如，缓存电路200_1与第一输出节点Q1和第一输出端Out1连接，配置为将第一输出节点Q1接收的输入信号缓存并输出到第一输出端Out1，且在预定时间内维持该输出；缓存电路200_2与第二输出节点Q2和第二输出端Out2连接，配置为将第二输出节点Q2接收的输入信号缓存并输出到第二输出端Out2，且在预定时间内维持该输出，以此类推。例如，N个输出端Out1、Out2、···、OutN可以分别连接到N条数据线，以向像素单元提供输入的数据信号。例如，缓存电路200的数量等于输出节点的数量，从而保证两者一一对应连接。
图2为本公开一实施例提供的另一种信号处理电路的示意框图。参考图2，该信号处理电路10包括分路电路100、第一缓存电路210和第二缓存电路220。分路电路100包括第一输出节点Q1和第二输出节点Q2。
第一缓存电路210的第一端211配置为和与之对应的输出节点(即第一输出节点Q1)连接，第一缓存电路210的第二端212配置为和第一电压端VDC连接以接收第一电压。第二缓存电路220的第一端221配置为和与之对应的输出节点(即第二输出节点Q2)连接，第二缓存电路220的第二端222配置为和第一电压端VDC连接以接收第一电压。例如，第一电压端VDC为直流电压端，可以提供直流高电平信号(例如，VDD)，也可以提供直流低电平信号(例如，VSS)，本公开的实施例对此不作限制。分路电路100与图1中描述的分路电路100相类似，此处不再赘述。
当输入控制端Mx提供的控制信号为有效电平时，分路电路100在不同的时刻将输入端Input提供的输入信号分别输出到第一输出节点Q1和第二输出节点Q2。例如，在第一时刻，分路电路100响应于控制信号将输入信号输出到第一输出节点Q1，且在预定时间内维持该输出；之后，在第二时刻，分路电路100响应于控制信号将输入信号输出到第二输出节点Q2，且在预定时间内维持该输出；之后，在第三时刻，分路电路100响应于控制信号将输入信号又输出到第一输出节点Q1，且在预定时间内维持该输出。以此类推，在后续各个时刻，分路电路100采用这种方式将输入信号循环输出到第一输出节点Q1和第二输出节点Q2。第一缓存电路210将第一输出节点Q1接收的输入信号缓存并输出到第一输出端Out1，第二缓存电路220将第二输出节点Q2接收的输入信号缓存并输出到第二输出端Out2。
通过这种方式，输入信号被分解为2路子信号，且子信号的频率是输入 信号的频率的一半，即子信号的周期是输入信号的周期的2倍。例如，将子信号提供给显示面板的像素单元以作为显示数据信号，像素单元中的像素电路响应于栅极扫描信号并在显示数据信号的作用下进行补偿或充电，从而可以使像素电路的补偿时间延长为原补偿时间的2倍，使数据电压写入更加充分，进而提高显示质量。需要说明的是，本公开的各实施例中，补偿时间的延长量与输入信号的频率以及输出节点和缓存电路的数量有关。在输入信号频率一定的情况下，可以根据实际需求设置输出节点和缓存电路的数量，从而使补偿时间的延长量满足需求。
图3为本公开一实施例提供的另一种信号处理电路的示意框图。参考图3，除了还进一步包括N个复位电路300外，该信号处理电路10和图1中描述的信号处理电路10基本上相同。在该实施例中，N个复位电路300与N个输出节点分别连接，配置为响应于复位信号线(复位信号端RST)提供的复位信号对N个输出节点复位(也即，对N个缓存电路200复位)。例如，复位电路300_1与复位信号端RST和第一输出节点Q1连接，复位电路300_2与复位信号端RST和第二输出节点Q2连接，以此类推。
需要说明的是，本公开的各实施例中，复位电路300的数量不受限制，可以根据输出节点和缓存电路200的数量而定。例如，复位电路300的数量等于输出节点和缓存电路200的数量，每一个复位电路300对与其对应连接的缓存电路200进行复位。
例如，显示面板工作时，每一帧图像的扫描时序包括空白时间和有效时间。在有效时间，像素单元的像素电路逐行扫描以显示图像；在空白时间，像素电路不进行扫描操作。例如，复位电路300在空白时间对各个缓存电路200进行复位，以使下一帧图像的显示数据信号更加准确地且更快地缓存到各个缓存电路200中，从而提高显示质量。例如，复位电路300可以在每一帧图像扫描开始前或者扫描结束后对各个缓存电路200进行复位，复位电路300也可以在特定时刻(例如，每一行像素单元的数据写入前)对对应的缓存电路200进行复位。
图4为本公开一实施例提供的另一种信号处理电路的示意框图。参考图4，除了还进一步包括第一复位电路310和第二复位电路320外，该实施例的信号处理电路10和图2中描述的信号处理电路10基本上相同。在该实施例中，第一复位电路310与第一输出节点Q1连接，配置为响应于复位信号线(复 位信号端RST)提供的复位信号对第一缓存电路210复位。第二复位电路320与第二输出节点Q2连接，配置为响应于复位信号线(复位信号端RST)提供的复位信号对第二缓存电路220复位。
例如，第一复位电路310的第一端311配置为和第一输出节点Q1连接，第一复位电路310的第二端312配置为和第二电压端VSS连接以接收第二电压，第一复位电路310的控制端313配置为和复位信号线(复位信号端RST)连接以接收复位信号。第二复位电路320的第一端321配置为和第二输出节点Q2连接，第二复位电路320的第二端322配置为和第二电压端VSS连接以接收第二电压，第二复位电路320的控制端323配置为和复位信号线(复位信号端RST)连接以接收复位信号。例如，第二电压端VSS提供直流低电平信号(例如，接地)，将该直流低电平信号称作第二电压并作为复位电压；或者第二电压端VSS也可以提供直流高电平信号，例如，在第一电压端VDC提供直流高电平信号的情形下，第二电压端VSS等于第一电压端VDC。
当复位信号为有效电平时，第一复位电路310将第二电压端VSS和第一输出节点Q1电连接，第二复位电路320将第二电压端VSS和第二输出节点Q2电连接，从而可以对第一输出节点Q1、第一缓存电路210、第二输出节点Q2和第二缓存电路220复位。例如，可以在每一帧图像扫描开始前或者扫描结束后进行复位。当然，本公开的实施例不限于此，也可以根据实际需求在特定的时刻进行复位，例如，在对应的缓存电路缓存数据之前进行复位。通过复位，可以使输入信号(例如，显示数据信号)更加准确地、更快地缓存到第一缓存电路210和第二缓存电路220中，从而提高显示质量。
图5为本公开一实施例提供的一种信号处理电路的分路电路的示意框图。参考图5，分路电路100包括输入端Input、第一输入控制端MxO、第二输入控制端MxE、第一开关电路110和第二开关电路120。第一开关电路110与输入端Input、第一输出节点Q1和第一输入控制端MxO连接，配置为响应于从第一输入控制端MxO接收的第一控制信号，将从输入端Input接收的输入信号输出到第一输出节点Q1。第二开关电路120与输入端Input、第二输出节点Q2和第二输入控制端MxE连接，配置为响应于从第二输入控制端MxE接收的第二控制信号，将从输入端Input接收的输入信号输出到第二输出节点Q2。
当第一控制信号为有效电平(即可以使第一开关电路110导通的电平) 时，第一开关电路110将第一输出节点Q1和输入端Input电连接，从而使输入信号输出到第一输出节点Q1。当第二控制信号为有效电平(即可以使第二开关电路120导通的电平)时，第二开关电路120将第二输出节点Q2和输入端Input电连接，从而使输入信号输出到第二输出节点Q2。例如，第一控制信号和第二控制信号交替为有效电平，从而使输入信号交替输出到第一输出节点Q1和第二输出节点Q2。
需要说明的是，本公开的各实施例中，开关电路的数量不受限制，可以根据实际需求而定。在本实施例的一个示例中，以2个开关电路(第一开关电路110和第二开关电路120)为例进行说明。例如，在其他示例中，分路电路100包括N个开关电路，相应地，输入控制端和输出节点也分别为N个，N个开关电路与输入端Input连接，且分别与N个输出节点以及N个输入控制端一一对应连接。N为大于等于2的整数。
图6为本公开一实施例提供的另一种信号处理电路的分路电路的示意框图。参考图6，除了输入控制端的连接方式不同以及还进一步包括反相电路130外，该实施例的分路电路100和图5中描述的分路电路100基本上相同。在该实施例中，第一输入控制端MxO和第二输入控制端MxE彼此连接，并且连接到相同的输入控制线(输入控制端Mx)，以接收相同的控制信号。第二开关电路120通过反相电路130与第二输入控制端MxE连接。也即是，第二开关电路120接收到的控制信号与第一开关电路110接收到的控制信号彼此反相，从而实现对第一开关电路110和第二开关电路120的交替控制。
例如，当第一输入控制端MxO和第二输入控制端MxE的控制信号为有效电平(即使第一开关电路110导通的电平)时，第一开关电路110将第一输出节点Q1和输入端Input电连接，而此时通过反相电路130的作用，第二开关电路120接收到的控制信号为无效电平(即使第二开关电路120截止的电平)，从而使第二输出节点Q2和输入端Input断开。当第一输入控制端MxO和第二输入控制端MxE的控制信号为无效电平时，第一开关电路110使第一输出节点Q1和输入端Input断开，而此时通过反相电路130的作用，第二开关电路120接收到的控制信号为有效电平，从而使第二输出节点Q2和输入端Input电连接。
通过这种方式，采用1个控制信号就实现了对第一开关电路110和第二开关电路120的交替控制，可以简化电路的控制方式，减少信号数量，避免 信号之间的相互干扰，从而增强第一输出节点Q1和第二输出节点Q2的信号隔离度。需要说明的是，本公开的各实施例中，反相电路130的设置方式不受限制，反相电路130可以与第一开关电路110和第二开关电路120之中的任意一个连接，这可以根据实际需求而定，例如，根据控制信号和开关电路之间的匹配关系而定。
图7为图2中所示的信号处理电路的一种具体实现示例的电路图。在下面的描述中，除非特殊说明，均以各晶体管为P型晶体管为例进行说明，但这并不构成对本公开实施例的限制。参考图7，该信号处理电路10包括第一晶体管T1、第二晶体管T2、第一电容C1和第二电容C2。
例如，分路电路100包括第一开关电路110和第二开关电路120。如图7所示，第一开关电路110可以实现为第一晶体管T1，第一晶体管T1作为开关晶体管。第一晶体管T1的栅极连接到第一输入控制端MxO，第一晶体管T1的第一极连接到输入端Input，第一晶体管T1的第二极连接到第一输出节点Q1。第二开关电路120可以实现为第二晶体管T2，第二晶体管T2作为开关晶体管。第二晶体管T2的栅极连接到第二输入控制端MxE，第二晶体管T2的第一极连接到输入端Input，第二晶体管T2的第二极连接到第二输出节点Q2。当第一输入控制端MxO提供的第一控制信号和第二输入控制端MxE提供的第二控制信号交替为有效电平时，第一晶体管T1和第二晶体管T2交替导通，从而使输入端Input的输入信号交替输出至第一输出节点Q1和第二输出节点Q2。
第一缓存电路210可以实现为第一电容C1。第一电容C1的第一极作为第一缓存电路210的第一端211连接到第一输出节点Q1，第一电容C1的第二极作为第一缓存电路210的第二端212连接到第一电压端VDC。第一电容C1可以缓存第一输出节点Q1接收的输入信号，并将该输入信号输出到第一输出端Out1。
第二缓存电路220可以实现为第二电容C2。第二电容C2的第一极作为第二缓存电路220的第一端221连接到第二输出节点Q2，第二电容C2的第二极作为第二缓存电路220的第二端222连接到第一电压端VDC。第二电容C2可以缓存第二输出节点Q2接收的输入信号，并将该输入信号输出到第二输出端Out2。
例如，在显示面板中，由于布线的影响，缓存电路200可以实现为如图8 所示的电路结构，在该实施例中，以第一缓存电路210为例进行说明。参考图8，第一缓存电路210包括第一子电容C11、第二子电容C12和电阻R。第一子电容C11的第一极连接到第一子节点Q11，第一子电容C11的第二极连接到第一电压端VDC。第二子电容C12的第一极连接到第二子节点Q12，第二子电容C12的第二极连接到第一电压端VDC。电阻R的第一极连接到第一子节点Q11，电阻R的第二极连接到第二子节点Q12。分路电路100响应于控制信号将输入信号输出到第一子节点Q11，第一缓存电路210将该输入信号缓存并通过第二子节点Q12输出到第一输出端Out1。
例如，第一子电容C11为通过工艺制程制作在显示面板上的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。例如，第二子电容C12为显示面板中数据线之间的寄生电容，可以通过数据线本身与其他器件、线路来实现。例如，电阻R为显示面板中数据线自身的电阻，而并非实际存在的电阻器件。
需要说明的是，本公开的各实施例中，各个缓存电路200中的寄生电容(第二子电容C12)的电容值可能相同，也可能不同，这与显示面板中数据线的布线方式有关。因此，为了保证各个缓存电路200的输出信号的基准一致，各个缓存电路200中的第一子电容C11的电容值会根据相应的寄生电容的电容值而调整，即各个缓存电路200中的第一子电容C11的电容值可能相同，也可能不同。例如，在其他示例中，通过调整数据线的布线方式，使缓存电路200中的寄生电容满足电容值的需求，因此可以省略第一子电容C11，仅靠寄生电容就可以实现对输入信号的缓存。在这种情形下，缓存电路200中无特别制作的电容器件，无需通过工艺制程制作，因此可以降低成本，提高生产效率。
图9为图4中所示的信号处理电路的一种具体实现示例的电路图。参考图9，除了还进一步包括第三晶体管T3和第四晶体管T4外，该实施例的信号处理电路10和图7中描述的信号处理电路10基本上相同。在该实施例中，第一复位电路310可以实现为第三晶体管T3，第三晶体管T3作为复位晶体管。第三晶体管T3的第一极作为第一复位电路310的第一端311连接到第一输出节点Q1，第三晶体管T3的第二极作为第一复位电路310的第二端312连接到第二电压端VSS，第三晶体管T3的栅极作为第一复位电路310的控制端313连接到复位信号线(复位信号端RST)。第三晶体管T3在复位信号为 有效电平时导通，将第一输出节点Q1和第二电压端VSS电连接，从而可以对第一缓存电路210(第一电容C1)进行复位。
第二复位电路320可以实现为第四晶体管T4，第四晶体管T4作为复位晶体管。第四晶体管T4的第一极作为第二复位电路320的第一端321连接到第二输出节点Q2，第四晶体管T4的第二极作为第二复位电路320的第二端322连接到第二电压端VSS，第四晶体管T4的栅极作为第二复位电路320的控制端323连接到复位信号线(复位信号端RST)。第四晶体管T4在复位信号为有效电平时导通，将第二输出节点Q2和第二电压端VSS电连接，从而可以对第二缓存电路220(第二电容C2)进行复位。
图10A为图6中所示的信号处理电路的分路电路的一种具体实现示例的电路图。在该实施例中，分路电路100中的第一分路电路110和第二分路电路120和图7中描述的电路基本上相同，此处不再赘述。参考图10A，反相电路130可以实现为第五晶体管T5和第六晶体管T6。第五晶体管T5的栅极和第六晶体管T6的栅极相连并连接到第二输入控制端MxE，第五晶体管T5的第一极连接到第三电压端VDD以接收第三电压，第五晶体管T5的第二极和第六晶体管T6的第一极相连并连接到第二晶体管T2的栅极，第六晶体管T6的第二极连接到第二电压端VSS。第一输入控制端MxO和第二输入控制端MxE彼此相连，并连接到相同的输入控制线(输入控制端Mx)，以接收相同的控制信号。例如，第三电压端VDD提供直流高电平信号，将该直流高电平信号称为第三电压。
例如，当第一输入控制端MxO和第二输入控制端MxE的控制信号为低电平时，第一晶体管T1导通。此时，第五晶体管T5也导通，使第三电压端VDD和第二晶体管T2的栅极电连接，从而使第二晶体管T2的栅极接收高电平信号，第二晶体管T2截止。需要注意的是，第六晶体管T6为N型晶体管，此时第六晶体管T6截止。
当第一输入控制端MxO和第二输入控制端MxE的控制信号为高电平时，第一晶体管T1截止。此时，第六晶体管T6导通，使第二电压端VSS和第二晶体管T2的栅极电连接，从而使第二晶体管T2的栅极接收低电平信号，第二晶体管T2导通。此时，第五晶体管T5截止。
图10B为图6中所示的信号处理电路的分路电路的另一种具体实现示例的电路图。在该实施例中，分路电路100中的第一分路电路110和第二分路 电路120分别为不同类型的晶体管，例如，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。第一输入控制端MxO和第二输入控制端MxE彼此相连，并连接到相同的输入控制线(输入控制端Mx)，以接收相同的控制信号。例如，当控制信号为低电平时，第一晶体管T1导通，第二晶体管T2截止；当控制信号为高电平时，第一晶体管T1截止，第二晶体管T2导通。
通过上述这些方式，可以对第一输入控制端MxO和第二输入控制端MxE的控制信号进行反相变换，仅采用1个控制信号就可以实现对第一晶体管T1和第二晶体管T2的控制，从而简化电路的控制方式，减少信号数量，避免信号之间的相互干扰，进而增强第一输出节点Q1和第二输出节点Q2的信号隔离度。
需要注意的是，在本公开的各个实施例的说明中，N个输出节点(Q1、Q2、···、QN)并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，除第六晶体管T6外，在本公开的实施例中的晶体管均以P型晶体管为例进行说明，此时，晶体管的第一极是源极，第二极是漏极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的信号处理电路10中的一个或多个晶体管也可以采用N型晶体管，此时，晶体管第一极是漏极，第二极是源极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
图11为本公开一实施例提供的一种信号处理电路的信号时序图。下面结合图11所示的信号时序图，对图7所示的信号处理电路10的工作原理进行 说明，并且这里以各个晶体管为P型晶体管为例进行说明，但是本公开的实施例不限于此。
例如，信号处理电路10工作时，提供控制信号(第一输入控制端MxO和第二输入控制端MxE提供)和输入信号(输入端Input提供)，使得分路电路100响应于控制信号依次将输入信号在2个不同时刻分别输出到2个输出节点(第一输出节点Q1和第二输出节点Q2)，并由第一缓存电路210将第一输出节点Q1接收的输入信号缓存并输出到第一输出端Out1，由第二缓存电路220将第二输出节点Q2接收的输入信号缓存并输出到第二输出端Out2。在图11所示的第一阶段1和第二阶段2中，该信号处理电路10可以分别进行如下操作。
在第一阶段1，第一输入控制端MxO提供低电平信号，第一晶体管T1导通，使该时刻的输入信号输出到第一输出节点Q1。例如，该时刻的输入信号为第一数据data1。第一电容C1将第一数据data1缓存并可在预定时间内输出该第一数据data1。第二输入控制端MxE提供高电平信号，第二晶体管T2截止，第二输出节点Q2保持上一阶段的信号或被复位后的信号。
在第二阶段2，第二输入控制端MxE提供低电平信号，第二晶体管T2导通，使该时刻的输入信号输出到第二输出节点Q2。例如，该时刻的输入信号为第二数据data2。第二电容C2将第二数据data2缓存并可在预定时间内输出该第二数据data2。第一输入控制端MxO提供高电平信号，第一晶体管T1截止，第一输出节点Q1保持上一阶段的信号(即第一数据data1)或被复位后的信号。
在后续各个阶段，在第一输入控制端MxO和第二输入控制端MxE的控制信号的控制下，第一晶体管T1和第二晶体管T2将输入信号交替输出至第一输出节点Q1和第二输出节点Q2，从而使输入信号分解为2路子信号，且第一输出节点Q1和第二输出节点Q2的信号频率为输入信号的频率的一半，即第一输出节点Q1和第二输出节点Q2的信号周期为输入信号的周期的2倍。
例如，将第一输出节点Q1和第二输出节点Q2的信号提供给显示面板的像素单元以作为显示数据信号，像素单元中的像素电路响应于栅极扫描信号并根据该显示数据信号进行补偿或充电，从而可以使像素电路的补偿时间延长为原补偿时间的2倍，使数据电压写入更加充分，进而提高显示质量。例如，当输入信号为120Hz时，第一输出节点Q1和第二输出节点Q2的信号分 别为60Hz。在显示数据信号为120Hz的频率时，传统的像素电路的补偿时间为3.3μs。该信号处理电路10提供给像素单元的显示数据信号的频率为60Hz，因此补偿时间为6.5μs，补偿时间得到延长。当然，本公开的实施例不限于此，输入信号(例如，显示数据信号)可以为任意频率。例如，输入信号可以为120Hz、90Hz、60Hz或其他适用的频率，以兼容常规的高更新率屏幕、AR/VR显示等。例如，通过输入信号的频率和输出节点数量的配合，可以根据需求调节补偿时间的延长量。例如，在其他示例中，输入信号为120Hz，输出节点为3个，则各个输出节点的信号频率为40Hz，以使补偿时间进一步延长。
图12为本公开一实施例提供的另一种信号处理电路的信号时序图。下面结合图12所示的信号时序图，对图9所示的信号处理电路10在复位阶段0的工作原理进行说明。
在复位阶段0，复位信号端RST提供低电平信号，第三晶体管T3和第四晶体管T4均导通，使第一输出节点Q1和第二输出节点Q2分别和第二电压端VSS电连接，从而对第一电容C1和第二电容C2复位，使第一输出节点Q1和第二输出节点Q2的信号为低电平。例如，第一输入控制端MxO和第二输入控制端MxE均提供高电平信号，使第一晶体管T1和第二晶体管T2均截止。
例如，可以在每一帧图像扫描开始前或者扫描结束后进行复位，也可以根据实际需求在特定的时刻进行复位。通过复位，可以使输入信号(例如，显示数据信号)更加准确地缓存到第一电容C1和第二电容C2中，从而提高显示质量。
本公开至少一实施例还提供一种显示面板，包括本公开任一实施例所述的信号处理电路和多条数据线。所述多条数据线中的N条数据线分别连接到所述信号处理电路的N个缓存电路，所述输入信号为显示数据信号。该显示面板可以延长像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。
图13为本公开一实施例提供的一种显示面板的示意框图。参考图13，该显示面板20包括阵列基板500、多个信号处理电路10、多条数据线510以及呈阵列分布的多个像素单元P。例如，信号处理电路10、数据线510和像素单元P均设置在阵列基板500上。信号处理电路10为本公开任一实施例所述的信号处理电路。例如，该阵列基板500包括显示区域和周边区域，多个像 素单元P设置在显示区域，多个信号处理电路10设置在周边区域。例如，多条数据线510中的N条数据线分别连接到信号处理电路10的N个缓存电路。与信号处理电路10连接的N条数据线510连接到同一列像素单元P。同一列像素单元P包括N个像素单元组，每个像素单元组连接到同一条数据线510。例如，N个像素单元组中的像素单元P在列方向上依序交替排列。例如，信号处理电路10的数目等于像素单元P的列数，数据线510的数目等于信号处理电路10的数目的N倍。需要说明的是，同一列像素单元P是指与同一个信号处理电路10的多个像素单元，而不限定同一列像素单元P的中心位于同一直线(沿列方向延伸的直线)。例如，如图13所示，同一列像素单元P的不同像素单元组的像素单元的中心可以在行方向上交错设置(例如，同一列像素单元P的不同像素单元组的像素单元的中心所在的直线彼此间隔设置)。又例如，根据实际应用需求，同一列像素单元P的中心还可以位于同一直线上。
在该实施例中，N等于2，即连接到同一个信号处理电路10的2条数据线510包括第一数据线511和第二数据线512。第一数据线511连接到第一缓存电路210，第二数据线512连接到第二缓存电路220。第一数据线511和第二数据线512连接到同一列像素单元P。同一列像素单元P包括2个像素单元组，即第一像素单元组和第二像素单元组。第一像素单元组包括位于奇数行的像素单元P，第二像素单元组包括位于偶数行的像素单元P。
例如，信号处理电路10还通过引线D1等与设置在阵列基板500之外的数据驱动电路400和控制电路(例如时序控制器T-CON)600连接，以分别从数据驱动电路400接收输入信号以及从控制电路600接收控制信号。例如，上述输入信号为显示数据信号。数据驱动电路400配置为向各列像素单元P提供显示数据信号。例如，数据驱动电路400可以是驱动芯片或数据驱动器。数据驱动电路400将提供给各列像素单元P的显示数据信号分别提供给与各列像素单元P对应连接的信号处理电路10。控制电路600配置为向信号处理电路10提供控制信号，例如，将2个控制信号分别提供给第一输入控制端MxO和第二输入控制端MxE。例如，多个信号处理电路10的第一输入控制端MxO连接到同一条信号线以接收同一个第一控制信号，多个信号处理电路10的第二输入控制端MxE连接到同一条信号线以接收同一个第二控制信号。例如，控制电路600也可以设置在阵列基板500上，或者集成到数据驱动电路400中。
例如，数据驱动电路400的输出端口的数目可以等于信号处理电路10的数目以及像素单元P的列数，也即，本公开的实施例提供的显示面板的数据驱动电路400的输出端口的数目相比于常规显示面板的数据驱动电路的端口数目保持不变。因此，本公开的实施例提供的显示面板可以采用现有的数据驱动电路(例如，驱动芯片)，由此可以显示面板的降低设计成本和制作成本。
需要说明的是，根据实际应用需求，信号处理电路10还可以设置在阵列基板500之外，信号处理电路10例如可以集成在数据驱动电路400中，以增加数据驱动电路400的输出端口的数目。
例如，连接到同一个信号处理电路10的N条数据线510位于阵列基板500的不同层。在该实施例中，N等于2，即第一数据线511和第二数据线512位于阵列基板500的不同层。这种设置方式可以减小数据线之间的信号干扰，并且不会增加阵列基板的工艺难度，有助于实现高像素密度(Pixels Per Inch,PPI)。例如，在一个示例中，在传统的阵列基板的数据线层制作第一数据线511，并增加一层绝缘层和一层金属层，在该金属层制作第二数据线512。这种方式可以有效减小第一数据线511和第二数据线512之间的信号干扰，并且不影响原有的数据线层的制作工艺。
需要说明的是，本公开的各实施例中，N条数据线510的相对位置关系不受限制，可以N条数据线510均位于不同层，也可以N条数据线510中的部分数据线510位于不同层。N条数据线510的上下层叠关系不受限制，可以根据显示面板的实际布线方式而定。当然，在工艺条件允许的情形下，N条数据线510也可以设置在同一层，可以简化制作工艺，减小面板厚度。
例如，显示面板20还包括栅极驱动电路700，多个像素单元P与栅极驱动电路700连接。栅极驱动电路700配置为提供多个栅极扫描信号以对显示面板20的像素单元P进行行扫描。栅极驱动电路700的数量不受限制，可以根据实际需求而定。例如，在其他示例中，显示面板20包括2个栅极驱动电路700，分别设置在显示面板20的两侧，以实现双边驱动。例如，设置在显示面板20一侧的栅极驱动电路700配置为驱动奇数行栅线，而设置在显示面板20另一侧的栅极驱动电路700配置为驱动偶数行栅线。
需要说明的是，本公开的各实施例中，栅极驱动电路700的设置方式不受限制，可以根据实际需求而定。例如，栅极驱动电路700可以是设置在阵列基板500之外的栅极驱动器。例如，栅极驱动电路700也可以设置在阵列 基板500上，以构成GOA电路(Gate-driver On Array)，从而减少显示面板20与其他部件的引线数量。
例如，为了配合第一缓存电路210和第二缓存电路220输出的显示数据信号，相邻行的栅极扫描信号的脉冲时间(也即，脉冲持续时间)部分重叠，即第M+1行的栅极扫描信号的脉冲时间与第M行的栅极扫描信号的脉冲时间部分重叠，M为大于0的整数。
例如，像素单元P包括像素电路，且像素电路例如可以实现为图15A示出的7T1C型像素电路、6T1C型像素电路、5T2C型像素电路或其它具有阈值补偿功能的像素电路。例如，图15A示出的像素电路的选通控制端GAT可经由栅线与栅极驱动电路700相连，像素电路的数据信号接收端DAT可经由数据线与信号处理电路10和数据驱动电路400相连。
图14为本公开一实施例提供的一种显示面板的信号时序图。下面结合图14所示的信号时序图，对图13所示的显示面板20的工作原理进行说明。显示面板20中的信号处理电路10的工作原理与图7中所示的信号处理电路10的工作原理类似，此处不再赘述。
在第一阶段1和第二阶段2，信号处理电路10在控制信号的控制下，将来自数据驱动电路400的显示数据信号分别输出到第一输出节点Q1和第二输出节点Q2，第一缓存电路210和第二缓存电路220分别将从引线D1接收到的显示数据信号缓存并输出到第一数据线511(DO1)和第二数据线512(DE1)。第一数据线511将第一输出节点Q1的信号提供给第一像素单元组(位于奇数行的像素单元P)，第二数据线512将第二输出节点Q2的信号提供给第二像素单元组(位于偶数行的像素单元P)。在后续各个阶段，以此方式将显示数据信号交替提供给第一像素单元组和第二像素单元组。
栅极驱动电路700提供多个栅极扫描信号(G1、G2、G3等)，以对多个像素单元P进行行扫描。在第一阶段1和第二阶段2，第一行栅极扫描信号G1(例如，向第一行像素单元提供的栅极扫描信号)为低电平，使第一行像素单元P打开，并在第一数据线511(DO1)提供的显示数据信号的作用下进行补偿或充电。在第二阶段2和第三阶段3，第二行栅极扫描信号G2(例如，向第二行像素单元提供的栅极扫描信号)为低电平，使第二行像素单元P打开，并在第二数据线512(DE1)提供的显示数据信号的作用下进行补偿或充电。在后续各个阶段，以此方式分别对位于奇数行的像素单元P和位于偶数 行的像素单元P进行补偿或充电。
例如，在该示例中，栅极扫描信号的脉冲时间t1等于显示数据信号周期t2的2倍，以尽量延长补偿时间或充电时间。例如，第M+1行的栅极扫描信号的脉冲时间与第M行的栅极扫描信号的脉冲时间部分重叠，重叠时间为t3。例如，重叠时间t3等于显示数据信号周期t2，即重叠时间t3等于脉冲时间t1的1/2。在这种方式下，像素单元P中的像素电路的补偿时间延长为原补偿时间的2倍。例如，在其他示例中，同一列像素单元P包括N个像素单元组时，重叠时间t3为脉冲时间t1的(N-1)/N，从而使像素单元P中的像素电路的补偿时间延长为原补偿时间的N倍。上述方式可以使数据电压写入更加充分，进而提高显示质量。
例如，栅极扫描信号的脉冲时间等于数据驱动电路400提供的显示数据信号周期的N倍；由于缓存电路的信号缓存功能，像素单元可以在栅极扫描信号的脉冲时间内持续接收显示数据信号，也即，可用于像素单元的补偿时间为显示数据信号周期的N倍，由此可以提升像素单元P的像素电路的补偿效果，进而可以提升显示面板的亮度均匀度。本公开至少一实施例还提供一种显示装置，包括本公开任一实施例所述的信号处理电路10或本公开任一实施例所述的显示面板20。该显示装置可以延长像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。
例如，该显示装置可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置的技术效果可以参考上述实施例中关于信号处理电路10和显示面板20的相应描述，此处不再赘述。
本公开至少一实施例还提供一种信号处理电路的驱动方法，可以用于驱动本公开任一实施例所述的信号处理电路10。利用该驱动方法，可以延长像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。
例如，在一个示例中，该信号处理电路的驱动方法包括如下操作：提供控制信号和输入信号，使得分路电路100响应于控制信号依次将输入信号在N个不同时刻分别输出到N个输出节点，并由缓存电路200将输入信号缓存并 输出，N为大于等于2的整数。
本公开至少一实施例还提供一种显示面板的驱动方法，可以用于驱动本公开任一实施例所述的显示面板20。利用该驱动方法，可以延长像素电路的补偿时间，兼容现有的像素电路和驱动芯片，可解决高更新率屏幕中像素电路补偿时间不足的问题，有助于提高显示质量。
例如，在一个示例中，该显示面板的驱动方法包括如下操作：
提供控制信号和显示数据信号，使得分路电路100响应于控制信号依次将显示数据信号在N个不同时刻分别输出到N个输出节点，并由缓存电路200将显示数据信号缓存并输出至对应的N条数据线510，N为大于等于2的整数。
例如，该显示面板的驱动方法还包括：提供栅极扫描信号以对显示面板20进行行扫描，相邻栅极扫描信号的脉冲时间彼此部分重叠。
需要说明的是，关于信号处理电路的驱动方法和显示面板的驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于信号处理电路10和显示面板20的工作原理的描述，此处不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括信号处理电路和多条数据线，
    其中，所述信号处理电路包括分路电路和N个缓存电路；
    所述分路电路包括N个输出节点；
    所述N个缓存电路与所述N个输出节点分别连接；
    所述分路电路配置为响应于控制信号将输入信号在N个不同时刻分别输出到所述N个输出节点；
    所述N个缓存电路的每个配置为将对应的输出节点接收的所述输入信号缓存；
    所述多条数据线中的N条数据线分别连接到所述信号处理电路的N个缓存电路，所述输入信号为显示数据信号。
  2. 根据权利要求1所述的显示面板，其中，所述N个缓存电路的每个的第一端配置为和与之对应的所述输出节点连接，所述N个缓存电路的每个的第二端配置为和第一电压端连接以接收第一电压。
  3. 根据权利要求2所述的显示面板，其中，所述N个缓存电路的每个包括电容，所述电容的第一极作为所述缓存电路的第一端，所述电容的第二极作为所述缓存电路的第二端。
  4. 根据权利要求1-3任一所述的显示面板，所述信号处理电路还包括N个复位电路，其中，所述N个复位电路与所述N个输出节点分别连接，配置为响应于复位信号对所述N个输出节点复位。
  5. 根据权利要求4所述的显示面板，其中，所述N个复位电路的每个的控制端配置为和复位信号线连接以接收所述复位信号，所述N个复位电路的每个的第一端配置为和对应的所述输出节点连接，所述N个复位电路的每个的第二端配置为和第二电压端连接以接收第二电压。
  6. 根据权利要求5所述的显示面板，其中，所述N个复位电路的每个包括复位晶体管，所述复位晶体管的栅极作为所述复位电路的控制端，所述复位晶体管的第一极作为所述复位电路的第一端，所述复位晶体管的第二极作为所述复位电路的第二端。
  7. 根据权利要求1-6任一所述的显示面板，其中，所述分路电路还包括输入端、N个输入控制端以及N个开关电路，所述N个开关电路与所述输入 端连接，且分别与所述N个输出节点以及所述N个输入控制端一一对应连接，
    所述N个开关电路的每个配置为响应于从对应的所述输入控制端接收的所述控制信号，将从所述输入端接收的所述输入信号输出到对应的所述输出节点。
  8. 根据权利要求7所述的显示面板，其中，所述N个开关电路的每个包括开关晶体管，所述开关晶体管的栅极连接到对应的所述输入控制端，所述开关晶体管的第一极连接到所述输入端，所述开关晶体管的第二极连接到对应的所述输出节点。
  9. 根据权利要求7或8所述的显示面板，其中，N等于2，且所述N个输入控制端彼此连接以连接到相同的输入控制线。
  10. 根据权利要求9所述的显示面板，其中，所述N个开关电路包括第一开关电路和第二开关电路，所述分路电路还包括反相电路，所述第一开关电路和所述第二开关电路其中之一通过所述反相电路与所述N个输入控制端连接。
  11. 根据权利要求1-10任一所述的显示面板，还包括呈阵列分布的多个像素单元，其中，与所述信号处理电路连接的N条数据线连接到同一列像素单元，所述同一列像素单元包括N个像素单元组，每个像素单元组连接到同一条数据线。
  12. 根据权利要求11所述的显示面板，其中，N等于2，所述N个像素单元组包括第一像素单元组和第二像素单元组，
    所述第一像素单元组包括位于奇数行的像素单元，所述第二像素单元组包括位于偶数行的像素单元。
  13. 根据权利要求11或12所述的显示面板，还包括阵列基板，其中，所述信号处理电路设置在所述阵列基板上。
  14. 根据权利要求13所述的显示面板，其中，连接到同一个信号处理电路的N条数据线位于所述阵列基板的不同层。
  15. 根据权利要求11-14任一所述的显示面板，还包括至少一个栅极驱动电路，其中，所述栅极驱动电路配置为提供多个栅极扫描信号以对所述显示面板的像素单元进行行扫描；以及
    第M+1行的栅极扫描信号的脉冲持续时间与第M行的栅极扫描信号的脉冲持续时间部分重叠，M为大于0的整数。
  16. 一种信号处理电路，包括：
    分路电路，包括N个输出节点；
    N个缓存电路，与所述N个输出节点分别连接；
    其中，所述分路电路配置为响应于控制信号将输入信号在N个不同时刻分别输出到所述N个输出节点；
    所述N个缓存电路的每个配置为将对应的输出节点接收的所述输入信号缓存；
    N为大于等于2的整数。
  17. 一种显示装置，包括如权利要求1-15任一所述的显示面板或如权利要求16所述的信号处理电路。
  18. 一种如权利要求1-15任一所述的显示面板的驱动方法，包括：
    提供所述控制信号和所述显示数据信号，使得所述分路电路响应于所述控制信号依次将所述显示数据信号在N个不同时刻分别输出到所述N个输出节点，并由所述N个缓存电路的每个将所述显示数据信号缓存并输出至对应的N条数据线。
  19. 根据权利要求18所述的驱动方法，还包括：
    提供栅极扫描信号以对所述显示面板进行行扫描，相邻的栅极扫描信号的脉冲持续时间彼此部分重叠。
  20. 一种如权利要求16所述的信号处理电路的驱动方法，包括：
    提供所述控制信号和所述输入信号，使得所述分路电路响应于所述控制信号依次将所述输入信号在N个不同时刻分别输出到所述N个输出节点，并由所述N个缓存电路的每个将所述输入信号缓存并输出。
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