WO2024000783A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2024000783A1
WO2024000783A1 PCT/CN2022/115449 CN2022115449W WO2024000783A1 WO 2024000783 A1 WO2024000783 A1 WO 2024000783A1 CN 2022115449 W CN2022115449 W CN 2022115449W WO 2024000783 A1 WO2024000783 A1 WO 2024000783A1
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Prior art keywords
transistor
metal
metal trace
initialization
trace
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PCT/CN2022/115449
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English (en)
French (fr)
Inventor
郭恩卿
李俊峰
盖翠丽
邢汝博
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云谷（固安）科技有限公司
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Priority to KR1020247007466A priority Critical patent/KR20240045264A/ko
Publication of WO2024000783A1 publication Critical patent/WO2024000783A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, for example, to an array substrate, a display panel and a display device.
  • This application provides an array substrate, a display panel and a display device to improve the display effect of the display screen.
  • an array substrate including: a substrate;
  • the pixel circuit includes a driving transistor, a first initialization transistor and a second initialization transistor;
  • the multi-layer metal layer at least includes a first metal trace extending along a first direction and a second metal trace extending along a second direction, and the first metal trace and the second metal trace are located on Different layers
  • the first initialization transistor is connected between the first metal trace and the gate of the drive transistor, and is configured to transmit the first initialization voltage on the first metal trace to the driver
  • the gate of the transistor the second initialization transistor is connected between the second metal line and the light-emitting element; the second initialization transistor is configured to transmit the second initialization voltage on the second metal line to Light-emitting element; the first direction and the second direction intersect and are both perpendicular to the thickness direction of the array substrate.
  • a display panel including the array substrate provided by any embodiment of the present application.
  • a display device including the display panel provided by any embodiment of the present application.
  • the technical solution provided by the embodiments of the present application is to stack an active layer and a multi-layer metal layer on a substrate, wherein the multi-layer metal layer at least includes a first metal trace extending along a first direction and a first metal trace extending along a second direction.
  • the second metal trace, the first metal trace and the second metal trace are located on different layers, the first initialization transistor is connected between the first metal trace and the gate of the driving transistor, and is configured to connect the first metal trace to the second metal trace.
  • the first initialization voltage is transmitted to the gate of the driving transistor, and the second initialization transistor is connected between the second metal line and the light-emitting element; the second initialization transistor is configured to transmit the second initialization voltage on the second metal line to Light emitting components.
  • the technical solution provided by the embodiment of the present application can provide corresponding initialization voltages to the corresponding first initialization transistor and second initialization transistor respectively through the first metal wiring and the second metal wiring arranged in different layers to adjust the gate of the driving transistor. and the potential state of the anode of the light-emitting element, thereby improving the stability of the driving current to improve the uniformity of display brightness and display color shift.
  • the layout space utilization can be improved, the layout structure can be optimized, and the display PPI can be improved.
  • Figure 1 is a schematic top structural view of an array substrate provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural diagram of an array substrate provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 7 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 8 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 9 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 10 is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 11 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 13 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 14 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 15 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 16 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 17 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 18 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 19 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 20 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 21 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 22 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 23 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 24 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • Figure 25 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 26 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • Figure 27 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 28 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic top view structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate shown in FIG. 1 can be along the cross-section line AA'.
  • Figure 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the array substrate provided by an embodiment of the present application includes: a substrate 21; 21 side of the active layer 10 and the multi-layer metal layer, a plurality of pixel circuits are formed in the array substrate, and the pixel circuit includes a driving transistor T1, a first initialization transistor T2 and a second initialization transistor T3.
  • the multi-layer metal layer at least includes a first metal trace 11 extending along a first direction and a second metal trace 12 extending along a second direction.
  • the first metal trace 11 and the second metal trace 12 are located on different layers.
  • the first initialization transistor T2 is connected between the first metal line 11 and the gate of the driving transistor T1, and is configured to transmit the first initialization voltage Vref1 on the first metal line 11 to the gate of the driving transistor T1.
  • Two initialization transistors T3 are connected between the second metal trace 12 and the light-emitting element D1; the second initialization transistor T3 is configured to transmit the second initialization voltage Vref2 on the second metal trace 12 to the light-emitting element D1; the first direction and The second directions intersect and are both perpendicular to the thickness direction of the array substrate.
  • the first initialization transistor T2 is connected between the first metal trace 11 and the gate of the driving transistor T1. It can be understood that one of the source electrode or the drain electrode of the first initialization transistor T2 is electrically connected to the first metal trace 11. , the other electrode of the source or drain of the first initialization transistor T2 is electrically connected to the gate of the driving transistor T1.
  • the second initialization transistor T3 is connected between the second metal line 12 and the light-emitting element D1. It can be understood that one of the source electrode or the drain electrode of the second initialization transistor T3 is electrically connected to the second metal line 12, and the second initialization transistor T3 is electrically connected to the second metal line 12.
  • the other electrode of the source electrode or the drain electrode of the initialization transistor T3 is electrically connected to the light-emitting element D1.
  • the electrical connection may be a direct connection or an indirect connection.
  • the substrate 21 can be used to provide protection and support for the array substrate, wherein the substrate 21 can be polyimide (PI), polyethylene naphthalate two formic acid glycol.
  • PI polyimide
  • a flexible substrate made of materials such as ester (PEN) or polyethylene terephthalate (PET), or a hard substrate made of materials such as glass.
  • the active layer 10 and a multi-layer metal layer are sequentially provided on one side of the substrate 21 .
  • the multi-layer metal layers are isolated from each other by an insulating layer.
  • the multi-layer metal layer includes a first metal layer M1 , a second metal layer M2 and In the third metal layer M3, a first interlayer insulating layer 22 is provided between the active layer 10 and the first metal layer M1, and a second interlayer insulating layer 23 is provided between the first metal layer M1 and the second metal layer M2. , a third interlayer insulating layer 24 is provided between the second metal layer M2 and the third metal layer M3, and a fourth interlayer insulating layer 25 is provided on the side of the third metal layer M3 away from the substrate 21.
  • the active layer 10 may be formed of polysilicon, metal oxide and other materials.
  • a plurality of pixel circuits are formed on the array substrate for generating driving current to drive the light-emitting element D1 connected to the pixel circuit to emit light.
  • the pixel circuit is formed of at least a thin film transistor including at least a driving transistor T1, a first initialization transistor T2, and a second initialization transistor T3.
  • the first initializing transistor T2 is configured to initialize the gate potential of the driving transistor T1
  • the second initializing transistor T3 is configured to initialize the anode potential of the light-emitting element D1.
  • the data voltage on the data line Data is written to the gate of the driving transistor T1 through the data writing transistor T4, the driving transistor T1 and the threshold compensation transistor T5, and is stored on the storage voltage Cst to realize data writing and threshold compensation. Function.
  • the driving transistor T1 When the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on, the driving transistor T1 generates a driving current to drive the light-emitting element D1 to emit light
  • the first initialization voltage Vref1 is provided by the first metal trace 11
  • the second initialization voltage Vref2 is provided by the second metal trace 12
  • the first metal trace 11 extends along the first direction
  • the second metal trace 12 extends along the second direction.
  • the first direction may be the Y direction
  • the second direction may be the X direction
  • both the X direction and the Y direction are perpendicular to the thickness direction of the array substrate (ie, the Z direction).
  • the first metal trace 11 and the second metal trace 12 are respectively formed of different layers of metal in the multi-layer metal layer.
  • the first metal trace 11 is located in the third metal layer M3
  • the second metal trace 12 is located in the second metal layer M2
  • the first metal trace 11 transmits the first initialization voltage Vref1 to the first initialization transistor T2
  • the second metal trace 11 is located in the second metal layer M2.
  • the trace 12 transmits the second initialization voltage Vref2 to the second initialization transistor T3.
  • corresponding initialization voltages can be provided to the gate of the driving transistor T1 and the anode of the light-emitting element D1 through the first metal wiring 11 and the second metal wiring 12 arranged in different layers, so as to enhance the threshold compensation of the driving transistor T1
  • the effect is to improve the uniformity of the driving current and reduce the influence of the parasitic capacitance of the light-emitting element D1 on the driving current, so as to reduce the color shift.
  • it can also optimize the layout structure, which is beneficial to improving the space utilization of the layout and increasing the display pixel density (PixelsPerInch, PPI).
  • the first metal trace 11 and the second metal trace 12 can also provide the same initializing voltage to the gate of the driving transistor T1 and the anode of the light-emitting element D1.
  • the pixel circuit is controlled through the driving timing to enhance the threshold compensation effect of the driving transistor T1, improve the uniformity of the driving current, and reduce the impact of the parasitic capacitance of the light-emitting element D1 on the driving current to reduce the color shift. Its specific work The principle will be described in the following examples.
  • the technical solution provided by the embodiments of the present application is to stack an active layer and a multi-layer metal layer on a substrate, wherein the multi-layer metal layer at least includes a first metal trace extending along a first direction and a first metal trace extending along a second direction.
  • the second metal trace, the first metal trace and the second metal trace are located on different layers, the first initialization transistor is connected between the first metal trace and the gate of the driving transistor, and is configured to connect the first metal trace to the second metal trace.
  • the first initialization voltage is transmitted to the gate of the driving transistor, and the second initialization transistor is connected between the second metal line and the light-emitting element; the second initialization transistor is configured to transmit the second initialization voltage on the second metal line to Light emitting components.
  • the technical solution provided by the embodiment of the present application can provide corresponding initialization voltages to the corresponding first initialization transistor and second initialization transistor respectively through the first metal wiring and the second metal wiring arranged in different layers to adjust the gate of the driving transistor. and the potential state of the anode of the light-emitting element, thereby improving the stability of the driving current to improve the uniformity of display brightness and display color shift.
  • the layout space utilization can be improved, the layout structure can be optimized, and the display PPI can be improved.
  • the first metal trace 11 includes first sub-metal traces 111 and second sub-metal traces 112 arranged in multiple columns, wherein each first sub-metal trace 111 is arranged in one column, and the plurality of sub-metal traces 111 are arranged in one column.
  • the second sub-metal traces 112 are arranged in a row; the first initialization transistor T2 is connected between the first sub-metal trace 111 and the gate of the driving transistor T1; the second initialization transistor T3 is connected to the second sub-metal trace 112 .
  • the multi-layer metal layer also includes third metal traces 13 and fourth metal traces 14, which are first scan lines and second scan lines respectively.
  • the third metal traces 13 and the fourth metal traces 14 are respectively along the first scan line and the second scan line. Extending in two directions, the vertical projection of the second metal trace 12 on the substrate 21 is between the vertical projection of the third metal trace 13 on the substrate 21 and the vertical projection of the fourth metal trace 14 on the substrate 21 , the third metal trace 13 and the fourth metal trace 14 may both be located on the first metal layer, the third metal trace 13 overlaps with the active layer 10 to form the first initialization transistor T2, and the fourth metal trace 14 is connected to the active layer 10.
  • the source layers 10 are overlapped to form the second initialization transistor T3.
  • the transistor formed by overlapping the third metal trace 13 and the active layer 10 is set as the second initialization transistor T3 in the previous row of pixel circuits adjacent to the current row of pixel circuits.
  • a single first sub-metal trace 111 is arranged in a row along the first direction, and a plurality of second sub-metal traces 112 are arranged in a row along the first direction.
  • the first sub-metal trace 111 and the second sub-metal trace 112 are insulated from each other.
  • the first end of the first initialization transistor T2 is connected to the first sub-metal line 111, the second end of the first initialization transistor T2 is connected to the gate of the driving transistor T1, and the first sub-metal line 111 is set to the first initialization state.
  • Transistor T2 provides the first initialization voltage Vref1.
  • the first end of the second initialization transistor T3 is connected to the first end of the second sub-metal line 112 , the second end of the second sub-metal line 112 is connected to the second metal line 12 , and the second end of the second initialization transistor T3 is connected to the first end of the second sub-metal line 112 . Both ends are connected to the anode of the light-emitting element D1.
  • the second sub-metal trace 112 serves as a switch to transmit the second initialization voltage Vref2 provided by the second metal trace 12 to the first end of the second initialization transistor T3.
  • the first initialization voltage Vref1 on the first metal trace 11 and the second initialization voltage Vref2 on the second metal trace 12 may be different.
  • the first initialization voltage Vref1 may be smaller than the second initialization voltage Vref2. Since the first initialization voltage Vref1 is small, it can pull the gate voltage of the driving transistor T1 to a lower potential, so that the gate potential of the driving transistor T1 is completely reset. For different pixel circuits, it can ensure that the data voltage can be completely written to The gate of the driving transistor T1 thereby strengthens the threshold compensation effect on the driving transistor T1, which is beneficial to improving the uniformity of the driving current and improving the image sticking condition.
  • FIG. 4 is a schematic top structural view of another array substrate provided by an embodiment of the present application, specifically showing a partial structure of the array pixel circuit.
  • the first sub-metal trace 111 extends along the Y direction and is connected with the first sub-metal trace 111 of the pixel circuit corresponding to the upper and lower rows to form a vertical line.
  • Each first sub-metal trace Lines 111 are all arranged in a row.
  • the second metal traces 12 extend along the X direction and are connected to the second metal traces 12 of the pixel circuits corresponding to the left and right columns to form horizontal lines.
  • the second sub-metal trace 112 extends along the Y direction, is connected to the second metal trace 12 , and is connected to the second initialization transistor T3 through the active layer 10 , so that the plurality of second sub-metal traces 112 are arranged in a row. . Among them, the specific structure of a single pixel circuit is shown in the dotted box.
  • the third metal wiring 13 or the fourth metal wiring 14 corresponding to the pixel circuits in two adjacent rows above and below can be shared, that is, the fourth metal wiring 14 corresponding to the n-th row of pixel circuits can be multiplexed into the n-th row of pixel circuits.
  • the fourth metal trace 14 of the n-th row pixel circuit overlaps with the third metal trace 13 of the n+1-th row pixel circuit. That is, the second scan line of the nth row is used as the first scan line of the n+1th row, which saves layout space and results in a higher PPI.
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a first leakage compensation transistor T8 and a second leakage compensation transistor T9.
  • the first leakage compensation transistor T8 is connected between the gate electrode of the driving transistor T1 and the second electrode of the second leakage compensation transistor T9.
  • the first electrode of the second leakage compensation transistor T9 is connected to the first initialization transistor T2.
  • the gate electrode of the first leakage compensation transistor T8 and the gate electrode of the second leakage compensation transistor T9 are connected to the same scan line, and are configured to turn off the leakage path of the driving transistor T1 when the data writing is completed, reduce the leakage current, and maintain driving The gate potential of transistor T1 is stable.
  • the pixel circuit further includes a first storage capacitor C1 , which is connected to the second electrode of the second leakage compensation transistor T9 and is configured to store the potential of the second electrode of the second leakage compensation transistor T9 .
  • a first storage capacitor C1 which is connected to the second electrode of the second leakage compensation transistor T9 and is configured to store the potential of the second electrode of the second leakage compensation transistor T9 .
  • the parasitic capacitance between the gate of the first leakage compensation transistor T8 and the gate of the driving transistor T1 is coupled, and the gate of the driving transistor T1 is The potential coupling makes the gate potential of the driving transistor T1 close to the first pole potential of the first leakage compensation transistor T8 (the gate of the driving transistor T1 is connected to the second pole of the first leakage compensation transistor T8, and the gate potential of the first leakage compensation transistor T8 is The first electrode is connected to the second electrode of the second leakage compensation transistor T9). Therefore, the voltage difference between the first electrode and the second electrode of the first leakage compensation transistor T8 is small, so
  • FIG. 6 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • the second storage capacitor C2 is not shown in FIG. 6 .
  • the multi-layer metal layer includes a first metal layer M1, a second metal layer M2, and a third metal layer M3.
  • the first metal layer M1 includes the gate of the driving transistor T1, the third metal trace 13,
  • the fourth metal trace 14 , the second metal layer M2 includes the second metal trace 12
  • the third metal layer M3 includes the first metal trace 11 .
  • the multi-layer metal layer also includes a fifth metal trace 15 used as a third scan line EMB, where the fifth metal trace 15 is in a different layer from the first metal trace 11 and the second metal trace 12 .
  • the fifth metal trace 15 is located on the first metal layer M1.
  • the vertical projection of the fifth metal trace 15 on the substrate is located on one side of the vertical projection of the second metal trace 12 on the substrate, and does not overlap with the vertical projection of the second metal trace 12 on the substrate, That is, staggered from the vertical projection of the second metal trace 12 on the substrate, the fifth metal trace 15 overlaps with the active layer 10 to form the first leakage compensation transistor T8 and the second leakage compensation transistor T9 respectively.
  • the second metal trace 12 is connected to the first storage capacitor C1.
  • the first storage capacitor C1 can be formed by overlapping the second metal trace 12 and the active layer 10, which is beneficial to saving layout space.
  • the multi-layer metal layer further includes sixth metal traces 16 and seventh metal traces 17 extending along the second direction, which are the fourth scan line S3 and the fifth scan line EM respectively.
  • the sixth metal trace 16 overlaps with the active layer 10 to form the data writing transistor T4 and the threshold compensation transistor T5 respectively
  • the seventh metal trace 17 overlaps with the active layer 10 to form the first light emission control transistor T6 and T5 respectively.
  • the second light emission control transistor T7 is the sixth metal traces 16 and seventh metal traces 17 extending along the second direction, which are the fourth scan line S3 and the fifth scan line EM respectively.
  • the active layer 10 overlapped with the sixth metal trace 16 to form the data writing transistor T4 is connected to the data line Data through a via hole, and the active layer 10 overlapped with the seventh metal trace 17 to form the first light emission control transistor T6 It is connected to the first power supply line VDD through a via hole (the second power supply line VSS is not shown in the figure).
  • first initialization voltage Vref1 and the second initialization voltage Vref2 can be adjusted independently.
  • FIG. 7 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • the second sub-metal wire 112 and the first sub-metal wire 111 are connected to form a mesh. That is to say, the first sub-metal trace 111 and the second sub-metal trace 112 are connected together. Since the second sub-metal trace 112 is also connected to the second metal trace 12, the first metal trace 11 and the second metal trace 12 are connected to each other to form a horizontal and vertical mesh structure.
  • the first initialization voltage Vref1 is equal to the second initialization voltage Vref2, that is, the second initialization voltage Vref2 can be multiplexed into the first initialization voltage Vref1.
  • FIG. 8 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • the first end of the first metal trace 11 is connected to the second metal trace 12
  • the second end of the first metal trace 11 is connected to the first initialization transistor T2 and the second initialization transistor T3 .
  • the difference from the layout structure shown in FIG. 7 is that the layout structure shown in FIG. 8 does not have the first sub-metal wiring 111.
  • the first metal wiring 11 is used to realize the connection between the second metal wiring 12 and the first initialization transistor T2 and the first sub-metal wiring 111.
  • the connection of the two initialization transistors T3, that is to say, the first initialization transistor T2 and the second initialization transistor T3 are indirectly connected to the second metal wire 12 through the first metal wire 11, and the second metal wire 12 on the second metal wire 12
  • the initialization voltage Vref2 is transmitted to the gate of the driving transistor T1 and the anode of the light-emitting element D1 through the first initialization transistor T2 and the second initialization transistor T3 respectively.
  • the second initializing voltage Vref2 is the first initializing voltage Vref1.
  • first sub-metal line 111 transmitting the first initialization voltage Vref1
  • FIG. 9 is a schematic top view of another array substrate provided by an embodiment of the present application.
  • the difference between the layout structure shown in Figure 9 and the layout structure shown in Figure 8 is that the structure of the active layer 10 is different.
  • a second leakage compensation transistor T9 is formed on the left side of the first leakage compensation transistor T8.
  • the third metal trace 13 includes a first main body part 131 and a first branch part 132.
  • the fourth metal trace 14 includes a second main body part 141 and a second branch part 142.
  • the first main body part 131 and the second main body part 141 are arranged along Extending in the second direction, the first branch portion 132 and the second branch portion 142 extend in the first direction.
  • the active layer 10 forming the second leakage compensation transistor T9 extends upward in the first direction, and then extends in the second direction to overlap with the first branch portion 132 of the third metal trace 13 to form the first initialization transistor T2.
  • the first main body portion 131 of the trace 13 overlaps with the active layer 10 to form the second initialization transistor T3 of the pixel circuit of the previous row.
  • the second main body portion 141 of the fourth metal trace 14 overlaps with the active layer 10 extending in the first direction to form the second initialization transistor T3 of the pixel circuit of this row.
  • the second branch portion 142 of the fourth metal trace 14 is The active layer 10 extending in the second direction forms the first initialization transistor T2 of the next row of pixel circuits.
  • the principle of the pixel circuit shown in Figure 9 is the same as that of the pixel circuit shown in Figures 8 and 6, and its specific working process will be introduced in detail in subsequent descriptions.
  • the vertical projection of the second metal trace 12 on the substrate 21 is located between the vertical projection of the fifth metal trace 15 on the substrate 21 and the vertical projection of the sixth metal trace 16 on the substrate 21 . between vertical projections, and the fifth metal trace 15 is located on the side of the second metal trace 12 away from the driving transistor T1.
  • FIG. 10 is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 11 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application, which is suitable for the pixel circuit shown in FIG. 5 .
  • Figure 11 specifically shows the driving timing of the black insertion stage.
  • this embodiment is only explained by taking the plurality of transistors as P-type transistors as an example. In other embodiments, the plurality of transistors may be N-type transistors.
  • the working process of the pixel circuit provided by the embodiment of the present application at least includes an initialization stage t1, a data writing stage t2, a voltage normalization stage t3, a light emitting stage t4, and a black insertion stage t5.
  • the first scan signal transmitted on the first scan line S1 is low level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the third scan signal transmitted on the third scan line EMB is high level.
  • the signal is low level
  • the fourth scanning signal transmitted on the fourth scanning line S3 is high level
  • the fifth scanning signal transmitted on the fifth scanning line EM is high level. Therefore, the first initialization transistor T2, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor T1 to initialize the gate potential of the driving transistor T1.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is low level
  • the third scan signal transmitted on the third scan line EMB is low level
  • the third scan signal is low level
  • the fourth scan signal transmitted on the fourth scan line S3 is low level
  • the fifth scan signal transmitted on the fifth scan line EM is high level. Therefore, the data writing transistor T4, the threshold compensation transistor T5, the second initialization transistor T3, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are turned on, and the data voltage on the data line Data is written to the gate of the driving transistor T1 pole.
  • the driving transistor T1 When the gate voltage of the driving transistor T1 reaches Vdata+Vth, the driving transistor T1 is turned off, and the voltage is stored on the first storage capacitor C1 and the second storage capacitor C2, where Vdata is the data voltage and Vth is the threshold voltage of the driving transistor. .
  • the second initialization voltage Vref2 is written to the anode of the light-emitting element D1 through the second initialization transistor T3, thereby initializing the anode potential of the light-emitting element D1.
  • the gate voltage of the driving transistor T1 is not equal to the storage voltage on the first storage capacitor C1.
  • the third scan signal transmitted on the third scan line EMB jumps from low level to high level.
  • the gate of the drive transistor T1 The voltage of the first electrode of the first leakage compensation transistor T8 is pulled up to be close to the voltage stored on the first storage capacitor C1, so the voltage difference between the first electrode and the second electrode of the first leakage compensation transistor T8 is small, so that the leakage current of the first leakage compensation transistor T8 Small, so as to maintain the stability of the gate voltage of the driving transistor T1.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the third scan signal transmitted on the third scan line EMB is high level.
  • the signal is high level
  • the fourth scanning signal transmitted on the fourth scanning line S3 is high level
  • the fifth scanning signal transmitted on the fifth scanning line EM is low level. Therefore, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on, the driving transistor T1 generates a driving current, and the light-emitting element D1 is driven to emit light. Since the gate voltage of the driving transistor T1 can remain stable for a long time, the uniformity of the driving current can be ensured and image sticking on the display screen can be improved.
  • the pixel circuit When the fifth scan signal transmitted on the fifth scan line EM jumps from low level to high level, the pixel circuit enters the black insertion stage t5. In the black insertion stage t5, the third scan signal transmitted on the third scan line EMB is always at a high level, and the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are in an off state.
  • the fourth scan signal transmitted on the fourth scan line S3 maintains a high level, and the low levels of the first scan signal transmitted on the first scan line S1 and the second scan signal transmitted on the second scan line S2 arrive successively. Since the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are in the off state, the first initialization voltage Vref1 is not written to the gate of the driving transistor T1, and only the second initialization voltage Vref2 is written to the anode of the light-emitting element D1 , to reset the anode potential of the light-emitting element D1.
  • the fifth scan signal transmitted on the fifth scan line EM jumps from high level to low level, and the light-emitting element D1 continues to emit light.
  • the black insertion stage can be performed multiple times.
  • the black insertion stage and resetting the anode potential of the light-emitting element D1 during the black insertion stage the low-frequency brightness component that is easily perceived by the human eye can be completely converted into High-frequency brightness components that are not easily perceived, thereby improving the flickering phenomenon of the display screen.
  • FIG. 12 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit also includes a first voltage writing control transistor T10.
  • the first voltage writing control transistor T10 and the data writing transistor T4 are connected in series to the data lines Data and Between the first pole of the driving transistor T1, the gate of the first voltage writing control transistor T10 is connected to the third scanning signal transmitted on the third scanning line EMB.
  • the driving timing shown in FIG. 11 can be used to drive the pixel circuit shown in FIG. 12 .
  • the fourth scan signal transmitted on the fourth scan line S3 and the second scan signal transmitted on the second scan line S2 are the same, so that the fourth scan signal transmitted on the fourth scan line S3 is in the black insertion phase t5
  • the scanning frequency of the scanning signal connected to the gate of the data writing transistor T4 is the same as the scanning signal connected to the gate of the first initialization transistor T2 and the scanning frequency connected to the gate of the second initialization transistor T3.
  • the scanning frequency of the scanning signal is higher than the preset high scanning frequency.
  • the preset high scanning frequency may be 60 Hz, and signals with a scanning frequency higher than the preset high scanning frequency are all high frequency signals.
  • the scanning signals on the first scanning line S1, the second scanning line S2 and the fourth scanning line S3 are all high-frequency signals.
  • the preset high scanning frequency may also be 75 Hz, 100 Hz or 120 Hz, etc., which is not specifically limited in this embodiment.
  • the first leakage compensation transistor T8 can maintain a low leakage current.
  • the fourth scan signal transmitted on the fourth scan line S3, the first scan signal transmitted on the first scan line S1, and the second scan signal transmitted on the second scan line S2 are all high-frequency signals, the first scan signal , the second scan signal and the fourth scan signal can be generated by the same set of gate drive circuits, which is beneficial to realizing narrow frame design.
  • FIG. 13 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 14 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present application, where FIG. 14 specifically shows the driving timing of the black insertion stage.
  • the driving timings shown in Figures 13 and 14 are applicable to the pixel circuit shown in Figure 12.
  • the working process of this pixel circuit is as follows:
  • the first scan signal transmitted on the first scan line S1 is low level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the third scan line EMB The third scan signal transmitted on the fourth scan line S3 is at a low level
  • the fourth scan signal transmitted on the fourth scan line S3 is at a high level
  • the fifth scan signal transmitted on the fifth scan line EM is at a high level. Therefore, the first initialization transistor T2, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor T1 to initialize the gate potential of the driving transistor T1.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is low level
  • the third scanning signal transmitted on line EMB is low level
  • the fourth scanning signal transmitted on fourth scanning line S3 is low level
  • the fifth scanning signal transmitted on fifth scanning line EM is high level. Therefore, the data writing transistor T4, the threshold compensation transistor T5, the second initialization transistor T3, the first voltage writing control transistor T10, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are turned on and connected with the data line Data. A voltage related to the data voltage is written to the gate of the driving transistor T1.
  • the driving transistor T1 When the gate voltage of the driving transistor T1 reaches Vdata+Vth, the driving transistor T1 is turned off, and the voltage is stored on the first storage capacitor C1 and the second storage capacitor C2, where Vdata is the data voltage and Vth is the threshold voltage of the driving transistor. .
  • the second initialization voltage Vref2 is written to the anode of the light-emitting element D1 through the second initialization transistor T3 to initialize the anode potential of the light-emitting element D1.
  • the gate voltage of the driving transistor T1 is close to the storage voltage on the first storage capacitor C1.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the fourth scan signal transmitted on the fourth scan line S3 is high level.
  • the scanning signal is high level
  • the fifth scanning signal transmitted on the fifth scanning line EM is high level.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the third scan signal transmitted on the third scan line EMB is high level.
  • the scanning signal is high level
  • the fourth scanning signal transmitted on the fourth scanning line S3 is low level
  • the fifth scanning signal transmitted on the fifth scanning line EM is high level. Therefore, the data writing transistor T4 and the threshold compensation transistor T5 are turned on, and the second electrode of the driving transistor T1 is connected with the first electrode of the first leakage compensation transistor T8. At this time, since the first voltage writing control transistor T10 is turned off, the data voltage on the data line Data is not written to the driving transistor T1.
  • the first scan signal transmitted on the first scan line S1 is high level
  • the second scan signal transmitted on the second scan line S2 is high level
  • the third scan signal transmitted on the third scan line EMB is high level.
  • the scanning signal is low level
  • the fourth scanning signal transmitted on the fourth scanning line S3 is high level
  • the fifth scanning signal transmitted on the fifth scanning line EM is high level. Therefore, the first voltage writing control transistor T10, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are turned on, and the gate electrode of the driving transistor T1 and the first electrode of the first leakage compensation transistor T8 are connected. Finally, the gate voltage of the driving transistor T1 increases slightly as the sub-threshold swing of the driving transistor T1 increases, which can compensate for the sub-threshold swing and thereby improve the uneven display phenomenon at low gray levels.
  • the first scanning signal transmitted on the first scanning line S1 is high level
  • the second scanning signal transmitted on the second scanning line S2 is high and low level
  • the third scanning line EMB The third scan signal transmitted is high level
  • the fourth scan signal transmitted on the fourth scan line S3 is high level
  • the fifth scan signal transmitted on the fifth scan line EM is low level. Therefore, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on, the driving transistor T1 generates a driving current, and the light-emitting element D1 is driven to emit light.
  • the fifth scan signal transmitted on the fifth scan line EM changes from low level to high level, the light-emitting element D1 goes out, and the pixel circuit enters the seventh stage t17 (corresponding to the black insertion stage).
  • the fourth scan signal transmitted on the fourth scan line S3 maintains a high level, and the low levels of the first scan signal transmitted on the first scan line S1 and the second scan signal transmitted on the second scan line S2 arrive successively.
  • the first scan signal is low level, the first initialization transistor T2 is turned on, but since the second leakage compensation transistor T9 and the first leakage compensation transistor T8 are turned off, the first initialization voltage Vref1 is not transmitted to the driving transistor T1 The gate will not affect the normal operation of the pixel circuit.
  • the second initialization transistor T3 When the second scan signal is low level, the second initialization transistor T3 is turned on, and the second initialization voltage Vref2 is transmitted to the anode of the light-emitting element D1 to initialize the anode potential of the light-emitting element D1.
  • the fifth scan signal transmitted on the fifth scan line EM jumps from high level to low level, and the light-emitting element D1 continues to emit light.
  • FIG. 15 is a schematic top structural view of another array substrate provided by an embodiment of the present application, for example, a schematic top structural view corresponding to the pixel circuit shown in FIG. 12 .
  • the active layer 10 forming the data writing transistor T4 extends upward along the first direction and overlaps with the fifth metal trace 15 to form the first voltage writing control transistor T10 , and the active layer 10 passes through The hole is connected to the data line Data.
  • the connection structure of other multiple transistors is the same as the layout structure of the pixel circuit shown in FIG. 6 and will not be described again here.
  • FIG. 16 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • the first sub-metal trace 111 and the second sub-metal trace 112 can be connected together, so that the second metal trace 12 and the first sub-metal trace 111 are connected to form a network. shape structure, which is conducive to signal transmission.
  • the connection between the second metal wire 12 and the first initialization transistor T2 and the second initialization transistor T3 is realized through the first metal wire 11 . That is to say, the first initialization transistor T2 and the second initialization transistor T3 are indirectly connected to the second metal wire 12 through the first metal wire 11, and the second initialization voltage Vref2 on the second metal wire 12 passes through the first metal wire 11.
  • the initialization transistor T2 and the second initialization transistor T3 transmit to the gate of the driving transistor T1 and the anode of the light-emitting element D1. Since there is no vertical line (first sub-metal line 111) transmitting the first initialization voltage Vref1, greater light transmittance can be obtained.
  • first sub-metal line 111 transmitting the first initialization voltage Vref1
  • FIG. 17 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a second voltage writing control transistor T11, and the second voltage writing control transistor T11 is connected to the second pole and the second leakage of the driving transistor T1. between the second pole of compensation transistor T9.
  • the second voltage writing control transistor T11 may be a double-gate transistor or a single-gate transistor.
  • the second voltage writing control transistor T11 and the first leakage compensation transistor T8 are connected to the same scanning signal. Therefore, the pixel circuit is also suitable for the driving timings shown in FIGS. 10 and 11 , and also for the driving timings shown in FIGS. 13 and 14 .
  • the second voltage writing control transistor T11 and the threshold compensation transistor T5 are connected in series, during the black insertion phase, since the fifth scanning signal transmitted on the fifth scanning line EM is always at a high level, the second voltage writing control transistor T11 , the second leakage compensation transistor T9 and the first leakage compensation transistor T8 are always off, so even if the data writing transistor T2 and the threshold compensation transistor T5 are turned on, the data voltage will not be written to the gate of the driving transistor T1 , which can ensure the normal operation of the pixel circuit. Therefore, the second scan signal transmitted on the second scan line S2 can be set as a high-frequency signal, and the first scan signal and the fourth scan signal can be generated by the same set of gate drive circuits, which is beneficial to realizing a narrow frame design.
  • FIG. 18 is a schematic structural diagram of another array substrate provided by an embodiment of the present application, for example, the layout structure corresponding to the pixel circuit shown in FIG. 17 .
  • the active layer 10 overlapping the second metal trace 12 extends along the first direction and overlaps the fifth metal trace 15 , so that the fifth metal trace 15
  • the overlapping portions of the active layer 10 respectively form a second voltage writing control transistor T11 (including a first sub-transistor T11-1 and a second sub-transistor T11-2), a first leakage compensation transistor T8 and a second leakage compensation transistor T9. , in a limited space, improving the space utilization of the layout.
  • FIG. 19 is a schematic structural diagram of another array substrate provided by an embodiment of the present application, for example, another layout structure corresponding to the pixel circuit shown in FIG. 17 .
  • the first sub-metal trace 111 and the second sub-metal trace 112 are connected together. Since the second sub-metal trace 112 is also connected to the second metal trace 12, therefore, the first metal trace 11 and The second metal traces 12 are connected to each other to form a horizontal and vertical mesh structure.
  • the threshold compensation effect of the drive transistor T1 can be improved through the drive timing (double pulse timing as shown in Figure 13), thereby improving the drive current inconsistency. Uniform situation to improve display effect.
  • Figure 20 is a schematic structural diagram of another array substrate provided by an embodiment of the present application, for example, another layout structure corresponding to the pixel circuit shown in Figure 17.
  • the third metal trace 13 includes a first main body part 131 and a first branch part 132
  • the fourth metal trace 14 includes a second main body part 141 and a second branch part 142 , the first main body part 131 and the second branch part 142 .
  • the main body part 141 extends along the second direction
  • the first branch part 132 and the second branch part 142 extend along the first direction.
  • the active layer 10 forming the second leakage compensation transistor T9 extends upward in the first direction, and then extends in the second direction to overlap with the first branch portion 132 of the third metal trace 13 to form the first initialization transistor T2.
  • the first main body portion 131 of the trace 13 overlaps with the active layer 10 to form the second initialization transistor T3 of the pixel circuit of the previous row.
  • the second main body portion 141 of the fourth metal trace 14 overlaps with the active layer 10 extending in the first direction to form the second initialization transistor T3 of the pixel circuit of this row.
  • the second branch portion 142 of the fourth metal trace 14 is The active layer 10 extending in the second direction forms the first initialization transistor T2 of the next row of pixel circuits.
  • connection between the second metal wire 12 and the first initialization transistor T2 and the second initialization transistor T3 is realized through the second sub-metal wire 112.
  • the vertical line of the first initialization voltage Vref1 so greater light transmittance can be obtained.
  • Figure 21 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 22 is a schematic structural diagram of another array substrate provided by an embodiment of the present application. They are respectively another layout corresponding to the pixel circuit shown in Figure 17 structure.
  • the second voltage writing control transistor T11 is a single-gate transistor. Referring to FIG. 21 and FIG. 22 , the only difference between the two is that the formation positions of the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are opposite. The other structures are exactly the same.
  • the vertical projection of the fifth metal trace 15 on the substrate is between the vertical projection of the sixth metal trace 16 on the substrate and the vertical projection of the second metal trace 12 on the substrate, This can make the distance between the first leakage compensation transistor T8 and the gate of the driving transistor T1 shorter, that is, the leakage path of the gate of the driving transistor T1 is shorter, which is beneficial to reducing the potential of other signals on the gate of the driving transistor T1
  • the coupling effect can reduce crosstalk between multiple pixel circuits.
  • FIG. 23 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 24 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • FIG. 24 is a layout structure corresponding to the pixel circuit shown in FIG. 23 .
  • the pixel circuit can simultaneously include a first voltage write control transistor T10 and a second voltage write control transistor T11, and the first voltage write control transistor T10, The second voltage writing control transistor T11, the first leakage compensation transistor T8 and the second leakage compensation transistor T9 are all connected to the fifth metal line (the third scanning line EMB).
  • FIG. 25 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 26 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • FIG. 26 is a layout structure corresponding to the pixel circuit shown in FIG. 25 .
  • the threshold compensation transistor T5 can be removed, and the second voltage write control transistor T11 is multiplexed as the threshold compensation transistor T5, which is beneficial to reducing the number of transistors. Reduce the space occupied by the layout.
  • the vertical projection of the second metal trace 12 on the substrate is located between the vertical projection of the fifth metal trace 15 on the substrate and the vertical projection of the sixth metal trace 16 on the substrate. between the vertical projections, and the vertical projection of the fifth metal trace 15 on the substrate is located on the side of the vertical projection of the second metal trace 12 on the substrate close to the vertical projection of the gate of the driving transistor T1 on the substrate , thus the distance between the first leakage compensation transistor T8 formed by overlapping the fifth metal trace 15 and the active layer 10 and the gate of the driving transistor T1 can be further shortened, which is beneficial to reducing the impact of other signals on the gate of the driving transistor T1
  • the coupling effect of the polar potential can reduce the crosstalk between multiple pixel circuits.
  • the first metal traces 11 can also be connected with the second metal traces 12 to form a mesh structure, or the first metal traces 11 can be removed and the second metal traces 12 can be used.
  • the two metal traces 12 provide initialization voltages for the first initialization transistor T2 and the second initialization transistor T3. The specific connection relationship will not be described again here. You can refer to the relevant descriptions in any of the above embodiments.
  • FIG. 27 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 28 is a schematic top structural view of another array substrate provided by an embodiment of the present application.
  • FIG. 28 is a layout structure corresponding to the pixel circuit shown in FIG. 27 .
  • the threshold compensation transistor T5 can be set as a double-gate transistor to further reduce the gate voltage of the driving transistor T1. leakage current.
  • the sixth metal trace 16 overlaps with the active layer 10 to respectively form the threshold compensation transistor T5 (including the third sub-transistor T5-1 and the fourth sub-transistor T5-2) and the data writing transistor T4.
  • the array substrate provided by the embodiment of the present application can reduce the gate leakage of the driving transistor, which is beneficial to stabilizing the driving current, thereby improving the uniformity of the display screen.
  • the first metal trace and the second metal trace can transmit different voltages to independently adjust the gate potential of the driving transistor and the anode of the light-emitting element. Potential, so that the improvement of low-grayscale color cast and low-frequency flicker no longer restrict each other, and it can also improve the image afterimage, thereby greatly improving the display effect.
  • the first metal trace and the second metal trace are in different layers, the first metal trace and the second metal trace can be laid out in a limited space, which is beneficial to improving the utilization rate of the layout space.
  • embodiments of the present application also provide a display panel, including the array substrate provided by any embodiment of the present application. Therefore, the display panel also has the beneficial effects described in any of the above embodiments.
  • FIG. 29 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: a television , laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted monitors, medical equipment, industrial control equipment, touch interactive terminals, etc.
  • the embodiments of this application are not particularly limited.
  • Steps can be reordered, added, or removed using various forms of the process shown above.
  • multiple steps described in this application can be executed in parallel, sequentially, or in different orders.
  • the desired results of the technical solution of this application can be achieved, there is no limitation here.

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Abstract

本申请公开了一种阵列基板、显示面板和显示装置，该阵列基板包括衬底，有源层和多层金属层，阵列基板中形成有多个像素电路，像素电路包括驱动晶体管、第一初始化晶体管和第二初始化晶体管；多层金属层至少包括沿第一方向延伸的第一金属走线和沿第二方向延伸的第二金属走线，第一金属走线和第二金属走线位于不同层，第一初始化晶体管连接于第一金属走线和驱动晶体管的栅极之间，设置为将第一金属走线上的第一初始化电压传输至驱动晶体管的栅极；第二初始化晶体管连接于第二金属走线和发光元件之间，设置为将第二金属走线上的第二初始化电压传输至发光元件。本申请提供的技术方案能够提高驱动电流的稳定性，以改善显示亮度的均一性和显示色偏的情况。

Description

阵列基板、显示面板和显示装置
本申请要求在2022年6月28日提交中国专利局、申请号为202210751702.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种阵列基板、显示面板和显示装置。
背景技术
随着显示技术的发展，人们对于显示装置的性能要求越来越高。
目前，显示面板中的像素电路普遍存在漏电问题，这将引起显示亮度的变化，导致人眼容易识别到显示画面的异常现象，影响了显示装置的显示效果。
发明内容
本申请提供了一种阵列基板、显示面板和显示装置，以改善显示画面的显示效果。
根据本申请的一方面，提供了一种阵列基板，包括：衬底；
层叠设置于所述衬底一侧的有源层和多层金属层，所述阵列基板中形成有多个像素电路，所述像素电路包括驱动晶体管、第一初始化晶体管和第二初始化晶体管；
其中，所述多层金属层至少包括沿第一方向延伸的第一金属走线和沿第二方向延伸的第二金属走线，所述第一金属走线和所述第二金属走线位于不同层，所述第一初始化晶体管连接于所述第一金属走线和所述驱动晶体管的栅极之间，设置为将所述第一金属走线上的第一初始化电压传输至所述驱动晶体管的栅极，所述第二初始化晶体管连接于所述第二金属走线和发光元件之间；所述第二初始化晶体管设置为将所述第二金属走线上的第二初始化电压传输至发光元件；所述第一方向和所述第二方向相交，且均垂直于所述阵列基板的厚度方向。
根据本申请的另一方面，提供了一种显示面板，包括本申请任意实施例所提供的阵列基板。
根据本申请的另一方面，提供了一种显示装置，包括本申请任意实施例所提供的显示面板。
本申请实施例提供的技术方案，在衬底上层叠设置有源层和多层金属层，其中，多层金属层至少包括沿第一方向延伸的第一金属走线和沿第二方向延伸的第二金属走线，第一金属走线和第二金属走线位于不同层，第一初始化晶体管连接于第一金属走线和驱动晶体管的栅极之间，设置为将第一金属走线上的第一初始化电压传输至驱动晶体管的栅极，第二初始化晶体管连接于第二金属走线和发光元件之间；第二初始化晶体管设置为将第二金属走线上的第二初始化电压传输至发光元件。本申请实施例提供的技术方案通过不同层设置的第一金属走线和第二金属走线可以分别向对应的第一初始化晶体管和第二初始化晶体管提供相应的初始化电压，以调节驱动晶体管栅极和发光元件阳极的电位状态，从而提高驱动电流的稳定性，以改善显示亮度的均一性和显示色偏的情况。此外，通过在有限的版图空间内设置第一金属走线和第二金属走线不同层，可以提高版图空间利用率，优化版图结构，有利于提高显示PPI。
附图说明
图1为本申请实施例提供的一种阵列基板的俯视结构示意图；
图2为本申请实施例提供的一种阵列基板的剖面结构示意图；
图3为本申请实施例提供的一种像素电路的结构示意图；
图4为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图5为本申请实施例提供的另一种像素电路的结构示意图；
图6为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图7为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图8为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图9为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图10为本申请实施例提供的一种像素电路的驱动时序波形图；
图11为本申请实施例提供的另一种像素电路的驱动时序波形图；
图12为本申请实施例提供的另一种像素电路的结构示意图；
图13为本申请实施例提供的另一种像素电路的驱动时序波形图；
图14为本申请实施例提供的另一种像素电路的驱动时序波形图；
图15为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图16为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图17为本申请实施例提供的另一种像素电路的结构示意图；
图18为本申请实施例提供的另一种阵列基板的结构示意图；
图19为本申请实施例提供的另一种阵列基板的结构示意图；
图20为本申请实施例提供的另一种阵列基板的结构示意图；
图21为本申请实施例提供的另一种阵列基板的结构示意图；
图22为本申请实施例提供的另一种阵列基板的结构示意图；
图23为本申请实施例提供的另一种像素电路的结构示意图；
图24为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图25为本申请实施例提供的另一种像素电路的结构示意图；
图26为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图27为本申请实施例提供的另一种像素电路的结构示意图；
图28为本申请实施例提供的另一种阵列基板的俯视结构示意图；
图29为本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
图1为本申请实施例提供的一种阵列基板的俯视结构示意图，图2为本申请实施例提供的一种阵列基板的剖面结构示意图，例如可为图1所述阵列基板沿剖线AA’剖切得到的剖面结构；图3为本申请实施例提供的一种像素电路的结构示意图，参考图1至图3，本申请实施例提供的阵列基板包括：衬底21；层叠设置于衬底21一侧的有源层10和多层金属层，阵列基板中形成有多个像素电路，像素电路包括驱动晶体管T1、第一初始化晶体管T2和第二初始化晶体管T3。
其中，多层金属层至少包括沿第一方向延伸的第一金属走线11和沿第二方向延伸的第二金属走线12，第一金属走线11和第二金属走线12位于不同层，第一初始化晶体管T2连接于第一金属走线11和驱动晶体管T1的栅极之间，设置为将第一金属走线11上的第一初始化电压Vref1传输至驱动晶体管T1的栅极，第二初始化晶体管T3连接于第二金属走线12和发光元件D1之间；第二初始化晶体管T3设置为将第二金属走线12上的第二初始化电压Vref2传输至发光元件D1；第一方向和第二方向相交，且均垂直于阵列基板的厚度方向。
第一初始化晶体管T2连接于第一金属走线11和驱动晶体管T1的栅极之间，可以理解为第一初始化晶体管T2的源极或漏极中的一个电极与第一金属走线11电连接，第一初始化晶体管T2的源极或漏极中的另一个电极与驱动晶体管T1的栅极电连接。第二初始化晶体管T3连接于第二金属走线12和发光元件D1之间，可以理解为第二初始化晶体管T3的源极或漏极中的一个电极与第二金属走线12电连接，第二初始化晶体管T3的源极或漏极中的另一个电极与发光元件D1电连接。电连接可以是直接连接，也可以是间接连接。例如，衬底21可以用于为阵列基板提供保护和支撑的作用，其中，衬底21可以是聚酰亚胺(Polyimide，PI)、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate two formic acid glycol ester，PEN)或者聚对苯二甲酸乙二醇酯(Polyethylene terephthalate，PET)等材料形成的柔性衬底，也可以为玻璃等材料形成硬质衬底。在衬底21一侧依次设置有有源层10和多层金属层，多层金属层之间通过绝缘层相互隔离，例如，多层金属层包括第一金属层M1、第二金属层M2和第三金属层M3，有源层10与第一金属层M1之间设置有第一层间绝缘层22，第一金属层M1与第二金属层M2之间设置有第二层间绝缘层23，第二金属层M2与第三金属层M3之间设置有第三层间绝缘层24，在第三金属层M3远离衬底21一侧还设置有第四层间绝缘层25。其中，有源层10可以由多晶硅、金属氧化物等材料形成。
阵列基板上形成有多个像素电路，用于产生驱动电流，以驱动与像素电路连接的发光元件D1发光。像素电路至少由薄膜晶体管形成，薄膜晶体管至少包括驱动晶体管T1、第一初始化晶体管T2和第二初始化晶体管T3。其中，第一初始化晶体管T2设置为对驱动晶体管T1的栅极电位进行初始化，第二初始化晶体管T3设置为对发光元件D1的阳极电位进行初始化。这里，数据线Data上的数据电压通过数据写入晶体管T4、驱动晶体管T1和阈值补偿晶体管T5写入电压至驱动晶体管T1的栅极，并存储在存储电压Cst上，实现数据写入以及阈值补偿功能。当第一发光控制晶体管T6和第二发光控制晶体管T7导通 时，驱动晶体管T1产生驱动电流，驱动发光元件D1发光。
在本实施例中，第一初始化电压Vref1由第一金属走线11提供，第二初始化电压Vref2由第二金属走线12提供。其中第一金属走线11沿第一方向延伸，第二金属走线12沿第二方向延伸。这里，第一方向可以是Y方向，第二方向可以是X方向，X方向和Y方向均垂直于阵列基板的厚度方向(即Z方向)。结合图1和图2，第一金属走线11和第二金属走线12分别由多层金属层中的不同层金属形成。例如，第一金属走线11位于第三金属层M3，第二金属走线12位于第二金属层M2，第一金属走线11向第一初始化晶体管T2传输第一初始化电压Vref1，第二金属走线12向第二初始化晶体管T3传输第二初始化电压Vref2。由此可以通过不同层设置的第一金属走线11和第二金属走线12分别向驱动晶体管T1的栅极和发光元件D1的阳极提供对应的初始化电压，以加强对驱动晶体管T1的阈值补偿效果，提高驱动电流的均一性，以及降低发光元件D1的寄生电容对驱动电流的影响，以减小色偏情况。同时，还能够优化版图结构，有利于提高版图的空间利用率，提高显示像素密度(PixelsPerInch，PPI)。
当然，第一金属走线11和第二金属走线12还可以向驱动晶体管T1的栅极和发光元件D1的阳极提供相同的初始化电压。通过驱动时序控制该像素电路，以加强对驱动晶体管T1的阈值补偿效果，提高驱动电流的均一性，以及降低发光元件D1的寄生电容对驱动电流的影响，以减小色偏情况，其具体工作原理将在以下实施例中进行描述。
本申请实施例提供的技术方案，在衬底上层叠设置有源层和多层金属层，其中，多层金属层至少包括沿第一方向延伸的第一金属走线和沿第二方向延伸的第二金属走线，第一金属走线和第二金属走线位于不同层，第一初始化晶体管连接于第一金属走线和驱动晶体管的栅极之间，设置为将第一金属走线上的第一初始化电压传输至驱动晶体管的栅极，第二初始化晶体管连接于第二金属走线和发光元件之间；第二初始化晶体管设置为将第二金属走线上的第二初始化电压传输至发光元件。本申请实施例提供的技术方案通过不同层设置的第一金属走线和第二金属走线可以分别向对应的第一初始化晶体管和第二初始化晶体管提供相应的初始化电压，以调节驱动晶体管栅极和发光元件阳极的电位状态，从而提高驱动电流的稳定性，以改善显示亮度的均一性和显示色偏的情况。此外，通过在有限的版图空间内设置第一金属走线和第二金属走线不同层，可以提高版图空间利用率，优化版图结构，有利于提高显示PPI。
继续参考图1，第一金属走线11包括呈多列排布的第一子金属走线111和第二子金属走线112，其中，每个第一子金属走线111呈一列设置，多个第二子金属走线112呈一列排布；第一初始化晶体管T2连接于第一子金属走线111和驱动晶体管T1的栅极之间；第二初始化晶体管T3连接第二子金属走线112。
其中，多层金属层还包括第三金属走线13和第四金属走线14，分别为第一扫描线和第二扫描线，第三金属走线13和第四金属走线14分别沿第二方向延伸，第二金属走线12在衬底21上的垂直投影位于第三金属走线13在衬底21上的垂直投影和第四金属走线14在衬底21上的垂直投影之间，第三金属走线13和第四金属走线14可以均位于第一金属层，第三金属走线13与有源层10交叠形成第一初始化晶体管T2，第四金属走线14与有源层10交叠形成第二初始化晶体管T3。这里，第三金属走线13与有源层10交叠形成的晶体管设置为本行像素电路相邻的上一行像素电路中的第二初始化晶体管T3。
例如，单条第一子金属走线111沿第一方向呈一列排列，多条第二子金属走线112沿第一方向呈一列排布，第一子金属走线111和第二子金属走线112相互绝缘。第一初始化晶体管T2的第一端与第一子金属走线111连接，第一初始化晶体管T2的第二端与驱动晶体管T1的栅极连接，第一子金属走线111设置为向第一初始化晶体管T2提供第一初始化电压Vref1。第二初始化晶体管T3的第一端与第二子金属走线112的第一端连接，第二子金属走线112的第二端与第二金属走线12连接，第二初始化晶体管T3的第二端与发光元件D1的阳极连接。这里，第二子金属走线112起到转接的作用，以将第二金属走线12提供的第二初始化电压Vref2传输至第二初始化晶体管T3的第一端。
由于第一金属走线11和第二金属走线12不同层，因此第一金属走线11上的第一初始化电压Vref1和第二金属走线12上的第二初始化电压Vref2可以不同。示例性地，在本实施例中，第一初始化电压Vref1可以小于第二初始化电压Vref2。由于第一初始化电压Vref1较小，能够将驱动晶体管T1的栅极电压拉至较低电位，使得驱动晶体管T1的栅极电位完全复位，针对不同的像素电路，能够保证数据电压可以完全写入至驱动晶体管T1的栅极，从而加强对驱动晶体管T1的阈值补偿效果，有利于改善驱动电流的均一性，改善残影情况。在对发光元件D1阳极初始化时，适当提高第二初始化电压Vref2，能够减小发光元件D1的寄生电容对驱动电流的影响，从而有利于减少亮度偏差引起的色偏情况。
例如，图4为本申请实施例提供的另一种阵列基板的俯视结构示意图，具体示出了阵列像素电路的部分结构。结合图1和图4，第一子金属走线111沿Y方向延伸，并与上下行对应的像素电路的第一子金属走线111连接在一起，形成竖线，每个第一子金属走线111均呈一列排布。第二金属走线12沿X方向延伸，并与左右列对应的像素电路的第二金属走线12连接在一起，形成横线。第二子金属走线112沿Y方向延伸，并与第二金属走线12连接，通过有源层10连接至第二初始化晶体管T3，由此多个第二子金 属走线112呈一列排布。其中，单个像素电路的具体结构如虚线框内所示。
在本实施例中，上下相邻两行像素电路对应的第三金属走线13或第四金属走线14可以共用，即第n行像素电路对应的第四金属走线14可以复用为第n+1行像素电路对应的第三金属走线13，其中，n为大于或等于1的整数。例如，第n行像素电路的第四金属走线14与第n+1行像素电路的第三金属走线13重合。也即第n行的第二扫描线用作第n+1行的第一扫描线，由于节省版图空间，形成较高的PPI。
图5为本申请实施例提供的另一种像素电路的结构示意图。参考图5，像素电路还包括第一漏电补偿晶体管T8和第二漏电补偿晶体管T9，第一漏电补偿晶体管T8连接于驱动晶体管T1的栅极和第二漏电补偿晶体管T9的第二极之间，第二漏电补偿晶体管T9的第一极与第一初始化晶体管T2连接。其中，第一漏电补偿晶体管T8的栅极和第二漏电补偿晶体管T9的栅极连接同一扫描线，设置为在数据写入完成时，关断驱动晶体管T1的漏电路径，降低漏电流，保持驱动晶体管T1的栅极电位稳定。
继续参考图5，像素电路还包括第一存储电容C1，第一存储电容C1与第二漏电补偿晶体管T9的第二极连接，设置为存储第二漏电补偿晶体管T9的第二极的电位。例如，当第一漏电补偿晶体管T8由导通变为关断时，第一漏电补偿晶体管T8的栅极与驱动晶体管T1的栅极之间的寄生电容发生耦合作用，将驱动晶体管T1的栅极电位耦合，使得驱动晶体管T1的栅极电位与第一漏电补偿晶体管T8第一极电位相近(驱动晶体管T1的栅极与第一漏电补偿晶体管T8的第二极连接，第一漏电补偿晶体管T8的第一极与第二漏电补偿晶体管T9的第二极连接)。因此，第一漏电补偿晶体管T8第一极和第二极之间的电压差较小，使得第一漏电补偿晶体管T8的漏电流较小，有利于维持驱动晶体管T1的栅极电位稳定。
图6为本申请实施例提供的另一种阵列基板的俯视结构示意图。其中，图6中未示出第二存储电容C2。参考图5和图6，多层金属层包括第一金属层M1、第二金属层M2和第三金属层M3，第一金属层M1包括驱动晶体管T1的栅极、第三金属走线13、第四金属走线14，第二金属层M2包括第二金属走线12，第三金属层M3包括第一金属走线11。多层金属层还包括第五金属走线15，用作第三扫描线EMB，其中，第五金属走线15与第一金属走线11和第二金属走线12均不同层。例如，第五金属走线15位于第一金属层M1。第五金属走线15在衬底上的垂直投影位于第二金属走线12在衬底上的垂直投影的一侧，且与第二金属走线12在衬底上的垂直投影不交叠，即与第二金属走线12在衬底上的垂直投影错开，第五金属走线15与有源层10交叠分别形成第一漏电补偿晶体管T8和第二漏电补偿晶体管T9。第二金属走线12与第一存储电容C1连接，第一存储电容C1可以由第二金属走线12与有源层10交叠形成，有利于节省版图空间。
继续参考图5和图6，多层金属层还包括沿第二方向延伸的第六金属走线16和第七金属走线17，分别为第四扫描线S3和第五扫描线EM。其中，第六金属走线16与有源层10交叠分别形成数据写入晶体管T4和阈值补偿晶体管T5，第七金属走线17与有源层10交叠分别形成第一发光控制晶体管T6和第二发光控制晶体管T7。与第六金属走线16交叠形成数据写入晶体管T4的有源层10通过过孔连接至数据线Data，与第七金属走线17交叠形成第一发光控制晶体管T6的有源层10通过过孔与第一电源线VDD连接(图中未示出第二电源线VSS)。
在上述多个实施例中，第一金属走线11和第二金属走线12之间无电性连接，也即第一子金属走线111和第二子金属走线112之间相互绝缘，可以单独调节第一初始化电压Vref1和第二初始化电压Vref2。
当然，第一金属走线11和第二金属走线12也可以连接在一起，形成网状结构。图7为本申请实施例提供的另一种阵列基板的俯视结构示意图。在上述多个技术方案的基础上，参考图7，例如，第二子金属走线112和第一子金属走线111连接形成网状。也就是说，第一子金属走线111与第二子金属走线112连接在一起。由于第二子金属走线112还与第二金属走线12连接，因此，第一金属走线11和第二金属走线12相互连接，形成横竖网状结构。此时，第一初始化电压Vref1等于第二初始化电压Vref2，即第二初始化电压Vref2可以复用为第一初始化电压Vref1。
图8为本申请实施例提供的另一种阵列基板的俯视结构示意图。参考图5和图8，例如，第一金属走线11的第一端连接第二金属走线12，第一金属走线11的第二端连接第一初始化晶体管T2和第二初始化晶体管T3。与图7所示版图结构不同之处在于，图8所示版图结构不存在第一子金属走线111，通过第一金属走线11实现第二金属走线12与第一初始化晶体管T2和第二初始化晶体管T3的连接，也就是说，第一初始化晶体管T2和第二初始化晶体管T3经第一金属走线11间接地连接至第二金属走线12，第二金属走线12上的第二初始化电压Vref2分别通过第一初始化晶体管T2和第二初始化晶体管T3传输至驱动晶体管T1的栅极和发光元件D1的阳极。此时第二初始化电压Vref2即为第一初始化电压Vref1。在本实施例中，由于不存在传输第一初始化电压Vref1的竖线(第一子金属线111)，因此可以获得更大的透光率。
其中，图8中多个晶体管的位置与图6相同，在此不再赘述。
图9为本申请实施例提供的另一种阵列基板的俯视结构示意图。其中图9所示的版图结构与图8所示 版图结构的不同之处在于，有源层10的结构不同。参考图9，第二漏电补偿晶体管T9形成于第一漏电补偿晶体管T8的左侧。第三金属走线13包括第一主体部131和第一分支部132，第四金属走线14包括第二主体部141和第二分支部142，第一主体部131和第二主体部141沿第二方向延伸，第一分支部132和第二分支部142沿第一方向延伸。形成第二漏电补偿晶体管T9的有源层10沿第一方向向上延伸，之后向第二方向延伸与第三金属走线13的第一分支部132交叠形成第一初始化晶体管T2，第三金属走线13的第一主体部131与有源层10交叠形成上一行像素电路的第二初始化晶体管T3。第四金属走线14的第二主体部141与沿第一方向延伸的有源层10交叠形成本行像素电路的第二初始化晶体管T3，第四金属走线14的第二分支部142与沿第二方向延伸的有源层10形成下一行像素电路的第一初始化晶体管T2。其中，图9所示像素电路的原理与图8和图6所示像素电路的原理相同，其具体工作过程将在后续描述中详细介绍。
在上述多个技术方案中，第二金属走线12在衬底21上的垂直投影位于第五金属走线15在衬底21上的垂直投影和第六金属走线16在衬底21上的垂直投影之间，且第五金属走线15位于第二金属走线12远离驱动晶体管T1的一侧。
图10为本申请实施例提供的一种像素电路的驱动时序波形图。图11为本申请实施例提供的另一种像素电路的驱动时序波形图，适用于图5所示像素电路。其中图11具体示出了插黑阶段的驱动时序。参考图5、图10和图11，本实施例仅以多个晶体管为P型晶体管为例进行说明，在其他实施例中，多个晶体管可以为N型晶体管。本申请实施例提供的像素电路的工作过程至少包括初始化阶段t1、数据写入阶段t2、电压归一化阶段t3、发光阶段t4和插黑阶段t5。
在初始化阶段t1，第一扫描线S1上传输的第一扫描信号为低电平，第二扫描线S2上传输的第二扫描信号为高电平，第三扫描线EMB上传输的第三扫描信号为低电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，第一初始化晶体管T2、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9导通，第一初始化电压Vref1传输到驱动晶体管T1的栅极，实现对驱动晶体管T1栅极电位的初始化。
在数据写入阶段t2，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为低电平，第三扫描线EMB上传输的第三扫描信号为低电平，第四扫描线S3上传输的第四扫描信号为低电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，数据写入晶体管T4、阈值补偿晶体管T5、第二初始化晶体管T3、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9导通，数据线Data上的数据电压写入至驱动晶体管T1的栅极。当驱动晶体管T1的栅极电压达到Vdata+Vth时，驱动晶体管T1关断，该电压存储在第一存储电容C1和第二存储电容C2上，其中Vdata为数据电压，Vth为驱动晶体管的阈值电压。同时，第二初始化电压Vref2通过第二初始化晶体管T3写入至发光元件D1的阳极，实现对发光元件D1阳极电位的初始化。此时，驱动晶体管T1的栅极电压不等于第一存储电容C1上的存储电压。
在电压归一化阶段t3，第三扫描线EMB上传输的第三扫描信号由低电平跳变为高电平，在驱动晶体管T1栅极的寄生电容的耦合作用下，驱动晶体管T1的栅极电压被拉高至与第一存储电容C1上存储的电压相近，因此第一漏电补偿晶体管T8第一极和第二极之间的电压差较小，使得第一漏电补偿晶体管T8的漏电流较小，从而能够维持驱动晶体管T1栅极电压稳定。
在发光阶段t4，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为高电平，第三扫描线EMB上传输的第三扫描信号为高电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为低电平。因此，第一发光控制晶体管T6和第二发光控制晶体管T7导通，驱动晶体管T1产生驱动电流，驱动发光元件D1发光。由于驱动晶体管T1的栅极电压能够长时间保持稳定，因此能够保证驱动电流的均一性，改善显示画面的残影情况。
当第五扫描线EM上传输的第五扫描信号由低电平跳变为高电平时，像素电路进入插黑阶段t5。在插黑阶段t5，第三扫描线EMB上传输的第三扫描信号一直为高电平，第一漏电补偿晶体管T8和第二漏电补偿晶体管T9处于关断状态。
第四扫描线S3上传输的第四扫描信号维持高电平，第一扫描线S1上传输的第一扫描信号和第二扫描线S2上传输的第二扫描信号的低电平相继到达。由于第一漏电补偿晶体管T8和第二漏电补偿晶体管T9处于关断状态，第一初始化电压Vref1不会写入到驱动晶体管T1的栅极，只有第二初始化电压Vref2写入到发光元件D1的阳极，对发光元件D1的阳极电位进行复位。
当插黑阶段t5结束后，第五扫描线EM上传输的第五扫描信号由高电平跳变为低电平，发光元件D1继续发光。
在本实施例中，插黑阶段可以进行多次，通过设置插黑阶段，并通过在插黑阶段对发光元件D1的阳极电位进行复位，能够完全将人眼容易感知到的低频亮度成分转换为不容易被感知到的高频亮度成分， 从而改善显示画面闪烁现象。
图12为本申请实施例提供的另一种像素电路的结构示意图。参考图12，在上述多个技术方案的基础上，例如，像素电路还包括第一电压写入控制晶体管T10，第一电压写入控制晶体管T10和数据写入晶体管T4串联连接于数据线Data和驱动晶体管T1的第一极之间，第一电压写入控制晶体管T10的栅极接入第三扫描线EMB上传输的第三扫描信号。
当驱动晶体管T1的第一极和第二极处的寄生电容较小时，可以采用图11所示的驱动时序对图12所示像素电路进行驱动。这里，可以设置第四扫描线S3上传输的第四扫描信号和第二扫描线S2上传输的第二扫描信号相同，使得第四扫描线S3上传输的第四扫描信号在插黑阶段t5内同样存在脉冲，从而提高第四扫描线S3上传输的第四扫描信号的扫描频率。在本实施例中，数据写入晶体管T4栅极接入的扫描信号的扫描频率与所述第一初始化晶体管T2栅极接入的扫描信号、以及所述第二初始化晶体管T3栅极接入的扫描信号的扫描频率均高于预设高扫描频率。其中，预设高扫描频率可以为60Hz，扫描频率高于该预设高扫描频率的信号均为高频信号。换句话说，第一扫描线S1、第二扫描线S2和第四扫描线S3上的扫描信号均为高频信号。
当然，在其他实施例中，预设高扫描频率还可以为75Hz、100Hz或者120Hz等，本实施例对此不进行具体限制。
在插黑阶段t5内，由于第一电压写入控制晶体管T10关断，即使阈值补偿晶体管T5和数据写入晶体管T4响应第四扫描信号导通，第一漏电补偿晶体管T8的第一极的电压也不会发生较大变化，第一漏电补偿晶体管T8的第二极和第一极之间仍能保持较小的电压差，因此第一漏电补偿晶体管T8能够维持较低的漏电流。由于第四扫描线S3上传输的第四扫描信号、第一扫描线S1上传输的第一扫描信号和第二扫描线S2上传输的第二扫描信号均为高频信号，因此第一扫描信号、第二扫描信号和第四扫描信号可以由同一组栅极驱动电路产生，有利于实现窄边框设计。
当驱动晶体管T1的第一极和第二极处的寄生电容较大时，可以采用双脉冲驱动的方式对驱动晶体管T1的亚阈值进行补偿。图13为本申请实施例提供的另一种像素电路的驱动时序波形图。图14为本申请实施例提供的另一种像素电路的驱动时序波形图，其中图14具体示出了插黑阶段的驱动时序。图13和图14所示驱动时序适用于图12所示的像素电路。该像素电路的工作过程如下：
在第一阶段t11(对应初始化阶段)，第一扫描线S1上传输的第一扫描信号为低电平，第二扫描线S2上传输的第二扫描信号为高电平，第三扫描线EMB上传输的第三扫描信号为低电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，第一初始化晶体管T2、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9导通，第一初始化电压Vref1传输到驱动晶体管T1的栅极，实现对驱动晶体管T1栅极电位的初始化。
在第二阶段t12(对应数据写入阶段)，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为低电平，第三扫描线EMB上传输的第三扫描信号为低电平，第四扫描线S3上传输的第四扫描信号为低电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，数据写入晶体管T4、阈值补偿晶体管T5、第二初始化晶体管T3、第一电压写入控制晶体管T10、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9导通，与数据线Data上的数据电压相关的电压写入至驱动晶体管T1的栅极。当驱动晶体管T1的栅极电压达到Vdata+Vth时，驱动晶体管T1关断，该电压存储在第一存储电容C1和第二存储电容C2上，其中Vdata为数据电压，Vth为驱动晶体管的阈值电压。同时，第二初始化电压Vref2通过第二初始化晶体管T3写入至发光元件D1的阳极，实现对发光元件D1阳极电位的初始化。此时，驱动晶体管T1的栅极电压接近于第一存储电容C1上的存储电压。
在第三阶段t13，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为高电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为高电平。当第三扫描线EMB上传输的第三扫描信号变为高电平时，第一电压写入控制晶体管T10关断，存储在驱动晶体管T1第一极的数据电压继续向第二极充电，经过一段时间后，驱动晶体管T1进入亚阈值区。驱动晶体管T1的亚阈值摆幅越大，驱动晶体管T1第二极的电压越高。
在第四阶段t14，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为高电平，第三扫描线EMB上传输的第三扫描信号为高电平，第四扫描线S3上传输的第四扫描信号为低电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，数据写入晶体管T4和阈值补偿晶体管T5导通，驱动晶体管T1的第二极与第一漏电补偿晶体管T8的第一极连通。此时，由于第一电压写入控制晶体管T10关断，数据线Data上的数据电压不会写入至驱动晶体管T1。
在第五阶段t15，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号为高电平，第三扫描线EMB上传输的第三扫描信号为低电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为高电平。因此，第一电压写入控制晶体管T10、第 一漏电补偿晶体管T8和第二漏电补偿晶体管T9导通，驱动晶体管T1的栅极和第一漏电补偿晶体管T8的第一极之间连通。最终，驱动晶体管T1的栅极电压随着驱动晶体管T1的亚阈值摆幅增大而略微增大，从而能够起到补偿亚阈值摆幅的作用，进而改善低灰阶下显示不均的现象。
在第六阶段t16(对应发光阶段)，第一扫描线S1上传输的第一扫描信号为高电平，第二扫描线S2上传输的第二扫描信号高低电平，第三扫描线EMB上传输的第三扫描信号为高电平，第四扫描线S3上传输的第四扫描信号为高电平，第五扫描线EM上传输的第五扫描信号为低电平。因此，第一发光控制晶体管T6和第二发光控制晶体管T7导通，驱动晶体管T1产生驱动电流，驱动发光元件D1发光。
当第五扫描线EM上传输的第五扫描信号由低电平变为高电平时，发光元件D1熄灭，像素电路进入第七阶段t17(对应插黑阶段)。第四扫描线S3上传输的第四扫描信号维持高电平，第一扫描线S1上传输的第一扫描信号和第二扫描线S2上传输的第二扫描信号的低电平相继到达。当第一扫描信号为低电平时，第一初始化晶体管T2导通，但是由于第二漏电补偿晶体管T9和第一漏电补偿晶体管T8关断，因此第一初始化电压Vref1不会传输至驱动晶体管T1的栅极，不会对像素电路的正常工作造成影响。当第二扫描信号为低电平时，第二初始化晶体管T3导通，第二初始化电压Vref2传输至发光元件D1的阳极，实现对发光元件D1阳极电位的初始化。
当插黑阶段结束后，第五扫描线EM上传输的第五扫描信号由高电平跳变为低电平，发光元件D1继续发光。
图15为本申请实施例提供的另一种阵列基板的俯视结构示意图，例如为对应图12所示像素电路的俯视结构示意图。参考图15，形成数据写入晶体管T4的有源层10沿第一方向向上延伸，并与第五金属走线15交叠形成第一电压写入控制晶体管T10，且该有源层10通过过孔与数据线Data连接。其他多个晶体管的连接结构与图6所示像素电路的版图结构相同，在此不再赘述。
图16为本申请实施例提供的另一种阵列基板的俯视结构示意图。在图15所示版图结构的基础上，可以将第一子金属走线111与第二子金属走线112连接在一起，使得第二金属走线12和第一子金属走线111连接形成网状结构，有利于信号的传输。当然，通过第一金属走线11实现第二金属走线12与第一初始化晶体管T2和第二初始化晶体管T3的连接。也就是说，第一初始化晶体管T2和第二初始化晶体管T3经第一金属走线11间接地连接至第二金属走线12，第二金属走线12上的第二初始化电压Vref2分别通过第一初始化晶体管T2和第二初始化晶体管T3传输至驱动晶体管T1的栅极和发光元件D1的阳极。由于不存在传输第一初始化电压Vref1的竖线(第一子金属线111)，因此可以获得更大的透光率，具体连接结构可以参考图8所示版图结构。
图17为本申请实施例提供的另一种像素电路的结构示意图。参考图17，在上述多个技术方案的基础上，例如，像素电路还包括第二电压写入控制晶体管T11，第二电压写入控制晶体管T11连接于驱动晶体管T1的第二极和第二漏电补偿晶体管T9的第二极之间。其中，第二电压写入控制晶体管T11可以为双栅晶体管，也可以为单栅晶体管。
在本实施例中，第二电压写入控制晶体管T11与第一漏电补偿晶体管T8连接同一扫描信号。因此，该像素电路同样适用于图10和图11所示的驱动时序，也适用于图13和图14所示驱动时序。且由于第二电压写入控制晶体管T11和阈值补偿晶体管T5串联连接，在插黑阶段，由于第五扫描线EM上传输的第五扫描信号一直为高电平，第二电压写入控制晶体管T11、第二漏电补偿晶体管T9和第一漏电补偿晶体管T8一直处于关断状态，因此即使数据写入晶体管T2和阈值补偿晶体管T5导通，也不会将数据电压写入至驱动晶体管T1的栅极，能够保证像素电路正常工作。因此，第二扫描线S2上传输的第二扫描信号可以设置为高频信号，与第一扫描信号和第四扫描信号可以由同一组栅极驱动电路产生，有利于实现窄边框设计。
图18为本申请实施例提供的另一种阵列基板的结构示意图，例如为图17所示像素电路对应的版图结构。参考图18，通过优化有源层10的结构，与第二金属走线12交叠的有源层10沿第一方向延伸并与第五金属走线15交叠，使得第五金属走线15与有源层10交叠部分分别形成第二电压写入控制晶体管T11(包括第一子晶体管T11-1和第二子晶体管T11-2)、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9，在有限的空间内，提高了版图的空间利用率。
图19为本申请实施例提供的另一种阵列基板的结构示意图，例如为图17所示像素电路对应的另一种版图结构。参考图19，第一子金属走线111与第二子金属走线112连接在一起，由于第二子金属走线112还与第二金属走线12连接，因此，第一金属走线11和第二金属走线12相互连接，形成横竖网状结构。此时，尽管不能单独调节第一初始化电压Vref1和第二初始化电压Vref2，但可以通过驱动时序(如图13所示双脉冲时序)来改善驱动晶体管T1的阈值补偿效果，进而实现改善驱动电流不均一的情况，以提高显示效果。
图20为本申请实施例提供的另一种阵列基板的结构示意图，例如为图17所示像素电路对应的另一 种版图结构。参考图20，第三金属走线13包括第一主体部131和第一分支部132，第四金属走线14包括第二主体部141和第二分支部142，第一主体部131和第二主体部141沿第二方向延伸，第一分支部132和第二分支部142沿第一方向延伸。形成第二漏电补偿晶体管T9的有源层10沿第一方向向上延伸，之后向第二方向延伸与第三金属走线13的第一分支部132交叠形成第一初始化晶体管T2，第三金属走线13的第一主体部131与有源层10交叠形成上一行像素电路的第二初始化晶体管T3。第四金属走线14的第二主体部141与沿第一方向延伸的有源层10交叠形成本行像素电路的第二初始化晶体管T3，第四金属走线14的第二分支部142与沿第二方向延伸的有源层10形成下一行像素电路的第一初始化晶体管T2。这里，通过第二子金属走线112实现第二金属走线12与第一初始化晶体管T2和第二初始化晶体管T3的连接，无需设置第一子金属走线111，使得版图结构中不存在单独传输第一初始化电压Vref1的竖线，因此可以获得更大的透光率。
图21为本申请实施例提供的另一种阵列基板的结构示意图，图22为本申请实施例提供的另一种阵列基板的结构示意图，分别为图17所示像素电路对应的另一种版图结构。这里，第二电压写入控制晶体管T11为单栅晶体管。参考图21和图22，二者的区别仅在于第一漏电补偿晶体管T8和第二漏电补偿晶体管T9的形成位置相反，其他结构完全相同。在本实施例中，第五金属走线15在衬底上的垂直投影位于第六金属走线16在衬底上的垂直投影和第二金属走线12在衬底上的垂直投影之间，这样能够使得第一漏电补偿晶体管T8与驱动晶体管T1的栅极之间的距离较短，也即驱动晶体管T1的栅极的漏电路径较短，有利于降低其他信号对驱动晶体管T1栅极的电位的耦合作用，能够减少多个像素电路之间的串扰情况。
图23为本申请实施例提供的另一种像素电路的结构示意图。图24为本申请实施例提供的另一种阵列基板的俯视结构示意图。其中，图24为对应图23所示像素电路的版图结构。参考图23和图24，在上述多个技术方案的基础上，像素电路可以同时包括第一电压写入控制晶体管T10和第二电压写入控制晶体管T11，且第一电压写入控制晶体管T10、第二电压写入控制晶体管T11、第一漏电补偿晶体管T8和第二漏电补偿晶体管T9均连接第五金属走线(第三扫描线EMB)。图24与图21所示版图结构的区别在于，在图24中，形成数据写入晶体管T4的有源层10沿第一方向向上延伸，并与第五金属走线15交叠形成第一电压写入控制晶体管T10。其他结构的相关描述可参考对图21的描述，在此不再赘述。
图25为本申请实施例提供的另一种像素电路的结构示意图。图26为本申请实施例提供的另一种阵列基板的俯视结构示意图。其中，图26为对应图25所示像素电路的版图结构。参考图25和图26，在图23所示像素电路的基础上，可以去掉阈值补偿晶体管T5，以第二电压写入控制晶体管T11复用为阈值补偿晶体管T5，有利于减小晶体管的数量，减小版图的占用空间。
继续参考图26，在本实施例中，第二金属走线12在衬底上的垂直投影位于第五金属走线15在衬底上的垂直投影和第六金属走线16在衬底上的垂直投影之间，且第五金属走线15在衬底上的垂直投影位于第二金属走线12在衬底上的垂直投影靠近驱动晶体管T1的栅极在衬底上的垂直投影的一侧，由此可以使得第五金属走线15与有源层10交叠形成的第一漏电补偿晶体管T8与驱动晶体管T1的栅极之间的距离进一步缩短，有利于降低其他信号对驱动晶体管T1栅极的电位的耦合作用，能够减少多个像素电路之间的串扰情况。
在本实施例中，在图26所示的版图结构中，第一金属走线11也可以与第二金属走线12连接在一起形成网状结构，或者去掉第一金属走线11，采用第二金属走线12为第一初始化晶体管T2和第二初始化晶体管T3提供初始化电压，其具体连接关系在此不再赘述，可以参考上述任意实施例中的相关描述。
图27为本申请实施例提供的另一种像素电路的结构示意图。图28为本申请实施例提供的另一种阵列基板的俯视结构示意图。其中，图28为对应图27所示像素电路的版图结构。参考图27和图28，在图23所示像素电路的基础上，通过改变有源层10的结构，可以将阈值补偿晶体管T5设置为双栅晶体管，以进一步减小驱动晶体管T1的栅极的漏电流。例如，第六金属走线16与有源层10交叠分别形成阈值补偿晶体管T5(包括第三子晶体管T5-1和第四子晶体管T5-2)和数据写入晶体管T4。
其中，图28仅示出了第一金属走线11和第二金属走线12连接在一起的情况，第一金属走线11和第二金属走线12相互绝缘设置的情况可以参考上述任意实施例中的相关描述，不再赘述。
本申请实施例提供的阵列基板，结合像素电路的结构、驱动时序以及版图布局，可以降低驱动晶体管的栅极漏电，有利于稳定驱动电流，从而提高显示画面的均一性。同时，通过分层设置第一金属走线和第二金属走线，可以使得第一金属走线和第二金属走线传输不同的电压，以独立调节驱动晶体管的栅极电位和发光元件的阳极电位，从而使得改善低灰阶色偏与低频闪烁之间不再相互制约，并且还能够改善残影情况，从而大大提高显示效果。且由于第一金属走线和第二金属走线不同层，因此可以在有限的空间内对第一金属走线和第二金属走线进行布局，有利于提高版图空间的利用率。
例如，本申请实施例还提供了一种显示面板，包括本申请任意实施例所提供的阵列基板，因此该显 示面板同样具备上述任意实施例所描述的有益效果。
例如，本申请实施例还提供了一种显示装置，包括上述实施例提供的显示面板，因此该显示装置同样具备上述任意实施例所描述的有益效果。图29为本申请实施例提供的一种显示装置的结构示意图，在本实施例中，该显示装置可以是手机，也可以为任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。
可以使用上面所示的多种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的多个步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的技术方案所期望的结果，本文在此不进行限制。

Claims (20)

  1. 一种阵列基板，包括：
    衬底；
    有源层和多层金属层，所述有源层和所述多层金属层层叠设置于所述衬底一侧；
    多个像素电路，所述像素电路设于所述阵列基板中，所述像素电路包括驱动晶体管、第一初始化晶体管和第二初始化晶体管；
    其中，所述多层金属层至少包括沿第一方向延伸的第一金属走线和沿第二方向延伸的第二金属走线，所述第一金属走线和所述第二金属走线位于不同层，所述第一初始化晶体管连接于所述第一金属走线和所述驱动晶体管的栅极之间，设置为将所述第一金属走线上的第一初始化电压传输至所述驱动晶体管的栅极；所述第二初始化晶体管连接于所述第二金属走线和发光元件之间，所述第二初始化晶体管设置为将所述第二金属走线上的第二初始化电压传输至所述发光元件；所述第一方向和所述第二方向相交，且分别垂直于所述阵列基板的厚度方向。
  2. 根据权利要求1所述的阵列基板，其中，所述第一金属走线包括呈多列排布的第一子金属走线和第二子金属走线，其中，每个所述第一子金属走线呈一列设置，多个所述第二子金属走线呈一列排布；
    所述第一初始化晶体管连接于所述第一子金属走线和所述驱动晶体管的栅极之间；
    所述第二初始化晶体管连接所述第二子金属走线。
  3. 根据权利要求2所述的阵列基板，其中，所述第二子金属走线和所述第一子金属走线连接形成网状；或者所述第二子金属走线和所述第一子金属走线绝缘设置。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一金属走线的第一端连接所述第二金属走线，所述第一金属走线的第二端连接所述第一初始化晶体管和所述第二初始化晶体管；
    所述第一初始化晶体管和所述第二初始化晶体管经所述第一金属走线间接连接至所述第二金属走线；
    所述第二初始化电压复用为所述第一初始化电压。
  5. 根据权利要求1所述的阵列基板，其中，所述多层金属层还包括第三金属走线和第四金属走线，所述第三金属走线和所述第四金属走线分别为第一扫描线和第二扫描线；所述第三金属走线和所述第四金属走线分别沿所述第二方向延伸，所述第二金属走线在所述衬底上的垂直投影位于所述第三金属走线在所述衬底上的垂直投影和所述第四金属走线在所述衬底上的垂直投影之间；所述第三金属走线与所述有源层交叠形成所述第一初始化晶体管，所述第四金属走线与所述有源层交叠形成所述第二初始化晶体管；
    或者，所述第三金属走线包括第一主体部和第一分支部，所述第四金属走线包括第二主体部和第二分支部，所述第一主体部和所述第二主体部沿所述第二方向延伸，所述第一分支部和所述第二分支部沿所述第一方向延伸，所述第一分支部与所述有源层交叠形成所述第一初始化晶体管，所述第二主体部与所述有源层交叠形成所述第二初始化晶体管。
  6. 根据权利要求5所述的阵列基板，其中，第n行所述像素电路对应的所述第四金属走线复用为第n+1行所述像素电路对应的所述第三金属走线，其中，n为大于或等于1的整数。
  7. 根据权利要求1-6任一项所述的阵列基板，其中，所述像素电路还包括第一漏电补偿晶体管和第二漏电补偿晶体管，所述第一漏电补偿晶体管的第二极与所述驱动晶体管的栅极连接，所述第一漏电补偿晶体管的第一极与所述第二漏电补偿晶体管的第二极连接，所述第二漏电补偿晶体管的第一极与所述第一初始化晶体管连接；
    所述多层金属层包括第一金属层、第二金属层和第三金属层，所述第一金属层包括所述驱动晶体管的栅极，所述第二金属层包括所述第二金属走线，所述第三金属层包括所述第一金属走线。
  8. 根据权利要求7所述的阵列基板，其中，所述多层金属层还包括第五金属走线，所述第五金属走线为第三扫描线，且与所述第一金属走线和所述第二金属走线不同层设置；
    所述第五金属走线在所述衬底上的垂直投影位于所述第二金属走线在所述衬底上的垂直投影的一侧，且与所述第二金属走线错开，所述第五金属走线与所述有源层交叠分别形成所述第一漏电补偿晶体管和所述第二漏电补偿晶体管。
  9. 根据权利要求8所述的阵列基板，其中，所述像素电路还包括第一存储电容，所述第一存储电容连接于所述第二金属走线和所述第二漏电补偿晶体管的第二极之间；
    所述第二金属走线与所述有源层交叠形成所述第一存储电容。
  10. 根据权利要求1-4任一项所述的阵列基板，其中，所述多层金属层还包括沿所述第二方向延伸的第六金属走线和第七金属走线，所述第六金属走线和所述第七金属走线分别为第四扫描线和第五扫描线；
    所述第六金属走线与所述有源层交叠分别形成数据写入晶体管和阈值补偿晶体管，所述第七金属走线与所述有源层交叠分别形成第一发光控制晶体管和第二发光控制晶体管。
  11. 根据权利要求10所述的阵列基板，其中，所述多层金属层还包括沿所述第二方向延伸的第五金属走线，所述第五金属走线为第三扫描线；
    所述第二金属走线在所述衬底上的垂直投影位于所述第五金属走线在所述衬底上的垂直投影和所述第六金属走线在所述衬底上的垂直投影之间；或者，所述第五金属走线在所述衬底上的垂直投影位于所述第二金属走线在所述衬底上的垂直投影和所述第六金属走线在所述衬底上的垂直投影之间。
  12. 根据权利要求11所述的阵列基板，其中，所述第五金属走线在所述衬底上的垂直投影位于所述第二金属走线在所述衬底上的垂直投影靠近所述驱动晶体管的栅极在所述衬底上的垂直投影一侧。
  13. 根据权利要求11所述的阵列基板，其中，所述像素电路还包括第一电压写入控制晶体管，所述第一电压写入控制晶体管和所述数据写入晶体管串联连接于数据线和所述驱动晶体管的第一极之间；
    形成所述数据写入晶体管的所述有源层沿所述第一方向延伸并与所述第五金属走线交叠，且通过过孔与所述数据线连接，所述第五金属走线与所述有源层交叠形成所述第一电压写入控制晶体管。
  14. 根据权利要求13所述的阵列基板，其中，所述第六金属走线上施加的扫描信号的扫描频率与所述第一初始化晶体管的栅极施加的扫描信号、以及所述第二初始化晶体管的栅极施加的扫描信号的扫描频率分别高于预设高扫描频率。
  15. 根据权利要求8所述的阵列基板，其中，所述像素电路还包括第二电压写入控制晶体管，所述第二电压写入控制晶体管连接于所述驱动晶体管的第二极和所述第二漏电补偿晶体管的第二极之间；
    与所述第二金属走线交叠的所述有源层沿所述第一方向延伸并与所述第五金属走线交叠，形成所述第二电压写入控制晶体管。
  16. 根据权利要求1所述的阵列基板，其中，所述第一初始化电压小于或等于所述第二初始化电压。
  17. 根据权利要求8所述的阵列基板，其中，所述多层金属层还包括沿所述第二方向延伸的第六金属走线，所述第六金属走线与所述有源层交叠分别形成数据写入晶体管和阈值补偿晶体管，所述像素补偿电路还包括第一电压写入控制晶体管和第二电压写入控制晶体管；
    所述第一电压写入控制晶体管和所述数据写入晶体管串联连接于数据线和所述驱动晶体管的第一极之间；形成所述数据写入晶体管的所述有源层沿所述第一方向延伸并与所述第五金属走线交叠，且通过过孔与所述数据线连接，所述第五金属走线与所述有源层交叠形成所述第一电压写入控制晶体管；
    所述第二电压写入控制晶体管连接于所述驱动晶体管的第二极和所述第二漏电补偿晶体管的第二极之间，与所述第二金属走线交叠的所述有源层沿第一方向延伸并与所述第五金属走线交叠，形成所述第二电压写入控制晶体管；
    所述第一电压写入控制晶体管、所述第二电压写入控制晶体管、所述第一漏电补偿晶体管和所述第二漏电补偿晶体管分别连接所述第五金属走线。
  18. 根据权利要求17所述的阵列基板，其中，所述阈值补偿晶体管为双栅晶体管。
  19. 一种显示面板，包括如权利要求1-18任一项所述的阵列基板。
  20. 一种显示装置，包括如权利要求19所述的显示面板。
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