WO2021237505A1 - 阵列基板、显示面板以及阵列基板的驱动方法 - Google Patents

阵列基板、显示面板以及阵列基板的驱动方法 Download PDF

Info

Publication number
WO2021237505A1
WO2021237505A1 PCT/CN2020/092573 CN2020092573W WO2021237505A1 WO 2021237505 A1 WO2021237505 A1 WO 2021237505A1 CN 2020092573 W CN2020092573 W CN 2020092573W WO 2021237505 A1 WO2021237505 A1 WO 2021237505A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel unit
column
reset
pixel
transistor
Prior art date
Application number
PCT/CN2020/092573
Other languages
English (en)
French (fr)
Inventor
赵爽
陈祯祐
杨中流
陈文波
徐卓
杨静
卢红婷
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/274,665 priority Critical patent/US20220199027A1/en
Priority to JP2021569201A priority patent/JP7568652B2/ja
Priority to EP20900718.6A priority patent/EP4002336A4/en
Priority to PCT/CN2020/092573 priority patent/WO2021237505A1/zh
Priority to CN202080000824.2A priority patent/CN113994416B/zh
Publication of WO2021237505A1 publication Critical patent/WO2021237505A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the embodiment of the present disclosure relates to an array substrate, a display panel, and a driving method of the array substrate.
  • Display panels mainly include Liquid Crystal Display (LCD) panels and Organic Light-Emitting Diode (OLED) display panels.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • an OLED display panel it includes multiple pixel units arranged in an array. The pixel units in the same row are connected to the same gate line, and the pixel units in the same column are connected to the same data line. Each pixel unit is provided on the gate line. The display is driven by the scan signal and the data signal provided by the data line.
  • At least one embodiment of the present disclosure provides an array substrate, including: a plurality of pairs of gate lines, each of the plurality of pairs of gate lines includes a first gate line and a second gate line; a plurality of data lines; a pixel array including: Multiple pixel units with multiple rows and multiple columns.
  • each of the plurality of pixel units includes a scan signal terminal, a data signal terminal, and a reset signal terminal, a plurality of rows of pixel units correspond to the plurality of pairs of gate lines in a one-to-one correspondence, and each column of pixel units corresponds to the plurality of gate lines.
  • the scan signal terminal of the pixel unit in the nth column of the pixel unit in the mth row is connected to the first gate line of the m-th pair of gate lines to receive the first scan signal
  • m and n are both A positive integer
  • the scan signal end of the pixel unit of the n+1 column in the m-th row of pixel units is connected to the second gate line of the m-th pair of gate lines to receive a second scan signal
  • the reset signal end of the pixel unit of the n+1th column in the pixel unit is connected to the first gate line of the m-th pair of gate lines to receive the first scan signal as a first reset signal
  • the data signal terminal is connected to a corresponding data line to receive the data signal.
  • the reset signal terminal of the pixel unit of the nth column in the mth row of pixel units is connected to the first gate line of the m-1 pair of gate lines to receive The first scan signal provided by the first gate line in the m-1 pair of gate lines is used as the second reset signal; or the reset signal end of the pixel unit of the nth column in the m-th row of pixel units is connected to the The second gate line of the m-1 pair of gate lines receives a second scan signal provided by the second gate line of the m-1 pair of gate lines as the second reset signal, and m is greater than 1. Integer.
  • the array substrate provided by the embodiment of the present disclosure further includes a plurality of reset signal lines, wherein the plurality of reset signal lines correspond to the plurality of rows of pixel units one-to-one;
  • the reset signal terminal of the column pixel unit is connected to the m-th reset signal line to receive the second reset signal.
  • the array substrate provided by the embodiment of the present disclosure further includes a first scan driving circuit, wherein the first scan driving circuit is connected to the plurality of reset signal lines and is configured to generate the second reset signal.
  • the array substrate provided by the embodiment of the present disclosure further includes a plurality of emission control signal lines, wherein the plurality of emission control signal lines correspond to the plurality of rows of pixel units one-to-one; each of the plurality of pixel units also It includes a light-emitting control signal terminal, and the light-emitting control signal terminal of the pixel unit of the m-th row is connected to the m-th light-emitting control signal line to receive the light-emitting control signal.
  • the array substrate provided by the embodiment of the present disclosure further includes a second scan driving circuit, wherein the second scan driving circuit is connected to the plurality of light emission control signal lines and is configured to generate the light emission control signal.
  • every two adjacent columns of pixel units correspond to the same data line, and the data signal terminals of the nth column of pixel units and the n+1th column of pixel units Connect to the same data line.
  • the array substrate provided by the embodiment of the present disclosure further includes a third scan driving circuit connected to the plurality of pairs of gate lines and configured to generate the first scan signal and the first scan signal. 2. Scanning signal.
  • the third scan driving circuit includes a first scan driving sub-circuit and a second scan driving sub-circuit, and the first scan driving sub-circuit is connected to each pair of gate lines. And is configured to generate the first scan signal; the second scan driving sub-circuit is connected to the second gate line in each pair of gate lines, and is configured to generate the second scan Signal.
  • the first scan driving sub-circuit and the second scan driving sub-circuit are respectively arranged on two opposite sides of the pixel array.
  • each pixel unit includes a pixel circuit, and the pixel circuit includes a reset circuit, a data writing and compensation circuit, a driving circuit, and a light emission control circuit.
  • the reset circuit includes the reset signal terminal and is connected to a reset voltage source, the drive circuit, and a light-emitting element, and is configured to apply a reset voltage to the drive circuit and the light-emitting element to affect the drive circuit and the light-emitting element.
  • the light-emitting element is reset;
  • the data writing and compensation circuit includes the scan signal terminal and the data signal terminal, and is connected to the drive circuit and is configured to write the data signal into the drive circuit And compensate the driving circuit;
  • the driving circuit is configured to generate a driving current for driving the light emitting element to emit light;
  • the light emitting control circuit includes a light emitting control signal terminal, and is connected to the first voltage source and the driving circuit And the light-emitting element is configured to apply a first voltage to the driving circuit, and apply a driving current generated by the driving circuit to the light-emitting element.
  • the reset circuit includes a first reset transistor and a second reset transistor;
  • the data writing and compensation circuit includes a data writing transistor, a compensation transistor, and a storage capacitor;
  • the driving circuit includes a driving transistor;
  • the light emission control circuit includes a first light emission control transistor and a second light emission control transistor;
  • the gate of the first reset transistor is connected to the reset signal terminal, and the first reset transistor One pole is connected to the reset voltage source, the second pole of the first reset transistor is connected to the gate of the driving transistor;
  • the gate of the second reset transistor is connected to the reset signal terminal, the first The first electrode of the two reset transistors is connected to the reset voltage source, the second electrode of the second reset transistor is connected to the first end of the light-emitting element;
  • the gate of the data writing transistor is connected to the scan Signal terminal, the first pole of the data writing transistor is connected to the data signal terminal, the second pole of the data writing transistor is connected to the first pole of the driving transistor;
  • the gate of the compensation transistor is connected To the scan signal terminal
  • At least one embodiment of the present disclosure further provides a display panel including the array substrate in any of the foregoing embodiments.
  • At least one embodiment of the present disclosure further provides a driving method applied to the array substrate in any of the foregoing embodiments, including: resetting the pixel unit of the nth column in the mth row of pixel units; and resetting the mth row of pixel units;
  • the pixel unit of the nth column in the row of pixel units performs data writing and compensation, while resetting the pixel unit of the n+1th column in the pixel unit of the mth row;
  • the pixel unit of the +1 column performs data writing and compensation; the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row are displayed.
  • data writing and compensation are performed on the pixel unit of the nth column in the m-th row of pixel units, and at the same time, the n+th pixel unit in the mth row of pixel units is written and compensated.
  • the resetting of 1 column of pixel units includes: providing the first scan signal to the nth column of pixel units in the m-th row of pixel units through the first gate line in the m-th pair of gate lines, and pass and A data line corresponding to the pixel unit of the nth column provides the data signal to the pixel unit of the nth column of the pixel unit of the mth row, so as to perform the operation on the pixel unit of the nth column of the pixel unit of the mth row.
  • resetting the pixel unit of the nth column in the m-th row of pixel units includes: The pixel unit of the nth column in the mth row of pixel units provides the first scan signal as a second reset signal to reset the pixel unit of the nth column in the mth row of pixel units; or, through the The second gate line in the m-1 pair of gate lines provides the second scan signal as the second reset signal to the pixel unit in the m-th row of pixel units in the n-th column, so as to control the m-th row
  • the pixel unit of the nth column in the pixel unit is reset.
  • resetting the pixel unit of the nth column in the pixel unit of the mth row includes: The pixel unit of the nth column of the pixel unit provides a second reset signal to reset the pixel unit of the nth column of the pixel unit of the mth row.
  • performing data writing and compensation on the pixel unit of the n+1th column in the pixel unit of the mth row includes:
  • the second gate line provides the second scan signal to the pixel unit of the n+1th column in the pixel unit of the mth row and sends the second scan signal to the pixel unit of the mth row through a data line corresponding to the pixel unit of the n+1th column.
  • the pixel unit of the n+1th column in the unit provides the data signal to perform data writing and compensation for the pixel unit of the n+1th column in the mth row of pixel units.
  • displaying the pixel unit of the nth column and the pixel unit of the n+1th column in the mth row of pixel units includes: Provide light emission control signals to the pixel units in the nth column and the pixel units in the n+1th column in the mth row of pixel units, so that the pixel units in the nth column and the n+1th column in the mth row of pixel units Pixel unit for display.
  • FIG. 1 is a schematic diagram of the structure of an array substrate
  • FIG. 2A is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • 2B is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 3A is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 3B is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 4B is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel unit in an array substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of the structure of each circuit in the pixel circuit in FIG. 5;
  • FIG. 7 is a timing diagram of signals for driving the pixel circuit in FIG. 6;
  • FIG. 8A is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the reset stage
  • 8B is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the data writing and compensation stage;
  • FIG. 8C is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the light-emitting stage
  • FIG. 9A is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure when it includes the pixel circuit in FIG. 6; FIG.
  • FIG. 9B is another schematic structural diagram of the array substrate provided by an embodiment of the present disclosure when it includes the pixel circuit in FIG. 6; FIG.
  • FIG. 10 is a timing diagram of signals for driving an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a driving method of an array substrate provided by an embodiment of the disclosure.
  • FIG. 1 is a schematic diagram of the structure of an array substrate.
  • the array substrate includes a base substrate and a plurality of gate lines S, a plurality of data lines D and a pixel array arranged on the base substrate.
  • the pixel array includes a plurality of pixel units P arranged in multiple rows and multiple columns, the M-th row of pixel units are connected to the M-th gate line S M to receive scanning signals, and the N-th column of pixel units are connected to the N- th data line D N To receive data signals.
  • Each pixel unit of the pixel array can work based on the received data signal under the control of the received scan signal, so as to emit the required grayscale light, thereby realizing image display.
  • the multiple columns of pixel units in the same row of pixel units will be scanned by the same gate line.
  • the opening time of the multiple columns of pixel units in the same row of pixel units is the same; in addition, because the multiple columns of pixel units in the same row of pixel units are connected to multiple different data lines, the Multiple columns of pixel units sequentially write data signals provided by multiple different data lines.
  • multiple columns of pixel cells in the same row of pixel cells will have different charging methods, such as first charging and then discharging and charging while discharging, which in turn will lead to multiple columns of pixel cells in the same row of pixel cells.
  • the display brightness is uneven, which affects the display quality.
  • At least one embodiment of the present disclosure provides an array substrate including: a plurality of pairs of gate lines, each of the plurality of pairs of gate lines includes a first gate line and a second gate line; a plurality of data lines; and, a pixel array , Including multiple pixel units arranged in multiple rows and multiple columns.
  • Each of the plurality of pixel units includes a scan signal terminal, a data signal terminal, and a reset signal terminal.
  • the scan signal end of the pixel unit of the nth column in the mth row of pixel units is connected to the first gate line of the mth pair of gate lines to receive the first scan signal, m and n are both positive integers; the mth row of pixel units The scan signal end of the pixel unit in the n+1th column in is connected to the second gate line of the m-th pair of gate lines to receive the second scan signal; the reset signal of the pixel unit in the n+1th column in the m-th row of pixel units The terminal is connected to the first gate line of the m-th pair of gate lines to receive the first scan signal as the first reset signal; the data signal terminal of each column of pixel units is connected to a corresponding data line to receive the data signal.
  • the scan signal terminal of the pixel unit of the nth column in the pixel unit of the mth row may be connected to the first gate line of the m-th pair of gate lines to receive the first scan signal.
  • the scan signal terminal of the pixel unit of the n+1th column in the m-row pixel unit may be connected to the second gate line of the m-th pair of gate lines to receive the second scan signal, so that the n-th column pixel in the m-th row pixel unit
  • the cell will be turned on first under the drive of the first scan signal provided by the first gate line in the m-th pair of gate lines, and the pixel cell in the n+1th column will be turned on by the second gate line provided by the second gate line in the m-th pair of gate lines.
  • the scanning signal is driven and then turned on, and the opening time of the pixel unit of the nth column in the pixel unit of the mth row and the pixel unit of the n+1th column are the same.
  • the charging method of the n-th column of pixel units in the m-th row of pixel units is the same as that of the n+1-th column of pixel units to avoid the problem of uneven display brightness of multiple columns of pixel units in the same row of pixel units. In turn, the display quality can be improved.
  • the scan signal terminal of the pixel unit of the nth column in the mth row of pixel units may be connected to the first gate line of the mth pair of gate lines
  • the reset signal terminal of the pixel unit of the n+1th column in the row pixel unit may also be connected to the first gate line of the m-th pair of gate lines, so that the first gate line of the m-th pair of gate lines can be provided to the m-th gate line.
  • the first scan signal of the pixel unit of the nth column in the row of pixel units is applied as the first reset signal to the pixel unit of the n+1th column in the pixel unit of the mth row, so as to correct the n+1th column of the pixel unit in the mth row.
  • the column pixel unit is reset.
  • the number of gate drivers (gate drivers on array, GOA) integrated on the array substrate can also be reduced, which is beneficial to the display device adopting the array substrate to achieve a narrow frame design.
  • FIG. 2A is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 2B is a schematic structural diagram of another array substrate provided by an embodiment of the disclosure.
  • the array substrate 10 includes a base substrate and a plurality of pairs of gate lines S, a plurality of data lines D, and a pixel array arranged on the base substrate.
  • the base substrate may be a glass substrate, a plastic substrate, etc., which is not limited in the embodiments of the present disclosure.
  • a plurality of pairs of gate lines S may be arranged on the base substrate along a first direction, and each pair of the plurality of pairs of gate lines S includes a first gate line So and a second gate line Se; a plurality of data lines D may be arranged along a second direction On the base substrate; the pixel array includes a plurality of pixel units 110 arranged in multiple rows and multiple columns, for example, the multiple pixel units 110 are located in a pixel area defined by the intersection of multiple pairs of gate lines S and multiple data lines D
  • Each pixel unit 110 includes a scan signal terminal GA, a data signal terminal DA, and a reset signal terminal RST to respectively receive a scan signal (for example, a first scan signal or a second scan signal) and a data signal for the pixel unit 110 And a reset signal (for example, the first reset signal or the second reset signal).
  • the first direction may be perpendicular to the second direction
  • the first direction may be the row direction of the pixel array (for example, the X direction in FIGS. 2A and 2B)
  • the second direction may be the column direction of the pixel array (for example, in FIG. 2B). 2A and Y direction in Figure 2B).
  • multiple rows of pixel units may correspond to multiple pairs of gate lines S, and each row of pixel units may be connected to a pair of corresponding gate lines S.
  • the m-th row of pixel units may correspond to The m-th pair of gate lines S m
  • the n-th column of pixel units in the m-th row of pixel units may correspond to the first gate line Se m in the m-th pair of gate lines S m
  • the column of pixel units may correspond to the second gate line So m of S m in the m-th pair of gate lines
  • the scan signal terminal GA of the n-th column of pixel units in the m-th row of pixel units may be connected to the m-th pair of gate lines S m a first gate line m Se to receive the first scan signal
  • the m-th gate line S m for the first gate lines and second gate lines Se So m m may be provided on both sides opposed to each other m-th row of the pixel unit, e.g., the m-th gate line S in m Se m first gate line may be disposed on the side of the m-th row of pixel units, the m-th gate line of the first S m Se m gate line may be disposed at a side of the m-th row of pixel units.
  • multiple columns of pixel units can correspond to multiple data lines D one-to-one, and each column of pixel units can be connected to a corresponding data line D.
  • the nth column of pixel units can correspond to the data line D.
  • There are n data lines Dn and the data signal terminal DA of the pixel unit of the nth column may be connected to the nth data line Dn to receive data signals.
  • each column of pixel units corresponds to one data line D in the plurality of data lines D, and every two adjacent columns of pixel units correspond to the same data line D, for example, the nth column of pixel units and the n+1th column
  • the pixel unit may correspond to the same data line
  • the pixel unit of the n+2th column (not shown) and the pixel unit of the n+3th column (not shown) may correspond to the same data line, ..., and so on.
  • the data signal terminal DA of the pixel unit in the nth column and the data signal terminal DA of the pixel unit in the n+1th column can be connected to the same data line to receive the data signal.
  • the data signal terminal DA of the pixel unit in the n+2 column and the nth column The data signal terminal DA of the +3 column pixel unit can be connected to the same data line to receive the data signal,..., and so on.
  • the n-th data line D n is arranged on the left side of the n-th column of pixel units, and there is a column of pixel units arranged between the two data lines D
  • the present disclosure is obviously not limited to this.
  • the n-th data line D n may be arranged on the right side of the n-th column of pixel units.
  • one data line D may be arranged between two adjacent columns of pixel units corresponding to it, that is, two data lines D Two columns of pixel units can be arranged in between.
  • FIG reset signal terminal RST n + 1 th column of pixels cells in the m-th row of the pixel unit of FIG. 2B may be connected to the m-th gate line S m of the first gate line for receiving a first So m Scan signal.
  • the first scan signal provided by the first gate line So m of the m-th pair of gate lines S m to the n-th column of pixel units in the m-th row of pixel units may be applied as the first reset signal to the m-th row.
  • the pixel unit of the n+1th column in the row of pixel units is to reset the pixel unit of the n+1th column in the mth row of pixel units.
  • the reset signal terminal of the pixel unit of the nth column in the mth row of pixel units is connected to the first gate line of the m-1th pair of gate lines to receive the m-th row of pixel units.
  • the first scan signal provided by the first gate line in the gate line is used as the second reset signal to reset the pixel unit of the nth column in the mth row of pixel units.
  • m is an integer greater than 1.
  • the reset signal RST terminal of the n-th column of the pixel unit m-th row in the pixel unit can be connected to the first gate line m-1 S m-1 in the first gate line So m-1.
  • the first scan signal provided by the first gate line So m-1 in the m-1 pair of gate lines S m-1 to the pixel unit in the n-th column of the pixel unit in the m-1 row can be used as
  • the second reset signal is applied to the pixel unit of the nth column in the pixel unit of the mth row to reset the pixel unit of the nth column in the pixel unit of the mth row.
  • the reset signal terminal RST of the pixel unit of the nth column in the m-th row of pixel units is connected to the first gate line So m-1 of the m-1 pair of gate lines S m-1 case, the reset signal RST terminal of the first n columns of pixel units m-1 rows of pixel cells connected to the gate line m-1 S m-1 in the second gate line Se m-1.
  • the second gate line Se m-1 of the m-1 pair of gate lines S m-1 provides the second scan signal of the pixel unit of the (n+1)th column in the m-1th row of pixel units. It may be applied as the second reset signal to the pixel unit of the nth column in the pixel unit of the m-1th row to reset the pixel unit of the nth column in the pixel unit of the m-1th row.
  • the reset method of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the m-1th row is the same as that of the pixel unit of the nth column and the n+1th column of the pixel unit of the mth row.
  • the reset method of the pixel unit is different. Specifically, in terms of the respective work cycles of the pixel unit in the m-1th row and the pixel unit in the mth row, in the pixel unit in the m-1th row, the utilization of the pixel unit in the nth column is provided to the pixel unit in the n+1th column.
  • the second scan signal of the unit is used as the second reset signal to reset; in the m-th row of pixel units, the n+1th column of pixel units uses the first scan signal provided to the nth column of pixel units as the first reset signal to reset .
  • the reset signal terminal of the pixel unit of the nth column in the mth row of pixel units is connected to the second gate line of the m-1th pair of gate lines to receive the mth -1
  • the second scan signal provided by the second gate line in the gate line is used as the second reset signal to reset the pixel unit of the nth column in the mth row of pixel units.
  • m is an integer greater than 1.
  • the reset signal RST terminal of the n-th column of the pixel unit m-th row in the pixel unit can be connected to the first gate line m-1 S m-1 in the second gate line Se m-1.
  • the second gate line Se m-1 of the m-1 pair of gate lines S m-1 provides the second scan signal of the pixel unit of the (n+1)th column in the m-1th row of pixel units. It can be applied as the second reset signal to the pixel unit of the nth column in the pixel unit of the mth row to reset the pixel unit of the nth column in the pixel unit of the mth row.
  • the reset signal terminal RST of the pixel unit of the nth column in the mth row of pixel units is connected to the second gate line Se m-1 of the m-1 pair of gate lines S m-1 case, the reset terminal RST signal is n + 1, the first column of pixels cells m-1 rows of pixel cells connected to the gate line m-1 S m-1 in the first gate line So m-1.
  • the first scan signal provided by the first gate line So m-1 in the m-1 pair of gate lines S m-1 to the pixel unit in the n-th column of the pixel unit in the m-1 row can be used as The first reset signal is applied to the (n+1)th column of pixel units in the (m-1)th row of pixel units to reset the (n+1)th column of pixel units in the (m-1)th row of pixel units.
  • the reset method of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the m-1th row is the same as that of the pixel unit of the nth column and the n+1th column of the pixel unit of the mth row.
  • the reset method of the pixel unit is the same. Specifically, in terms of the respective work cycles of the pixel unit in the m-1 row and the pixel unit in the m row, in the pixel unit in the m-1 row and the pixel unit in the m row, the pixel unit in the n+1 column uses The first scan signal provided to the pixel unit of the nth column is used as a first reset signal for resetting.
  • the first reset signal and the second reset signal are for pixel units in different columns (for example, the nth column and the n+1th column) in the same row of pixel units. It is only used to distinguish in the description, not to indicate the time limit.
  • the first reset signal may refer to a signal for resetting the pixel unit of the n+1th column
  • the second reset signal may refer to a signal for resetting the pixel unit of the nth column.
  • the pixel unit of the n-th column receives from the first gate line So m-1 of the m-1 pair of gate lines S m-1
  • the first scan signal is used as the second reset signal
  • the pixel unit of the n+1th column receives the first scan signal as the first reset signal from the first gate line So m in the m-th pair of gate lines S m;
  • the pixel unit of the nth column receives the second scan signal as the second reset signal from the second gate line Se m-1 of the m-1 pair of gate lines S m-1.
  • the pixel unit of the n-th column receives the second scan signal from the second gate line Se m-1 of the m-1 pair of gate lines S m-1 as the second reset.
  • n + 1 th column of the pixel unit receives the first signal from the m-th scanning lines S of m in the gate of the first gate line as a first reset signal So m; m-1 in the first row of the pixel unit, the n + 1
  • the column pixel unit receives the first scan signal as the first reset signal from the first gate line So m-1 of the m-1 pair of gate lines S m-1.
  • each pixel unit of the plurality of pixel units further includes a light-emission control signal terminal to receive the light-emission control signal for the pixel unit.
  • the array substrate provided by this embodiment may further include a plurality of light emission control signal lines arranged on the base substrate, and the plurality of light emission control signal lines correspond to the multiple rows of pixel units one-to-one, and the light emission control of the m-th row of pixel units The signal terminal is connected to the m-th light-emitting control signal line to receive the light-emitting control signal.
  • each pixel unit 110 further includes an emission control signal terminal EM.
  • the array substrate 10 further includes a plurality of light emission control signal lines E arranged on the base substrate, for example, a plurality of light emission control signal lines E may be arranged on the base substrate along the first direction.
  • the multiple light-emitting control signal lines E may correspond to multiple rows of pixel units one-to-one, and each row of pixel units may be connected to one light-emitting control signal line E corresponding thereto.
  • the m-th row of pixel units corresponding to the m-th emission control signal line E m, the m-th row of pixel units light emission control signal EM terminal may be connected to the m-th emission control signal line to receive the E m emitting control signal.
  • the present embodiment is obviously not limited to this disclosed embodiment.
  • the m E m emission control signal line may be disposed on the side of the m-th row of pixel units.
  • the array substrate may further include a plurality of reset signal lines disposed on the base substrate, and the plurality of reset signal lines correspond to a plurality of rows of pixel units one-to-one, and the nth column of the mth row of pixel units The reset signal end of the pixel unit is connected to the m-th reset signal line to receive the second reset signal, so as to reset the n-th column of pixel units in the m-th row of pixel units.
  • FIG. 3A is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 3B is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the array substrate 10 further includes a plurality of reset signal lines R disposed on the base substrate.
  • the plurality of reset signal lines R may be disposed on the base substrate along the first direction.
  • the reset signal terminal RST of the pixel unit in the n+1th column of the pixel unit in the mth row may be connected to the first gate line So in the m-th pair of gate lines Sm.
  • m uses the first scan signal as the first reset signal to reset the pixel unit of the n+1th column in the pixel unit of the mth row.
  • multiple reset signal lines R can correspond to multiple rows of pixel units one-to-one, and each row of pixel units can be connected to a corresponding reset signal line R.
  • the mth row of pixel units may correspond to the mth reset signal line Rm
  • the reset signal terminal RST of the nth column of pixel units in the mth row of pixel units may be connected to the mth reset signal line Rm to receive the mth reset signal line Rm.
  • the second reset signal is used to reset the pixel unit of the nth column in the pixel unit of the mth row.
  • the m R & lt m reset signal line of the m-th gate line S m of the first gate lines and second gate lines Se So m m may be provided on both sides opposed to each other m-th row of the pixel unit, e.g., Article m m R & lt reset signal line may be disposed on the side of the m-th row of pixel units, the m-th gate line S m for the first gate lines and second gate lines Se So m m m-th row may be provided in pixel units The underside.
  • the reset signal terminal RST of the pixel unit of the nth column in the pixel unit of the m-1th row may be connected to the m-1th reset signal line Rm-1 to receive the second reset signal to correct the
  • the pixel unit of the nth column in the pixel unit of the m-1 row is reset, and m is an integer greater than 1.
  • the reset signal terminal RST of the pixel unit in the (n+1)th column of the pixel unit in the m-1th row may be connected to the first gate line So m- of the m-1 pair of gate lines S m-1. 1 Receiving the first scan signal as the first reset signal to reset the pixel unit of the (n+1)th column in the pixel unit of the m-1th row.
  • the reset method of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the m-1th row is the same as that of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the m-1th row.
  • the reset method of the unit can be the same. Specifically, in terms of the respective working cycles of the pixel unit in the m-1 row and the pixel unit in the m row, in the pixel unit in the m-1 row and the pixel unit in the m row, the pixel unit in the nth column uses a separately provided pixel unit.
  • the second reset signal is used for resetting, and the pixel unit of the n+1th column is reset by using the first scan signal provided to the pixel unit of the nth column as the second reset signal.
  • the reset signal terminal RST of the pixel unit in the (n+1)th column of the pixel unit in the m-1th row may be connected to the m-1th reset signal line R m-1 to receive the first reset signal. Reset the pixel unit of the n+1th column in the pixel unit of the m-1th row.
  • the reset signal terminal RST of the pixel unit of the nth column in the pixel unit of the m-1th row may be connected to the second gate line Se m-1 of the m- 1th pair of gate lines S m-1.
  • the second scan signal is received as the second reset signal to reset the pixel unit of the nth column in the pixel unit of the m-1th row.
  • the reset method of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the m-1th row is the same as that of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row.
  • the reset method of the unit can be different. Specifically, in terms of the respective work cycles of the pixel unit of the m-1 row and the pixel unit of the m row, in the pixel unit of the m-1 row, the pixel unit of the nth column is provided to the pixel unit of the n+1th column.
  • the second scan signal is used as the second reset signal for resetting.
  • the pixel unit of the n+1th column is reset by the first reset signal provided separately; in the pixel unit of the mth row, the pixel unit of the nth column is reset by using the separately provided first reset signal.
  • the second reset signal is used for resetting, and the pixel unit of the n+1th column is reset by using the first scan signal provided to the pixel unit of the nth column as the first reset signal.
  • the signal for resetting the pixel unit of the n+1th column is called the first reset signal
  • the signal for resetting the pixel unit of the nth column is called Do the second reset signal.
  • the m-th row in the pixel unit, the n-th column of the pixel unit receives the second reset signal from the m-th reset signal line R m 3B, the first column of pixels n + 1
  • the unit receives the first scan signal from the first gate line So m of the m-th pair of gate lines S m as the first reset signal; as shown in FIG.
  • the pixel unit of the nth column receives the second reset signal
  • the pixel unit of the n+1th column receives the first gate line So m-1 from the first gate line So m-1 of the m- 1th pair of gate lines S m-1
  • the scan signal is used as the first reset signal; as shown in FIG. 3B, in the pixel unit of the m-1th row, the pixel unit of the nth column pairs the second gate line Se m- of the gate line S m-1 from the m-1th row of the pixel unit. 1 Receive the second scan signal as the second reset signal, and the pixel unit of the n+1th column receives the first reset signal from the m-1th reset signal line Rm-1.
  • FIGS. 3A and 3B For the sake of simplicity, only the multiple reset signal lines R in FIGS. 3A and 3B are described in detail here.
  • the multiple pairs of gate lines S, multiple data lines D, and multiple light-emitting control signals in FIGS. 3A and 3B For the description of the line E and the plurality of pixel units 110, please refer to the above description of the multiple pairs of gate lines S, multiple data lines D, multiple light-emitting control signal lines E, and multiple pixel units 100 in FIGS. 2A and 2B. Description, I won’t repeat it here.
  • FIGS. 2A, 2B, 3A, and 3B the multiple pairs of gate lines S, multiple reset signal lines R, and multiple light-emitting control signal lines E are performed in order from top to bottom.
  • the data lines D are numbered in the order from left to right, but this is only for convenience of description, and does not limit the absolute position relationship of each signal line.
  • the embodiments of the present disclosure are obviously not limited to this .
  • multiple pairs of gate lines S, multiple reset signal lines R, and multiple light-emitting control signal lines E may be numbered in a bottom-to-top order, and/or multiple data lines D may be numbered in a right-to-left order. Numbering.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a first scan driving circuit disposed on the base substrate, and the first scan driving circuit is connected to a plurality of reset signal lines and is configured to generate a second reset signal.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a second scan driving circuit disposed on the base substrate, and the second scan driving circuit is connected to a plurality of light emission control signal lines and is configured to generate light emission control signals.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a third scan driving circuit disposed on the base substrate, and the third scan driving circuit is connected to a plurality of pairs of gate lines and is configured to generate the first scan signal and the first scan signal. 2. Scanning signal.
  • FIG. 4A is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • the array substrate 10 further includes a first scan driving circuit 210, a second scan driving circuit 220, and a third scan driving circuit 230 disposed on the base substrate.
  • the first scan driving circuit 210 may be connected to a plurality of reset signal lines R and configured to generate a second reset signal.
  • a first scan driving circuit 210 may provide a second reset signal to the n-th column pixel units in the m-th row of pixel units by the m-th reset signal line R m.
  • the second scan driving circuit 220 may be connected to a plurality of light emission control signal lines E, and is configured to generate light emission control signals.
  • a second scan driving circuit 220 may control the signal line E m by the m-th light emission control signal to provide a light emitting m-th row in the n-th unit pixel column of the pixel unit and the n + 1 columns of pixel units.
  • the third scan driving circuit 230 may be connected to multiple pairs of gate lines S and configured to generate a first scan signal and a second scan signal.
  • the third scan driving circuit 230 may be provided by the m-th gate line S m of the first gate line to the n-th column So m m-th row of pixel units in the pixel units of the first scan signal, and can be of the m the gate line S m Se m second gate line a second scan signal to the n + 1 th row of the m columns of pixel units in the pixel unit.
  • FIG. 4A shows that the second reset signal, the light emission control signal, and the first scan signal and the second scan signal are respectively generated by the first scan driving circuit 210, the second scan driving circuit 220, and the third scan driving circuit 230.
  • the second reset signal, the light emission control signal, and the first scan signal and the second scan signal may be provided by the same larger scan driving circuit.
  • FIG. 4A shows that the first scan driving circuit 210, the second scan driving circuit 220, and the third scan driving circuit 230 are all disposed on the left side of the pixel array
  • the embodiments of the present disclosure are obviously not limited to this.
  • the first scan driving circuit 210, the second scan driving circuit 220, and the third scan driving circuit 230 may all be arranged on the right, upper or lower side of the pixel array, or the first scan driving circuit 210 and the second scan driving circuit
  • the circuit 220 and the third scan driving circuit 230 may be respectively disposed on different sides of the pixel array.
  • the first scan driving circuit 210, the second scan driving circuit 220, and the third scan driving circuit 230 shown in FIG. 4A may be gate driving integrated circuits (chips), which may be arranged on the base substrate by bonding. Or it can be directly prepared on the base substrate through a semiconductor process, that is, in the form of GOA.
  • FIG. 4A shows that the first scan driving circuit 210, the second scan driving circuit 220, and the third scan driving circuit 230 are separately provided, the first scan driving circuit 210, the second scan driving circuit 220, and the third scan The driving circuit 230 may be provided in a combined manner, for example, provided by the same gate driving integrated circuit, or prepared in the same area on the base substrate.
  • the third scan driving circuit includes a first scan driving sub-circuit and a second scan driving sub-circuit.
  • the first scan driving sub-circuit is connected to the first gate line of each pair of gate lines and is configured to generate a first scan signal;
  • the second scan driving sub-circuit is connected to the second gate line of each pair of gate lines and is It is configured to generate a second scan signal.
  • FIG. 4B is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • the third scan driving circuit 230 includes a first scan driving sub-circuit 231 and a second scan driving sub-circuit 232.
  • the first scan driving sub-circuit 231 may be connected to the first gate line So in each pair of gate lines S and configured to generate a first scan signal.
  • the first sub-scan driving circuit 231 may provide a first scan signal to the n-th column pixel units in the m-th row of pixel units by the m-th gate line S m of the first gate line So m.
  • the second scan driving sub-circuit 232 may be connected to the second gate line Se in each pair of gate lines S and configured to generate a second scan signal.
  • the second scan driving sub-circuit 232 may provide the second scan signal to the pixel unit of the m-th row of pixel units through the second gate line Se m of the m-th pair of gate lines S m.
  • first scan driving sub-circuit 231 and the second scan driving sub-circuit 232 in FIG. 4B are described in detail here, and the first scan driving circuit 210 and the second scan driving circuit 220 in 4B are described in detail. Please refer to the related description of the first scan driving circuit 210 and the second scan driving circuit 220 in FIG. 4A above, which will not be repeated here.
  • FIG. 4B shows that the first scan driving sub-circuit 231 and the second scan driving sub-circuit 232 are respectively disposed on opposite sides (left and right) of the pixel array
  • the implementation of the present disclosure The example is obviously not limited to this.
  • the first scan driving sub-circuit 231 and the second scan driving sub-circuit 232 may be arranged on the same side of the pixel array.
  • the first scan driving sub-circuit 231 and the second scan driving sub-circuit 232 may both be arranged in the pixel array. Left, right, upper or lower side.
  • connection lines in the array substrate 10 in FIGS. 4A and 4B Is connected to the pixel array in the same manner as in the array substrate 10 in FIG. 3A, but the connection method between each connection line and the pixel array in the array substrate 10 in FIGS. 4A and 4B can also be adopted in FIG. 3B
  • the connection mode of each connection line in the array substrate 10 in FIG. 4A and FIG. 4B to the pixel array can also be the connection mode in the array substrate 10 in FIG. 2A or FIG. 2B.
  • the array substrate 10 in FIG. 4B may not include a plurality of reset signal lines R, and accordingly does not include the first scan driving circuit 210.
  • multiple columns of pixel units correspond to multiple data lines in a one-to-one correspondence, but the embodiments of the present disclosure are obviously not limited to this.
  • at least two columns of pixel units may correspond to one data line.
  • two adjacent columns of pixel units correspond to the same data line
  • two adjacent columns of pixel units may correspond to the same data line.
  • the data signal end of the unit can be connected to the same data line to receive the same data signal (see the embodiment shown in FIG. 9B later), thereby realizing the sharing of data lines, reducing the number of data lines and the number of data driving circuits, Thereby reducing manufacturing costs.
  • each pixel unit includes a pixel circuit and a light-emitting element
  • the pixel circuit includes a reset circuit, a data writing and compensation circuit, a driving circuit, and a light-emitting control circuit.
  • the reset circuit includes a reset signal terminal and is connected to a reset voltage source, a driving circuit and a light emitting element, and is configured to apply a reset voltage to the driving circuit and the light emitting element to reset the driving circuit and the light emitting element;
  • the data writing and compensation circuit includes The scan signal terminal and the data signal terminal are connected to the driving circuit, and are configured to write the data signal into the driving circuit and compensate the driving circuit;
  • the driving circuit is configured to generate a driving current for driving the light-emitting element to emit light;
  • the light-emitting control circuit includes light-emitting
  • the control signal terminal is connected to the first voltage source, the driving circuit and the light emitting element, and is configured to apply the first voltage to the driving circuit and apply the driving current generated by the driving circuit to the light emitting element.
  • FIG. 5 is a schematic structural diagram of a pixel unit in an array substrate provided by an embodiment of the disclosure.
  • the pixel unit 100 includes a pixel circuit 110 and a light-emitting element 120.
  • the pixel circuit 110 includes a reset circuit 111, a data writing and compensation circuit 112, a driving circuit 113, and a light emission control circuit 114.
  • the reset circuit 111 includes a reset signal terminal RST, which is connected to the reset voltage source VINT, the drive circuit 113, and the light emitting element 120, and is configured to reset received from the reset voltage source VINT under the control of the reset signal. Voltage is applied to the driving circuit 113 and the light emitting element 120 to reset the driving circuit 113 and the light emitting element 120.
  • the reset signal here may be the first reset signal or the second reset signal described in the previous embodiment, and the reset signal mentioned in the subsequent embodiment has a similar meaning to this, so it will not be repeated.
  • the data writing and compensation circuit 112 includes a scan signal terminal GA and a data signal terminal DA, is connected to the drive circuit 113, and is configured to write the data signal into the drive circuit 113 under the control of the scan signal , And compensate the driving circuit 113.
  • the scan signal here may be the first scan signal or the second scan signal described in the previous embodiment, and the scan signal mentioned in the subsequent embodiment has a similar meaning to this, so it will not be repeated.
  • the driving circuit 130 is connected to the reset circuit 111, the data writing and compensation circuit 112, and the light emission control circuit 114, and is configured to generate a driving current for driving the light emitting element 120 to emit light.
  • the light emission control circuit 114 includes a light emission control signal terminal EM, which is connected to the first voltage source VDD, the driving circuit 113 and the light emitting element 120, and is configured to be controlled from the first voltage source under the control of the light emission control signal.
  • the first voltage received by VDD is applied to the driving circuit 113 and the driving current generated by the driving circuit 120 is applied to the light emitting element 120.
  • the light emitting element 120 is connected to the second voltage source VSS, the reset circuit 111, and the light emission control circuit 114, and is configured to emit light under the driving of the driving current generated by the driving circuit 113.
  • the light-emitting element 120 may be a light-emitting diode or the like.
  • the light emitting diode may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED) or the like.
  • the reset circuit includes a first reset transistor and a second reset transistor
  • the data writing and compensation circuit includes a data writing transistor, a compensation transistor, and a storage capacitor
  • the driving circuit includes a driving transistor
  • the light emission control circuit includes a first light emission control transistor and a second light emission control transistor.
  • the gate of the data writing transistor is connected to the scan signal terminal, the first electrode of the data writing transistor is connected to the data signal terminal, the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; the gate of the compensation transistor The first electrode of the compensation transistor is connected to the second electrode of the drive transistor, the second electrode of the compensation transistor is connected to the gate of the drive transistor; the first end of the storage capacitor is connected to the first voltage source, The second terminal of the capacitor is connected to the gate of the driving transistor; the gate of the first reset transistor is connected to the reset signal terminal, the first terminal of the first reset transistor is connected to the reset voltage source, and the second terminal of the first reset transistor is connected to The gate of the driving transistor; the gate of the second reset transistor is connected to the reset signal terminal, the first electrode of the second reset transistor is connected to the reset voltage source, and the second electrode of the second reset transistor is connected to the first terminal of the light-emitting element; The gate of the first light emission control transistor is connected to the light emission control signal terminal, the first electrode of the first light emission
  • FIG. 6 is a schematic diagram of the structure of each circuit in the pixel circuit in FIG. 5.
  • the reset circuit 111 includes a first reset transistor T1 and a second reset transistor T2;
  • the data writing and compensation circuit 112 includes a data writing transistor T3, a compensation transistor T4, and a storage capacitor Cst;
  • the driving circuit 113 includes a driving transistor Td;
  • the light emission control circuit 114 includes a first light emission control transistor T5 and a second light emission control transistor T6.
  • the gate of the first reset transistor T1 is connected to the reset signal terminal RST to receive the reset signal
  • the first electrode of the first reset transistor T1 is connected to the first voltage source VINT to receive the first voltage
  • the first reset The second electrode of the transistor T1 is connected to the gate of the driving transistor Td.
  • the gate of the second reset transistor T2 is connected to the reset signal terminal RST to receive the reset signal
  • the first pole of the second reset transistor T2 is connected to the first voltage source VINT to receive the first voltage
  • the second reset The second terminal of the transistor T2 is connected to the first terminal of the light-emitting element 120.
  • the gate of the data writing transistor T3 is connected to the scan signal terminal GA to receive the scan signal
  • the first pole of the data writing transistor T3 is connected to the data signal terminal to receive the data signal
  • the data writing transistor T3 The second electrode is connected to the first electrode of the driving transistor Td.
  • the gate of the compensation transistor T4 is connected to the scan signal terminal GA to receive the scan signal, the first electrode of the compensation transistor T4 is connected to the second electrode of the driving transistor Td, and the second electrode of the compensation transistor T4 is connected to the driving transistor.
  • the gate of the transistor Td is connected to the scan signal terminal GA to receive the scan signal, the first electrode of the compensation transistor T4 is connected to the second electrode of the driving transistor Td, and the second electrode of the compensation transistor T4 is connected to the driving transistor.
  • the gate of the transistor Td is connected to the scan signal terminal GA to receive the scan signal
  • the first electrode of the compensation transistor T4 is connected to the second electrode of the driving transistor Td
  • the second electrode of the compensation transistor T4 is connected to the driving transistor.
  • the gate of the transistor Td is connected to the driving transistor.
  • the first end of the storage capacitor Cst is connected to the first voltage source, and the second end of the storage capacitor Cst is connected to the gate of the driving transistor Td.
  • the gate of the first light emission control transistor T5 is connected to the light emission control signal terminal EM to receive the light emission control signal, and the first electrode of the first light emission control transistor T5 is connected to the first voltage source VDD to receive the first voltage.
  • the second pole of the first light-emitting control transistor T5 is connected to the first pole of the driving transistor T5.
  • the gate of the second emission control transistor T6 is connected to the emission control signal terminal EM to receive the emission control signal
  • the first pole of the second emission control transistor T6 is connected to the second pole of the driving transistor Td
  • the second pole of the second emission control transistor T6 is connected to the second pole of the driving transistor Td.
  • the second terminal of the light-emitting transistor T6 is connected to the first terminal of the light-emitting element 120.
  • the second terminal of the light emitting element 120 is connected to the second voltage source Vss to receive the second voltage.
  • the light-emitting element 120 is an organic light-emitting diode (OLED)
  • the anode of the OLED is the first end of the light-emitting element 120
  • the cathode of the OLED is the second end of the light-emitting element 120.
  • the embodiments of the present disclosure are all taking the reset voltage source VINT inputting a low voltage, the first voltage source VDD inputting a high voltage, and the second voltage source VSS inputting a low voltage, or the second end of the light-emitting element 120 is grounded as an example.
  • the description, and the high and low here only indicate the relative magnitude relationship between the input voltages.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors used in the embodiments of the present disclosure can all be P-type transistors or N-type transistors, and it is only necessary to refer to the respective poles of the transistors of the selected type with reference to the respective transistors in the embodiments of the present disclosure. Connect the poles accordingly, and make the corresponding voltage terminals provide the corresponding high voltage or low voltage.
  • the input terminal is the drain and the output terminal is the source, and the control terminal is the gate;
  • the P-type transistor the input terminal is the source and the output terminal is the drain, and the control terminal is the gate. pole.
  • the level of the control signal at the control terminal is also different.
  • an N-type transistor when the control signal is at a high level, the N-type transistor is in an on state; and when the control signal is at a low level, the N-type transistor is in an off state.
  • a P-type transistor when the control signal is at a low level, the P-type transistor is in an on state; and when the control signal is at a high level, the P-type transistor is in an off state.
  • oxide semiconductors such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), can be used as the active layer of thin film transistors.
  • Crystalline silicon for example, hydrogenated amorphous silicon
  • Low-temperature polysilicon generally refers to a situation where the crystallization temperature of polysilicon obtained from the crystallization of amorphous silicon is lower than 600 degrees Celsius.
  • FIG. 7 is a timing chart of signals for driving the pixel circuit in FIG. 6.
  • the working process of the pixel circuit 110 includes three stages, which are a reset stage P1, a data writing and compensation stage P2, and a light-emitting stage P3.
  • FIG. 8A is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the reset stage.
  • FIG. 8B is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the data writing and compensation stage.
  • FIG. 8C is an equivalent circuit diagram of the pixel circuit shown in FIG. 6 in the light-emitting stage.
  • VDD, VSS, and VINT are used to indicate the corresponding voltage source and the corresponding voltage; RST, GA, DA, and EM are used to indicate the corresponding The signal terminal is also used to indicate the corresponding signal.
  • the transistors marked with "x" in FIG. 8A, FIG. 8B, and FIG. 8C all indicate that the transistor is in the off state in the corresponding stage.
  • FIG. 7 and FIG. 8A, FIG. 8B, and FIG. 8C illustrate the working process of the pixel circuit in FIG. 6.
  • a low-level reset signal RST As shown in FIG. 7, in the reset phase P1, a low-level reset signal RST, a high-level scan signal GA, a high-level light-emitting control signal EM, and a low-level data signal DA are input.
  • the gate of the first reset transistor T1 receives a low-level reset signal RST, and the first reset transistor T1 is turned on, thereby applying the reset voltage VINT to the gate of the driving transistor Td
  • the gate of the driving transistor Td is reset, so that the driving transistor Td enters the data writing and compensation phase P2 in a conductive state.
  • the gate of the second reset transistor T2 receives a low-level reset signal RST, and the second reset transistor T2 is turned on, so that the reset voltage VINT is applied to the anode of the OLED to affect the OLED
  • the anode is reset, so that the OLED does not emit light before the light-emitting stage P3.
  • the gate of the data writing transistor T3 receives the high-level scanning signal GA, and the data writing transistor T3 is turned off; the gate of the compensation transistor T4 receives the high-level The scanning signal GA, the compensation transistor T4 is turned off; the gate of the first light-emission control transistor T5 receives the high-level light-emission control signal EM, the first light-emission control transistor T5 is turned off; the gate of the second light-emission control transistor T6 receives the high voltage With the flat emission control signal EM, the second emission control transistor T6 is turned off.
  • a high-level reset signal RST As shown in FIG. 7, in the data writing and compensation stage P2, a high-level reset signal RST, a low-level scan signal GA, a high-level light-emitting control signal EM, and a high-level data signal DA are input.
  • the gate of the data writing transistor T3 receives the low-level scan signal GA, and the data writing transistor T3 is turned on, thereby writing the data signal to the first node N1 (ie, the first pole of the driving transistor Td).
  • the gate of the compensation transistor T4 receives the low-level scan signal GA, and the compensation transistor T3 is turned on.
  • the data signal DA charges the storage capacitor Cst through the data writing transistor T3, the driving transistor Td, and the compensation transistor T4, that is, the second node N2 (That is, the gate of the driving transistor Td) is charged, and the voltage of the third node N3 gradually rises.
  • Vda represents the voltage of the data signal DA
  • Vth represents the threshold voltage of the drive transistor Td. Since in this embodiment, the drive transistor T1 is described as an example of a P-type transistor, the threshold voltage Vth here can be a negative value. .
  • the voltage of the second node N2 is Vdata+Vth, that is to say, the voltage information of the data signal DA and the threshold voltage Vth is stored in the storage capacitor Cst for subsequent use in the light-emitting phase P3 At this time, the threshold voltage of the driving transistor Td is compensated.
  • the gate of the first reset transistor T1 receives a high-level reset signal RST, the first reset transistor T1 is turned off; the gate of the second reset transistor T2 Receiving a high-level reset signal, the second reset transistor T2 is turned off; the gate of the first light-emission control transistor T5 receives a high-level light-emission control signal EM, and the first light-emission control transistor T5 is turned off; and the second light-emission control transistor T6 The gate of T6 receives the high-level emission control signal EM, and the second emission control transistor T6 is turned off.
  • a high-level reset signal RST As shown in FIG. 7, in the light-emitting stage P3, a high-level reset signal RST, a high-level scan signal GA, a low-level light-emitting control signal EM, and a low-level data signal DA are input.
  • the gate of the first light-emitting control transistor T5 receives the low-level light-emitting control signal EM, and the first light-emitting control transistor T5 is turned on, thereby applying the first voltage VDD to the first light-emitting control signal EM.
  • Node N1 ie, the first pole of the driving transistor Td.
  • the gate of the second emission control transistor T6 receives the low-level emission control signal EM, and the second emission control transistor T6 is turned on, thereby applying the driving current generated by the driving transistor Td to the OLED.
  • the gate of the first reset transistor T1 receives a high-level reset signal RST, and the first reset transistor T1 is turned off; the gate of the second reset transistor T2 receives a high voltage.
  • Flat reset signal the second reset transistor T2 is turned off;
  • the gate of the data writing transistor T3 receives the high-level scanning signal GA, and the data writing transistor T3 is turned off;
  • the gate of the compensation transistor T4 receives the high-level scanning With signal GA, the compensation transistor T4 is turned off.
  • the driving transistor Td is also turned on.
  • the anode and cathode of the OLED are respectively connected to the first voltage VDD (high voltage) and the second voltage VSS (low voltage), so that they are driven by the driving current generated by the driving transistor Td. Glow.
  • I D K(V GS -Vth) 2
  • Vth represents the threshold voltage of the drive transistor Td
  • V GS represents the voltage between the gate and source of the drive transistor Td
  • K is a constant.
  • K in the above formula can be expressed as:
  • m n is the electron mobility of the driving transistor Td
  • C ox is the gate capacitance per unit driving transistor Td
  • W is a channel width of the driving transistor Td
  • L is a channel length of the driving transistor Td.
  • FIG. 9A is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure when it includes the pixel circuit in FIG. 6.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T2 are connected to the m-1th reset signal line R m-1 to receive the second reset signal
  • the gate of the data writing transistor T3 and the gate of the compensation transistor T4 are connected to the first gate line So m-1 of the m-1 pair of gate lines S m-1
  • the first electrode of the data writing transistor T3 is connected to the n-th data line Dn to receive the data signal
  • the gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6 are connected to The m-1th light-emission control signal line Em -1 is to receive the light-emission control signal.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T2 are connected to the m-1th pair of gates.
  • the first gate line So m-1 in the line S m receives the first scan signal as the first reset signal, and the gate of the data writing transistor T3 and the gate of the compensation transistor T4 are connected to the m-1 pair of gate lines S m 1-second gate line Se m-1 for receiving the second scan signal, data is written to a first electrode of the transistor connected to the n + 1 data lines D n + 1 to receive the data signal, the first light emitting T3
  • the gate of the control transistor T5 and the gate of the second light-emission control transistor T6 are connected to the m-1th light-emission control signal line Em -1 to receive the light-emission control signal.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T2 are connected to the mth reset signal line Rm to receive a second reset signal
  • data is written to the gate of the transistor T3 and the gate of the compensation transistor T4 is connected to the m-th gate line S m
  • the first gate line for receiving a first scan signal is m
  • data write transistor T3 a first electrode connected to the n-th data lines D n to receive the data signal
  • the first light emission control gate of the transistor T5 and a second light emission control gate of the transistor T6 is connected to the m-th emission control signal line to receive the E m emitting control signal.
  • the first n + 1 columns of pixel units in the m-th row in the pixel unit, the reset gate of the first transistor T1 and a second reset transistor T2 is connected to the gate line m of the m S
  • the first gate line So m of S m receives the first scan signal as the first reset signal
  • the gate of the data writing transistor T3 and the gate of the compensation transistor T4 are connected to the second gate line Se in the m-th pair of gate lines S m m to receive the second scan signal
  • the first pole of the data writing transistor T3 is connected to the n+1 data line D n+1 to receive the data signal
  • the gate of the first light emitting control transistor T5 and the second light emitting control transistor T6 is connected to the gate of the m-th emission control signal line to receive the E m emitting control signal.
  • the array substrate 10 including the pixel circuit in FIG. 6 shown in FIG. 9A adopts the structure of the array substrate 10 shown in FIG. 3A
  • the embodiments of the present disclosure are obviously not limited to this.
  • the array substrate 10 shown in FIG. 9A may adopt the structure of the array substrate 10 in FIG. 2A, FIG. 2B, or FIG. 3B.
  • the array substrate may not include the reset signal line R; pixel unit, the reset gate of the first transistor T1 and second transistor T2 is reset gate connected to the pair of m-1 1 m-gate lines in the second gate line Se S m-1 to receive the second scan signal As a second reset signal; in the pixel unit of the nth column in the mth row of pixel units, the gate of the first reset transistor T1 and the gate of the second reset transistor T2 are connected to the m-1 pair of gate lines S m- a first gate line So m-1 for receiving the first scan signal as the second reset signal.
  • connection manner of other transistors in the pixel unit of the n+1th column reference may be made to the above description of the array substrate 10 in FIG. 9A (that is, the structure of the array substrate 10 in FIG. 3A is adopted), which is not repeated here.
  • the array substrate including the pixel circuit in FIG. 6 adopts the structure of the array substrate 10 in FIG. 2B
  • the array substrate may not include the reset signal line R; the pixel unit in the nth column in the mth row gate, the reset gate of the first transistor T1 and a second reset transistor T2 is connected to the pair of m-1 1 m-gate lines in the second gate line Se S m-1 to receive a second signal as the scanning 2. Reset signal.
  • connection manner of other transistors in the pixel unit of the n+1th column reference may be made to the above description of the array substrate 10 in FIG. 9A (that is, the structure of the array substrate 10 in FIG. 3A is adopted), which is not repeated here.
  • the array substrate including the pixel circuit in FIG. 6 adopts the structure of the array substrate 10 in FIG. 3B
  • the a second gate electrode and the reset gate of the transistor T2 is connected to the pair of m-1 1 m-gate lines in the second gate line Se S m-1 to receive the second scan signal as the second reset signal;
  • first m- In the n+1th column of pixel units in one row of pixel units, the gates of the first reset transistor T1 and the gates of the second reset transistor T2 are connected to the m-1th reset signal line Rm-1 .
  • connection manner of other transistors in the pixel unit of the n+1th column reference may be made to the above description of the array substrate 10 in FIG. 9A (that is, the structure of the array substrate 10 in FIG. 3A is adopted), which is not repeated here.
  • FIG. 9B is another schematic structural diagram of the array substrate provided by an embodiment of the present disclosure when it includes the pixel circuit in FIG. 6.
  • the first electrode of the data writing transistor T3 is connected to the i-th data line Di to Receive a data signal; in the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row, the first electrode of the data writing transistor T3 is connected to the i-th data line Di to receive the data signal. Comparing FIGS. 9A and 9B, it can be seen that in the array substrate 10 shown in FIG.
  • the pixel unit in the nth column and the pixel unit in the n+1th column are connected to different data lines D, and the pixel unit in the nth column is connected to the n
  • the data line D n the pixel unit of the n+1th column is connected to the n+1th data line D n+1 ; however, in the array substrate 10 shown in FIG. 9B, the pixel unit of the nth column and the n+1th column pixel cell connected to the same data line.
  • connection mode of the data writing transistor T3 and the data line in the array substrate in FIG. 9B is described in detail here.
  • connection mode of other transistors in the array substrate in FIG. 9B please refer to The related description made above for the array substrate in FIG. 9A will not be repeated here.
  • FIG. 10 is a timing diagram of signals for driving the array substrate provided by an embodiment of the present disclosure.
  • the working process of the pixel unit of the nth column in the mth row of pixel units is divided into three stages, which are the first reset stage P1 n , the first data writing and compensation stage P2 n, and the first light emitting stage.
  • Stage P3 n the working process of the pixel unit of the nth column in the mth row of pixel units is also divided into three stages, namely the second reset stage P1 n+1 , the second data writing and compensation stage P2 n+1 and The third light-emitting stage P3 n+1 .
  • a low-level reset signal RST n is provided to the pixel unit in the m-th row of pixel units in the n-th column, so that the pixel units in the n-th column in the m-th row of pixel units are Perform a reset.
  • the reset signal RST n may refer to the first scan signal provided by the first gate line So m-1 of the m-1 pair of gate lines S m-1
  • the reset signal RST n may refer to the second gate line Se m-1 of the m-1 pair of gate lines S m-1.
  • the reset signal RST n may refer to the second reset signal provided by the m-th reset signal line R m .
  • a low-level scan signal GA n and a high-level data signal DA n are provided to the pixel unit of the nth column in the m-th row of pixel units to Data writing and compensation are performed on the pixel unit of the nth column in the pixel unit of the mth row.
  • the scan signal GA n refers to the first scan signal provided by the first gate line So m in the m-th pair of gate lines S m.
  • the data signal DA n refers to a data signal provided by a data line corresponding to the pixel unit of the nth column.
  • the data signal DA n refers to the data signal provided by the n-th data signal line D n.
  • a low-level emission control signal EM n is provided to the pixel unit of the m-th row of the pixel unit of the n-th column, so that the pixel unit of the n-th column of the m-th row of pixel unit Unit to display.
  • light emission control signal EM n refers to the m-th light emission control line E m emitting signal to provide a control signal.
  • a low-level reset signal RST n+1 is provided to the pixel unit of the m-th row of the pixel unit in the n+1-th column to The pixel unit of the n+1th column is reset.
  • the reset signal RST n+1 refers to the first scan signal provided by the first gate line So m in the m- th pair of gate lines S m , that is, the scan signal GA n .
  • the data signal DA n+1 is used to write and compensate data for the pixel unit of the n+1th column in the pixel unit of the mth row.
  • the scan signal GA n+1 refers to the first scan signal provided by the second gate line Se m in the m- th pair of gate lines S m.
  • the data signal DA n+1 refers to a data signal provided by a data line corresponding to the pixel unit of the n+1th column.
  • the data signal DA n+1 refers to the data signal provided by the n+1 th data signal line D n+1.
  • a low-level emission control signal EM n+1 is provided to the pixel unit in the m-th row of pixel units in the n+1-th column, so that the m-th row of pixel units The pixel unit of the n+1th column in the display.
  • light emission control signal EM n + 1 refers to the m-th light emission control line E m emitting signal to provide a control signal.
  • the scan signal GA n of the pixel unit of the nth column may serve as the reset signal RST n+1 of the pixel unit of the n+1th column.
  • the pixel unit of the n+1th column can be reset, that is, the first data writing and compensation stage P2 n and the The two reset phases P1 n+1 may be synchronized in time.
  • the m-th row in the pixel unit, the n-th column of the pixel emitting unit emission control signal of the EM n and n + 1 columns of pixel units of the EM n + 1 control signal is the same emission control signal, i.e. ,
  • the first light-emitting stage P3 n and the second light-emitting stage P3 n+1 may be synchronized in time.
  • the pixel unit of the nth column is reset first, and data is written and compensated for the pixel unit of the nth column at the same time, and the pixel unit of the n+1th column is Reset, and then perform data writing and compensation on the pixel unit of the n+1th column, and finally display the pixel unit of the nth column and the pixel unit of the n+1th column at the same time.
  • the first reset stage P1 n the first data writing and compensation stage P2 n , the first light emitting stage P3 n , the second reset stage P1 n+1 , and the second data writing and compensation stage P2 n
  • the time sequence of the +1 and the third light-emitting stage P3 n+1 is: P1 n ⁇ P2 n & P1 n+1 ⁇ P2 n+1 ⁇ P3 n & P3 n+1 .
  • the charging process of the pixel unit of the nth column and the pixel unit of the n+1th column (the first data writing and compensation stage P2 n and the second data writing and compensation stage P2 n +1 ) separately and the charging time is the same, and the light-emitting process (the first light-emitting stage P3n and the third light-emitting stage P3n+1) of the pixel unit of the nth column and the pixel unit of the n+1th column are synchronized and the light-emitting duration is the same.
  • the light-emitting brightness of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row is made uniform, and the display quality is improved.
  • the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row receive different data signals (the pixel unit of the nth column receives the data signal D n , the pixel unit of the nth column receives the data signal D n, The pixel unit of column n+1 receives the data signal D n+1 ), but due to the charging process of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row (the first data writing and compensation stage P2 n and the second data writing and compensation stage P2 n+1 ) are carried out separately, so the pixel unit of the nth column and the pixel unit of the n+1th column can be connected to the same data line to receive the same data signal.
  • the signal is in a high level state in both the first data writing and compensation phase P2 n and the second data writing and compensation phase P2 n+1. Since in the first data writing and compensation phase P2 nth column pixel unit is turned on and n+1th column pixel unit is turned off (scan signal GAn is at low level, scanning signal GAn+1 is at high level), and in the first data writing and compensation phase, The second data writing and compensation stage P2 n+1 the pixel unit of the nth column is turned off and the pixel unit of the n+1th column is turned on (the scanning signal GAn is at a high level, and the scanning signal GAn+1 is at a low level), so through the same
  • the data line can provide a high-level data signal to the pixel unit of the nth column in the first data writing and compensation stage P2 n , and to the pixel unit of the n+1th column in the second data writing and compensation stage P2 n+1 Provide high-level data signals.
  • At least one embodiment of the present disclosure further provides a display panel including the array substrate provided by any embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 11, the display panel 1 may include a data driving circuit 20 and an array substrate 10 provided in any embodiment of the present disclosure.
  • the data driving circuit 20 is connected to a plurality of data lines D, and is configured to generate data signals.
  • the data driving circuit 20 may provide data signals to the n-th column in the pixel unit array substrate 10 through the n-th data lines D n.
  • the display panel 1 may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc. These components may, for example, adopt existing conventional components, which will not be described in detail here.
  • the display panel 1 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 1 can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 1 may also have a touch function, that is, the display panel 1 may be a touch display panel.
  • the display panel 1 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the display panel provided by the embodiment of the present disclosure has the same or similar beneficial effects as the array substrate provided by the foregoing embodiment of the present disclosure. Since the array substrate has been described in detail in the foregoing embodiment, it will not be repeated here.
  • At least one embodiment of the present disclosure also provides a driving method applied to the array substrate provided by any embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a driving method of an array substrate provided by an embodiment of the disclosure. As shown in FIG. 12, the driving method may include:
  • Step S10 reset the pixel unit of the nth column in the pixel unit of the mth row;
  • Step S20 Perform data writing and compensation on the pixel unit of the nth column in the pixel unit of the mth row, and reset the pixel unit of the n+1th column in the pixel unit of the mth row at the same time;
  • Step S30 perform data writing and compensation on the pixel unit of the n+1th column in the pixel unit of the mth row;
  • Step S40 Display the pixel units of the nth column and the pixel units of the n+1th column in the pixel units of the mth row.
  • step S20 It may include: supplying the first scan signal to the pixel unit of the nth column in the m-th row of pixel units through the first gate line in the m-th pair of gate lines, and directing the first scan signal to the pixel unit of the nth column through a data line corresponding to the pixel unit of the nth column.
  • the pixel unit of the n-th column in the m-th row of pixel units provides data signals to write and compensate the data of the n-th column of the pixel unit in the m-th row of pixel units.
  • the pixel unit of the n+1th column in the pixel unit of the mth row provides the first scan signal as the first reset signal to reset the pixel unit of the n+1th column of the pixel unit of the mth row.
  • step S10 may include: The first gate line in the m-th row of pixel units provides a first scan signal as a second reset signal to the n-th column of pixel units to reset the n-th column of pixel units in the m-th row of pixel units.
  • step S10 may include: The second gate line in the m-th row of pixel units provides a second scan signal as a second reset signal to the n-th column of pixel units to reset the n-th column of pixel units in the m-th row of pixel units.
  • step S10 may include: A reset signal line provides a second reset signal to the pixel unit of the nth column in the pixel unit of the mth row, so as to reset the pixel unit of the nth column of the pixel unit of the mth row.
  • step S30 may include: directing the n+th row of the pixel unit to the n+th row of the pixel unit through the second gate line in the mth pair of gate lines.
  • One column of pixel units provides the second scan signal and provides data signals to the n+1th column of pixel units in the mth row of pixel units through a data line corresponding to the n+1th column of pixel units, so as to provide data signals to the mth row of pixel units
  • the pixel unit in the n+1th column of the pixel unit performs data writing and compensation.
  • step S40 may include: providing a light-emitting control signal to the pixel unit in the n-th column and the pixel unit in the n+1-th column in the m-th row of pixel units through the m-th light-emitting control signal line, so that the m-th row of pixel units The pixel unit of the nth column and the pixel unit of the n+1th column are displayed.
  • the driving method of the array substrate can first charge the pixel unit of the nth column in the pixel unit of the mth row, and then charge the pixel unit of the n+1th column of the pixel unit of the mth row, and finally Display the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row, thereby charging the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row
  • the method is the same, and the display brightness of the pixel unit of the nth column and the pixel unit of the n+1th column in the pixel unit of the mth row are uniform.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、显示面板以及阵列基板的驱动方法。阵列基板包括：多对栅线(S)，多对栅线(S)中的每对包括第一栅线(So)和第二栅线(Se)；多条数据线(D)；像素阵列，包括排布为多行多列的多个像素单元(110)。第m行像素单元中的第n列像素单元(110)的扫描信号端(GA)连接到第m对栅线(Sm)中的第一栅线(Se m)以接收第一扫描信号，m和n均为正整数；第m行像素单元中的第n+1列像素单元(110)的扫描信号端(GA)连接到第m对栅线(Sm)中的第二栅线(So m)以接收第二扫描信号；第m行像素单元中的第n+1列像素单元(110)的复位信号端(RST)连接到第m对栅线(Sm)中的第一栅线(Se m)以接收第一扫描信号作为第一复位信号；每列像素单元(110)的数据信号端(DA)连接到对应的一条数据线(D)以接收数据信号。

Description

阵列基板、显示面板以及阵列基板的驱动方法 技术领域
本公开的实施例涉及一种阵列基板、显示面板以及阵列基板的驱动方法。
背景技术
随着显示技术的发展，各种显示面板得到了越来越广泛的应用。显示面板主要包括液晶显示(Liquid Crystal Display,LCD)面板和有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板。例如，在OLED显示面板中，包括阵列排布的多个像素单元，同一行的像素单元连接到同一条栅线，同一列的像素单元连接到同一条数据线，每个像素单元在栅线提供的扫描信号和数据线提供的数据信号的驱动下进行显示。
发明内容
本公开至少一实施例提供一种阵列基板，包括：多对栅线，多对栅线中的每对包括第一栅线和第二栅线；多条数据线；像素阵列，包括排布为多行多列的多个像素单元。其中，所述多个像素单元中的每个包括扫描信号端、数据信号端和复位信号端，多行像素单元与所述多对栅线与一一对应，每列像素单元对应于所述多条数据线中的一条数据线；第m行像素单元中的第n列像素单元的扫描信号端连接到第m对栅线中的第一栅线以接收第一扫描信号，m和n均为正整数；所述第m行像素单元中的第n+1列像素单元的扫描信号端连接到所述第m对栅线中的第二栅线以接收第二扫描信号；所述第m行像素单元中的第n+1列像素单元的复位信号端连接到所述第m对栅线中的第一栅线以接收所述第一扫描信号作为第一复位信号；所述每列像素单元的数据信号端连接到对应的一条数据线以接收数据信号。
例如，在本公开的实施例提供的阵列基板中，所述第m行像素单元中的第n列像素单元的复位信号端连接到第m-1对栅线中的第一栅线，以接收所述第m-1对栅线中的第一栅线提供的第一扫描信号作为第二复位信号；或者所述第m行像素单元中的第n列像素单元的复位信号端连接到所述第m-1对栅线中的第二栅线，以接收所述第m-1对栅线中的第二栅线提供的第二扫描信号作为所述第二复位信号，m为大于1的整数。
例如，本公开的实施例提供的阵列基板还包括多条复位信号线，其中，所述多条复位信号线与所述多行像素单元一一对应；所述第m行像素单元中的第n列像素单元的复位信号端连接到第m条复位信号线以接收第二复位信号。
例如，本公开的实施例提供的阵列基板还包括第一扫描驱动电路，其中，所述第一扫描驱动电路连接至所述多条复位信号线，且被配置为产生所述第二复位信号。
例如，本公开的实施例提供的阵列基板还包括多条发光控制信号线，其中，所述多条发光控制信号线与所述多行像素单元一一对应；所述多个像素单元每个还包括发光控制信号端，所述第m行像素单元的发光控制信号端连接到第m条发光控制信号线以接收发光控制信号。
例如，本公开的实施例提供的阵列基板还包括第二扫描驱动电路，其中，所述第二扫描驱动电路连接至所述多条发光控制信号线，且配置为产生所述发光控制信号。
例如，在本公开的实施例提供的阵列基板中，每相邻的两列像素单元对应于同一条数据线，所述第n列像素单元和所述第n+1列像素单元的数据信号端连接到同一条数据线。
例如，本公开的实施例提供的阵列基板还包括第三扫描驱动电路，所述第三扫描驱动电路连接到所述多对栅线，且被配置为产生所述第一扫描信号和所述第二扫描信号。
例如，在本公开的实施例提供的阵列基板中，所述第三扫描驱动电路包括第一扫描驱动子电路和第二扫描驱动子电路，所述第一扫描驱动子电路连接到每对栅线中的第一栅线，且被配置为产生所述第一扫描信号；所述第二扫描驱动子电路连接到每对栅线中的第二栅线，且被配置为产生所述第二扫描信号。
例如，在本公开的实施例提供的阵列基板中，所述第一扫描驱动子电路和所述第二扫描驱动子电路分别设置在所述像素阵列的彼此相对的两侧。
例如，在本公开的实施例提供的阵列基板中，所述每个像素单元包括像素电路，所述像素电路包括：复位电路、数据写入与补偿电路、驱动电路和发光控制电路。所述复位电路包括所述复位信号端，并且连接至复位电压源、所述驱动电路和发光元件，被配置为将复位电压施加至所述驱动电路和所述发光元件以对所述驱动电路和所述发光元件进行复位；所述数据写入与补偿电路包括所述扫描信号端和所述数据信号端，并且连接至所述驱动电路，被配置为将所述数据信号写入所述驱动 电路并对所述驱动电路进行补偿；所述驱动电路被配置为产生驱动所述发光元件发光的驱动电流；所述发光控制电路包括发光控制信号端，并且连接至第一电压源、所述驱动电路和所述发光元件，被配置为将第一电压施加至所述驱动电路，且将所述驱动电路产生的驱动电流施加至所述发光元件。
例如，在本公开的实施例提供的阵列基板中，所述复位电路包括第一复位晶体管和第二复位晶体管；所述数据写入与补偿电路包括数据写入晶体管、补偿晶体管和存储电容；所述驱动电路包括驱动晶体管；所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管；所述第一复位晶体管的栅极连接至所述复位信号端，所述第一复位晶体管的第一极连接至所述复位电压源，所述第一复位晶体管的第二极连接至所述驱动晶体管的栅极；所述第二复位晶体管的栅极连接至所述复位信号端，所述第二复位晶体管的第一极连接至所述复位电压源，所述第二复位晶体管的第二极连接至所述发光元件的第一端；所述数据写入晶体管的栅极连接至所述扫描信号端，所述数据写入晶体管的第一极连接至所述数据信号端，所述数据写入晶体管的第二极连接至所述驱动晶体管的第一极；所述补偿晶体管的栅极连接至所述扫描信号端，所述补偿晶体管的第一极连接至所述驱动晶体管的第二极，所述补偿晶体管的第二极连接至所述驱动晶体管的栅极；所述存储电容的第一端连接至所述第一电压源，所述存储电容的第二端连接至所述驱动晶体管的栅极；所述第一发光控制晶体管的栅极连接至所述发光控制信号端，所述第一发光控制晶体管的第一极连接至所述第一电压源，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极；所述第二发光控制晶体管的栅极连接至所述发光控制信号端，所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端。
本公开至少一实施例还提供一种显示面板，包括前述任一实施例中的阵列基板。
本公开至少一实施例还提供一种应用于前述任一实施例中的阵列基板的驱动方法，包括：对所述第m行像素单元中的第n列像素单元进行复位；对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时对所述第m行像素单元中的第n+1列像素单元进行复位；对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿；使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
例如，在本公开的实施例提供的驱动方法中，对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时对所述第m行像素单元中的第n+1列像素单元进行复位，包括：通过所述第m对栅线中的第一栅线向所述第m行像素单元中的第n列像素单元提供所述第一扫描信号，并通过与所述第n列像素单元相对应的一条数据线向所述第m行像素单元中的第n列像素单元提供所述数据信号，以对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时通过所述第m对栅线中的第一栅线向第m行像素单元中的第n+1列像素单元提供所述第一扫描信号作为所述第一复位信号，以对所述第m行像素单元中的第n+1列像素单元进行复位。
例如，在本公开的实施例提供的驱动方法中，对所述第m行像素单元中的第n列像素单元进行复位，包括：通过第m-1对栅线中的第一栅线向所述第m行像素单元中的第n列像素单元提供所述第一扫描信号作为第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位；或者，通过所述第m-1对栅线中的第二栅线向所述第m行像素单元中的第n列像素单元提供所述第二扫描信号作为所述第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位。
例如，在本公开的实施例提供的驱动方法中，对所述第m行像素单元中的第n列像素单元进行复位，包括：通过第m条复位信号线向所述第m行像素单元中的第n列像素单元提供第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位。
例如，在本公开的实施例提供的驱动方法中，对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿，包括：通过所述第m对栅线中的第二栅线向所述第m行像素单元中的第n+1列像素单元提供所述第二扫描信号并通过与所述第n+1列像素单元对应的一条数据线向第m行像素单元中的第n+1列像素单元提供所述数据信号，以对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿。
例如，在本公开的实施例提供的驱动方法中，使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示，包括：通过第m条发光控制信号线向所述第m行像素单元中的第n列像素单元和第n+1列像素单元提供发光控制信号，以使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附 图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的结构示意图；
图2A为本公开的实施例提供的一种阵列基板的结构示意图；
图2B为本公开的实施例提供的另一种阵列基板的结构示意图；
图3A是本公开的实施例提供的又一种阵列基板的结构示意图；
图3B是本公开的实施例提供的又一种阵列基板的结构示意图；
图4A为本公开的实施例提供的又一种阵列基板的结构示意图；
图4B为本公开的实施例提供的又一种阵列基板的结构示意图；
图5为本公开的实施例提供的阵列基板中的像素单元的结构示意图；
图6为图5中的像素电路中的各个电路的结构示意图；
图7为驱动图6中的像素电路的信号的时序图；
图8A为图6所示的像素电路在复位阶段的等效电路图；
图8B为图6所示的像素电路在数据写入与补偿阶段的等效电路图；
图8C为图6所示的像素电路在发光阶段的等效电路图；
图9A是本公开的实施例提供的阵列基板在包括图6中的像素电路时的一种结构示意图；
图9B是本公开的实施例提供的阵列基板在包括图6中的像素电路时的另一种结构示意图；
图10是驱动本公开的实施例提供的阵列基板的信号的时序图；
图11为本公开一实施例提供的显示面板的结构示意图；以及
图12为本公开的实施例提供的阵列基板的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似 的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种阵列基板的结构示意图。如图1所示，该阵列基板包括衬底基板以及设置在衬底基板上的多条栅线S、多条数据线D和像素阵列。像素阵列包括排布为多行多列的多个像素单元P，第M行像素单元连接到第M条栅线S M以接收扫描信号，第N列像素单元连接到第N条数据线D N以接收数据信号。像素阵列的每个像素单元可以在接收到的扫描信号的控制下基于接收到的数据信号进行工作，以发出需要的灰度的光，由此实现图像显示。
在图1所示的阵列基板中，由于同一行像素单元中的多列像素单元连接到同一条栅线，因此同一行像素单元中的多列像素单元会在由同一条栅线提供的扫描信号的驱动下同时打开，同一行像素单元中的多列像素单元的打开时间一致；此外，由于同一行像素单元中的多列像素单元连接到多条不同的数据线，因此同一行像素单元中的多列像素单元会先后写入由多条不同的数据线提供的数据信号。在这种情况下，就会导致同一行像素单元中的多列像素单元具有不同的充电方式，诸如先充电后放电和边充电边放电，这进而会导致同一行像素单元中的多列像素单元的显示亮度不均匀，影响显示质量。
本公开至少一实施例提供一种阵列基板，该阵列基板包括：多对栅线，多对栅线中的每对包括第一栅线和第二栅线；多条数据线；以及，像素阵列，包括排布为多行多列的多个像素单元。多个像素单元中的每个包括扫描信号端、数据信号端和复位信号端，多行像素单元与多对栅线与一一对应，每列像素单元对应于多条数据线中的一条数据线；第m行像素单元中的第n列像素单元的扫描信号端连接到第m对栅线中的第一栅线以接收第一扫描信号，m和n均为正整数；第m行像素单元中的第n+1列像素单元的扫描信号端连接到第m对栅线中的第二栅线以接收第二扫描信号；第m行像素单元中的第n+1列像素单元的复位信号端连接到所述第m对栅线中的第一栅线以接收第一扫描信号作为第一复位信号；每列像素单元的数据信号端连接到对应的一条数据线以接收数据信号。
在本公开的实施例提供的阵列基板中，第m行像素单元中的第n 列像素单元的扫描信号端可以连接到第m对栅线中的第一栅线以接收第一扫描信号，第m行像素单元中的第n+1列像素单元的扫描信号端可以连接到第m对栅线中的第二栅线以接收第二扫描信号，从而第m行像素单元中的第n列像素单元会在第m对栅线中的第一栅线提供的第一扫描信号的驱动下先打开，第n+1列像素单元会在第m对栅线中的第二栅线提供的第二扫描信号的驱动下后打开，并且可使得第m行像素单元中的第n列像素单元和第n+1列像素单元的打开时间长短一致。在这种情况下，第m行像素单元中的第n列像素单元和第n+1列像素单元的充电方式相同，避免同一行像素单元中的多列像素单元的显示亮度不均匀的问题，进而可以改善显示质量。
此外，在本公开的至少一实施例提供的阵列基板中，第m行像素单元中的第n列像素单元的扫描信号端可以连接到第m对栅线中的第一栅线，并且第m行像素单元中的第n+1列像素单元的复位信号端也可以连接到第m对栅线中的第一栅线，从而可以将第m对栅线中的第一栅线提供给第m行像素单元中的第n列像素单元的第一扫描信号作为第一复位信号施加到第m行像素单元中的第n+1列像素单元，以对第m行像素单元中的第n+1列像素单元进行复位。在这种情况下，还可以减少集成在阵列基板上的栅极驱动器(gate driver on array，GOA)的数量，有利于采用该阵列基板的显示装置实现窄边框设计。
下面结合附图对本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体实施例中的不同特征可以相互组合，从而得到新的实施例，这些新的实施例也都属于本公开保护的范围。
图2A为本公开的实施例提供的一种阵列基板的结构示意图。图2B为本公开的实施例提供的另一种阵列基板的结构示意图。
如图2A和图2B所示，阵列基板10包括衬底基板以及设置在衬底基板上的多对栅线S、多条数据线D和像素阵列。该衬底基板可以为玻璃基板、塑料基板等，本公开的实施例对此不作限制。多对栅线S可以沿第一方向设置在衬底基板上，多对栅线S中的每对包括第一栅线So和第二栅线Se；多条数据线D可以沿第二方向设置在衬底基板上；像素阵列包括排布为多行多列的多个像素单元110，例如，多个像素单元110位于由多对栅线S和多条数据线D交叉限定出的像素区域中，每个像素单元110包括扫描信号端GA、数据信号端DA和复位信号端RST，以分别接收用于该像素单元110的扫描信号(例如，第一扫描信号或第二扫描信号)、数据信号和复位信号(例如，第一复位信号或第二复位 信号)。
例如，第一方向可以与第二方向垂直，第一方向可以是像素阵列的行方向(例如，图2A和图2B中的X方向)，第二方向可以是像素阵列的列方向(例如，图2A和图2B中的Y方向)。
如图2和图2B所示，多行像素单元可以与多对栅线S一一对应，每行像素单元可以连接到与其对应的一对栅线S，例如，第m行像素单元可以对应于第m对栅线S m，第m行像素单元中的第n列像素单元可以对应于第m对栅线S m中的第一栅线Se m，第m行像素单元中的第n+1列像素单元可以对应于第m对栅线中S m的第二栅线So m，第m行像素单元中的第n列像素单元的扫描信号端GA可以连接到第m对栅线S m中的第一栅线Se m以接收第一扫描信号，第m行像素单元中的第n+1列像素单元的扫描信号端GA可以连接到第m对栅线S m中的第二栅线So m以接收第二扫描信号，m和n均为正整数。
需要说明的是，尽管在图2A和图2B中示出第m对栅线S m中的第一栅线Se m和第二栅线So m设置在第m行像素单元的同一侧，但是本公开的实施例显然不限于此。例如，第m对栅线S m中的第一栅线Se m和第二栅线So m可以设置在第m行像素单元的彼此相对的两侧，例如，第m对栅线S m中的第一栅线Se m可以设置在第m行像素单元的上侧，第m对栅线S m中的第一栅线Se m可以设置在第m行像素单元的下侧。
如图2A和图2B所示，多列像素单元可以与多条数据线D一一对应，每列像素单元可以连接到与其对应的一条数据线D，例如，第n列像素单元可以对应于第n条数据线D n，第n列像素单元的数据信号端DA可以连接到第n条数据线D n以接收数据信号。
需要说明的是，尽管在图2A和图2B中示出多列像素单元与多条数据线D一一对应，但是本公开的实施例显然不限于此。例如，每列像素单元对应于多条数据线D中的一条数据线D，且每相邻的两列像素单元对应于同一条数据线D，例如，第n列像素单元和第n+1列像素单元可以对应于同一条数据线，第n+2列像素单元(未示出)和第n+3列像素单元(未示出)可以对应于同一条数据线，……，以此类推。第n列像素单元的数据信号端DA和第n+1列像素单元的数据信号端DA可以连接到同一条数据线以接收数据信号，第n+2列像素单元的数据信号端DA和第n+3列像素单元的数据信号端DA可以连接到同一条数据线以接收数据信号，…….，以此类推。
需要说明的是，尽管在图2A和图2B中示出第n条数据线D n设置在第n列像素单元的左侧，两条数据线D之间设置有一列像素单元， 但是本公开的实施例显然不限于此。例如，第n条数据线D n可以设置在第n列像素单元的右侧。此外，在相邻的两列像素单元对应于同一条数据线D的情况下，一条数据线D可以设置在与其对应的相邻的两列像素单元之间，也就是说，两条数据线D之间可以设置有两列像素单元。
如图2A和图2B所示，第m行像素单元中的第n+1列像素单元的复位信号端RST可以连接到第m对栅线S m中的第一栅线So m以接收第一扫描信号。在这种情况下，第m对栅线S m中的第一栅线So m提供给第m行像素单元中的第n列像素单元的第一扫描信号可以作为第一复位信号施加到第m行像素单元中的第n+1列像素单元，以对第m行像素单元中的第n+1列像素单元进行复位。
在本公开的一些实施例提供的阵列基板中，第m行像素单元中的第n列像素单元的复位信号端连接到第m-1对栅线中的第一栅线，以接收第m-1对栅线中的第一栅线提供的第一扫描信号作为第二复位信号，以对第m行像素单元中的第n列像素单元进行复位，此时，m为大于1的整数。
如图2A所示，第m行像素单元中的第n列像素单元的复位信号端RST可以连接到第m-1对栅线S m-1中的第一栅线So m-1。在这种情况下，第m-1对栅线S m-1中的第一栅线So m-1提供给第m-1行像素单元中的第n列像素单元的第一扫描信号可以作为第二复位信号施加到第m行像素单元中的第n列像素单元，以对第m行像素单元中的第n列像素单元进行复位。
此外，如图2A所示，在第m行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第一栅线So m-1的情况下，第m-1行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第二栅线Se m-1。在这种情况下，第m-1对栅线S m-1中的第二栅线Se m-1提供给第m-1行像素单元中的第n+1列像素单元的第二扫描信号可以作为第二复位信号施加到第m-1行像素单元中的第n列像素单元，以对第m-1行像素单元中的第n列像素单元进行复位。
参考图2A可知，在第m行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第一栅线So m-1的情况下，第m-1行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第二栅线Se m-1，第m行像素单元中的第n+1列像素单元的复位信号端RST连接到第m对栅线S m中的第一栅线So m。在这种情况下，第m-1行像素单元中的第n列像素单元和第n+1列像素单元 的复位方式与第m行像素单元中的第n列像素单元和第n+1列像素单元的复位方式是不同的。具体地，就第m-1行像素单元和第m行像素单元各自的工作周期而言，在第m-1行像素单元中，第n列像素单元利用是利用提供给第n+1列像素单元的第二扫描信号作为第二复位信号进行复位；在第m行像素单元中，第n+1列像素单元是利用提供给第n列像素单元的第一扫描信号作为第一复位信号进行复位。
在本公开的另一些实施例提供的阵列基板中，第m行像素单元中的第n列像素单元的复位信号端连接到第m-1对栅线中的第二栅线，以接收第m-1对栅线中的第二栅线提供的第二扫描信号作为第二复位信号，以对第m行像素单元中的第n列像素单元进行复位，此时m为大于1的整数。
如图2B所示，第m行像素单元中的第n列像素单元的复位信号端RST可以连接到第m-1对栅线S m-1中的第二栅线Se m-1。在这种情况下，第m-1对栅线S m-1中的第二栅线Se m-1提供给第m-1行像素单元中的第n+1列像素单元的第二扫描信号可以作为第二复位信号施加到第m行像素单元中的第n列像素单元，以对第m行像素单元中的第n列像素单元进行复位。
此外，如图2B所示，在第m行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第二栅线Se m-1的情况下，第m-1行像素单元中的第n+1列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第一栅线So m-1。在这种情况下，第m-1对栅线S m-1中的第一栅线So m-1提供给第m-1行像素单元中的第n列像素单元的第一扫描信号可以作为第一复位信号施加到第m-1行像素单元中的第n+1列像素单元，以对第m-1行像素单元中的第n+1列像素单元进行复位。
参考图2B可知，在第m行像素单元中的第n列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第二栅线Se m-1的情况下，第m-1行像素单元中的第n+1列像素单元的复位信号端RST连接到第m-1对栅线S m-1中的第一栅线So m-1，第m行像素单元中的第n+1列像素单元的复位信号端RST连接到第m对栅线S m中的第一栅线So m。在这种情况下，第m-1行像素单元中的第n列像素单元和第n+1列像素单元的复位方式与第m行像素单元中的第n列像素单元和第n+1列像素单元的复位方式是相同的。具体地，就第m-1行像素单元和第m行像素单元各自的工作周期而言，在第m-1行像素单元和第m行像素单元中，第n+1列像素单元都是利用提供给第n列像素单元的第一扫描信号作为第一复位信号进行复位。
需要说明的是，在本公开中，第一复位信号和第二复位信号是针对同一行像素单元中的不同列(例如，第n列和第n+1列)中的像素单元而言的，仅仅用于在描述中进行区分，而非表示时间上的先后等限制。例如，第一复位信号可以指对第n+1列像素单元进行复位的信号，第二复位信号可以指对第n列像素单元进行复位的信号。例如，在这种情况下，如图2A所示，在第m行像素单元中，第n列像素单元从第m-1对栅线S m-1中的第一栅线So m-1接收第一扫描信号作为第二复位信号，第n+1列像素单元从第m对栅线S m中的第一栅线So m接收第一扫描信号作为第一复位信号；在第m-1行像素单元中，第n列像素单元从第m-1对栅线S m-1中的第二栅线Se m-1接收第二扫描信号作为第二复位信号。如图2B所示，在第m行像素单元中，第n列像素单元从第m-1对栅线S m-1中的第二栅线Se m-1接收第二扫描信号作为第二复位信号，第n+1列像素单元从第m对栅线S m中的第一栅线So m接收第一扫描信号作为第一复位信号；在第m-1行像素单元中，第n+1列像素单元从第m-1对栅线S m-1中的第一栅线So m-1接收第一扫描信号作为第一复位信号。在本公开的至少一实施例提供的阵列基板中，多个像素单元中的每个像素单元还包括发光控制信号端，以接收用于该像素单元的发光控制信号。相应地，该实施例提供的阵列基板还可以包括设置在衬底基板上的多条发光控制信号线，多条发光控制信号线与多行像素单元一一对应，第m行像素单元的发光控制信号端连接到第m条发光控制信号线以接收发光控制信号。
如图2A和图2B所示，每个像素单元110还包括发光控制信号端EM。阵列基板10还包括设置在衬底基板上的多条发光控制信号线E，例如，多条发光控制信号线E可以沿第一方向设置在衬底基板上。多条发光控制信号线E可以与多行像素单元一一对应，每行像素单元可以连接到与其对应的一条发光控制信号线E。例如，第m行像素单元对应于第m条发光控制信号线E m，第m行像素单元的发光控制信号端EM可以连接到第m条发光控制信号线E m以接收发光控制信号。
需要说明的是，尽管在图2A和图2B中示出第m条发光控制信号线E m设置在第m行像素单元的下侧，但是本公开的实施例显然不限于此。例如，第m条发光控制信号线E m可以设置在第m行像素单元的上侧。
本公开的一些实施例中，阵列基板还可以包括设置在衬底基板上的多条复位信号线，多条复位信号线与多行像素单元一一对应，第m行像素单元中的第n列像素单元的复位信号端连接到第m条复位信号线 以接收第二复位信号，以对第m行像素单元中的第n列像素单元进行复位。
图3A是本公开的实施例提供的又一种阵列基板的结构示意图。图3B是本公开的实施例提供的又一种阵列基板的结构示意图。
如图3A和图3B所示，阵列基板10还包括设置在衬底基板上的多条复位信号线R，例如，多条复位信号线R可以沿第一方向设置在衬底基板上。在图3A和图3B所示的阵列基板10中，第m行像素单元中的第n+1列像素单元的复位信号端RST可以连接到第m对栅线S m中的第一栅线So m以接收第一扫描信号作为第一复位信号，以对第m行像素单元中的第n+1列像素单元进行复位。
如图3A和图3B所示，多条复位信号线R可以与多行像素单元一一对应，每行像素单元可以连接到与其对应的一条复位信号线R。例如，第m行像素单元可以对应于第m条复位信号线R m，第m行像素单元中的第n列像素单元的复位信号端RST可以连接到第m条复位信号线R m以接收第二复位信号，以对第m行像素单元中的第n列像素单元进行复位。
需要说明的是，尽管在图3A和图3B中示出第m条复位信号线R m与第m对栅线S m中的第一栅线Se m和第二栅线So m设置在第m行像素单元的同一侧，但是本公开的实施例显然不限于此。例如，第m条复位信号线R m与第m对栅线S m中的第一栅线Se m和第二栅线So m可以设置在第m行像素单元的彼此相对的两侧，例如，第m条复位信号线R m可以设置在第m行像素单元的上侧，第m对栅线S m中的第一栅线Se m和第二栅线So m可以设置在第m行像素单元的下侧。
如图3A所示，第m-1行像素单元中的第n列像素单元的复位信号端RST可以连接到第m-1条复位信号线R m-1以接收第二复位信号，以对第m-1行像素单元中的第n列像素单元进行复位，m为大于1的整数。在这种情况下，第m-1行像素单元中的第n+1列像素单元的复位信号端RST可以连接到第m-1对栅线S m-1中的第一栅线So m-1以接收第一扫描信号作为第一复位信号，以对第m-1行像素单元中的第n+1列像素单元进行复位。
参考图3A可知，第m-1行像素单元中的第n列像素单元和第n+1列像素单元的复位方式与第m行像素单元中的第n列像素单元和第n+1列像素单元的复位方式可以是相同的。具体地，就第m-1行像素单元和第m行像素单元各自的工作周期而言，在m-1行像素单元和第m行像素单元中，第n列像素单元是利用单独提供的第二复位信号进行复位， 第n+1列像素单元是利用提供给第n列像素单元的第一扫描信号作为第二复位信号进行复位。
如图3B所示，第m-1行像素单元中的第n+1列像素单元的复位信号端RST可以连接到第m-1条复位信号线R m-1以接收第一复位信号，以对第m-1行像素单元中的第n+1列像素单元进行复位。在这种情况下，第m-1行像素单元中的第n列像素单元的复位信号端RST可以连接到第m-1对栅线S m-1中的第二栅线Se m-1以接收第二扫描信号作为第二复位信号，以对第m-1行像素单元中的第n列像素单元进行复位。
参考图3B可知，第m-1行像素单元中的第n列像素单元和第n+1列像素单元的复位方式与第m行像素单元中的第n列像素单元和第n+1列像素单元的复位方式可以是不同的。具体地，就第m-1行像素单元和第m行像素单元各自的工作周期而言，在m-1行像素单元中，第n列像素单元是利用提供给第n+1列像素单元的第二扫描信号作为第二复位信号进行复位，第n+1列像素单元是利用单独提供的第一复位信号进行复位；在第m行像素单元中，第n列像素单元是利用单独提供的第二复位信号进行复位，第n+1列像素单元是利用提供给第n列像素单元的第一扫描信号作为第一复位信号进行复位。
需要说明的是，在本公开的实施例中，为了进行区分，将对第n+1列像素单元进行复位的信号称做第一复位信号，并将对第n列像素单元进行复位的信号称做第二复位信号。例如，在这种情况下，如图3A和3B所示，在第m行像素单元中，第n列像素单元从第m条复位信号线R m接收第二复位信号，第n+1列像素单元从第m对栅线S m中的第一栅线So m接收第一扫描信号作为第一复位信号；如图3A所示，在第m-1行像素单元中，第n列像素单元从第m-1条复位信号线R m-1接收第二复位信号，第n+1列像素单元从第m-1对栅线S m-1中的第一栅线So m-1接收第一扫描信号作为第一复位信号；如图3B所示，在第m-1行像素单元中，第n列像素单元从第m-1对栅线S m-1中的第二栅线Se m-1接收第二扫描信号作为第二复位信号，第n+1列像素单元从第m-1条复位信号线R m-1接收第一复位信号。
为了简便起见，这里仅对图3A和图3B中的多条复位信号线R进行了详细描述，关于图3A和图3B中的多对栅线S、多条数据线D、多条发光控制信号线E和多个像素单元110的描述，可以参考上面对图2A和图2B中的多对栅线S、多条数据线D、多条发光控制信号线E和多个像素单元100的相关描述，这里不再赘述。
需要说明的是，尽管在图2A、图2B、图3A和图3B中，以从上 到下的顺序对多对栅线S、多条复位信号线R、多条发光控制信号线E进行了编号，并以从左到右的顺序对多条数据线D进行了编号，但是这仅仅是为了方便描述，而非限定各条信号线的绝对位置关系，本公开的实施例显然也不限于此。例如，可以以从下到上的顺序对多对栅线S、多条复位信号线R、多条发光控制信号线E进行编号，和/或以从右到左的顺序对多条数据线D进行编号。
本公开的至少一实施例提供的阵列基板还可以包括设置在衬底基板上的第一扫描驱动电路，第一扫描驱动电路连接至多条复位信号线，且被配置为产生第二复位信号。
本公开的至少一实施例提供的阵列基板还可以包括设置在衬底基板上的第二扫描驱动电路，第二扫描驱动电路连接至多条发光控制信号线，且配置为产生发光控制信号。
本公开的至少一实施例提供的阵列基板还可以包括设置在衬底基板上的第三扫描驱动电路，第三扫描驱动电路连接到多对栅线，且被配置为产生第一扫描信号和第二扫描信号。
图4A为本公开的实施例提供的又一种阵列基板的结构示意图。
如图4A所示，阵列基板10还包括设置在衬底基板上的第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230。
如图4A所示，第一扫描驱动电路210可以连接到多条复位信号线R，且被配置为产生第二复位信号。例如，第一扫描驱动电路210可以通过第m条复位信号线R m向第m行像素单元中的第n列像素单元提供第二复位信号。
如图4A所示，第二扫描驱动电路220可以连接到多条发光控制信号线E，且被配置为产生发光控制信号。例如，第二扫描驱动电路220可以通过第m条发光控制信号线E m向第m行像素单元中的第n列像素单元和第n+1列像素单元提供发光控制信号。
如图4A所示，第三扫描驱动电路230可以连接到多对栅线S，且配置为产生第一扫描信号和第二扫描信号。例如，第三扫描驱动电路230可以通过第m对栅线S m中的第一栅线So m向第m行像素单元中的第n列像素单元提供第一扫描信号，并且可以通过第m对栅线S m中的第二栅线Se m向第m行像素单元中的第n+1列像素单元提供第二扫描信号。
需要说明的是，尽管图4A示出第二复位信号、发光控制信号以及第一扫描信号和第二扫描信号分别由第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230提供，但是本公开的实施例显然 不限于此。例如，第二复位信号、发光控制信号以及第一扫描信号和第二扫描信号可以由同一个更大的扫描驱动电路提供。
需要说明的是，尽管图4A中示出第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230均设置在像素阵列的左侧，但是本公开的实施例显然不限于此。例如，第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230可以均设置在像素阵列的右侧、上侧或下侧，或者第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230可以分别设置在像素阵列的不同侧。
例如，图4A中示出的第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230可以是栅极驱动集成电路(芯片)，从而可以通过绑定方式设置在衬底基板上，或者可以通过半导体工艺直接制备在衬底基板上，即采用GOA形式。此外，尽管图4A示出第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230是单独提供的，但是第一扫描驱动电路210、第二扫描驱动电路220和第三扫描驱动电路230可以以组合的方式提供，例如，由同一个栅极驱动集成电路提供，或者制备在衬底基板上的同一个区域中。在本公开的另一实施例提供的阵列基板中，第三扫描驱动电路包括第一扫描驱动子电路和第二扫描驱动子电路。第一扫描驱动子电路连接到每对栅线中的第一栅线，且被配置为产生第一扫描信号；第二扫描驱动子电路连接到每对栅线中的第二栅线，且被配置为产生第二扫描信号。
图4B为本公开的实施例提供的又一种阵列基板的结构示意图。
如图4B所示，第三扫描驱动电路230包括第一扫描驱动子电路231和第二扫描驱动子电路232。
如图4B所示，第一扫描驱动子电路231可以连接到每对栅线S中的第一栅线So，并被配置为产生第一扫描信号。例如，第一扫描驱动子电路231可以通过第m对栅线S m中的第一栅线So m向第m行像素单元中的第n列像素单元提供第一扫描信号。
如图4B所示，第二扫描驱动子电路232可以连接到每对栅线S中的第二栅线Se，并被配置为产生第二扫描信号。例如，第二扫描驱动子电路232可以通过第m对栅线S m中的第二栅线Se m向第m行像素单元中的第n+1列像素单元提供第二扫描信号。
为了简便起见，这里仅对图4B中的第一扫描驱动子电路231和第二扫描驱动子电路232进行了详细描述，关于4B中的第一扫描驱动电路210、第二扫描驱动电路220的描述，可以参考上面对图4A中的第一扫描驱动电路210、第二扫描驱动电路220的相关描述，这里不再赘 述。
需要说明的是，尽管图4B中示出第一扫描驱动子电路231和第二扫描驱动子电路232分别设置在像素阵列的彼此相对的两侧(左侧和右侧)，但是本公开的实施例显然不限于此。例如，第一扫描驱动子电路231和第二扫描驱动子电路232可以设置在像素阵列的同一侧，例如，第一扫描驱动子电路231和第二扫描驱动子电路232可以均设置在像素阵列的左侧、右侧、上侧或下侧。
需要说明的是，尽管图4A和图4B中的阵列基板10中的各条连接线(例如，多对栅线S、多条数据线D、多条复位信号线R和多条发光控制线E)与像素阵列的连接方式与图3A中的阵列基板10中的连接方式相同，但是图4A和图4B中的阵列基板10中的各条连接线与像素阵列的连接方式也可以采用图3B中的阵列基板10中的连接方式。此外，图4A和图4B中的阵列基板10中的各条连接线与像素阵列的连接方式也可以采用图2A或图2B中的阵列基板10中的连接方式，在这种情况下，图4A和图4B中的阵列基板10可以不包括多条复位信号线R，相应地也不包括第一扫描驱动电路210。
在上述图2A-图4B所示的实施例中，多列像素单元与多条数据线一一对应，但是本公开的实施例显然不限于此。例如，在图2A-图4B所示的实施例的变形中还可以至少两列像素单元对应于一条数据线，例如，相邻的两列像素单元对应于同一条数据线，相邻两列像素单元的数据信号端可以连接到同一条数据线以接收同一个数据信号(参见后面图9B所示的实施例)，由此实现数据线的共享，减少数据线的数量以及数据驱动电路的数量，从而降低制造成本。
在本公开的实施例提供的阵列基板中，每个像素单元包括像素电路和发光元件，像素电路包括复位电路、数据写入与补偿电路、驱动电路和发光控制电路。复位电路包括复位信号端，并且连接至复位电压源、驱动电路和发光元件，被配置为将复位电压施加至驱动电路和发光元件以对驱动电路和发光元件进行复位；数据写入与补偿电路包括扫描信号端和数据信号端，并且连接至驱动电路，被配置为将数据信号写入驱动电路并对驱动电路进行补偿；驱动电路被配置为产生驱动发光元件发光的驱动电流；发光控制电路包括发光控制信号端，并且连接至第一电压源、驱动电路和发光元件，被配置为将第一电压施加至驱动电路，且将驱动电路产生的驱动电流施加至发光元件。
图5为本公开的实施例提供的阵列基板中的像素单元的结构示意图。如图5所示，像素单元100包括像素电路110和发光元件120。像 素电路110包括复位电路111、数据写入与补偿电路112、驱动电路113和发光控制电路114。
如图5所示，复位电路111包括复位信号端RST，连接到复位电压源VINT、驱动电路113和发光元件120，并且被配置为在复位信号的控制下将从复位电压源VINT接收到的复位电压施加到驱动电路113和发光元件120，以对驱动电路113和发光元件120进行复位。例如，这里的复位信号可以是前面的实施例中所述的第一复位信号或第二复位信号，后续的实施例中提到的复位信号具有与此类似的含义，因此将不再赘述。
如图5所示，数据写入与补偿电路112包括扫描信号端GA和数据信号端DA，连接到驱动电路113，并且被配置为在扫描信号的控制下将数据信号写入到驱动电路113中，并对驱动电路113进行补偿。例如，这里的扫描信号可以是前面的实施例中所述的第一扫描信号或第二扫描信号，后续的实施例中提到的扫描信号具有与此类似的含义，因此将不再赘述。
如图5所示，驱动电路130连接至复位电路111、数据写入与补偿电路112和发光控制电路114，并且被配置为产生驱动发光元件120发光的驱动电流。
如图5所示，发光控制电路114包括发光控制信号端EM，连接到第一电压源VDD、驱动电路113和发光元件120，并且被配置为在发光控制信号的控制下将从第一电压源VDD接收到的第一电压施加至驱动电路113，并将驱动电路120产生的驱动电流施加至发光元件120。
如图5所示，发光元件120连接至第二电压源VSS、复位电路111和发光控制电路114，并且被配置为在驱动电路113产生的驱动电流的驱动下发光。
例如，发光元件120可以为发光二极管等。发光二极管可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等。
在本公开的至少一实施例提供的阵列基板中，复位电路包括第一复位晶体管和第二复位晶体管，数据写入与补偿电路包括数据写入晶体管、补偿晶体管和存储电容，驱动电路包括驱动晶体管，发光控制电路包括第一发光控制晶体管和第二发光控制晶体管。数据写入晶体管的栅极连接至扫描信号端，数据写入晶体管的第一极连接至数据信号端，数据写入晶体管的第二极连接至所述驱动晶体管的第一极；补偿晶体管的栅极连接至扫描信号端，补偿晶体管的第一极连接至驱动晶体管的第二极，补偿晶体管的第二极连接至驱动晶体管的栅极；存储电容的第一端 连接至第一电压源，存储电容的第二端连接至驱动晶体管的栅极；第一复位晶体管的栅极连接至复位信号端，第一复位晶体管的第一极连接至复位电压源，第一复位晶体管的第二极连接至驱动晶体管的栅极；第二复位晶体管的栅极连接至复位信号端，第二复位晶体管的第一极连接至复位电压源，第二复位晶体管的第二极连接至发光元件的第一端；第一发光控制晶体管的栅极连接至发光控制信号端，第一发光控制晶体管的第一极连接至第一电压源，第一发光控制晶体管的第二极连接至驱动晶体管的第一极；第二发光控制晶体管的栅极连接至发光控制信号端，第二发光控制晶体管的第一极连接至驱动晶体管的第二极，第二发光控制晶体管的第二极连接至发光元件的第一端。
图6为图5中的像素电路中的各个电路的结构示意图。如图6所示，复位电路111包括第一复位晶体管T1和第二复位晶体管T2；数据写入与补偿电路112包括数据写入晶体管T3、补偿晶体管T4和存储电容Cst；驱动电路113包括驱动晶体管Td；发光控制电路114包括第一发光控制晶体管T5和第二发光控制晶体管T6。
如图6所示，第一复位晶体管T1的栅极连接至复位信号端RST以接收复位信号，第一复位晶体管T1的第一极连接至第一电压源VINT以接收第一电压，第一复位晶体管T1的第二极连接至驱动晶体管Td的栅极。
如图6所示，第二复位晶体管T2的栅极连接至复位信号端RST以接收复位信号，第二复位晶体管T2的第一极连接至第一电压源VINT以接收第一电压，第二复位晶体管T2的第二极连接至发光元件120的第一端。
如图6所示，数据写入晶体管T3的栅极连接至扫描信号端GA以接收扫描信号，数据写入晶体管T3的第一极连接至数据信号端以接收数据信号，数据写入晶体管T3的第二极连接至驱动晶体管Td的第一极。
如图6所示，补偿晶体管T4的栅极连接至扫描信号端GA以接收扫描信号，补偿晶体管T4的第一极连接至驱动晶体管Td的第二极，补偿晶体管T4的第二极连接至驱动晶体管Td的栅极。
如图6所示，存储电容Cst的第一端连接到第一电压源，存储电容Cst的第二端连接到驱动晶体管Td的栅极。
如图6所示，第一发光控制晶体管T5的栅极连接至发光控制信号端EM以接收发光控制信号，第一发光控制晶体管T5的第一极连接至第一电压源VDD以接收第一电压，第一发光控制晶体管T5的第二极 连接至驱动晶体管T5的第一极。
如图6所示，第二发光控制晶体管T6的栅极连接至发光控制信号端EM以接收发光控制信号，第二发光控制晶体管T6的第一极连接至驱动晶体管Td的第二极，第二发光晶体管T6的第二极连接至发光元件120的第一端。
如图6所示，发光元件120的第二端连接至第二电压源Vss以接收第二电压。例如，如图6所示，发光元件120是有机发光二极管(OLED)，OLED的阳极为发光元件120的第一端，OLED的阴极为发光元件120的第二端。
需要说明的是，本公开实施例均是以复位电压源VINT输入低电压，第一电压源VDD输入高电压，第二电压源VSS输入低电压，或将发光元件120的第二端接地为例进行的说明，并且这里的高、低仅表示输入的电压之间的相对大小关系。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，需要说明的是，本公开的实施例中采用的晶体管均可以为P型晶体管或N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，对于N型晶体管，其输入端为漏极而输出端为源极，其控制端为栅极；对于P型晶体管，其输入端为源极而输出端为漏极，其控制端为栅极。对于不同类型的晶体管，其控制端的控制信号的电平也不相同。例如，对于N型晶体管，在控制信号为高电平时，该N型晶体管处于导通状态；而在控制信号为低电平时，N型晶体管处于截止状态。对于P型晶体管时，在控制信号为低电平时，该P型晶体管处于导通状态；而在控制信号为高电平时，P型晶体管处于截止状态。当采用N型晶体管时，可以采用氧化物半导体，例如氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)，作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。低温多晶硅通常指由非晶硅结晶得到多晶硅的结晶温度低于600摄氏度的情形。
图7为驱动图6中的像素电路的信号的时序图。如图7所示，像素电路110的工作过程包括三个阶段，分别为复位阶段P1、数据写入和补偿阶段P2以及发光阶段P3。
图8A为图6所示的像素电路在复位阶段的等效电路图。图8B为图6所示的像素电路在数据写入与补偿阶段的等效电路图。图8C为图6所示的像素电路在发光阶段的等效电路图。
在图7以及图8A、图8B和图8C中，VDD、VSS和VINT既用于表示相应的电压源，也用于表示相应的电压；RST、GA、DA、和EM既用于表示相应的信号端，也用于表示相应的信号。此外，在图8A、图8B和图8C中用“×”标识的晶体管均表示该晶体管在对应阶段内处于截止状态。
下面以第一复位晶体管T1、第二复位晶体管T2、数据写入晶体管T3、补偿晶体管T4、驱动晶体管Td、第一发光控制晶体管T5和第二发光控制晶体管T6均采用P型晶体管为例，结合图7以及图8A、图8B和图8C对图6中的像素电路的工作过程进行说明。
如图7所示，在复位阶段P1，输入低电平的复位信号RST，高电平的扫描信号GA、高电平的发光控制信号EM和低电平的数据信号DA。
在复位阶段P1，如图8A所示，第一复位晶体管T1的栅极接收到低电平的复位信号RST，第一复位晶体管T1导通，从而将复位电压VINT施加至驱动晶体管Td的栅极以对驱动晶体管Td的栅极进行复位，使得驱动晶体管Td以导通状态进入数据写入与补偿阶段P2。
在复位阶段P1，如图8A所示，第二复位晶体管T2的栅极接收低电平的复位信号RST，第二复位晶体管T2导通，从而将复位电压VINT施加至OLED的阳极以对OLED的阳极进行复位，使得OLED在发光阶段P3之前不发光。
此外，在复位阶段P1，如图8A所示，数据写入晶体管T3的栅极接收到高点平的扫描信号GA，数据写入晶体管T3截止；补偿晶体管T4的栅极接收到高电平的扫描信号GA，补偿晶体管T4截止；第一发光控制晶体管T5的栅极接收到高电平的发光控制信号EM，第一发光控制晶体管T5截止；第二发光控制晶体管T6的栅极接收到高电平的发光控制信号EM，第二发光控制晶体管T6截止。
如图7所示，在数据写入与补偿阶段P2，输入高电平的复位信号RST，低电平的扫描信号GA、高电平的发光控制信号EM和高电平的数据信号DA。
在数据写入与补偿阶段P2，如图8B所示，数据写入晶体管T3的栅极接收到低电平的扫描信号GA，数据写入晶体管T3导通，从而将数据信号写入第一节点N1(即，驱动晶体管Td的第一极)。补偿晶体管T4的栅极接收到低电平的扫描信号GA，补偿晶体管T3导通。由于数据写入晶体管T3、驱动晶体管Td和补偿晶体管T4均导通，所以数据信号DA经过数据写入晶体管T3、驱动晶体管Td和补偿晶体管T4对存储电容Cst进行充电，也就是对第二节点N2(即，驱动晶体管Td的栅极)进行充电，第三节点N3的电压逐渐升高。
容易理解，在数据写入与补偿阶段P2，由于数据写入晶体管T3导通，第一节点N1的电压保持为Vda。同时，根据驱动晶体管Td自身的特性，当第二节点N2的电压升高至Vda+Vth时，驱动晶体管Td截止，充电过程结束。这里，Vda表示数据信号DA的电压，Vth表示驱动晶体管Td的阈值电压，由于在本实施例中，驱动晶体管T1是以P型晶体管为例进行说明的，所以此处阈值电压Vth可以是负值。
经过数据写入和补偿阶段2后，第二节点N2的电压为Vdata+Vth，也就是说数据信号DA和阈值电压Vth的电压信息被存储在存储电容Cst中，以用于后续在发光阶段P3时，对驱动晶体管Td的阈值电压进行补偿。
此外，在数据写入与补偿阶段P2，如图8B所示，第一复位晶体管T1的栅极接收到高电平的复位信号RST，第一复位晶体管T1截止；第二复位晶体管T2的栅极接收到高电平的复位信号，第二复位晶体管T2截止；第一发光控制晶体管T5的栅极接收到高电平的发光控制信号EM，第一发光控制晶体管T5截止；第二发光控制晶体管T6的栅极接收到高电平的发光控制信号EM，第二发光控制晶体管T6截止。
如图7所示，在发光阶段P3，输入高电平的复位信号RST，高电平的扫描信号GA、低电平的发光控制信号EM和低电平的数据信号DA。
在发光阶段P3，如图8C所示，第一发光控制晶体管T5的栅极接收到低电平的发光控制信号EM，第一发光控制晶体管T5导通，从而将第一电压VDD施加至第一节点N1(即，驱动晶体管Td的第一极)。第二发光控制晶体管T6的栅极接收到低电平的发光控制信号EM，第二发光控制晶体管T6导通，从而将驱动晶体管Td产生的驱动电流施加至OLED。
此外，在发光阶段P3，如图8C所示，第一复位晶体管T1的栅极接收到高电平的复位信号RST，第一复位晶体管T1截止；第二复位晶 体管T2的栅极接收到高电平的复位信号，第二复位晶体管T2截止；数据写入晶体管T3的栅极接收到高点平的扫描信号GA，数据写入晶体管T3截止；补偿晶体管T4的栅极接收到高电平的扫描信号GA，补偿晶体管T4截止。
容易理解，在发光阶段P3，由于第一发光控制晶体管T5导通，第一节点N1的电压为VDD，而第二节点N2的电压为Vdata+Vth，所以驱动晶体管Td也导通。
在发光阶段P3，如图8C所示，OLED的阳极和阴极分别接入了第一电压VDD(高电压)和第二电压VSS(低电压)，从而在驱动晶体管Td产生的驱动电流的驱动下发光。
基于驱动晶体管Td的饱和电流公式，驱动OLED发光的驱动电流I D可以根据下式得出：
I D＝K(V GS-Vth) 2
＝K[(Vda+Vth-VDD)-Vth] 2
＝K(Vda-VDD) 2
在上述公式中，Vth表示驱动晶体管Td的阈值电压，V GS表示驱动晶体管Td的栅极和源极之间的电压，K为常数。从上式可以看出，流经OLED的驱动电流I D1不再与驱动晶体管Td的阈值电压Vth有关，而只与数据信号DA的电压Vda有关，由此可以实现对驱动晶体管Td的阈值电压Vth的补偿，解决了驱动晶体管Td由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I D的影响，从而可以改善显示效果。
例如，上述公式中K可以表示为：
K＝0.5m nC ox(W/L)，
其中，m n为驱动晶体管Td的电子迁移率，C ox为驱动晶体管Td的栅极单位电容量，W为驱动晶体管Td的沟道宽，L为驱动晶体管Td的沟道长。
图9A是本公开的实施例提供的阵列基板在包括图6中的像素电路时的一种结构示意图。
如图9A所示，在第m-1行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1条复位信号线R m-1以接收第二复位信号，数据写入晶体管T3的栅极和补偿晶体管T4的栅极连接到第m-1对栅线S m-1中的第一栅线So m-1以接收第一扫描信号，数据写入晶体管T3的第一极连接到第n条数据线D n以接收数据信号，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极连接到第m-1条发光控制信号线E m-1以接收发光控制信号。
如图9A所示，在第m-1行像素单元中的第n+1列像素单元中，第一复 位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1对栅线S m中的第一栅线So m-1以接收第一扫描信号作为第一复位信号，数据写入晶体管T3的栅极和补偿晶体管T4的栅极连接到第m-1对栅线S m-1中的第二栅线Se m-1以接收第二扫描信号，数据写入晶体管T3的第一极连接到第n+1条数据线D n+1以接收数据信号，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极连接到第m-1条发光控制信号线E m-1以接收发光控制信号。
如图9A所示，在第m行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m条复位信号线R m以接收第二复位信号，数据写入晶体管T3的栅极和补偿晶体管T4的栅极连接到第m对栅线S m中的第一栅线So m以接收第一扫描信号，数据写入晶体管T3的第一极连接到第n条数据线D n以接收数据信号，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极连接到第m条发光控制信号线E m以接收发光控制信号。
如图9A所示，在第m行像素单元中的第n+1列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m对栅线S m中的第一栅线So m以接收第一扫描信号作为第一复位信号，数据写入晶体管T3的栅极和补偿晶体管T4的栅极连接到第m对栅线S m中的第二栅线Se m以接收第二扫描信号，数据写入晶体管T3的第一极连接到第n+1条数据线D n+1以接收数据信号，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极连接到第m条发光控制信号线E m以接收发光控制信号。
需要说明的是，尽管图9A示出的包括图6中的像素电路的阵列基板10采用了图3A中所示的阵列基板10的结构，但是本公开的实施例显然不限于此。图9A示出的阵列基板10可以采用图2A、图2B或图3B中的阵列基板10的结构。
例如，在包括图6中的像素电路的阵列基板采用图2A中的阵列基板10的结构的情况下，阵列基板可以不包括复位信号线R；在第m-1行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1对栅线S m-1中的第二栅线Se m-1以接收第二扫描信号作为第二复位信号；在第m行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1对栅线S m-1中的第一栅线So m-1以接收第一扫描信号作为第二复位信号。在这种情况下，关于第m-1行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式以及第m行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式，可以参考上面对图9A的阵列基板10(即，采用图3A中的阵列基板10的结构)所做的描述，这里不再赘述。
例如，在包括图6中的像素电路的阵列基板采用图2B中的阵列基板10的结构的情况下，阵列基板可以不包括复位信号线R；在第m行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1对栅线S m-1中的第二栅线Se m-1以接收第二扫描信号作为第二复位信号。在这种情况下，关于第m-1行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式以及第m行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式，可以参考上面对图9A的阵列基板10(即，采用图3A中的阵列基板10的结构)所做的描述，这里不再赘述。
例如，在包括图6中的像素电路的阵列基板采用图3B中的阵列基板10的结构的情况下，在第m-1行像素单元中的第n列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1对栅线S m-1中的第二栅线Se m-1以接收第二扫描信号作为第二复位信号；在第m-1行像素单元中的第n+1列像素单元中，第一复位晶体管T1的栅极和第二复位晶体管T2的栅极连接到第m-1条复位信号线R m-1。在这种情况下，关于第m-1行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式以及第m行像素单元中的第n列像素单元和第n+1列像素单元中的其他晶体管的连接方式，可以参考上面对图9A的阵列基板10(即，采用图3A中的阵列基板10的结构)所做的描述，这里不再赘述。
图9B是本公开的实施例提供的阵列基板在包括图6中的像素电路时的另一种结构示意图。
如图9B所示，在第m-1行像素单元中的第n列像素单元和第n+1列像素单元中，数据写入晶体管T3的第一极连接到第i条数据线D i以接收数据信号；在第m行像素单元中的第n列像素单元和第n+1列像素单元中，数据写入晶体管T3的第一极连接到第i条数据线Di以接收数据信号。对比图9A和图9B可知，在图9A所示的阵列基板10中，第n列像素单元和第n+1列像素单元连接到不同的数据线D，第n列像素单元连接到第n条数据线D n，第n+1列像素单元连接到第n+1条数据线D n+1；然而，在图9B所示的阵列基板10中，第n列像素单元和第n+1列像素单元连接到同一条数据线D，第n列像素单元和第n+1列像素单元均连接到第i条数据线D i。
为了简便起见，这里仅对图9B中的阵列基板中的数据写入晶体管T3与数据线的连接方式进行了详细描述，关于图9B中的阵列基板中的其他晶体管的连接方式的描述，可以参考上面对图9A中的阵列基板所做的相关描述，这里不再赘述。
图10是驱动本公开的实施例提供的阵列基板的信号的时序图。
下面参考图10，对本公开的实施例提供的阵列基板中的第m行像素单元的工作过程进行说明。
如图10所示，第m行像素单元中的第n列像素单元的工作过程分为三个阶段，分别是第一复位阶段P1 n、第一数据写入与补偿阶段P2 n和第一发光阶段P3 n；第m行像素单元中的第n列像素单元的工作过程也分为三个阶段，分别是第二复位阶段P1 n+1、第二数据写入与补偿阶段P2 n+1和第三发光阶段P3 n+1。
如图10所示，在第一复位阶段P1 n向第m行像素单元中的第n列像素单元提供低电平的复位信号RST n，以对第m行像素单元中的第n列像素单元进行复位。
例如，在阵列基板采用图2A中的阵列基板10的结构时，复位信号RST n可以指第m-1对栅线S m-1中的第一栅线So m-1提供的第一扫描信号充当的第二复位信号；在阵列基板采用图2B中的阵列基板10的结构时，复位信号RST n可以指第m-1对栅线S m-1中的第二栅线Se m-1提供的第二扫描信号充当的第二复位信号；在阵列基板采用图3A或图3B中的阵列基板10的结构时，复位信号RST n可以指第m条复位信号线R m提供的第二复位信号。
如图10所示，在第一数据写入与补偿阶段P2 n向第m行像素单元中的第n列像素单元提供低电平的扫描信号GA n和高电平的数据信号DA n，以对第m行像素单元中的第n列像素单元进行数据写入和补偿。
例如，扫描信号GA n指的是第m对栅线S m中的第一栅线So m提供的第一扫描信号。
例如，数据信号DA n指的是与第n列像素单元对应的一条数据线提供的数据信号。例如，在多条数据线与多列像素像素单元一一对应的情况下，数据信号DA n指第n条数据信号线D n提供的数据信号。
如图10所示，在第一发光阶段P3 n向第m行像素单元中的第n列像素单元提供低电平的发光控制信号EM n，以使第m行像素单元中的第n列像素单元进行显示。
例如，发光控制信号EM n指的是第m条发光控制信号线E m提供的发光控制信号。
如图10所示，在第二复位阶段P1 n+1向第m行像素单元中的第n+1列像素单元提供低电平的复位信号RST n+1，以对第m行像素单元中的第n+1列像素单元进行复位。
例如，复位信号RST n+1指的是第m对栅线S m中的第一栅线So m提供的第一扫描信号，也就是扫描信号GA n。
如图10所示，在第二数据写入与补偿阶段P2 n+1向第m行像素单元中的 第n+1列像素单元提供低电平的扫描信号GA n+1和高电平的数据信号DA n+1，以对第m行像素单元中的第n+1列像素单元进行数据写入和补偿。
例如，扫描信号GA n+1指的是第m对栅线S m中的第二栅线Se m提供的第一扫描信号。
例如，数据信号DA n+1指的是与第n+1列像素单元对应的一条数据线提供的数据信号。例如，在多条数据线与多列像素像素单元一一对应的情况下，数据信号DA n+1指第n+1条数据信号线D n+1提供的数据信号。
如图10所示，在第二发光阶段P3 n+1向第m行像素单元中的第n+1列像素单元提供低电平的发光控制信号EM n+1，以使第m行像素单元中的第n+1列像素单元进行显示。
例如，发光控制信号EM n+1指的是第m条发光控制信号线E m提供的发光控制信号。
参考图10可知，在第m行像素单元中，第n列像素单元的扫描信号GA n可以充当第n+1列像素单元的复位信号RST n+1。在这种情况下，在对第n列像素单元进行数据写入与补偿的同时，可以对第n+1列像素单元进行复位，也就是说，第一数据写入与补偿阶段P2 n与第二复位阶段P1 n+1在时间上可以是同步的。
参考图10可知，在第m行像素单元中，第n列像素单元的发光控制信号EM n与第n+1列像素单元的发光控制信号EM n+1是同一个发光控制信号，也就是说，第一发光阶段P3 n与第二发光阶段P3 n+1在时间上可以是同步的。
此外，参考图10可知，在第m行像素单元中，是先对第n列像素单元进行复位，在同时对第n列像素单元进行数据写入与补偿并对第n+1列像素单元进行复位，然后在对第n+1列像素单元进行数据写入与补偿，最后同时使第n列像素单元和第n+1列像素单元进行显示。在这种情况下，第一复位阶段P1 n、第一数据写入与补偿阶段P2 n、第一发光阶段P3 n、第二复位阶段P1 n+1、第二数据写入与补偿阶段P2 n+1和第三发光阶段P3 n+1在时间上的顺序为：P1 n→P2 n&P1 n+1→P2 n+1→P3 n&P3 n+1。由此可知，在第m行像素单元中，第n列像素单元和第n+1列像素单元的充电过程(第一数据写入与补偿阶段P2 n和第二数据写入与补偿阶段P2 n+1)分开进行且充电时长相同，并且第n列像素单元和第n+1列像素单元的发光过程(第一发光阶段P3n和第三发光阶段P3n+1)同步且发光时长相同，这可以使得第m行像素单元中的第n列像素单元和第n+1列像素单元的发光亮度均匀，改善显示质量。
需要说明的是，尽管在图10中示出第m行像素单元中的第n列像素单元和第n+1列像素单元接收不同的数据信号(第n列像素单元接收数据信号D n，第n+1列像素单元接收数据信号D n+1)，但是由于第m行像素单元中的 第n列像素单元和第n+1列像素单元的充电过程(第一数据写入与补偿阶段P2 n和第二数据写入与补偿阶段P2 n+1)是分开进行的，所以第n列像素单元和第n+1列像素单元可以连接到同一条数据线以接收同一个数据信号，这个数据信号在第一数据写入与补偿阶段P2 n和第二数据写入与补偿阶段P2 n+1均处于高电平状态。由于在第一数据写入与补偿阶段P2 n第n列像素单元打开而第n+1列像素单元关闭(扫描信号GAn处于低电平，扫描信号GAn+1处于高电平)，且在第二数据写入与补偿阶段P2 n+1第n列像素单元关闭而第n+1列像素单元打开(扫描信号GAn处于高电平，扫描信号GAn+1处于低电平)，所以通过同一条数据线可以在第一数据写入与补偿阶段P2 n向第n列像素单元提供高电平的数据信号，并且在第二数据写入与补偿阶段P2 n+1向第n+1列像素单元提供高电平的数据信号。需要说明的是，尽管仅结合图10对本公开的实施例提供的阵列基板中的第m行像素单元的工作过程进行了说明，但是本公开的实施例提供的阵列基板中的其他行的像素单元(例如，第m-1行像素单元)的工作过程与第m行像素单元的工作过程是类似的，因此可以参考上面结合图10对第m行像素单元的工作过程所做的描述，这里不再赘述。
本公开至少一实施例还提供一种显示面板，该显示面板包括本公开任一实施例提供的阵列基板。
图11为本公开一实施例提供的显示面板的结构示意图。如图11所示，显示面板1可以包括数据驱动电路20和本公开任一实施例提供的阵列基板10。
如图11所示，数据驱动电路20连接至多条数据线D，并且被配置为产生数据信号。例如，数据驱动电路20可以通过第n条数据线D n向阵列基板10中的第n列像素单元提供数据信号。
例如，显示面板1还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示面板1可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板1不仅可以为平面面板，也可以为曲面面板，甚至球面面板。例如，显示面板1还可以具备触控功能，即显示面板1可以为触控显示面板。
例如，显示面板1可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的显示面板具有与本公开前述实施例提供的阵列基板相同或相似的有益效果，由于阵列基板在前述实施例中已经进行 了详细说明，此处不再赘述。
本公开至少一实施例还提供一种应用于本公开任一实施例提供的阵列基板的驱动方法。
图12为本公开的实施例提供的阵列基板的驱动方法的流程图。如图12所示，该驱动方法可以包括：
步骤S10：对第m行像素单元中的第n列像素单元进行复位；
步骤S20：对第m行像素单元中的第n列像素单元进行数据写入和补偿，同时对第m行像素单元中的第n+1列像素单元进行复位；
步骤S30：对第m行像素单元中的第n+1列像素单元进行数据写入和补偿；以及
步骤S40：使第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
例如，当在第m行像素单元中的第n列像素单元的扫描信号端连接至第m对栅线中的第一栅线，第m行像素单元中的第n列像素单元的数据信号端连接至与第n列像素单元对应的一条数据线，且第m行像素单元中的第n+1列像素单元的复位信号端连接至第m对栅线中的第一栅线时，步骤S20可以包括：通过第m对栅线中的第一栅线向第m行像素单元中的第n列像素单元提供第一扫描信号，并通过与第n列像素单元相对应的一条数据线向第m行像素单元中的第n列像素单元提供数据信号，以对第m行像素单元中的第n列像素单元进行数据写入和补偿，同时通过第m对栅线中的第一栅线向第m行像素单元中的第n+1列像素单元提供第一扫描信号作为第一复位信号，以对第m行像素单元中的第n+1列像素单元进行复位。
例如，当第m行像素单元中的第n列像素单元的复位信号端连接至第m-1对栅线中的第一栅线时，步骤S10可以包括：通过第m-1对栅线中的第一栅线向第m行像素单元中的第n列像素单元提供第一扫描信号作为第二复位信号，以对第m行像素单元中的第n列像素单元进行复位。
例如，当第m行像素单元中的第n列像素单元的复位信号端连接至第m-1对栅线中的第二栅线时，步骤S10可以包括：通过第m-1对栅线中的第二栅线向第m行像素单元中的第n列像素单元提供第二扫描信号作为第二复位信号，以对第m行像素单元中的第n列像素单元进行复位。
例如，在阵列基板包括多条复位信号线的情况下，当第m行像素单元中的第n列像素单元的复位信号端连接至第m条复位信号线时， 步骤S10可以包括：通过第m条复位信号线向第m行像素单元中的第n列像素单元提供第二复位信号，以对第m行像素单元中的第n列像素单元进行复位。
例如，当第m行像素单元中的第n+1列像素单元的扫描信号端连接至第m对栅线中的第二栅线，且第m行像素单元中的第n+1列像素单元的数据信号端连接到与第n+1列像素单元相对应的一条数据线时，步骤S30可以包括：通过第m对栅线中的第二栅线向第m行像素单元中的第n+1列像素单元提供第二扫描信号并通过与第n+1列像素单元对应的一条数据线向第m行像素单元中的第n+1列像素单元提供数据信号，以对第m行像素单元中的第n+1列像素单元进行数据写入和补偿。
例如，在阵列基板包括多条发光控制信号线的情况下，当第m行像素单元中的第n列像素单元和第n+1列像素单元的发光控制信号端连接至第m条发光控制信号线时，步骤S40可以包括：通过第m条发光控制信号线向第m行像素单元中的第n列像素单元和第n+1列像素单元提供发光控制信号，以使第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
本公开的实施例提供的阵列基板的驱动方法可以先对第m行像素单元中的第n列像素单元进行充电，再对第m行像素单元中的第n+1列像素单元进行充电，最后使第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示，由此可使得第m行像素单元中的第n列像素单元和第n+1列像素单元的充电方式一致，且使得第m行像素单元中的第n列像素单元和第n+1列像素单元显示亮度均匀。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (19)

  1. 一种阵列基板，包括：
    多对栅线，多对栅线中的每对包括第一栅线和第二栅线；
    多条数据线；和
    像素阵列，包括排布为多行多列的多个像素单元，
    其中，所述多个像素单元中的每个包括扫描信号端、数据信号端和复位信号端，多行像素单元与所述多对栅线与一一对应，每列像素单元对应于所述多条数据线中的一条数据线；
    第m行像素单元中的第n列像素单元的扫描信号端连接到第m对栅线中的第一栅线以接收第一扫描信号，m和n均为正整数；
    所述第m行像素单元中的第n+1列像素单元的扫描信号端连接到所述第m对栅线中的第二栅线以接收第二扫描信号；
    所述第m行像素单元中的第n+1列像素单元的复位信号端连接到所述第m对栅线中的第一栅线以接收所述第一扫描信号作为第一复位信号；
    所述每列像素单元的数据信号端连接到对应的一条数据线以接收数据信号。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第m行像素单元中的第n列像素单元的复位信号端连接到第m-1对栅线中的第一栅线，以接收所述第m-1对栅线中的第一栅线提供的第一扫描信号作为第二复位信号，或者
    所述第m行像素单元中的第n列像素单元的复位信号端连接到所述第m-1对栅线中的第二栅线，以接收所述第m-1对栅线中的第二栅线提供的第二扫描信号作为所述第二复位信号，
    m为大于1的整数。
  3. 根据权利要求1所述的阵列基板，还包括多条复位信号线，
    其中，所述多条复位信号线与所述多行像素单元一一对应；
    所述第m行像素单元中的第n列像素单元的复位信号端连接到第m条复位信号线以接收第二复位信号。
  4. 根据权利要求3所述的阵列基板，还包括第一扫描驱动电路，
    其中，所述第一扫描驱动电路连接至所述多条复位信号线，且被配置为产生所述第二复位信号。
  5. 根据权利要求1-4中任一项所述的阵列基板，还包括多条发光控制信号线，
    其中，所述多条发光控制信号线与所述多行像素单元一一对应；
    所述多个像素单元每个还包括发光控制信号端，所述第m行像素单元的发光控制信号端连接到第m条发光控制信号线以接收发光控制信号。
  6. 根据权利要求5所述的阵列基板，还包括第二扫描驱动电路，
    其中，所述第二扫描驱动电路连接至所述多条发光控制信号线，且配置为产生所述发光控制信号。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中，每相邻的两列像素单元对应于同一条数据线，
    所述第n列像素单元和所述第n+1列像素单元的数据信号端连接到同一条数据线。
  8. 根据权利要求1-7中任一项所述的阵列基板，还包括第三扫描驱动电路，
    所述第三扫描驱动电路连接到所述多对栅线，且被配置为产生所述第一扫描信号和所述第二扫描信号。
  9. 根据权利要求8所述的阵列基板，其中，所述第三扫描驱动电路包括第一扫描驱动子电路和第二扫描驱动子电路，
    所述第一扫描驱动子电路连接到每对栅线中的第一栅线，且被配置为产生所述第一扫描信号；
    所述第二扫描驱动子电路连接到每对栅线中的第二栅线，且被配置为产生所述第二扫描信号。
  10. 根据权利要求9所述的阵列基板，其中，所述第一扫描驱动子电路和所述第二扫描驱动子电路分别设置在所述像素阵列的彼此相对的两侧。
  11. 根据权利要求1-10中任一项所述的阵列基板，其中，所述每个像素单元包括像素电路，所述像素电路包括：复位电路、数据写入与补偿电路、驱动电路和发光控制电路，
    所述复位电路包括所述复位信号端，并且连接至复位电压源、所述驱动电路和发光元件，被配置为将复位电压施加至所述驱动电路和所述发光元件以对所述驱动电路和所述发光元件进行复位；
    所述数据写入与补偿电路包括所述扫描信号端和所述数据信号端，并且连接至所述驱动电路，被配置为将所述数据信号写入所述驱动电路并对所述驱动电路进行补偿；
    所述驱动电路被配置为产生驱动所述发光元件发光的驱动电流；
    所述发光控制电路包括发光控制信号端，并且连接至第一电压源、 所述驱动电路和所述发光元件，被配置为将第一电压施加至所述驱动电路，且将所述驱动电路产生的驱动电流施加至所述发光元件。
  12. 根据权利要求11所述的阵列基板，其中，所述复位电路包括第一复位晶体管和第二复位晶体管；
    所述数据写入与补偿电路包括数据写入晶体管、补偿晶体管和存储电容；
    所述驱动电路包括驱动晶体管；
    所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管；
    所述第一复位晶体管的栅极连接至所述复位信号端，所述第一复位晶体管的第一极连接至所述复位电压源，所述第一复位晶体管的第二极连接至所述驱动晶体管的栅极；
    所述第二复位晶体管的栅极连接至所述复位信号端，所述第二复位晶体管的第一极连接至所述复位电压源，所述第二复位晶体管的第二极连接至所述发光元件的第一端；
    所述数据写入晶体管的栅极连接至所述扫描信号端，所述数据写入晶体管的第一极连接至所述数据信号端，所述数据写入晶体管的第二极连接至所述驱动晶体管的第一极；
    所述补偿晶体管的栅极连接至所述扫描信号端，所述补偿晶体管的第一极连接至所述驱动晶体管的第二极，所述补偿晶体管的第二极连接至所述驱动晶体管的栅极；
    所述存储电容的第一端连接至所述第一电压源，所述存储电容的第二端连接至所述驱动晶体管的栅极；
    所述第一发光控制晶体管的栅极连接至所述发光控制信号端，所述第一发光控制晶体管的第一极连接至所述第一电压源，所述第一发光控制晶体管的第二极连接至所述驱动晶体管的第一极；
    所述第二发光控制晶体管的栅极连接至所述发光控制信号端，所述第二发光控制晶体管的第一极连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接至所述发光元件的第一端。
  13. 一种显示面板，包括权利要求1-12中任一所述的阵列基板。
  14. 一种如权利要求1所述的阵列基板的驱动方法，包括：
    对所述第m行像素单元中的第n列像素单元进行复位；
    对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时对所述第m行像素单元中的第n+1列像素单元进行复位；
    对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿；
    使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
  15. 根据权利要求14所述的驱动方法，其中，对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时对所述第m行像素单元中的第n+1列像素单元进行复位，包括：
    通过所述第m对栅线中的第一栅线向所述第m行像素单元中的第n列像素单元提供所述第一扫描信号，并通过与所述第n列像素单元相对应的一条数据线向所述第m行像素单元中的第n列像素单元提供所述数据信号，以对所述第m行像素单元中的第n列像素单元进行数据写入和补偿，同时通过所述第m对栅线中的第一栅线向第m行像素单元中的第n+1列像素单元提供所述第一扫描信号作为所述第一复位信号，以对所述第m行像素单元中的第n+1列像素单元进行复位。
  16. 根据权利要求15所述的驱动方法，其中，对所述第m行像素单元中的第n列像素单元进行复位，包括：
    通过第m-1对栅线中的第一栅线向所述第m行像素单元中的第n列像素单元提供所述第一扫描信号作为第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位；或者
    通过所述第m-1对栅线中的第二栅线向所述第m行像素单元中的第n列像素单元提供所述第二扫描信号作为所述第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位。
  17. 根据权利要求16所述的驱动方法，其中，所述阵列基板还包括多条发光复位信号线，
    对所述第m行像素单元中的第n列像素单元进行复位，包括：
    通过第m条复位信号线向所述第m行像素单元中的第n列像素单元提供第二复位信号，以对所述第m行像素单元中的第n列像素单元进行复位。
  18. 根据权利要求14-17中任一项所述的驱动方法，其中，对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿，包括：
    通过所述第m对栅线中的第二栅线向所述第m行像素单元中的第n+1列像素单元提供所述第二扫描信号并通过与所述第n+1列像素单元对应的一条数据线向第m行像素单元中的第n+1列像素单元提供所述数据信号，以对所述第m行像素单元中的第n+1列像素单元进行数据写入和补偿。
  19. 根据权利要求14-18中任一项所述的驱动方法，其中，所述阵列基板还包括多条发光控制信号线，
    使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示，包括：
    通过第m条发光控制信号线向所述第m行像素单元中的第n列像素单元和第n+1列像素单元提供发光控制信号，以使所述第m行像素单元中的第n列像素单元和第n+1列像素单元进行显示。
PCT/CN2020/092573 2020-05-27 2020-05-27 阵列基板、显示面板以及阵列基板的驱动方法 WO2021237505A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US17/274,665 US20220199027A1 (en) 2020-05-27 2020-05-27 Array substrate, display panel and driving method of array substrate
JP2021569201A JP7568652B2 (ja) 2020-05-27 2020-05-27 アレイ基板、表示パネル及びアレイ基板の駆動方法
EP20900718.6A EP4002336A4 (en) 2020-05-27 2020-05-27 MATRIX SUBSTRATE, BILLBOARD, AND METHOD OF ATTACKING MATRIX SUBSTRATE
PCT/CN2020/092573 WO2021237505A1 (zh) 2020-05-27 2020-05-27 阵列基板、显示面板以及阵列基板的驱动方法
CN202080000824.2A CN113994416B (zh) 2020-05-27 2020-05-27 阵列基板、显示面板以及阵列基板的驱动方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/092573 WO2021237505A1 (zh) 2020-05-27 2020-05-27 阵列基板、显示面板以及阵列基板的驱动方法

Publications (1)

Publication Number Publication Date
WO2021237505A1 true WO2021237505A1 (zh) 2021-12-02

Family

ID=78745234

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/092573 WO2021237505A1 (zh) 2020-05-27 2020-05-27 阵列基板、显示面板以及阵列基板的驱动方法

Country Status (5)

Country Link
US (1) US20220199027A1 (zh)
EP (1) EP4002336A4 (zh)
JP (1) JP7568652B2 (zh)
CN (1) CN113994416B (zh)
WO (1) WO2021237505A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023178570A1 (zh) * 2022-03-23 2023-09-28 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390392A (zh) * 2013-07-18 2013-11-13 合肥京东方光电科技有限公司 Goa电路、阵列基板、显示装置及驱动方法
CN203325406U (zh) * 2013-07-03 2013-12-04 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路及显示装置
US9269428B2 (en) * 2014-06-12 2016-02-23 Windbond Electronics Corp. RRAM memory device and method thereof
CN205507290U (zh) * 2016-04-11 2016-08-24 京东方科技集团股份有限公司 触控显示模组、触控显示面板和装置
CN109389937A (zh) * 2017-08-03 2019-02-26 上海和辉光电有限公司 一种像素电路、显示装置及像素电路的驱动方法
CN110599971A (zh) * 2019-08-02 2019-12-20 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN110969989A (zh) * 2019-12-20 2020-04-07 京东方科技集团股份有限公司 像素电路的驱动方法和控制驱动方法
CN210627878U (zh) * 2020-01-02 2020-05-26 京东方科技集团股份有限公司 像素电路和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010060648A (ja) 2008-09-01 2010-03-18 Hitachi Displays Ltd 画像表示装置
CN102646386B (zh) * 2011-05-13 2014-08-06 京东方科技集团股份有限公司 一种像素单元电路、像素阵列、面板及面板驱动方法
JP5939076B2 (ja) * 2012-07-31 2016-06-22 ソニー株式会社 表示装置、駆動回路、駆動方法、および電子機器
CN103700346B (zh) * 2013-12-27 2016-08-31 合肥京东方光电科技有限公司 像素驱动电路、阵列基板、显示装置和像素驱动方法
KR102257941B1 (ko) * 2014-06-17 2021-05-31 삼성디스플레이 주식회사 유기 발광 표시 장치
CN104575384B (zh) 2015-01-17 2017-06-16 昆山工研院新型平板显示技术中心有限公司 有源有机发光显示器及其驱动电路
KR102570986B1 (ko) 2016-11-15 2023-08-28 삼성디스플레이 주식회사 표시 패널 및 표시 장치
CN106710525B (zh) 2017-01-06 2019-02-05 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
CN109599062A (zh) 2017-09-30 2019-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107680537B (zh) * 2017-11-21 2019-11-29 上海天马微电子有限公司 一种像素电路的驱动方法
KR102571661B1 (ko) * 2018-11-09 2023-08-28 엘지디스플레이 주식회사 표시패널 및 표시장치
CN109637453B (zh) 2019-01-31 2021-03-09 上海天马微电子有限公司 显示面板及其驱动方法、显示装置
CN110675824B (zh) 2019-10-09 2021-08-27 京东方科技集团股份有限公司 一种信号输出电路、驱动ic、显示装置及其驱动方法
CN110660360B (zh) * 2019-10-12 2021-05-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN110767665B (zh) 2019-11-29 2022-05-31 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
EP4036903A4 (en) 2020-06-30 2023-01-11 BOE Technology Group Co., Ltd. ARRAY SUBSTRATE AND DISPLAY PANEL AND DISPLAY DEVICE SAME

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203325406U (zh) * 2013-07-03 2013-12-04 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路及显示装置
CN103390392A (zh) * 2013-07-18 2013-11-13 合肥京东方光电科技有限公司 Goa电路、阵列基板、显示装置及驱动方法
US9269428B2 (en) * 2014-06-12 2016-02-23 Windbond Electronics Corp. RRAM memory device and method thereof
CN205507290U (zh) * 2016-04-11 2016-08-24 京东方科技集团股份有限公司 触控显示模组、触控显示面板和装置
CN109389937A (zh) * 2017-08-03 2019-02-26 上海和辉光电有限公司 一种像素电路、显示装置及像素电路的驱动方法
CN110599971A (zh) * 2019-08-02 2019-12-20 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN110969989A (zh) * 2019-12-20 2020-04-07 京东方科技集团股份有限公司 像素电路的驱动方法和控制驱动方法
CN210627878U (zh) * 2020-01-02 2020-05-26 京东方科技集团股份有限公司 像素电路和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023178570A1 (zh) * 2022-03-23 2023-09-28 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Also Published As

Publication number Publication date
US20220199027A1 (en) 2022-06-23
CN113994416A (zh) 2022-01-28
EP4002336A4 (en) 2022-08-24
CN113994416B (zh) 2023-12-12
JP2023536014A (ja) 2023-08-23
JP7568652B2 (ja) 2024-10-16
EP4002336A1 (en) 2022-05-25

Similar Documents

Publication Publication Date Title
CN110660360B (zh) 像素电路及其驱动方法、显示面板
CN110176213B (zh) 像素电路及其驱动方法、显示面板
CN110268465B (zh) 像素电路、显示面板及像素电路的驱动方法
US20240119897A1 (en) Pixel Circuit and Driving Method Therefor and Display Panel
US12118939B2 (en) Pixel circuit and driving method therefor, array substrate, and display device
US11657759B2 (en) Pixel circuit and method of driving the same, display panel
US11205381B2 (en) Display panel, display device and compensation method
US20210312861A1 (en) Pixel circuit and driving method thereof, array substrate, and display device
CN107799062B (zh) 一种像素电路及其驱动方法、显示装置
US9972249B2 (en) Pixel structure and driving method thereof, organic light emitting display panel and display apparatus
CN104751804A (zh) 一种像素电路、其驱动方法及相关装置
US11862085B2 (en) Pixel circuit and driving method therefor, array substrate and display apparatus
CN110895915A (zh) 像素电路及其驱动方法、显示装置
WO2019037476A1 (zh) 像素补偿电路、其驱动方法、显示面板及显示装置
US11450270B2 (en) Pixel circuit and method of driving the same, display device
US11922881B2 (en) Pixel circuit and driving method thereof, array substrate and display apparatus
CN106971691A (zh) 一种像素电路、驱动方法及显示装置
US12002425B2 (en) Pixel circuit and driving method therefor, and display apparatus
WO2024046066A1 (zh) 像素电路、像素驱动方法、显示基板和显示装置
US20210210013A1 (en) Pixel circuit and driving method, display panel, display device
CN113990259A (zh) 像素驱动电路及显示面板
CN112037714A (zh) 一种像素电路、其驱动方法、显示面板及显示装置
WO2021237505A1 (zh) 阵列基板、显示面板以及阵列基板的驱动方法
WO2024187379A1 (zh) 像素电路、显示装置及驱动方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021569201

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20900718

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020900718

Country of ref document: EP

Effective date: 20220216

NENP Non-entry into the national phase

Ref country code: DE