WO2024046066A1 - 像素电路、像素驱动方法、显示基板和显示装置 - Google Patents

像素电路、像素驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2024046066A1
WO2024046066A1 PCT/CN2023/111905 CN2023111905W WO2024046066A1 WO 2024046066 A1 WO2024046066 A1 WO 2024046066A1 CN 2023111905 W CN2023111905 W CN 2023111905W WO 2024046066 A1 WO2024046066 A1 WO 2024046066A1
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WIPO (PCT)
Prior art keywords
circuit
control
transistor
electrically connected
line
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Application number
PCT/CN2023/111905
Other languages
English (en)
French (fr)
Inventor
侯唯玮
李秋婕
张凯
王培�
田雨
李南军
姚代朋
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024046066A1 publication Critical patent/WO2024046066A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a pixel driving method, a display substrate and a display device.
  • an embodiment of the present disclosure provides a pixel circuit including a driving circuit, a first reset circuit, a first node control circuit, a first light emitting control circuit and a light emitting element;
  • the control end of the driving circuit is electrically connected to the first node
  • the first reset circuit is electrically connected to the first node, the first initial voltage line and the first pole of the light-emitting element respectively, and is used to reset the first node under the control of the potential of the first node.
  • the first initial voltage provided by the initial voltage line is written into the first pole of the light-emitting element to initialize the first pole of the light-emitting element;
  • the first node control circuit is electrically connected to the data line, the first node, the first end of the driving circuit and the second end of the driving circuit respectively, and is used to adjust the data voltage provided by the data line and The threshold voltage of the driving transistor included in the driving circuit controls the potential of the first node;
  • the first light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element respectively, and is used to control the light-emitting control signal provided by the light-emitting control line. Controlling communication between the second end of the driving circuit and the first pole of the light-emitting element;
  • the drive circuit is used to generate a drive current under the control of the potential of the first node
  • the second pole of the light-emitting element is electrically connected to the first voltage line.
  • the first node control circuit includes a data writing circuit, a compensation control circuit and an energy storage circuit;
  • the data writing circuit is electrically connected to the scanning line, the data line and the first end of the driving circuit respectively, and is used to write the data voltage provided by the data line under the control of the scanning signal provided by the scanning line. Enter the first end of the driving circuit;
  • the compensation control circuit is electrically connected to the scan line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the control end of the drive circuit under the control of the scan signal. Communicated with the second end of the driving circuit;
  • the first end of the energy storage circuit is electrically connected to the control end of the drive circuit, the second end of the energy storage circuit is electrically connected to the second voltage line, and the energy storage circuit is used to store electrical energy.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit
  • the second reset circuit is electrically connected to the reset control line, the second initial voltage line and the control end of the drive circuit respectively, and is used to reset the second reset circuit under the control of the reset control signal provided by the reset control line.
  • the second initial voltage provided by the initial voltage line is provided to the control terminal of the driving circuit to initialize the control terminal of the driving circuit.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emission control circuit
  • the second lighting control circuit is electrically connected to the lighting control line, the second voltage line and the first end of the driving circuit respectively, and is used to control the driving under the control of the lighting control signal provided by the lighting control line.
  • the first end of the circuit is connected to the second voltage line;
  • the second lighting control circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the driving circuit. The first end is electrically connected.
  • the first reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first initial voltage line, and the second electrode of the first transistor is electrically connected to the light emitting The first pole of the component is electrically connected.
  • the driving circuit includes a driving transistor, and the first lighting control circuit includes a second transistor;
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the driving transistor is electrically connected to the first terminal of the driving circuit.
  • the second terminal is electrically connected;
  • the control electrode of the second transistor is electrically connected to the light-emitting control line
  • the first electrode of the second transistor is electrically connected to the second terminal of the drive circuit
  • the second electrode of the second transistor is electrically connected to the light-emitting control line.
  • the first electrode of the light-emitting element is electrically connected.
  • the data writing circuit includes a third transistor, and the compensation control circuit includes a fourth transistor;
  • the energy storage circuit includes a first capacitor;
  • the control electrode of the third transistor is electrically connected to the scan line, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the first electrode of the drive circuit. terminal electrical connection;
  • the control electrode of the fourth transistor is electrically connected to the scan line, the first electrode of the fourth transistor is electrically connected to the control end of the drive circuit, and the second electrode of the fourth transistor is electrically connected to the drive circuit. The second end is electrically connected;
  • the first plate of the first capacitor is electrically connected to the control terminal of the drive circuit, and the second plate of the first capacitor is electrically connected to the second voltage line.
  • the second reset circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the reset control line, the first electrode of the fifth transistor is electrically connected to the second initial voltage line, and the second electrode of the fifth transistor is electrically connected to the drive The control terminal of the circuit is electrically connected.
  • embodiments of the present disclosure also provide a pixel driving method, which is applied to the above-mentioned pixel circuit.
  • the display cycle includes a data writing phase and a display phase that are set successively;
  • the pixel driving method includes:
  • the data line provides a data voltage
  • the first node control circuit controls the potential of the first node according to the data voltage and the threshold voltage of the driving transistor in the driving circuit
  • the first reset circuit writes the first initial voltage into the first pole of the light-emitting element under the control of the potential of the first node. , to initialize the first pole of the light-emitting element.
  • the pixel driving method further includes: when the data voltage is not a data voltage corresponding to a black screen, during the display stage, the first light-emitting control circuit controls the light-emitting control signal provided by the light-emitting control line. Under the control, the second end of the driving circuit is connected to the first pole of the light-emitting element, and the driving circuit generates a current to drive the light-emitting element under the control of the potential of its control end;
  • the pixel circuit also includes a second light emitting control circuit; the pixel driving method further includes: a second light emitting control circuit, under the control of the light emitting control signal, controls the first end of the driving circuit to connect the second voltage connections between lines.
  • the pixel circuit also includes a second reset circuit;
  • the display cycle also includes an initialization stage set before the data writing stage;
  • the pixel driving method further includes:
  • the second reset circuit provides the second initial voltage provided by the second initial voltage line to the control end of the drive circuit under the control of the reset control signal provided by the reset control line to control the Initialize the control end of the drive circuit.
  • an embodiment of the present disclosure also provides a display substrate, including a plurality of rows of Multiple columns of the above pixel circuit.
  • the display substrate includes a first initial voltage line, a reset control line, a scan line, a light emission control line, a second initial voltage line, a high voltage line and a data line;
  • the pixel circuit includes a drive circuit, a first reset circuit, a first node control circuit, a first lighting control circuit, a second reset circuit, a second lighting control circuit and a first reset circuit;
  • the first node control circuit includes a compensation circuit Control circuit and data writing circuit;
  • the first reset circuit includes a first transistor, the first lighting control circuit includes a second transistor, the data writing circuit includes a third transistor, the compensation control circuit includes a fourth transistor, and the second reset circuit including a fifth transistor, the second lighting control circuit including a sixth transistor, and the driving circuit including a driving transistor;
  • the first electrode of the first transistor is electrically connected to the first initial voltage line
  • the control electrode of the second transistor and the control electrode of the sixth transistor are both electrically connected to the light-emitting control line
  • the third transistor is electrically connected to the first initial voltage line
  • the control electrodes of the three transistors and the control electrode of the fourth transistor are both electrically connected to the scan line
  • the control level of the fifth transistor is electrically connected to the reset control line
  • the first electrode of the fifth transistor is electrically connected to the reset control line.
  • the second initial voltage line is electrically connected
  • the first pole of the sixth transistor is electrically connected to the high voltage line;
  • the first initial voltage line, the reset control line, the scan line, the light emission control line and the second initial voltage line extend along a first direction, and the high voltage line and the data line extend along a first direction. Extend in two directions;
  • the first initial voltage line, the reset control line, the scan line, the light emission control line and the second initial voltage line are arranged in sequence along the second direction; the first direction and the second direction intersect;
  • the fourth transistor, the second transistor and the first transistor are arranged in sequence along the second direction;
  • the fifth transistor and the driving transistor are arranged sequentially along the second direction;
  • the third transistor and the sixth transistor are arranged sequentially along the second direction;
  • the orthographic projection of the channel of the third transistor on the base substrate and the orthographic projection of the channel of the sixth transistor on the base substrate are arranged between the orthographic projection of the high voltage line on the base substrate and between the orthographic projections of the data lines on the base substrate;
  • the orthographic projection of the gate of the driving transistor on the base substrate is set between the orthographic projection of the scanning line on the base substrate and the orthographic projection of the light-emitting control line on the base substrate. between.
  • the pixel circuit also includes a first capacitor
  • the gate of the driving transistor is multiplexed as the first plate of the first capacitor; a plate of the first capacitor is formed on the first gate metal layer;
  • the second plate of the first capacitor is formed on the second gate metal layer
  • the orthographic projection of the high voltage line on the base substrate at least partially overlaps the orthographic projection of the second plate of the first capacitor on the base substrate.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • Figure 1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is a working timing diagram of at least one embodiment of the pixel circuit shown in Figure 5 of the present disclosure.
  • Figure 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 7 in the initialization stage of the present disclosure
  • Figure 9 is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 7 in the data writing stage of the present disclosure
  • Figure 10 is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 7 in the display stage of the present disclosure
  • Figure 11 is a layout diagram of the semiconductor layer in Figure 17;
  • Figure 12 is a layout diagram of the first gate metal layer in Figure 17;
  • Figure 13 is a layout diagram of the second gate metal layer in Figure 17;
  • Figure 14 is a layout diagram of the first source and drain metal layer in Figure 17;
  • Figure 15 is a layout diagram of the second source and drain metal layer in Figure 17;
  • Figure 16 is a layout diagram of the anode layer in Figure 17;
  • FIG. 17 is a layout diagram of at least one embodiment of the pixel circuit corresponding to FIG. 5 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, The control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit includes a driving circuit 11, a first reset circuit 12, a first node control circuit 13, a first light emitting control circuit 14 and a light emitting element E0;
  • the control end of the driving circuit 11 is electrically connected to the first node N1;
  • the first reset circuit 12 is electrically connected to the first node N1, the first initial voltage line I1 and the first pole of the light-emitting element E0 respectively, and is used to control the potential of the first node N1, Write the first initial voltage Vi1 provided by the first initial voltage line I1 into the first pole of the light-emitting element E0 to initialize the first pole of the light-emitting element E0 so that the light-emitting element E0 does not emit light. ;
  • the first node control circuit 13 is electrically connected to the data line DA, the first node N1, the first end of the driving circuit 11 and the second end of the driving circuit 11 respectively, for controlling the data line DA.
  • the data voltage provided by DA and the threshold voltage of the drive transistor included in the drive circuit 11 control the potential of the first node N1;
  • the first light-emitting control circuit 14 is electrically connected to the light-emitting control line E1, the second end of the driving circuit 11 and the first pole of the light-emitting element E0, respectively, for providing light-emitting control on the light-emitting control line E1. Under the control of the signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0;
  • the drive circuit 11 is electrically connected to the first node N1, and is used to generate a drive current under the control of the potential of the first node N1;
  • the second electrode of the light-emitting element E0 is electrically connected to the first voltage line V1.
  • the first voltage line may be a ground terminal or a low voltage line, but is not limited to this.
  • the display cycle includes a data writing phase and a display phase that are set successively;
  • the data line DA provides the data voltage Vdata
  • the first node control circuit 13 controls the potential of the first node N1 according to the data voltage Vdata and the threshold voltage of the driving transistor in the driving circuit 11;
  • the first reset circuit 12 controls the potential of the first node N1 to set the first initial voltage line I1 to the first voltage Vdata.
  • An initial voltage Vi1 The first pole of the light-emitting element E0 is written to initialize the first pole of the light-emitting element E0, and the light-emitting element E0 does not emit light.
  • the potential of the first node N1 is used as the voltage of the control drive circuit 11 and the first reset circuit 12 at the same time.
  • the first initial voltage line I1 The provided first initial voltage is continuously provided to the first pole of the light-emitting element E0 (the first pole of the light-emitting element E0 can be the anode), changing the original black screen display logic, switching the first initialization voltage to the black screen anode signal, It can avoid the phenomenon of weak bright spots and HBM bright spots in the black screen due to the characteristic deviation of the driving transistor included in the driving circuit 11, and provide the efficiency of switching the anode from high potential to low potential, reducing smearing and some afterimage phenomena.
  • This disclosure does not need to change the process quantity and accuracy, and can greatly improve the yield, reduce the HBM highlight phenomenon, and improve the image quality at the same time.
  • the first light-emitting control circuit 14 provides light-emitting control on the light-emitting control line E1
  • the second terminal of the control driving circuit 11 is connected to the first pole of the light-emitting element E0.
  • the driving circuit 11 Under the control of the potential of the control terminal, the driving circuit 11 generates a current to drive the light-emitting element E0.
  • the driving circuit 11 drives the light-emitting element E0 to emit light.
  • the characteristic deviation of the driving transistor often occurs, resulting in the phenomenon of weak bright spots and HBM bright spots in the black screen, as well as the smear phenomenon in the white text screen on the black background. These phenomena are due to the existence of the anode in the black screen state. Due to the potential, the short initialization time of the anode before the light-emitting stage will affect the quality of the black screen of the light-emitting element, causing the display panel to fail to darken quickly. This is because the black screen display logic of the related 7T1C pixel circuit is in the anode initialization stage before the light-emitting stage. After the anode is initialized, the anode is kept in a floating state. It is inevitable that other current factors will affect the anode potential.
  • the first node control circuit includes a data writing circuit 21 and a compensation control circuit 22 and energy storage circuit 23;
  • the data writing circuit 21 is electrically connected to the scanning line GA, the data line DA and the first end of the driving circuit 11 respectively, and is used to write the data line under the control of the scanning signal provided by the scanning line GA.
  • the data voltage Vdata provided by DA is written into the first terminal of the driving circuit 11;
  • the compensation control circuit 22 is electrically connected to the scan line GA, the control end of the drive circuit 11 and the second end of the drive circuit 11 respectively, and is used to control the drive under the control of the scan signal.
  • the control end of the circuit 11 is connected to the second end of the drive circuit 11;
  • the first end of the energy storage circuit 23 is electrically connected to the control end of the drive circuit 11, and the second end of the energy storage circuit 23 is electrically connected to the second voltage line V2.
  • the energy storage circuit 23 is to store the voltage of the first node N1.
  • the second voltage line may be a high voltage line, but is not limited thereto.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second reset circuit 31;
  • the second reset circuit 31 is electrically connected to the reset control line R1, the second initial voltage line I2 and the control terminal of the drive circuit 11 respectively, and is used for controlling the reset control signal provided by the reset control line R1.
  • the second initial voltage Vi2 provided by the second initial voltage line I2 is provided to the control end of the driving circuit 11 to initialize the control end of the driving circuit 11 .
  • the display cycle may also include an initialization stage set before the data writing stage; the pixel driving method further includes:
  • the second reset circuit 31 provides the second initial voltage Vi2 provided by the second initial voltage line I2 to the control of the driving circuit 11 under the control of the reset control signal provided by the reset control line R1. terminal to initialize the first node N1, so that at the beginning of the data writing phase, the driving circuit 11 can conduct the connection between its first terminal and the second terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second light emission control circuit 41;
  • the second light-emitting control circuit 41 is electrically connected to the light-emitting control line E1, the second voltage line V2 and the first end of the driving circuit 11, respectively, for controlling the light-emitting control signal provided by the light-emitting control line E1. , controlling the connection between the first end of the driving circuit 11 and the second voltage line V2.
  • the first reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first initial voltage line, and the second electrode of the first transistor is electrically connected to the light emitting The first pole of the component is electrically connected.
  • the driving circuit includes a driving transistor, and the first lighting control circuit includes a second transistor;
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the driving transistor is electrically connected to the first terminal of the driving circuit.
  • the second terminal is electrically connected;
  • the control electrode of the second transistor is electrically connected to the light-emitting control line
  • the first electrode of the second transistor is electrically connected to the second terminal of the drive circuit
  • the second electrode of the second transistor is electrically connected to the light-emitting control line.
  • the first electrode of the light-emitting element is electrically connected.
  • the data writing circuit includes a third transistor
  • the compensation control circuit includes a fourth transistor
  • the energy storage circuit includes a first capacitor
  • the control electrode of the third transistor is electrically connected to the scan line, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the first electrode of the drive circuit. terminal electrical connection;
  • the control electrode of the fourth transistor is electrically connected to the scan line, the first electrode of the fourth transistor is electrically connected to the control end of the drive circuit, and the second electrode of the fourth transistor is electrically connected to the drive circuit. The second end is electrically connected;
  • the first plate of the first capacitor is electrically connected to the control terminal of the drive circuit, and the second substrate of the first capacitor is electrically connected to the second voltage line.
  • the second reset circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the reset control line, the first electrode of the fifth transistor is electrically connected to the second initial voltage line, and the second electrode of the fifth transistor is electrically connected to the drive The control terminal of the circuit is electrically connected.
  • the second lighting control circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the The first terminal of the driving circuit is electrically connected.
  • the first reset circuit 12 includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first node N1, the source of the first transistor T1 is electrically connected to the first initial voltage line I1, and the drain of the first transistor T1 is electrically connected to the first node N1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the driving circuit 11 includes a driving transistor T0, and the first light emitting control circuit 14 includes a second transistor T2;
  • the gate of the driving transistor T0 is electrically connected to the first node N1;
  • the gate of the second transistor T2 is electrically connected to the light-emitting control line E1
  • the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0
  • the drain of the second transistor T0 is electrically connected to the light-emitting control line E1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the data writing circuit 21 includes a third transistor T3, the compensation control circuit 22 includes a fourth transistor T4; the energy storage circuit 23 includes a first capacitor C1;
  • the gate of the third transistor T3 is electrically connected to the scan line GA, the source of the third transistor T3 is electrically connected to the data line DA, and the drain of the third transistor T3 is electrically connected to the driving transistor.
  • the source of T0 is electrically connected;
  • the gate electrode of the fourth transistor T4 is electrically connected to the scan line GA, the source electrode of the fourth transistor T4 is electrically connected to the gate electrode of the driving transistor T0, and the drain electrode of the fourth transistor T4 is electrically connected to the gate electrode of the driving transistor T0.
  • the drain of the driving transistor T0 is electrically connected;
  • the first plate of the first capacitor C1 is electrically connected to the gate of the driving transistor T0.
  • the first capacitor C1 The second plate is electrically connected to the high voltage line VDD;
  • the second reset circuit 31 includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the reset control line R1, the source of the fifth transistor T5 is electrically connected to the second initial voltage line I2, and the drain of the fifth transistor T5 is electrically connected to the reset control line R1.
  • the gate of the driving transistor T0 is electrically connected;
  • the second light emission control circuit 41 includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the light-emitting control line E1
  • the source of the sixth transistor T6 is electrically connected to the high voltage line VDD
  • the drain of the sixth transistor T6 is electrically connected to the light-emitting control line E1.
  • the source of the driving transistor T0 is electrically connected;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage line VSS.
  • T1 and T5 are N-type transistors
  • T2, T3, T4, T6 and T0 are P-type transistors.
  • T1 and T5 may both be oxide transistors, and T2, T3, T4, T6, and T0 may all be LTPS (low temperature polysilicon) transistors.
  • the pixel shown in FIG. 5 The circuit is a LTPO (low temperature polycrystalline oxide) circuit but is not limited to this.
  • T1 and T5 can also be N-type transistors using other channel materials, and T1 and T5 can also be low-temperature polysilicon transistors like other transistors.
  • the display cycle may include an initialization phase S1, a data writing phase S2 and a display phase S3 that are set successively;
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • GA provides a high voltage signal.
  • T5 is turned on to initialize the potential of the first node N1
  • I2 provides a -5V voltage signal to the first node N1.
  • at least one embodiment of the present disclosure uses one less control object of a reset control signal, which has a certain effect on reducing PNL power consumption;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • GA provides a low voltage signal
  • VDD provides a 1V voltage signal.
  • T4 is turned on, and DA provides the data voltage Vdata.
  • the voltage of Vdata is greater than or equal to -2V and less than or equal to 1V
  • the threshold voltage of T0 is -2.5V.
  • T0 is turned on, and C1 is charged through Vdata.
  • the potential of N1 is greater than or equal to -4.5V and less than or equal to -1.5V, and T1 remains closed;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • GA provides a low voltage signal.
  • the voltage value of Vdata is 4V, keeping the potential of N1 at 1.5V.
  • I1 provides a -1V voltage signal
  • VDD is adjusted to output a 1V voltage signal so that T0 can work in the cut-off area; under a black screen, T1 is in a normally open state;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • GA provides a high voltage signal.
  • T2 and T6 are turned on, T0 drives O1 to emit light
  • T0 The driving current that drives O1 to emit light is K(Vdata-Vdd) 2 , where K is the current coefficient of T0, and Vdd is the voltage value of the high-voltage signal provided by VDD;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • GA provides a high voltage signal.
  • T1 is in the normally open state
  • T0 is in the closed state
  • I1 Provides a -1V voltage signal.
  • the anode potential of O1 is always maintained at -1V, which greatly reduces the risk of bright spots, while increasing the corresponding speed of the picture from bright to dark, and improving the picture quality.
  • VDD can provide a 1V voltage signal, but is not limited thereto.
  • the potential of the reset control signal When the reset control signal provided by R1 is a low voltage signal, the potential of the reset control signal may be -6V; when the reset control signal provided by R1 is a high voltage signal, the potential of the reset control signal may be 6V;
  • the potential of the scanning signal may be -6V; when the scanning signal provided by the GA is a high voltage signal, the potential of the scanning signal may be 6V.
  • the pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes a data writing stage and a display stage set successively; the pixel driving method includes:
  • the data line provides a data voltage
  • the first node control circuit controls the potential of the first node according to the data voltage and the threshold voltage of the driving transistor in the driving circuit
  • the first reset circuit writes the first initial voltage into the first pole of the light-emitting element under the control of the potential of the first node. , to initialize the first pole of the light-emitting element so that the light-emitting element does not emit light.
  • the potential of the first node serves as the voltage of the control drive circuit and the first reset circuit at the same time.
  • the first initial voltage line provides the first The initial voltage is continuously provided to the first electrode of the light-emitting element (the first electrode of the light-emitting element may be the anode), changing the original black screen
  • the display logic switches the first initialization voltage to the black screen anode signal, which can avoid the phenomenon of weak bright spots and HBM bright spots on the black screen due to the characteristic deviation of the drive transistor included in the drive circuit, and improve the efficiency of the anode switching from high potential to low potential. , reduce smear and partial afterimage phenomena.
  • the pixel driving method further includes: when the data voltage is not a data voltage corresponding to a black screen, during the display stage, the first light-emitting control circuit provides light-emitting control on the light-emitting control line. Under the control of the signal, the second terminal of the control driving circuit is connected to the first pole of the light-emitting element. Under the control of the potential of the control terminal, the driving circuit generates a current to drive the light-emitting element.
  • the pixel circuit also includes a second reset circuit;
  • the display cycle also includes an initialization stage set before the data writing stage;
  • the pixel driving method further includes:
  • the second reset circuit provides the second initial voltage provided by the second initial voltage line to the control end of the drive circuit under the control of the reset control signal provided by the reset control line to control the
  • the control end of the driving circuit is initialized, so that when the data writing phase starts, the driving circuit can conduct the connection between its first end and the second end.
  • the pixel circuit further includes a second light emission control circuit; the pixel driving method includes:
  • the second lighting control circuit controls the connection between the first end of the driving circuit and the second voltage line under the control of the lighting control signal.
  • the display substrate according to the embodiment of the present disclosure includes the above-mentioned multi-row and multi-column pixel circuits disposed on the base substrate.
  • Figures 11-17 are schematic diagrams of a single pixel circuit layout in which all transistors in the pixel circuit corresponding to Figure 5 are low-temperature polysilicon transistors.
  • the display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer that are sequentially stacked in a direction away from the base substrate. layer and anode layer.
  • the display substrate includes a plurality of first initial voltage lines, a plurality of reset control lines, a plurality of scan lines, a plurality of light emission control lines, a plurality of second initial voltage lines, a plurality of high voltage lines and multiple data lines;
  • the pixel circuit includes a drive circuit, a first reset circuit, a first node control circuit, a first light-emitting control circuit, a second reset circuit, a second light-emitting control circuit and a first reset circuit;
  • the first node control circuit includes a compensation control circuit and a data writing circuit;
  • the first reset circuit includes a first transistor, the first lighting control circuit includes a second transistor, the data writing circuit includes a third transistor, the compensation control circuit includes a fourth transistor, and the second reset circuit including a fifth transistor, the second lighting control circuit including a sixth transistor, and the driving circuit including a driving transistor;
  • the first electrode of the first transistor is electrically connected to the first initial voltage line
  • the control electrode of the second transistor and the control electrode of the sixth transistor are both electrically connected to the light-emitting control line
  • the third transistor is electrically connected to the first initial voltage line
  • the control electrodes of the three transistors and the control electrode of the fourth transistor are both electrically connected to the scan line
  • the control level of the fifth transistor is electrically connected to the reset control line
  • the first electrode of the fifth transistor is electrically connected to the reset control line.
  • the second initial voltage line is electrically connected
  • the first pole of the sixth transistor is electrically connected to the high voltage line;
  • the first initial voltage line, the reset control line, the scan line, the light emission control line and the second initial voltage line extend along a first direction, and the high voltage line and the data line extend along a first direction. Extend in two directions;
  • the first initial voltage line, the reset control line, the scan line, the light emission control line and the second initial voltage line are arranged in sequence along the second direction; the first direction and the second direction intersect;
  • the fourth transistor, the second transistor and the first transistor are arranged in sequence along the second direction;
  • the fifth transistor and the driving transistor are arranged sequentially along the second direction;
  • the third transistor and the sixth transistor are arranged sequentially along the second direction;
  • the orthographic projection of the channel of the third transistor on the base substrate and the orthographic projection of the channel of the sixth transistor on the base substrate are arranged between the orthographic projection of the high voltage line on the base substrate and between the orthographic projections of the data lines on the base substrate;
  • the orthographic projection of the gate of the driving transistor on the base substrate is set between the orthographic projection of the scanning line on the base substrate and the orthographic projection of the light-emitting control line on the base substrate. between.
  • control electrode may be a gate electrode, each of the transistors includes a gate electrode and an active layer, and the active layer includes a channel region, a source electrode and a drain electrode; the first transistor active layer, the active layer of the second transistor, the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor and the active layer of the sixth transistor.
  • the active layer is located on the semiconductor layer, and the gate electrode is located on the first gate metal layer.
  • the pixel circuit further includes a first capacitor
  • the gate of the driving transistor is multiplexed as the first plate of the first capacitor; a plate of the first capacitor is formed on the first gate metal layer;
  • the second plate of the first capacitor is formed on the second gate metal layer
  • the orthographic projection of the high voltage line on the base substrate at least partially overlaps the orthographic projection of the second plate of the first capacitor on the base substrate.
  • FIG. 11 is a layout diagram of the semiconductor layer in FIG. 17
  • FIG. 12 is a layout diagram of the first gate metal layer in FIG. 17
  • FIG. 13 is a layout diagram of the second gate metal layer in FIG. 17
  • FIG. 14 is a diagram of FIG. 17
  • the layout diagram of the first source-drain metal layer in Figure 15 is the layout diagram of the second source-drain metal layer in Figure 17
  • Figure 16 is the layout diagram of the anode layer in Figure 17
  • Figure 17 is FIG. 5 corresponds to a layout diagram of at least one embodiment of a pixel circuit.
  • the channel labeled A0 is the channel of T0
  • the channel labeled A1 is the channel of T1
  • the channel labeled A2 is the channel of T2
  • the channel labeled A3 is the channel of T3
  • the channel labeled A4 is the channel of T4.
  • the channel numbered A5 is the T5 channel
  • the A6 number is the T6 channel.
  • the line labeled R1 is the reset control line
  • the line labeled GA is the scan line
  • the line labeled E1 is the emission control line
  • the line labeled G0 is the gate of T0
  • the line labeled G1 is the gate of T1.
  • the one labeled G2 is the gate of T2
  • the one labeled G3 is the gate of T3
  • the one labeled G4 is the gate of T4
  • the one labeled G5 is the gate of T5
  • the one labeled G6 is the gate of T6 ;
  • G0 is reused as the first plate of C1.
  • the portion where the reset control line R1 overlaps with the semiconductor layer is the gate electrode G5 of the fifth transistor, and the portion where the scan line GA overlaps with the semiconductor layer is respectively the gate electrode G4 of the fourth transistor and the gate electrode of the third transistor.
  • the gate G3, the overlapping portions of the light emission control line E1 and the semiconductor layer are respectively the gate G2 of the second transistor and the gate G6 of the sixth transistor.
  • the line marked I1 is the first initial voltage line
  • the line marked I2 is the second initial voltage line
  • the line marked C1b is the second plate of C1.
  • VDD is the high voltage line
  • L1 is the first conductive connection part
  • L2 is the second conductive connection part
  • L3 is the third conductive connection part
  • L4 is the fourth conductive connection part.
  • the data line labeled DA is the data line.
  • the anode labeled AN is the anode of the organic light emitting diode.
  • the first initial voltage line I1, the second initial voltage line I2, the reset control line R1, the scan line GA and the light emission control line E1 all extend in the horizontal direction; VDD and DA extend in the vertical direction. ;
  • I1, R1, GA, E1 and I2 are arranged in sequence along the vertical direction;
  • T4, T2 and T1 are arranged in sequence along the vertical direction;
  • T5 and T0 are arranged in sequence along the vertical direction;
  • T3 and T6 are arranged in sequence along the vertical direction;
  • the orthographic projection of the channel of T3 on the base substrate and the orthographic projection of the channel of T6 on the base substrate are set in the orthographic projection of the high voltage line VDD on the base substrate and the orthographic projection of the data line DA on the base substrate. between orthographic projections;
  • the orthographic projection of the gate electrode G0 of T0 on the base substrate is disposed between the orthographic projection of the scan line GA on the base substrate and the orthographic projection of the light emission control line E1 on the base substrate.
  • the pixel circuit further includes a first capacitor
  • the gate electrode G0 of the driving transistor T0 is multiplexed as the first plate of the first capacitor;
  • the electrode plate is formed on the first gate metal layer;
  • the second plate C1b of the first capacitor is formed on the second gate metal layer
  • the orthographic projection of the high voltage line VDD on the base substrate at least partially overlaps the orthographic projection of the second plate C1b of the first capacitor on the base substrate to reduce the lateral occupation of the pixel circuit Space.
  • the one marked S5 is the source of T5
  • the one marked D5 is the drain of T5
  • the one marked S4 is the source of T4
  • the one marked D4 is the drain of T4
  • the one marked is S2 is the source of T2
  • D2 is the drain of T2
  • D1 is the drain of T1
  • S1 is the source of T1
  • S5 is the source of T5
  • D5 is the drain of T5
  • S3 is the source of T3
  • D3 is the drain of T3
  • D6 is the source of T6
  • D0 is the drain of T0;
  • S5 is electrically connected to I2 through the via hole
  • D5 is electrically connected to the first conductive connection part L1 through the via hole
  • the first conductive connection part L1 is connected to the gate of the driving transistor T0 through the via hole.
  • S4 is electrically connected to the second conductive connection part L2 through a via hole, and the second conductive connection part L2 is connected to the first conductive connection part L1;
  • D2 is electrically connected to the anode AN of O1 through the via hole; D2 is electrically connected to the third conductive connection part L3 through the via hole; the third conductive connection part L3 is electrically connected to D1 through the via hole, so that D1 and D2 are electrically connected;
  • S1 is electrically connected to the first initial voltage line I1 through the via hole;
  • G1 is electrically connected to the fourth conductive connection part L4 through the via hole, and
  • L4 is electrically connected to the gate electrode G0 of the driving transistor T0 through the via hole;
  • S3 is electrically connected to the data line DA through a via hole, and D3, D6 and S0 are connected;
  • S6 is electrically connected to the high-voltage line VDD through a via
  • the second plate C1b of C1 is electrically connected to the high-voltage line VDD through a via hole.
  • the display device includes the above-mentioned display substrate.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种像素电路、像素驱动方法、显示基板和显示装置。像素电路包括驱动电路(11)、第一复位电路(12)、第一节点控制电路(13)、第一发光控制电路(14)和发光元件(E0)；第一复位电路(12)在第一节点(N1)的电位的控制下，将第一初始电压(Vi1)写入发光元件(E0)的第一极；第一节点控制电路(13)根据数据电压(Vdata)和驱动电路(11)包括的驱动晶体管(T0)的阈值电压，控制第一节点(N1)的电位；第一发光控制电路(14)在发光控制信号的控制下，控制驱动电路(11)的第二端与发光元件(E0)的第一极之间连通；驱动电路(11)用于产生驱动电流。

Description

像素电路、像素驱动方法、显示基板和显示装置
相关申请的交叉引用
本申请主张在2022年8月30日在中国提交的中国专利申请号No.202211057035.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素驱动方法、显示基板和显示装置。
背景技术
现有的像素电路中常会由于驱动晶体管特性偏移出现黑画面弱亮点现象和HBM(High Brightness Model，高亮度模式)亮点现象，以及在黑底白字画面出现拖影现象，这些现象是由于在黑画面状态下阳极处仍存在电位所致。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括驱动电路、第一复位电路、第一节点控制电路、第一发光控制电路和发光元件；
所述驱动电路的控制端与第一节点电连接；
所述第一复位电路分别与所述第一节点、第一初始电压线和所述发光元件的第一极电连接，用于在所述第一节点的电位的控制下，将所述第一初始电压线提供的第一初始电压写入所述发光元件的第一极，以对所述发光元件的第一极进行初始化；
所述第一节点控制电路分别与数据线、所述第一节点、所述驱动电路的第一端和所述驱动电路的第二端电连接，用于根据所述数据线提供的数据电压和所述驱动电路包括的驱动晶体管的阈值电压，控制所述第一节点的电位；
所述第一发光控制电路分别与发光控制线、所述驱动电路的第二端与所述发光元件的第一极电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
所述驱动电路用于在所述第一节点的电位的控制下，产生驱动电流；
所述发光元件的第二极与第一电压线电连接。
可选的，所述第一节点控制电路包括数据写入电路、补偿控制电路和储能电路；
所述数据写入电路分别与扫描线、数据线和所述驱动电路的第一端电连接，用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端；
所述补偿控制电路分别与所述扫描线、所述驱动电路的控制端与所述驱动电路的第二端电连接，用于在所述扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述第二电压线电连接，所述储能电路用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括第二复位电路；
所述第二复位电路分别与复位控制线、第二初始电压线和所述驱动电路的控制端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第二初始电压线提供的第二初始电压提供至所述驱动电路的控制端，以对所述驱动电路的控制端进行初始化。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与发光控制线、第二电压线和所述驱动电路的第一端电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通；
所述第二发光控制电路包括第六晶体管；
所述第六晶体管的控制极与所述发光控制线电连接，所述第六晶体管的第一极与所述第二电压线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一初始电压线电连接，所述第一晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述驱动电路包括驱动晶体管，所述第一发光控制电路包括第二晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第二晶体管的控制极与所述发光控制线电连接，所述第二晶体管的第一极与所述驱动电路的第二端电连接，所述第二晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管；所 述储能电路包括第一电容；
所述第三晶体管的控制极与所述扫描线电连接，所述第三晶体管的第一极与所述数据线电连接，所述第三晶体管的第二极与所述驱动电路的第一端电连接；
所述第四晶体管的控制极与所述扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述驱动电路的第二端电连接；
所述第一电容的第一极板与所述驱动电路的控制端电连接，所述第一电容的第二极板与所述第二电压线电连接。
可选的，所述第二复位电路包括第五晶体管；
所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
在第二个方面中，本公开实施例还提供了一种像素驱动方法，应用于上述的像素电路，显示周期包括先后设置的数据写入阶段和显示阶段；所述像素驱动方法包括：
在数据写入阶段，数据线提供数据电压，第一节点控制电路根据所述数据电压与驱动电路中的驱动晶体管的阈值电压，控制第一节点的电位；
在所述显示阶段，当所述数据电压为对应于黑画面的数据电压时，第一复位电路在所述第一节点的电位的控制下，将第一初始电压写入发光元件的第一极，以对所述发光元件的第一极进行初始化。
可选的，所述像素驱动方法还包括：当所述数据电压不为对应于黑画面的数据电压时，在所述显示阶段，第一发光控制电路在发光控制线提供的发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路在其控制端的电位的控制下，产生驱动发光元件的电流；
所述像素电路还包括第二发光控制电路；所述像素驱动方法还包括：第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通。
可选的，所述像素电路还包括第二复位电路；显示周期还包括设置于数据写入阶段之前的初始化阶段；所述像素驱动方法还包括：
在所述初始化阶段，第二复位电路在复位控制线提供的复位控制信号的控制下，将所述第二初始电压线提供的第二初始电压提供至所述驱动电路的控制端，以对所述驱动电路的控制端进行初始化。
在第三个方面中，本公开实施例还提供一种显示基板，包括设置于衬底基板上的多行 多列上述的像素电路。
可选的，所述显示基板包括第一初始电压线、复位控制线、扫描线、发光控制线、第二初始电压线、高电压线和数据线；
所述像素电路包括驱动电路、第一复位电路、第一节点控制电路、第一发光控制电路、第二复位电路、第二发光控制电路和第一复位电路；所述第一节点控制电路包括补偿控制电路和数据写入电路；
所述第一复位电路包括第一晶体管，所述第一发光控制电路包括第二晶体管，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管，所述第二复位电路包括第五晶体管，所述第二发光控制电路包括第六晶体管，所述驱动电路包括驱动晶体管；
所述第一晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的控制极和所述第六晶体管的控制极都与所述发光控制线电连接，所述第三晶体管的控制极和所述第四晶体管的控制极都与所述扫描线电连接，所述第五晶体管的控制级与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第六晶体管的第一极与所述高电压线电连接；
所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第一方向延伸，所述高电压线与所述数据线沿第二方向延伸；
所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第二方向依次排列；所述第一方向与所述第二方向相交；
所述第四晶体管、所述第二晶体管和所述第一晶体管沿第二方向依次排列；
所述第五晶体管和所述驱动晶体管沿第二方向依次排列；
所述第三晶体管和所述第六晶体管沿第二方向依次排列；
所述第三晶体管的沟道在衬底基板上的正投影与所述第六晶体管的沟道在衬底基板上的正投影，设置于所述高电压线在衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间；
所述驱动晶体管的栅极在所述衬底基板上的正投影设置于所述扫描线在所述衬底基板上的正投影与所述发光控制线在所述衬底基板上的正投影之间。
可选的，所述像素电路还包括第一电容；
所述驱动晶体管的栅极复用为所述第一电容的第一极板；所述第一电容的一极板形成于第一栅金属层；
所述第一电容的第二极板形成于第二栅金属层；
所述高电压线在所述衬底基板上的正投影与所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的显示基板。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的电路图；
图6是本公开如图5所示的像素电路的至少一实施例的工作时序图；
图7是本公开至少一实施例所述的像素电路的电路图；
图8是本公开如图7所示的像素电路的至少一实施例在初始化阶段的工作状态示意图；
图9是本公开如图7所示的像素电路的至少一实施例在数据写入阶段的工作状态示意图；
图10是本公开如图7所示的像素电路的至少一实施例在显示阶段的工作状态示意图；
图11是图17中的半导体层的布局图；
图12是图17中的第一栅金属层的布局图；
图13是图17中的第二栅金属层的布局图；
图14是图17中的第一源漏金属层的布局图；
图15是图17中的第二源漏金属层的布局图；
图16是图17中的阳极层的布局图；
图17是图5对应的像素电路的至少一实施例的布局图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实 施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括驱动电路11、第一复位电路12、第一节点控制电路13、第一发光控制电路14和发光元件E0；
所述驱动电路11的控制端与第一节点N1电连接；
所述第一复位电路12分别与所述第一节点N1、第一初始电压线I1和所述发光元件E0的第一极电连接，用于在所述第一节点N1的电位的控制下，将所述第一初始电压线I1提供的第一初始电压Vi1写入所述发光元件E0的第一极，以对所述发光元件E0的第一极初始化，以使得所述发光元件E0不发光；
所述第一节点控制电路13分别与数据线DA、所述第一节点N1、所述驱动电路11的第一端和所述驱动电路11的第二端电连接，用于根据所述数据线DA提供的数据电压和所述驱动电路11包括的驱动晶体管的阈值电压，控制所述第一节点N1的电位；
所述第一发光控制电路14分别与发光控制线E1、所述驱动电路11的第二端与所述发光元件E0的第一极电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；
所述驱动电路11与所述第一节点N1电连接，用于在所述第一节点N1的电位的控制下，产生驱动电流；
所述发光元件E0的第二极与第一电压线V1电连接。
可选的，所述第一电压线可以为地端或低电压线，但不以此为限。
本公开实施例所述的像素电路在工作时，显示周期包括先后设置的数据写入阶段和显示阶段；
在数据写入阶段，数据线DA提供数据电压Vdata，第一节点控制电路13根据所述数据电压Vdata与驱动电路11中的驱动晶体管的阈值电压，控制第一节点N1的电位；
在所述显示阶段，当所述数据电压Vdata为对应于黑画面的数据电压时，第一复位电路12在所述第一节点N1的电位的控制下，将第一初始电压线I1提供的第一初始电压Vi1 写入发光元件E0的第一极，以对所述发光元件E0的第一极进行初始化，发光元件E0不发光。
本公开实施例所述的像素电路在工作时，第一节点N1的电位同时作为控制驱动电路11和第一复位电路12的电压，在黑画面显示Pattern(图案)下，第一初始电压线I1提供的第一初始电压持续提供至发光元件E0的第一极(所述发光元件E0的第一极可以为阳极)，改变原有黑画面显示逻辑，切换第一初始化电压为黑画面阳极信号，可以避免部分由于驱动电路11包括的驱动晶体管特性偏移出现的黑画面弱亮点与HBM亮点现象，并提供阳极自高电位切换至低电位的效率，减少拖影与部分残影现象。
本公开无需更改工艺数量与精度，既可以大大提升良率，降低HBM亮点现象，同时提升画质。
本公开实施例所述的像素电路在工作时，当所述数据电压不为对应于黑画面的数据电压时，在所述显示阶段，第一发光控制电路14在发光控制线E1提供的发光控制信号的控制下，控制驱动电路11的第二端与发光元件E0的第一极之间连通，驱动电路11在其控制端的电位的控制下，产生驱动发光元件E0的电流。
在具体实施时，当数据电压不是对应于黑画面的数据电压时，在显示阶段，由驱动电路11驱动发光元件E0发光。
在相关技术中，7T1C像素电路中常会出现驱动晶体管特性偏移出现黑画面弱亮点现象和HBM亮点现象，以及在黑底白字画面出现拖影现象，这些现象是由于在黑画面状态下阳极处存在电位所致，在发光阶段之前，对阳极初始化的时间短会影响到发光元件黑画面画质问题，出现显示面板无法迅速黑下来的现象。这是由于相关的7T1C像素电路的黑画面显示逻辑是在发光阶段之前的阳极初始化阶段，对阳极进行初始化后就让阳极保持为floating(浮空)状态，难免出现其他电流因素影响阳极电位。
在本公开至少一实施例中，如图2所示，在图1所示的像素电路的至少一实施例的基础上，所述第一节点控制电路包括数据写入电路21、补偿控制电路22和储能电路23；
所述数据写入电路21分别与扫描线GA、数据线DA和所述驱动电路11的第一端电连接，用于在所述扫描线GA提供的扫描信号的控制下，将所述数据线DA提供的数据电压Vdata写入所述驱动电路11的第一端；
所述补偿控制电路22分别与所述扫描线GA、所述驱动电路11的控制端与所述驱动电路11的第二端电连接，用于在所述扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
所述储能电路23的第一端与所述驱动电路11的控制端电连接，所述储能电路23的第二端与所述第二电压线V2电连接，所述储能电路23用于储存第一节点N1的电压。
可选的，所述第二电压线可以为高电压线，但不以此为限。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二复位电路31；
所述第二复位电路31分别与复位控制线R1、第二初始电压线I2和所述驱动电路11的控制端电连接，用于在所述复位控制线R1提供的复位控制信号的控制下，将所述第二初始电压线I2提供的第二初始电压Vi2提供至所述驱动电路11的控制端，以对所述驱动电路11的控制端进行初始化。
本公开如图3所示的像素电路的至少一实施例在工作时，显示周期还可以包括设置于数据写入阶段之前的初始化阶段；所述像素驱动方法还包括：
在所述初始化阶段，第二复位电路31在复位控制线R1提供的复位控制信号的控制下，将所述第二初始电压线I2提供的第二初始电压Vi2提供至所述驱动电路11的控制端，以对第一节点N1进行初始化，使得在所述数据写入阶段开始时，所述驱动电路11能够导通其第一端与第二端之间的连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二发光控制电路41；
所述第二发光控制电路41分别与发光控制线E1、第二电压线V2和所述驱动电路11的第一端电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述驱动电路11的第一端与所述第二电压线V2之间连通。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一初始电压线电连接，所述第一晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述驱动电路包括驱动晶体管，所述第一发光控制电路包括第二晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第二晶体管的控制极与所述发光控制线电连接，所述第二晶体管的第一极与所述驱动电路的第二端电连接，所述第二晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管；所述储能电路包括第一电容；
所述第三晶体管的控制极与所述扫描线电连接，所述第三晶体管的第一极与所述数据线电连接，所述第三晶体管的第二极与所述驱动电路的第一端电连接；
所述第四晶体管的控制极与所述扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述驱动电路的第二端电连接；
所述第一电容的第一极板与所述驱动电路的控制端电连接，所述第一电容的第二基板与所述第二电压线电连接。
可选的，所述第二复位电路包括第五晶体管；
所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第二发光控制电路包括第六晶体管；
所述第六晶体管的控制极与所述发光控制线电连接，所述第六晶体管的第一极与所述所述第二电压线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接。
如图5所示，在图4所示的像素电路的至少一实施例的基础上，所述第一复位电路12包括第一晶体管T1；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与所述第一节点N1电连接，所述第一晶体管T1的源极与所述第一初始电压线I1电连接，所述第一晶体管T1的漏极与所述有机发光二极管O1的阳极电连接；
所述驱动电路11包括驱动晶体管T0，所述第一发光控制电路14包括第二晶体管T2；
所述驱动晶体管T0的栅极与所述第一节点N1电连接；
所述第二晶体管T2的栅极与所述发光控制线E1电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接，所述第二晶体管T0的漏极与所述有机发光二极管O1的阳极电连接；
所述数据写入电路21包括第三晶体管T3，所述补偿控制电路22包括第四晶体管T4；所述储能电路23包括第一电容C1；
所述第三晶体管T3的栅极与所述扫描线GA电连接，所述第三晶体管T3的源极与所述数据线DA电连接，所述第三晶体管T3的漏极与所述驱动晶体管T0的源极电连接；
所述第四晶体管T4的栅极与所述扫描线GA电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的栅极电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的漏极电连接；
所述第一电容C1的第一极板与所述驱动晶体管T0的栅极电连接，所述第一电容C1 的第二极板与高电压线VDD电连接；
所述第二复位电路31包括第五晶体管T5；
所述第五晶体管T5的栅极与所述复位控制线R1电连接，所述第五晶体管T5的源极与所述第二初始电压线I2电连接，所述第五晶体管T5的漏极与所述驱动晶体管T0的栅极电连接；
所述第二发光控制电路41包括第六晶体管T6；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的源极与所述所述高电压线VDD电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的源极电连接；
所述有机发光二极管O1的阴极与低电压线VSS电连接。
在图5所示的至少一实施例中，T1和T5为N型晶体管，T2、T3、T4、T6和T0为P型晶体管。
在图5所示的至少一实施例中，T1和T5可以都为氧化物晶体管，T2、T3、T4、T6和T0可以都为LTPS(低温多晶硅)晶体管，此时，图5所示的像素电路为LTPO(低温多晶氧化物)电路但不以此为限。在实际操作时，T1和T5也可以为使用其他沟道材料的N型晶体管，T1和T5也可以与其他晶体管一样是低温多晶硅晶体管。
如图6所示，本公开如图5所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、数据写入阶段S2和显示阶段S3；
在初始化阶段S1，E1提供高电压信号，R1提供高电压信号，GA提供高电压信号，如图7所示，T5打开，对第一节点N1的电位进行初始化，I2提供-5V电压信号至第一节点N1；若上一帧画面为黑画面，则在数据写入阶段S2无需对O1的阳极进行初始化；若上一帧画面为亮起状态，当前帧画面为黑画面则在数据写入阶段S2控制T1开启，本公开至少一实施例与相关技术相比减少采用了一个复位控制信号的控制对象，对PNL功耗有一定降低作用；
在数据写入阶段S2，E1提供高电压信号，R1提供低电压信号，GA提供低电压信号，VDD提供1V电压信号，如图8所示，T4打开，DA提供数据电压Vdata，在当前帧画面不为黑画面时，Vdata的电压在大于等于-2V而小于等于1V，而T0的阈值电压为-2.5V，则在数据写入阶段S2开始时，T0导通，通过Vdata为C1充电，以提升N1的电位，直至N1的电位变为Vdata+Vth，此时N1的电位大于等于-4.5V而小于等于-1.5V，T1保持关闭状态；
在数据写入阶段S2，E1提供高电压信号，R1提供低电压信号，GA提供低电压信号，在当前帧画面为黑画面时，Vdata的电压值为4V，使得N1的电位保持在1.5V，I1提供-1V电压信号，同时VDD调整为输出1V电压信号，以使得T0可以工作于截止区；在黑画面下，T1为常开状态；
在显示阶段S3，E1提供低电压信号，R1提供低电压信号，GA提供高电压信号，在当前帧画面不为黑画面时，如图9所示，T2和T6打开，T0驱动O1发光，T0驱动O1发光的驱动电流为K(Vdata-Vdd)2，其中，K为T0的电流系数，Vdd为VDD提供的高电压信号的电压值；
在显示阶段S3，E1提供低电压信号，R1提供低电压信号，GA提供高电压信号，在当前帧画面为黑画面时，如图10所示，T1处于常开状态，T0为关闭状态，I1提供-1V电压信号，此时O1的阳极电位始终保持为-1V，大大降低了亮点风险，同时提升了画面由亮到暗的相应速度，提升了画质。
在本公开至少一实施例中，VDD可以提供1V电压信号，但不以此为限。
在图6中，当E1提供的发光控制信号为低电压信号时，所述发光控制信号的电位可以为-6V；当E1提供的发光控制信号为高电压信号时，所述发光控制信号的电位可以为6V；
当R1提供的复位控制信号为低电压信号时，所述复位控制信号的电位可以为-6V；当R1提供的复位控制信号为高电压信号时，所述复位控制信号的电位可以为6V；
当GA提供的扫描信号为低电压信号时，所述扫描信号的电位可以为-6V；当GA提供的扫描信号为高电压信号时，所述扫描信号的电位可以为6V。
本公开实施例所述的像素驱动方法，应用于上述的像素电路，显示周期包括先后设置的数据写入阶段和显示阶段；所述像素驱动方法包括：
在数据写入阶段，数据线提供数据电压，第一节点控制电路根据所述数据电压与驱动电路中的驱动晶体管的阈值电压，控制第一节点的电位；
在所述显示阶段，当所述数据电压为对应于黑画面的数据电压时，第一复位电路在所述第一节点的电位的控制下，将第一初始电压写入发光元件的第一极，以对所述发光元件的第一极进行初始化，以使得所述发光元件不发光。
在本公开实施例所述的像素驱动方法中，第一节点的电位同时作为控制驱动电路和第一复位电路的电压，在黑画面显示Pattern(图案)下，第一初始电压线提供的第一初始电压持续提供至发光元件的第一极(所述发光元件的第一极可以为阳极)，改变原有黑画面 显示逻辑，切换第一初始化电压为黑画面阳极信号，可以避免部分由于驱动电路包括的驱动晶体管特性偏移出现的黑画面弱亮点与HBM亮点现象，并提供阳极自高电位切换至低电位的效率，减少拖影与部分残影现象。
在本公开实施例中，所述像素驱动方法还包括：当所述数据电压不为对应于黑画面的数据电压时，在所述显示阶段，第一发光控制电路在发光控制线提供的发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路在其控制端的电位的控制下，产生驱动发光元件的电流。
可选的，所述像素电路还包括第二复位电路；显示周期还包括设置于数据写入阶段之前的初始化阶段；所述像素驱动方法还包括：
在所述初始化阶段，第二复位电路在复位控制线提供的复位控制信号的控制下，将所述第二初始电压线提供的第二初始电压提供至所述驱动电路的控制端，以对所述驱动电路的控制端进行初始化，使得在所述数据写入阶段开始时，所述驱动电路能够导通其第一端与第二端之间的连接。
在本公开至少一实施例中，所述像素电路还包括第二发光控制电路；所述像素驱动方法包括：
第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通。
本公开实施例所述的显示基板包括设置于衬底基板上的上述的多行多列像素电路。
图11-17为图5对应的像素电路中所有晶体管均为低温多晶硅晶体管的单个像素电路布局示意图。在本公开至少一实施例中，显示基板包括沿远离衬底基板的方向依次层叠设置的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层、第二源漏金属层和阳极层。
在本公开至少一实施例中，所述显示基板包括多条第一初始电压线、多条复位控制线、多条扫描线、多条发光控制线、多条第二初始电压线、多条高电压线和多条数据线；所述像素电路包括驱动电路、第一复位电路、第一节点控制电路、第一发光控制电路、第二复位电路、第二发光控制电路和第一复位电路；所述第一节点控制电路包括补偿控制电路和数据写入电路；
所述第一复位电路包括第一晶体管，所述第一发光控制电路包括第二晶体管，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管，所述第二复位电路包括第五晶体管，所述第二发光控制电路包括第六晶体管，所述驱动电路包括驱动晶体管；
所述第一晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的控制极和所述第六晶体管的控制极都与所述发光控制线电连接，所述第三晶体管的控制极和所述第四晶体管的控制极都与所述扫描线电连接，所述第五晶体管的控制级与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第六晶体管的第一极与所述高电压线电连接；
所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第一方向延伸，所述高电压线与所述数据线沿第二方向延伸；
所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第二方向依次排列；所述第一方向与所述第二方向相交；
所述第四晶体管、所述第二晶体管和所述第一晶体管沿第二方向依次排列；
所述第五晶体管和所述驱动晶体管沿第二方向依次排列；
所述第三晶体管和所述第六晶体管沿第二方向依次排列；
所述第三晶体管的沟道在衬底基板上的正投影与所述第六晶体管的沟道在衬底基板上的正投影，设置于所述高电压线在衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间；
所述驱动晶体管的栅极在所述衬底基板上的正投影设置于所述扫描线在所述衬底基板上的正投影与所述发光控制线在所述衬底基板上的正投影之间。
在本公开至少一实施例中，所述控制极可以为栅极，各所述晶体管包括栅极和有源层，有源层包括沟道区、源极和漏极；所述第一晶体管的有源层、所述第二晶体管的有源层、所述第三晶体管的有源层、所述第四晶体管的有源层、所述第五晶体管的有源层和所述第六晶体管的有源层位于所述半导体层，所述栅极位于第一栅金属层。
在本公开至少一实施例中，所述像素电路还包括第一电容；
所述驱动晶体管的栅极复用为所述第一电容的第一极板；所述第一电容的一极板形成于第一栅金属层；
所述第一电容的第二极板形成于第二栅金属层；
所述高电压线在所述衬底基板上的正投影与所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠。
图11是图17中的半导体层的布局图，图12是图17中的第一栅金属层的布局图，图13是图17中的第二栅金属层的布局图，图14是图17中的第一源漏金属层的布局图，图15是图17中的第二源漏金属层的布局图，图16是图17中的阳极层的布局图，图17是 图5对应的像素电路的至少一实施例的布局图。
在图11中，标号为A0的为T0的沟道，标号为A1的为T1的沟道，标号为A2的为T2的沟道，A3的为T3的沟道，标号为A4的为T4的沟道，标号为A5的为T5的沟道，A6的为T6的沟道。
在图12中，标号为R1的为复位控制线，标号为GA的为扫描线，标号为E1的为发光控制线，标号为G0的为T0的栅极，标号为G1的为T1的栅极，标号为G2的为T2的栅极，标号为G3的为T3的栅极，标号为G4的为T4的栅极，标号为G5的为T5的栅极，标号为G6的为T6的栅极；
G0复用为C1的第一极板。
如图12所示，复位控制线R1与半导体层交叠的部分为第五晶体管的栅极G5，扫描线GA与半导体层交叠的部分分别为第四晶体管的栅极G4、第三晶体管的栅极G3，发光控制线E1与半导体层交叠的部分分别为第二晶体管的栅极G2、第六晶体管的栅极G6。
在图13中，标号为I1的为第一初始电压线，标号为I2的第二初始电压线，标号为C1b的为C1的第二极板。
在图14中，标号为VDD的为高电压线，标号为L1的为第一导电连接部，标号为L2的为第二导电连接部，标号为L3的为第三导电连接部，标号为L4的为第四导电连接部。
在图15中，标号为DA的为数据线。
在图16中，标号为AN的为有机发光二极管的阳极。
如图11至图17所示，第一初始电压线I1、第二初始电压线I2、复位控制线R1、扫描线GA和发光控制线E1都沿水平方向延伸；VDD和DA沿竖直方向延伸；
I1、R1、GA、E1和I2沿竖直方向依次排列；
T4、T2和T1沿竖直方向依次排列；
T5和T0沿竖直方向依次排列；
T3和T6沿竖直方向依次排列；
T3的沟道在衬底基板上的正投影与T6的沟道在衬底基板上的正投影，设置于高电压线VDD在衬底基板上的正投影与数据线DA在衬底基板上的正投影之间；
T0的栅极G0在衬底基板上的正投影设置于所述扫描线GA在所述衬底基板上的正投影与所述发光控制线E1在所述衬底基板上的正投影之间。
在本公开至少一实施例中，所述像素电路还包括第一电容；
所述驱动晶体管T0的栅极G0复用为所述第一电容的第一极板；所述第一电容的一 极板形成于第一栅金属层；
所述第一电容的第二极板C1b形成于第二栅金属层；
所述高电压线VDD在所述衬底基板上的正投影与所述第一电容的第二极板C1b在所述衬底基板上的正投影至少部分重叠，以减少所述像素电路横向占用的空间。
在图11和图17中，标号为S5的为T5的源极，标号为D5的为T5的漏极，标号为S4的为T4的源极，标号为D4的为T4的漏极，标号为S2的为T2的源极，标号为D2的为T2的漏极，标号为D1的为T1的漏极，标号为S1的为T1的源极，标号为S5的为T5的源极，标号为D5的为T5的漏极，标号为S3的为T3的源极，标号为D3的为T3的漏极，标号为D6的为T6的源极，标号为S6的为T6的源极；标号为D0的为T0的漏极；
在图11中，标号为S0的为T0的源极；
如图11-图17所示，S5通过过孔与I2电连接，D5通过过孔与第一导电连接部L1电连接，所述第一导电连接部L1通过过孔与驱动晶体管T0的栅极G0电连接；
S4通过过孔与第二导电连接部L2电连接，所述第二导电连接部L2与第一导电连接部L1连通；
D4、S2和D0相互连通；
D2通过过孔与O1的阳极AN电连接；D2通过过孔与第三导电连接部L3电连接；所述第三导电连接部L3通过过孔与D1电连接，以使得D1和D2电连接；
S1通过过孔与第一初始电压线I1电连接；G1通过过孔与第四导电连接部L4电连接，L4通过过孔与驱动晶体管T0的栅极G0电连接；
S3通过过孔与数据线DA电连接，D3、D6和S0连通；
S6通过过孔与高电压线VDD电连接；
C1的第二极板C1b通过过孔与高电压线VDD电连接。
本公开实施例所述的显示装置包括上述的显示基板。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种像素电路，包括驱动电路、第一复位电路、第一节点控制电路、第一发光控制电路和发光元件；
    所述驱动电路的控制端与第一节点电连接；
    所述第一复位电路分别与所述第一节点、第一初始电压线和所述发光元件的第一极电连接，用于在所述第一节点的电位的控制下，将所述第一初始电压线提供的第一初始电压写入所述发光元件的第一极，以对所述发光元件的第一极进行初始化；
    所述第一节点控制电路分别与数据线、所述第一节点、所述驱动电路的第一端和所述驱动电路的第二端电连接，用于根据所述数据线提供的数据电压和所述驱动电路包括的驱动晶体管的阈值电压，控制所述第一节点的电位；
    所述第一发光控制电路分别与发光控制线、所述驱动电路的第二端与所述发光元件的第一极电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
    所述驱动电路用于在所述第一节点的电位的控制下，产生驱动电流；
    所述发光元件的第二极与第一电压线电连接。
  2. 如权利要求1所述的像素电路，其中，所述第一节点控制电路包括数据写入电路、补偿控制电路和储能电路；
    所述数据写入电路分别与扫描线、数据线和所述驱动电路的第一端电连接，用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端；
    所述补偿控制电路分别与所述扫描线、所述驱动电路的控制端与所述驱动电路的第二端电连接，用于在所述扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述第二电压线电连接，所述储能电路用于储存电能。
  3. 如权利要求1所述的像素电路，其中，还包括第二复位电路；
    所述第二复位电路分别与复位控制线、第二初始电压线和所述驱动电路的控制端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第二初始电压线提供的 第二初始电压提供至所述驱动电路的控制端。
  4. 如权利要求1所述的像素电路，其中，还包括第二发光控制电路；
    所述第二发光控制电路分别与发光控制线、第二电压线和所述驱动电路的第一端电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通；
    所述第二发光控制电路包括第六晶体管；
    所述第六晶体管的控制极与所述发光控制线电连接，所述第六晶体管的第一极与所述所述第二电压线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接。
  5. 如权利要求1所述的像素电路，其中，所述第一复位电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一初始电压线电连接，所述第一晶体管的第二极与所述发光元件的第一极电连接。
  6. 如权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述第一发光控制电路包括第二晶体管；
    所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
    所述第二晶体管的控制极与所述发光控制线电连接，所述第二晶体管的第一极与所述驱动电路的第二端电连接，所述第二晶体管的第二极与所述发光元件的第一极电连接。
  7. 如权利要求2所述的像素电路，其中，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管；所述储能电路包括第一电容；
    所述第三晶体管的控制极与所述扫描线电连接，所述第三晶体管的第一极与所述数据线电连接，所述第三晶体管的第二极与所述驱动电路的第一端电连接；
    所述第四晶体管的控制极与所述扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述驱动电路的第二端电连接；
    所述第一电容的第一极板与所述驱动电路的控制端电连接，所述第一电容的第二极板与所述第二电压线电连接。
  8. 如权利要求3所述的像素电路，其中，所述第二复位电路包括第五晶体管；
    所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
  9. 一种像素驱动方法，应用于如权利要求1至8中任一权利要求所述的像素电路， 显示周期包括先后设置的数据写入阶段和显示阶段；所述像素驱动方法包括：
    在数据写入阶段，数据线提供数据电压，第一节点控制电路根据所述数据电压与驱动电路中的驱动晶体管的阈值电压，控制第一节点的电位；
    在所述显示阶段，当所述数据电压为对应于黑画面的数据电压时，第一复位电路在所述第一节点的电位的控制下，将第一初始电压写入发光元件的第一极，以对所述发光元件的第一极进行初始化。
  10. 如权利要求9所述的像素驱动方法，其中，所述像素驱动方法还包括：当所述数据电压不为对应于黑画面的数据电压时，在所述显示阶段，第一发光控制电路在发光控制线提供的发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路在其控制端的电位的控制下，产生驱动发光元件的电流；
    所述像素电路还包括第二发光控制电路；所述像素驱动方法还包括：第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通。
  11. 如权利要求9或10所述的像素驱动方法，其中，所述像素电路还包括第二复位电路；显示周期还包括设置于数据写入阶段之前的初始化阶段；所述像素驱动方法还包括：
    在所述初始化阶段，第二复位电路在复位控制线提供的复位控制信号的控制下，将所述第二初始电压线提供的第二初始电压提供至所述驱动电路的控制端，以对所述驱动电路的控制端进行初始化。
  12. 一种显示基板，包括设置于衬底基板上的多行多列如权利要求1至8中任一权利要求所述的像素电路。
  13. 如权利要求12所述的显示基板，其中，所述显示基板包括第一初始电压线、复位控制线、扫描线、发光控制线、第二初始电压线、高电压线和数据线；
    所述像素电路包括驱动电路、第一复位电路、第一节点控制电路、第一发光控制电路、第二复位电路、第二发光控制电路和第一复位电路；所述第一节点控制电路包括补偿控制电路和数据写入电路；
    所述第一复位电路包括第一晶体管，所述第一发光控制电路包括第二晶体管，所述数据写入电路包括第三晶体管，所述补偿控制电路包括第四晶体管，所述第二复位电路包括第五晶体管，所述第二发光控制电路包括第六晶体管，所述驱动电路包括驱动晶体管；
    所述第一晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的控制极和所述第六晶体管的控制极都与所述发光控制线电连接，所述第三晶体管的控制极和所述第 四晶体管的控制极都与所述扫描线电连接，所述第五晶体管的控制级与所述复位控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第六晶体管的第一极与所述高电压线电连接；
    所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第一方向延伸，所述高电压线与所述数据线沿第二方向延伸；
    所述第一初始电压线、所述复位控制线、所述扫描线、所述发光控制线和所述第二初始电压线沿第二方向依次排列；所述第一方向与所述第二方向相交；
    所述第四晶体管、所述第二晶体管和所述第一晶体管沿第二方向依次排列；
    所述第五晶体管和所述驱动晶体管沿第二方向依次排列；
    所述第三晶体管和所述第六晶体管沿第二方向依次排列；
    所述第三晶体管的沟道在衬底基板上的正投影与所述第六晶体管的沟道在衬底基板上的正投影，设置于所述高电压线在衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间；
    所述驱动晶体管的栅极在所述衬底基板上的正投影设置于所述扫描线在所述衬底基板上的正投影与所述发光控制线在所述衬底基板上的正投影之间。
  14. 如权利要求13所述的显示基板，其中，所述像素电路还包括第一电容；
    所述驱动晶体管的栅极复用为所述第一电容的第一极板；所述第一电容的一极板形成于第一栅金属层；
    所述第一电容的第二极板形成于第二栅金属层；
    所述高电压线在所述衬底基板上的正投影与所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠。
  15. 一种显示装置，包括如权利要求12至14中任一权利要求所述的显示基板。
PCT/CN2023/111905 2022-08-30 2023-08-09 像素电路、像素驱动方法、显示基板和显示装置 WO2024046066A1 (zh)

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