WO2023005597A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2023005597A1
WO2023005597A1 PCT/CN2022/103292 CN2022103292W WO2023005597A1 WO 2023005597 A1 WO2023005597 A1 WO 2023005597A1 CN 2022103292 W CN2022103292 W CN 2022103292W WO 2023005597 A1 WO2023005597 A1 WO 2023005597A1
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Prior art keywords
transistor
subcircuit
circuit
pole
sub
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PCT/CN2022/103292
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English (en)
French (fr)
Inventor
施昆雁
陈亚菲
王刚
付强
宋二龙
张锴
徐鹏
蔡兴瑞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US18/278,706 priority Critical patent/US20240135885A1/en
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023005597A1 publication Critical patent/WO2023005597A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a pixel driving circuit and a display panel.
  • AMOLED Active matrix organic electrode light emitting diode display panel
  • OLED Organic Light-Emitting Diode
  • AMOLED can emit light by driving a thin-film transistor to generate a driving current in a saturated state, and the driving current drives the light-emitting device to emit light.
  • the present invention aims to solve at least one of the technical problems in the prior art, and provides a pixel driving circuit and a display panel.
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes: a data writing subcircuit, a threshold compensation subcircuit, a driving subcircuit, and a storage subcircuit; wherein,
  • the data writing sub-circuit includes a fourth transistor, the first pole of the fourth transistor is connected to the data line, the second pole is connected to the first end of the driving sub-circuit, and the control pole is connected to the first scanning line; the fourth transistor Oxide thin film transistors are used;
  • a threshold compensation subcircuit configured to compensate the threshold voltage of the driving subcircuit in response to a second scan signal
  • the storage sub-circuit is configured to store the data voltage signal
  • the driving sub-circuit is configured to provide a driving current for the light emitting device to be driven according to the voltages of the first terminal and the control terminal.
  • the pixel driving circuit further includes: a first reset subcircuit and a second reset subcircuit;
  • the first reset subcircuit is configured to respond to a first reset signal, and reset the voltage of the control terminal of the driving subcircuit through a first initialization signal;
  • the second reset subcircuit is configured to respond to a second reset signal and reset the first pole of the light emitting device to be driven through a second initialization signal.
  • the first reset subcircuit includes a first transistor; the second reset subcircuit includes a seventh transistor;
  • the first pole of the first transistor is connected to the first initialization signal terminal, the second pole is connected to the control terminal of the driving sub-circuit, and the control pole is connected to the first reset signal terminal;
  • the first pole of the seventh transistor is connected to the first pole of the light-emitting device to be driven, the second pole is connected to the second initialization signal terminal, and the control pole is connected to the second reset signal terminal.
  • the first transistor is an oxide thin film transistor.
  • the pixel driving circuit further includes: a first light emission control subcircuit and a second light emission control subcircuit;
  • the first light emission control subcircuit is configured to control whether a first voltage can be written into the first terminal of the driving subcircuit in response to a first light emission control signal;
  • the second light emission control subcircuit is configured to switch on or off the connection between the driving subcircuit and the light emitting device to be driven in response to a second light emission control signal.
  • the first light emission control subcircuit includes: a fifth transistor; the second light emission control subcircuit includes: a sixth transistor;
  • the first pole of the fifth transistor is connected to the first power supply terminal, the second pole is connected to the first terminal of the driving sub-circuit, and the control pole is connected to the first enabling signal terminal;
  • the first pole of the sixth control transistor is connected to the second terminal of the driving sub-circuit, the second pole is connected to the first pole of the light emitting device to be driven, and the control pole is connected to the second enabling signal terminal.
  • the pixel driving circuit further includes: a data voltage supply sub-circuit;
  • the data voltage supply subcircuit is configured to write a first voltage to the data line during the initialization phase, so that the data writing subcircuit transmits to the first terminal of the driving subcircuit; the first voltage is greater than or It is equal to the data voltage corresponding to the maximum brightness value that the light emitting device can display; or, the first voltage is greater than or equal to the data voltage corresponding to the minimum brightness value that the light emitting device can display.
  • the pixel driving circuit further includes: an auxiliary sub-circuit
  • the auxiliary sub-circuit is configured to reduce the leakage current of the fourth transistor under the control of the third scan signal.
  • the auxiliary subcircuit includes: an eighth transistor;
  • the first pole of the eighth transistor is connected to the data line
  • the second pole is connected to the first pole of the fourth transistor
  • the control pole is connected to the third scanning line.
  • the pixel driving circuit further includes: a first scanning control subcircuit and a second scanning control subcircuit:
  • the first scan control subcircuit is configured to provide the first scan signal to the fourth transistor during the data writing and threshold compensation stages;
  • the second scan control subcircuit is configured to provide the threshold compensation subcircuit with the second scan signal during the data writing and threshold compensation phases;
  • the start time of the first scan signal is earlier than the start time of the second scan signal; the end time of the first scan signal is the same as the end time of the second scan signal.
  • the duration of the first scanning signal is 1.2 to 2.0 times the duration of the second scanning signal.
  • the driving sub-circuit includes: a third transistor
  • the first pole of the second drive transistor is connected to the second pole of the fourth transistor, the second pole is connected to the second terminal of the threshold compensation subcircuit, and the control pole is connected to the first terminal of the threshold compensation subcircuit.
  • the threshold compensation subcircuit includes a second transistor
  • the first pole of the second transistor is connected to the control terminal of the driving sub-circuit, the second pole is connected to the second terminal of the driving sub-circuit, and the control pole is connected to the second scanning line.
  • the second transistor is an oxide thin film transistor.
  • the storage sub-circuit includes a storage capacitor
  • the first end of the storage capacitor is connected to the first power supply end, and the second end is connected to the control end of the driving sub-circuit.
  • an embodiment of the present disclosure provides a display panel, which includes any pixel driving circuit described above.
  • FIG. 1 is a schematic diagram of an exemplary display substrate structure.
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit.
  • FIG. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 6 is a working timing diagram of the pixel driving circuit shown in FIG. 5 .
  • FIG. 7 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 8 is a working timing diagram of the pixel driving circuit shown in FIG. 7 .
  • FIG. 9 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 10 is a working timing diagram of the pixel driving circuit shown in FIG. 9 .
  • Fig. 1 is a schematic structural diagram of an exemplary display substrate
  • Fig. 2 is a schematic diagram of an exemplary pixel driving circuit
  • the display substrate includes a plurality of pixel units arranged in an array, each Each pixel unit 100 includes a pixel driving circuit and a light emitting device OLED.
  • the pixel driving circuit in each pixel unit 100 may include: a first reset subcircuit 2, a threshold compensation subcircuit 81, a driving subcircuit 1, a data writing subcircuit 14, a first light emission control subcircuit 51, a second light emission control subcircuit The circuit 52 , the second reset sub-circuit 4 and the storage sub-circuit 6 .
  • the first reset subcircuit 2 is connected to the control terminal of the driving subcircuit 1 and is configured to reset the control terminal of the driving subcircuit 1 under the control of the first reset signal.
  • the threshold compensation sub-circuit 8 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 1 , and is configured to perform threshold compensation on the driving sub-circuit 1 .
  • the data writing sub-circuit 14 is electrically connected to the first end of the driving sub-circuit 1 and is configured to write data signals into the storage sub-circuit under the control of the scanning signal.
  • the storage sub-circuit 8 is respectively electrically connected to the control terminal of the driving sub-circuit 1 and the first power supply terminal VDD, and is configured to store data signals.
  • the first light emission control sub-circuit 51 is respectively connected to the first power supply terminal VDD and the first terminal of the driving sub-circuit 1, and is configured to realize the connection on or off between the driving sub-circuit 1 and the first power supply terminal VDD.
  • the two light emission control sub-circuits 52 are respectively electrically connected to the second end of the driving sub-circuit 1 and the first pole of the light-emitting device OLED, and are configured to realize the connection between the driving sub-circuit 1 and the light-emitting device OLED.
  • the second reset subcircuit 4 is electrically connected to the first pole of the light emitting device OLED, and is configured to reset the control terminal of the driving subcircuit 1 and the first pole of the light emitting device OLED under the control of the second reset control signal.
  • the first reset subcircuit includes a first transistor T11
  • the threshold compensation subcircuit 8 includes a second transistor T12
  • the driving subcircuit 1 includes a third transistor T13
  • the control terminal of the driving subcircuit 1 includes a third transistor T13.
  • the control electrode the first end of the driving subcircuit 1 includes the first electrode of the third transistor T13
  • the second end of the driving subcircuit 1 includes the second electrode of the third transistor T13.
  • the data writing sub-circuit 14 includes a fourth transistor T14, the storage sub-circuit 6 includes a storage capacitor second transistor st11, the first light emission control sub-circuit 51 includes a fifth transistor T5, and the second light emission control sub-circuit 52 includes a sixth transistor T6,
  • the second reset sub-circuit 4 includes a seventh transistor T7.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the pixel driving circuit in FIG. elaborates the technical solution of the present disclosure in detail, that is, in the description of the present disclosure, the third transistor T3, the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the first transistor T1
  • Both the seventh transistor T7 and the like can be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can use N-type transistors (for example, N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control pole is used as the gate of the transistor, one of the first pole and the second pole is used as the source of the transistor, and the other is used as the transistor
  • the drain of the transistor; and the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the first pole is the source and the second pole is the drain, so the sources of all or part of the transistors in the embodiments of the present disclosure and drain are interchangeable as required.
  • the drain of the fourth transistor T4 is electrically connected to the source of the third transistor T3, the source of the fourth transistor T4 is configured to be electrically connected to the data line Data to receive a data signal, and the gate of the fourth transistor T4
  • the electrode is configured to be electrically connected to the first scanning signal line G1 to receive the scanning signal;
  • the second plate of the storage capacitor C is electrically connected to the first power supply terminal VDD, and the first plate of the storage capacitor C is connected to the gate of the third transistor T3 poles are electrically connected;
  • the source of the second transistor T2 is electrically connected to the gate of the third transistor T3, the drain of the second transistor T2 is electrically connected to the drain of the third transistor T3, and the gate of the second transistor T2 is configured as It is electrically connected to the second scanning signal line G2 to receive the compensation control signal;
  • the source of the first transistor T1 is configured to be electrically connected to the first initialization signal terminal Vinit1 to receive the first reset signal, and the drain of the first transistor T1 is connected
  • the gates of the three transistors T3 are electrically connected, the gate of the first transistor T1 is configured to be electrically connected to the first reset signal terminal Re1 to receive the first reset control signal; the drain of the seventh transistor T7 is configured to be connected to the first initialization
  • the signal terminal Vinit1 is electrically connected to receive the first reset signal
  • the source of the seventh transistor T7 is electrically connected to the first electrode of the light emitting device OLED
  • the gate of the seventh transistor T7 is configured to be electrically connected to the second reset signal terminal Re2 to Receive the second reset control signal
  • the source of the fifth transistor T5 is electrically connected to the first power supply terminal VDD
  • the drain of the fifth transistor T5 is electrically connected to the source of the third transistor T3, and the gate of the fifth transistor T5 is configured To be electrically connected to the first enable signal terminal EM1 to receive the first light-emitting control signal
  • the source of the sixth transistor T6 is electrically connected to the drain of the third transistor T3, and the drain of the sixth transistor T6 is connected
  • One electrode is electrically connected, the gate of the sixth transistor T6 is configured to be electrically connected to the second enable signal terminal EM2 to receive the second light emission control signal; the second electrode of the light emitting device OLED is electrically connected to the second power supply terminal VSS.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant second voltage
  • the second power supply terminal VSS can be a voltage source to output a constant second voltage
  • the second voltage is a negative voltage or the like.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal can be the same, that is, the gate of the fourth transistor T4 and the gate of the second transistor T2 can be electrically connected to the same signal line, such as the first scan signal line G1, to receive For the same signal (for example, a scanning signal), at this time, the display substrate may not be provided with the second scanning signal line G2 to reduce the number of signal lines.
  • the gate of the fourth transistor T4 and the gate of the second transistor T2 may also be electrically connected to different signal lines, that is, the gate of the fourth transistor T4 is electrically connected to the first scanning signal line G1, and the gate of the second transistor T2 is electrically connected to the first scanning signal line G1.
  • the gate of T2 is electrically connected to the second scanning signal line G2, and the signals transmitted by the first scanning signal line G1 and the second scanning signal line G2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate of the fourth transistor T4 and the second transistor T2 can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the gate of the fourth transistor T4 and the gate of the second transistor T2 are electrically connected to the first scanning signal line Ga(A) as an example for illustration.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 may be electrically connected to the same signal line, for example, the first enable The signal terminal EM1 is used to receive the same signal (for example, the first light-emitting control signal). At this time, the display substrate may not be provided with the second enable signal terminal EM2 to reduce the number of ports.
  • the gate of the fifth transistor T5 and the gate of the sixth transistor T6 may also be electrically connected to different signal terminals, that is, the gate of the fifth transistor T5 is electrically connected to the first enable signal terminal EM1, and the gate of the sixth transistor T5 is electrically connected to the first enable signal terminal EM1, and the gate of the sixth transistor T6
  • the gate of the six-transistor T6 is electrically connected to the second enable signal terminal EM2 , and the signals transmitted by the first enable signal terminal EM1 and the second enable signal terminal EM2 are the same.
  • the fifth transistor T5 and the sixth transistor T6 are transistors of different types, for example, the fifth transistor T5 is a P-type transistor, and the sixth transistor T6 is an N-type transistor, the first light-emitting control signal and the sixth transistor The two light-emitting control signals may also be different, which is not limited in the embodiments of the present disclosure.
  • the gates of the fifth transistor T5 and the sixth transistor T6 are connected to the enable signal terminal EM as an example for illustration.
  • the first reset control signal and the second reset control signal may be the same, that is, the gate of the first transistor T1 and the gate of the seventh transistor T7 may be electrically connected to the same signal line, such as the first reset signal terminal Re1, To receive the same signal (for example, the first sub-reset control signal), at this time, the display substrate may not be provided with the second reset signal terminal Re2 to reduce the number of signal lines.
  • the gate of the first transistor T1 and the gate of the seventh transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first transistor T1 is electrically connected to the first reset signal terminal Re1, and the gate of the seventh transistor T7 is electrically connected to the first reset signal terminal Re1.
  • the gate of T7 is electrically connected to the second reset signal terminal Re2, and the signals transmitted by the first reset signal terminal Re1 and the second reset signal terminal Re2 are the same. It should be noted that the first reset signal and the second reset signal may also be different. In the embodiment of the present disclosure, it is taken as an example that both the gate of the first transistor T1 and the gate of the seventh transistor T7 are electrically connected to the reset signal terminal Re.
  • the second reset control signal may be the same as the scan signal, that is, the gate of the seventh transistor T7 may be electrically connected to the scan signal line Ga(A) to receive the scan signal as the second sub-reset control signal.
  • the source of the first transistor T1 and the drain of the seventh transistor T7 are respectively connected to the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2, and the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 can be DC Reference voltage terminal to output a constant DC reference voltage.
  • the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 may be the same, for example, the source of the first transistor T1 and the drain of the seventh transistor T7 are connected to the same initialization signal terminal.
  • the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the first reset signal to control the gate of the third transistor T3 and the light-emitting element. It only needs to reset the first pole, which is not limited in the present disclosure.
  • the source of the first transistor T1 and the drain of the seventh transistor T7 may both be connected to the reset power signal line Vinit.
  • both the gate of the first transistor T1 and the gate of the seventh transistor T7 are electrically connected to Re1; the source of the first transistor T1 and the drain of the seventh transistor T7 Take the power equalization connection to the reset power signal line Vinit as an example for illustration.
  • the second reset sub-circuit 4 and the storage sub-circuit 8 are only schematic, the first reset sub-circuit 2, the threshold compensation sub-circuit 8, the driving sub-circuit 1, the data writing sub-circuit 7, and the first lighting control sub-circuit 51.
  • the specific structures of the second lighting control sub-circuit 52, the second reset sub-circuit 4, and the storage sub-circuit 8 can be set according to actual application requirements, and are not specifically limited in this embodiment of the present disclosure.
  • circuit structure such as a 7T12C structure, a 6T1C structure, a 6T12C structure or a 9T12C structure, is not limited in this embodiment of the present disclosure.
  • the light emitting device OLED in the embodiment of the invention may be an organic light emitting diode (Organic Light Emitting Diode, OLED).
  • OLED Organic Light Emitting Diode
  • the light-emitting device OLED can also be a miniature inorganic light-emitting diode, further, it can be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a miniature light-emitting diode (Mini Light Emitting Diode, Mini LED).
  • One of the first pole and the second pole of the light emitting device OLED is an anode, and the other is a cathode; in the embodiment of the present invention, the first pole of the light emitting device OLED is an anode, and the second pole is a cathode as an example for illustration.
  • the inventors have found that when the fourth transistor in the pixel driving circuit leaks electricity, it is easy to cause abnormal display. To solve this problem, the inventors provide the following technical solutions.
  • FIG. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure; as shown in FIG. 3 , an embodiment of the present disclosure provides a pixel driving circuit, which includes a data writing sub-circuit 7 and a threshold compensation sub-circuit 8.
  • the threshold compensation sub-circuit 8 is configured to compensate the threshold voltage of the driving sub-circuit 1 in response to the second scanning signal.
  • the storage sub-circuit 6 is configured to store the data voltage signal.
  • the driving sub-circuit 1 is configured to provide a driving current for the light emitting device OLED to be driven according to the voltages of the first terminal and the control terminal thereof.
  • the data writing sub-circuit 7 in the embodiment of the present disclosure may include a fourth transistor T4, the source of the fourth transistor T4 is connected to the data line Data, and the drain of the fourth transistor T4 is connected to the first drive sub-circuit 1. Terminal, the gate of the fourth transistor T4 is connected to the first scan line G1.
  • the fourth transistor T4 is an oxide thin film transistor.
  • the fourth transistor T4 is an N-type transistor, write a high-level signal to the first scan line G1, the fourth transistor T4 is turned on, and the data voltage written in the data line Data will be written into the first drive sub-circuit 1 end.
  • the data writing sub-circuit 7 since the data writing sub-circuit 7 includes the fourth transistor T4, and the fourth transistor T4 adopts an oxide thin film transistor, it can greatly reduce the leakage of the fourth transistor T4 and cause the first terminal of the driving sub-circuit 1 to The voltage is pulled up, causing abnormal display problems.
  • the pixel driving circuit of the embodiment of the present disclosure not only includes the above structure, but also includes a first reset sub-circuit 2 and a second reset sub-circuit 4; the first reset sub-circuit 2 It is configured to respond to a first reset signal and reset the voltage of the control terminal of the driving sub-circuit 1 through a first initialization signal.
  • the second reset sub-circuit 4 is configured to respond to the second reset signal, and reset the first pole of the to-be-driven light emitting device OLED through the second initialization signal.
  • the channel width W of the fourth transistor T4 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the first reset subcircuit 2 includes a first transistor T1;
  • the second reset subcircuit 4 includes a seventh transistor T7; wherein, the source of the first transistor T1 is connected to the first initialization signal terminal Vinit1, and the source of the first transistor T1
  • the drain is connected to the control terminal of the driving sub-circuit 1, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1.
  • the source of the seventh transistor T7 is connected to the first electrode of the to-be-driven light-emitting device OLED, the drain of the seventh transistor T7 is connected to the second initialization signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2.
  • the absolute value of the voltage value of the reset voltage written by the first reset signal terminal Re1 may be greater than 1.5 times the absolute value of the threshold voltage, so as to ensure that the bias effect can be quickly achieved in a short period of time.
  • the absolute value of the voltage value of the reset voltage may be greater than 2 times, 2.5 times or 3 times the absolute value of the threshold voltage, but not limited thereto.
  • the voltage written into the first initialization signal terminal Vinit1 is For example, -2V, -3V, -4V, -5V, -6V, etc., but not limited thereto.
  • the channel width W of the first transistor T1 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the channel width W of the seventh transistor T7 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0 , 3.2, 3.5, 4.0, etc.
  • the first transistor T1 can be an oxide thin film transistor.
  • the first transistor T1 can be an N-type thin film transistor.
  • the first transistor T1 can be formed while forming the fourth transistor T4. be formed.
  • the use of an oxide thin film transistor for the first transistor T1 can effectively reduce the problem that the leakage of the first transistor T1 affects the potential of the control terminal of the driving sub-circuit 1 .
  • the seventh transistor T7 may be an N-type transistor or a P-type transistor. In the embodiment of the present disclosure, it is described that the seventh transistor T7 is a P-type transistor as an example.
  • the first reset signal written into the first reset signal terminal Re1 is a high-level signal
  • the second reset signal written into the second reset signal terminal Re2 is a low-level signal.
  • Both the first transistor T1 and the seventh transistor T7 are turned on, and the first initialization voltage written on the first initialization signal resets the control terminal of the drive sub-circuit 1 through the first transistor T1, and the first initialization voltage written on the second initialization signal terminal Vinit2
  • the second initialization voltage resets the anode of the light emitting device OLED to be driven through the seventh transistor T7.
  • the first transistor T1 and the seventh transistor T7 are respectively controlled by the two reset signal terminals Re, so they can be kept in the frame, and the seventh transistor T7 is controlled to be turned on through the second reset control line to control the light emitting device OLED.
  • the holding frame refers to a time period between refreshing two frames of pictures. In this way, the brightness difference between the refresh frame and the maintain frame can be effectively improved, and the probability of flicker (Flicker) on the display panel can be reduced.
  • FIG. 4 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure; as shown in FIG.
  • the switching characteristics of the seventh transistor T7 in the second reset sub-circuit 4 are the same.
  • the gates of the first transistor T1 and the seventh transistor T7 can be connected to the same reset signal terminal Re at the same time, and the source of the first transistor T1 and the drain of the seventh transistor T7 can be connected to the same initialization signal terminal Vinit, that is, the first transistor T1 and the seventh transistor T7 work at the same time, so that timing control is convenient and wiring is simple.
  • the pixel driving circuit in the embodiment of the present disclosure not only includes the above structure, but also includes a first light emission control sub-circuit 51 and a second light emission control sub-circuit 52 .
  • the first light emission control subcircuit 51 is configured to control whether the first voltage can be written into the first end of the driving subcircuit 1 in response to the first light emission control signal.
  • the second light emission control sub-circuit 52 is configured to switch on or off the connection between the driving sub-circuit 1 and the light emitting device OLED to be driven in response to the second light emission control signal.
  • the first light emission control subcircuit 51 includes a fifth transistor T5; the second light emission control subcircuit 52 includes a sixth transistor T6.
  • the source of the fifth transistor T5 is connected to the first power supply terminal VDD, the drain of the fifth transistor T5 is connected to the first terminal of the driving sub-circuit 1, and the gate of the fifth transistor T5 is connected to the first enable signal terminal EM1 .
  • the source of the sixth control transistor is connected to the second end of the driving sub-circuit 1 , the drain of the sixth control transistor is connected to the anode of the light-emitting device OLED to be driven, and the gate of the sixth control transistor is connected to the second enable signal terminal EM2 .
  • both the fifth transistor T5 and the sixth transistor T6 may be P-type transistors, and of course N-type transistors may also be used. In the embodiment of the present disclosure, both the fifth transistor T5 and the sixth transistor T6 are P-type transistors. In addition, both the fifth transistor T5 and the sixth transistor T6 can be low-temperature polysilicon thin film transistors, and of course other types of thin film transistors can also be used. In the embodiment of the present disclosure, both the fifth transistor T5 and the sixth transistor T6 are low-temperature polysilicon thin film Take transistors as an example.
  • the gate of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the same enable signal terminal EM, which can effectively reduce the Wiring helps to increase the pixel aperture ratio of the display panel.
  • the gate of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the same enable signal terminal EM.
  • the light-emitting control signal written by the enable signal terminal EM is a low-level signal, and at this time, the gate of the fifth transistor T5 and the sixth transistor T6 are turned on at the same time, so that the driving sub-circuit 1
  • the voltage on the power supply terminal VDD and its gate voltage are generated to drive the light emitting device OLED to emit light.
  • the driving sub-circuit 1 may include a third transistor T3 .
  • the source of the third transistor T3 is used as the first end of the driving sub-circuit 1
  • the drain of the third transistor T3 is used as the second end of the driving sub-circuit 1
  • the gate of the third transistor T3 is used as the driving sub-circuit 1.
  • the source of the third transistor T3 is connected to the drain of the fourth transistor T4
  • the drain of the third transistor T3 is connected to the anode of the light emitting device OLED to be driven
  • the gate of the third transistor T3 is connected to the storage sub-circuit 6 .
  • the third transistor T3 in the light-emitting phase, can generate a driving current according to the voltages of its source and gate, so as to drive the light-emitting device OLED to emit light.
  • the threshold voltage Vth of the third transistor T3 can be -2 ⁇ -5V, preferably, Vth can be greater than or equal to -4V and less than or equal to -2.5V; for example, Vth can be -4V, -3.5V V, -3V or -2.5V, but not limited thereto.
  • the threshold compensation sub-circuit 8 may include a second transistor T2 .
  • the source of the second transistor T2 is connected to the control terminal of the driving sub-circuit 1
  • the drain of the second transistor T2 is connected to the second terminal of the driving sub-circuit 1
  • the gate of the second transistor T2 is connected to the second scanning line G2 .
  • the second transistor T2 may be a P-type transistor or an N-type transistor. In FIG. 3 , the second transistor T2 is taken as a P-type transistor as an example.
  • the second scanning signal written in the second scanning line G2 is a low-level signal, and the second transistor T2 is turned on, so that the control terminal of the driving sub-circuit 1 and the The second end is short-circuited to perform threshold compensation for the control end of the driving sub-circuit 1 .
  • the second transistor T2 is an oxide thin film transistor, and the second transistor T2 is an N-type transistor.
  • the storage subcircuit 6 may include a storage capacitor C, a first terminal of the storage capacitor C is connected to the control terminal of the driving subcircuit 1 , and a second terminal of the storage capacitor C is connected to the first power supply terminal VDD.
  • the storage capacitor C is mainly used to store the data voltage written in the data line Data during the data writing and threshold compensation stages.
  • FIG. 5 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure; as shown in FIG. and the second scan control sub-circuit 11.
  • the first scan control sub-circuit 10 is configured to provide the first scan signal to the fourth transistor T4 in the phase of data writing and threshold compensation.
  • the second scan control sub-circuit 11 is configured to provide the threshold compensation sub-circuit 8 with the second scan signal during the data writing and threshold compensation phase.
  • the start time of the first scan signal is earlier than the start of the second scan signal. time; the end time of the first scan signal is the same as the end time of the second scan signal.
  • the duration of the first scanning signal is 1.2-2.0 times of the duration of the second scanning signal. In this case, it can be ensured that the data voltage can be sufficiently written during the data voltage writing and threshold compensation phases.
  • the first scan control sub-circuit 10 and the second scan control sub-circuit 11 may specifically be shift registers.
  • the pixel driving circuit includes a data writing subcircuit 7, a threshold compensation subcircuit 8, a driving subcircuit 1, a storage subcircuit 6, a first light emitting control subcircuit 51, a second light emitting subcircuit The control subcircuit 52 , the first reset subcircuit 2 and the second reset subcircuit 4 .
  • the data writing sub-circuit 7 includes a fourth transistor T4, the driving sub-circuit 1 includes a third transistor T3, the threshold compensation sub-circuit 8 includes a second transistor T2, the first reset sub-circuit 2 includes a first transistor T1, and the first light emitting
  • the control subcircuit 51 includes a fifth transistor T5, the second light emission control subcircuit 52 includes a sixth transistor T6, and the second reset subcircuit 4 includes a seventh transistor T7.
  • the source of the fourth transistor T4 is connected to the data line Data
  • the drain of the fourth transistor T4 is connected to the first end of the driving sub-circuit 1
  • the gate of the fourth transistor T4 is connected to the first scanning line G1 is connected to the first scanning control circuit.
  • the source of the second transistor T2 is connected to the gate of the third transistor T3 and the first end of the second transistor st21 of the storage capacitor, and the drain of the second transistor T2 is connected to the drain of the third transistor T3 and the source of the sixth transistor T6 , the gate of the second transistor T2 is connected to the second scanning line G2, and the second scanning line G2 is connected to the second scanning control circuit.
  • the source of the first transistor T1 is connected to the first initialization signal terminal Vinit1, the drain of the first transistor T1 is connected to the gate of the third transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1.
  • the source of the fifth transistor T5 is connected to the first power supply terminal VDD, the drain of the fifth transistor T5 is connected to the source of the third transistor T3, and the gate of the fifth transistor T5 is connected to the first enable signal terminal EM1.
  • the source of the sixth control transistor is connected to the second end of the driving sub-circuit 1 , the drain of the sixth control transistor is connected to the anode of the light-emitting device OLED to be driven, and the gate of the sixth control transistor is connected to the second enable signal terminal EM2 .
  • the source of the seventh transistor T7 is connected to the first electrode of the to-be-driven light-emitting device OLED, the drain of the seventh transistor T7 is connected to the second initialization signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal.
  • the first transistor T1 and the fourth transistor T4 in the pixel driving circuit are oxide thin film transistors, and are N-type transistors.
  • the third transistor T3 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 adopt low-temperature polysilicon transistors and are P-type transistors.
  • FIG. 6 is a working timing diagram of the pixel driving circuit shown in FIG. 5 ; the working process of the pixel driving circuit in FIG. 5 will be described below in conjunction with the timing diagram of FIG. 6 .
  • Initialization stage (T1) The first reset signal written to the first reset signal terminal Re1 is a high-level signal, and the second reset signal written to the second reset signal terminal Re2 is a low-level signal. At this time, the first The transistor T1 and the seventh transistor T7 are turned on. The first initialization voltage written on the first initialization signal terminal Vinit1 resets the gate voltage of the third transistor T3 through the first transistor T1 . The second initialization voltage written on the second initialization signal terminal Vinit2 resets the anode of the light emitting device OLED to be driven through the seventh transistor T7.
  • the anode of the light-emitting device OLED is written into the second initialization voltage (Vinit2 ⁇ VSS, VSS is the voltage of the second voltage source voltage line VSS connected to the cathode of the light-emitting device OLED) through the seventh transistor T7, so that the light-emitting device OLED is no longer In the forward conduction state, the internal electric field formed by the directional movement of impurity ions in the light-emitting device OLED gradually disappears, thereby restoring the characteristics of the light-emitting device OLED.
  • the fourth transistor T4 is turned on first, and the data voltage written on the data line Data is written into the source of the third transistor T3, and the second transistor T2 is turned on after a preset time after the fourth transistor T4 is turned on, and the third transistor T3 is turned on.
  • the gate and drain of are short-circuited, and the threshold voltage is written into the gate of the third transistor T3 until the third transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the third transistor T3), and is stored in the second transistor st21 and the second transistor st of the storage capacitor.
  • the voltages of the first terminal and the second terminal of the storage capacitor C are Vdata+Vth and VDD respectively.
  • Light-emitting phase (T3): the enable signal terminal EM writes a low-level signal, both the fifth transistor T5 and the sixth transistor T6 are turned on, the source of the third transistor T3 is connected to the first power supply terminal VDD, and the third transistor T3 The source voltage changes instantaneously from Vdata in the previous stage to VDD.
  • the light-emitting device OLED emits light under the driving of the third transistor T3.
  • the third transistor T3 works in the saturation region, the gate voltage of the third transistor T3 is Vdata+Vth, and the source voltage of the third transistor T3 is VDD, so the third transistor T3
  • the light emitting current of the light emitting device OLED is equal to the current flowing through the third transistor T3, and its expression is as follows:
  • ⁇ n is the electron mobility of the third transistor T3
  • C ox is the insulation capacitance per unit area, is the width-to-length ratio of the third transistor T3.
  • the structure of the pixel driving circuit is substantially the same as that of the pixel driving circuit shown in FIG.
  • the thin film transistor is a P-type transistor. That is to say, it is the same as the switching characteristic of the seventh transistor T7 in the second reset sub-circuit 4 .
  • the gates of the first transistor T1 and the seventh transistor T7 can be connected to the same reset signal terminal Re at the same time, and the source of the first transistor T1 and the drain of the seventh transistor T7 can be connected to the same initialization signal terminal Vinit, that is, the first transistor T1 and the seventh transistor T7 work at the same time, so that timing control is convenient and wiring is simple.
  • the working process of the pixel driving circuit is only different in the initialization stage, and the rest of the stages are the same, so only the initialization stage will be introduced below.
  • Initialization stage Write a high-level signal to the reset signal terminal Re, and both the first transistor T1 and the seventh transistor T7 are turned on. At this time, the gate of the third transistor T3 and the gate to be driven can be controlled by the initialization voltage on the initialization signal terminal Vinit. The anode of the light emitting device OLED is reset.
  • FIG. 7 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in FIG. 7 , the pixel driving circuit may have substantially the same structure as the pixel driving circuit shown in FIG. , the pixel driving circuit further includes a data voltage supply sub-circuit 12 connected to the source of the fourth transistor T4 through the data line Data.
  • the data voltage supply sub-circuit 12 is configured to write the data voltage first voltage to the data line Data in the initialization phase, so that the data writing sub-circuit 7 is transmitted to the first end of the driving sub-circuit 1; the first voltage The first voltage is greater than or equal to the data voltage corresponding to the maximum luminance value of the light-emitting device OLEDOLED; or, the first voltage is less than or equal to the data voltage corresponding to the minimum luminance value of the light-emitting device OLEDOLED. . That is to say, writing a larger voltage to the source of the third transistor T3 during the initialization phase can eliminate the threshold voltage shift of the third transistor T3 caused by hysteresis. Alternatively, writing a lower voltage to the source of the third transistor T3 during the initialization phase can also eliminate the threshold voltage shift of the third transistor T3 caused by hysteresis.
  • FIG. 8 is a working timing diagram of the pixel driving circuit shown in FIG. 7 ; the working process of the pixel driving circuit shown in FIG. 7 will be described below in conjunction with FIG. 8 .
  • Initialization stage (T1) The first reset signal written to the first reset signal terminal Re1 is a high-level signal, the second reset signal written to the second reset signal terminal Re2 is a low-level signal, and the first scan signal The written first scanning signal is a high-level signal, and at this time, the fourth transistor T4, the first transistor T1 and the seventh transistor T7 are turned on.
  • the first initialization voltage written on the first initialization signal terminal Vinit1 resets the gate voltage of the third transistor T3 through the first transistor T1 .
  • the second initialization voltage written on the second initialization signal terminal Vinit2 resets the anode of the light emitting device OLED to be driven through the seventh transistor T7.
  • the anode of the light-emitting device OLED writes the second initialization voltage (Vinit2 ⁇ VSS) through the seventh transistor T7, so that the light-emitting device OLEDOLED is no longer in the forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light-emitting device OLED gradually disappear, thereby restoring the characteristics of the light-emitting device OLED.
  • the data voltage written into the data line Data by the data voltage supply sub-circuit 12 is the first voltage Vdata1, and the first voltage Vdata1 is written into the source of the third transistor T3 through the fourth transistor T4.
  • the fourth transistor T4 remains turned on, and the data voltage (second voltage Vdata) written on the data line Data is written into the source of the third transistor T3, and the second transistor T2 is turned on after a preset time after the fourth transistor T4 is turned on. , the gate and drain of the third transistor T3 are short-circuited, and the threshold voltage is written into the gate of the third transistor T3 until the third transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the BT22), and is stored in the storage capacitor C.
  • the voltages of the first terminal and the second terminal of the storage capacitor C are Vdata+Vth and VDD respectively.
  • Light-emitting phase (T3): the enable signal terminal EM writes a low-level signal, both the fifth transistor T5 and the sixth transistor T6 are turned on, the source of the third transistor T3 is connected to the first power supply terminal VDD, and the third transistor T3 The source voltage changes instantaneously from Vdata in the previous stage to VDD.
  • the light-emitting device OLED emits light under the driving of the third transistor T3.
  • the third transistor T3 works in the saturation region, the gate voltage of the third transistor T3 is Vdata+Vth, and the source voltage of the third transistor T3 is VDD, so the third transistor T3
  • the light emitting current of the light emitting device OLED is equal to the current flowing through the third transistor T3, and its expression is as follows:
  • ⁇ n is the electron mobility of the third transistor T3
  • C ox is the insulation capacitance per unit area, is the width-to-length ratio of the third transistor T3.
  • FIG. 9 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure; as shown in FIG. 9 , the structure of this pixel driving circuit is substantially the same as that shown in FIG.
  • the pixel driving circuit further includes an auxiliary sub-circuit 29 configured to reduce the leakage current of the fourth transistor T4 under the control of the third scan signal.
  • the auxiliary sub-circuit 29 includes: an eighth transistor T8; the source of the eighth transistor T8 is connected to the data line D; the fourth transistor t; the fourth transistor; the drain of the eighth transistor T8 is connected to the source of the fourth transistor T4; The gate of the eighth transistor T8 is connected to the third scan line G and the fourth transistor 23 .
  • the switching characteristics of the eighth transistor T8 are opposite to those of the fourth transistor T4, that is, the eighth transistor T8 is a P-type transistor. Specifically, in the initialization stage and the data writing and threshold compensation stage, a low-level signal is written into the third scan line G and the fourth transistor 23, a high-level signal is written into the fourth transistor T4, and the fourth transistor T4 and the fourth transistor T4 are controlled. The eighth transistor T8 works simultaneously.
  • FIG. 10 is a working timing diagram of the pixel driving circuit shown in FIG. 9 ; the working process of the pixel driving circuit in FIG. 9 will be described in detail below in conjunction with the timing diagram shown in FIG. 10 .
  • Initialization stage (T1) The first reset signal written to the first reset signal terminal Re1 is a high-level signal, the second reset signal written to the second reset signal terminal Re2 is a low-level signal, and the first scan signal The first scanning signal written is a high-level signal, and the point scanning signal written to the third scanning signal line is a low-level signal.
  • the fourth transistor T4, the eighth transistor T8, the first transistor T1 and the seventh transistor T7 opens.
  • the first initialization voltage written on the first initialization signal terminal Vinit1 resets the gate voltage of the third transistor T3 through the first transistor T1 .
  • the second initialization voltage written on the second initialization signal terminal Vinit2 resets the anode of the light emitting device OLED to be driven through the seventh transistor T7.
  • the anode of the light-emitting device OLED writes the second initialization voltage (Vinit2 ⁇ VSS) through the seventh transistor T7, so that the light-emitting device OLEDOLED is no longer in the forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light-emitting device OLED gradually disappear, thereby restoring the characteristics of the light-emitting device OLED.
  • the data voltage written into the data line Data by the data voltage supply sub-circuit 12 is the first voltage, and the first voltage is written into the source of the third transistor T3 through the fourth transistor T4 and the eighth transistor T8.
  • the fourth transistor 23 of the third scan line G writes the third scan signal and maintains a low level signal.
  • the fourth transistor T4 and the eighth transistor T8 remain turned on, and the data voltage (second voltage Vdata) written on the data line Data is written into the source of the third transistor T3, and after a preset time after the fourth transistor T4 is turned on,
  • the second transistor T2 is turned on, the gate and drain of the third transistor T3 are short-circuited, and the threshold voltage is written into the gate of the third transistor T3 until the third transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the third transistor T3), and is stored in the storage capacitor C.
  • the voltages of the first terminal and the second terminal of the storage capacitor C are Vdata+Vth and VDD respectively.
  • Light-emitting phase (T3): the enable signal terminal EM writes a low-level signal, both the fifth transistor T5 and the sixth transistor T6 are turned on, the source of the third transistor T3 is connected to the first power supply terminal VDD, and the third transistor T3 The source voltage changes instantaneously from Vdata in the previous stage to VDD.
  • the light-emitting device OLED emits light under the driving of the third transistor T3.
  • the third transistor T3 works in the saturation region, the gate voltage of the third transistor T3 is Vdata+Vth, and the source voltage of the third transistor T3 is VDD, so the third transistor T3
  • the light emitting current of the light emitting device OLED is equal to the current flowing through the third transistor T3, and its expression is as follows:
  • ⁇ n is the electron mobility of the third transistor T3
  • C ox is the insulation capacitance per unit area, is the width-to-length ratio of the third transistor T3.
  • an embodiment of the present invention further provides a display panel, which includes any one of the above-mentioned pixel driving circuits. Therefore, the display effect of the display panel of this embodiment is better.
  • the display panel can be a liquid crystal display device or an electroluminescence display device, such as an OLED panel, a Micro LED panel, a Mini LED panel, any display device such as a mobile phone, a tablet computer, a TV set, a monitor, a notebook computer, a digital photo frame, or a navigator. functional product or component.

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Abstract

一种像素驱动电路及显示面板，其中像素驱动电路包括：数据写入子电路（7）、阈值补偿子电路（8）、驱动子电路（1）和存储子电路（6）；其中，数据写入子电路（7）包括第四晶体管（T4），第四晶体管（T4）的第一极连接数据线（Vdata），第二极连接驱动子电路（1）的第一端，控制极连接第一扫描线（G1）；第四晶体管（T4）采用氧化物薄膜晶体管；阈值补偿子电路（8），被配置为响应于第二扫描信号（G2），对驱动子电路（1）的阈值电压进行补偿；存储子电路（6），被配置为对数据电压信号进行存储；驱动子电路（1），被配置为根据其第一端和控制端的电压为待驱动的发光器件（OLED）提供驱动电流。

Description

像素驱动电路及显示面板 技术领域
本公开属于显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
有源矩阵有机电极发光二极管显示面板(Active Matrix Organic Light EmittingDiode，简称：AMOLED)的应用越来越广泛。AMOLED的像素显示器件为有机发光二极管(Organic Light-Emitting Diode,简称OLED)，AMOLED能够发光是通过驱动薄膜晶体管在饱和状态下产生驱动电流，该驱动电流驱动发光器件发光。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种像素驱动电路及显示面板。
第一方面，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路和存储子电路；其中，
所述数据写入子电路包括第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接驱动子电路的第一端，控制极连接第一扫描线；所述第四晶体管采用氧化物薄膜晶体管；
阈值补偿子电路，被配置为响应于第二扫描信号，对所述驱动子电路的阈值电压进行补偿；
所述存储子电路，被配置为对数据电压信号进行存储；
所述驱动子电路，被配置为根据其第一端和控制端的电压为待驱动的发光器件提供驱动电流。
其中，所述像素驱动电路还包括：第一复位子电路和第二复位子电路；
所述第一复位子电路，被配置为响应于第一复位信号，并通过第一初始化信号对所述驱动子电路的控制端的电压进行复位；
所述第二复位子电路，被配置为响应于第二复位信号，并通过第二初始化信号对所述待驱动的发光器件的第一极进行复位。
其中，所述第一复位子电路包括第一晶体管；所述第二复位子电路包括第七晶体管；
所述第一晶体管的第一极连接第一初始化信号端，第二极连接所述驱动子电路的控制端，控制极连接第一复位信号端；
所述第七晶体管的第一极连接所述待驱动的所述发光器件的第一极，第二极连接第二初始化信号端，控制极连接第二复位信号端。
其中，所述第一晶体管采用氧化物薄膜晶体管。
其中，所述像素驱动电路还包括：第一发光控制子电路和第二发光控制子电路；
所述第一发光控制子电路，被配置为响应于第一发光控制信号，控制第一电压是否能够被写入所述驱动子电路的第一端；
所述第二发光控制子电路，被配置为响应于第二发光控制信号，导通或断开所述驱动子电路和所述待驱动的发光器件之间的连接。
其中，所述第一发光控制子电路包括：第五晶体管；所述第二发光控制子电路包括：第六晶体管；
所述第五晶体管的第一极连接第一电源端，第二极连接所述驱动子电路的第一端，控制极连接第一使能信号端；
所述第六控制晶体管的第一极连接所述驱动子电路的第二端，第二极连接所述待驱动的发光器件的第一极，控制极连接第二使能信号端。
其中，所述像素驱动电路还包括：数据电压供给子电路；
所述数据电压供给子电路，被配置为在初始化阶段，给数据线写入第一电压，以使数据写入子电路传输至所述驱动子电路的第一端；所述第一电压大于或者等于所述发光器件能够显示最大亮度值对应的数据电压；或者，所述第一电压大于或者等于所述发光器件能够显示最小亮度值对应的数据电 压。
其中，所述像素驱动电路还包括：辅助子电路；
所述辅助子电路，被配置为在第三扫描信号的控制下，减小所述第四晶体管的漏电流。
其中，所述辅助子电路包括：第八晶体管；
所述第八晶体管的第一极连接数据线，第二极连接所述第四晶体管的第一极，控制极连接第三扫描线。
其中，所述像素驱动电路还包括：第一扫描控制子电路和第二扫描控制子电路：
所述第一扫描控制子电路，被配置为在数据写入及阈值补偿阶段为第四晶体管提供所述第一扫描信号；
所述第二扫描控制子电路，被配置为在数据写入及阈值补偿阶段为阈值补偿子电路提供所述第二扫描信号；
所述第一扫描信号的起始时刻早于所述第二扫描信号的起始时刻；所述第一扫描信号的终止时刻所述第二扫描信号的终止时刻相同。
其中，所述第一扫描信号时长为所述第二扫描信号时长的1.2～2.0倍。
其中，所述驱动子电路包括：第三晶体管；
所述第二驱动晶体管的第一极连接所述第四晶体管的第二极，第二极连接阈值补偿子电路的第二端，控制极连接所述阈值补偿子电路的第一端。
其中，所述阈值补偿子电路包括第二晶体管；
所述第二晶体管的第一极连接所述驱动子电路的控制端，第二极连接所述驱动子电路的第二端，控制极连接第二扫描线。
其中，所述第二晶体管采用氧化物薄膜晶体管。
其中，所述存储子电路包括存储电容；
所述存储电容的第一端连接第一电源端，第二端连接所述驱动子电路的控制端。
第二方面，本公开实施例提供一种显示面板，其包括上述任一像素驱动电路。
附图说明
图1为一种示例性的显示基板结构示意图。
图2为一种示例性的像素驱动电路的示意图。
图3为本公开实施例的一种像素驱动电路的示意图。
图4为本公开实施例的另一种像素驱动电路的示意图。
图5为本公开实施例的另一种像素驱动电路的示意图。
图6为图5所示的像素驱动电路的工作时序图。
图7为本公开实施例的另一种像素驱动电路的示意图。
图8为图7所示的像素驱动电路的工作时序图。
图9为本公开实施例的另一种像素驱动电路的示意图。
图10为图9所示的像素驱动电路的工作时序图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种示例性的显示基板结构示意图；图2为一种示例性的像素驱动电路的示意图；如图1和2所示，该显示基板包括呈阵列排布的多个像素单元，每个像素单元100中均包括像素驱动电路和发光器件OLED。各像素单元100中的像素驱动电路可以包括：第一复位子电路2、阈值补偿子电路81、驱动子电路1、数据写入子电路14、第一发光控制子电路51、第二发光控制子电路52、第二复位子电路4及存储子电路6。
其中，第一复位子电路2与驱动子电路1的控制端连接，且被配置为在第一复位信号的控制下对驱动子电路1的控制端进行复位。阈值补偿子电路8分别与驱动子电路1的控制端和第二端电连接，且被配置为对驱动子电路1进行阈值补偿。数据写入子电路14与驱动子电路1的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储子电路。存储子电路8分别与驱动子电路1的控制端和第一电源端VDD电连接，且被配置为存储数据信号。第一发光控制子电路51分别与第一电源端VDD以及驱动子电路1的第一端相连，且被配置为实现驱动子电路1和第一电源端VDD间的连接导通或断开，第二发光控制子电路52分别与驱动子电路1的第二端和发光器件OLED的第一极电连接，且被配置为实现驱动子电路1和发光器件OLED之间的连接导通或断开。第二复位子电路4与发光器件OLED的第一极电连接，且被配置为在第二复位控制信号的控制下对驱动子电路1的控制端和发光器件OLED的第一极进行复位。
继续参照图2，第一复位子电路包括第一晶体管T11，阈值补偿子电路8包括第二晶体管T12，驱动子电路1包括第三晶体管T13，驱动子电路1的控制端包括第三晶体管T13的控制极，驱动子电路1的第一端包括第三晶体管T13的第一极，驱动子电路1的第二端包括第三晶体管T13的第二极。数据写入子电路14包括第四晶体管T14，存储子电路6包括存储电容第二晶体管st11，第一发光控制子电路51包括第五晶体管T5，第二发光控制子电路52包括第六晶体管T6，第二复位子电路4包括第七晶体管T7。
在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，图2中的像素驱动电路以晶体管为P型晶体管 (例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，第三晶体管T3、第四晶体管T4、第二晶体管T2、第五晶体管T5、第六晶体管T6、第一晶体管T1和第七晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
另外，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
继续参照图2，第四晶体管T4漏极的与第三晶体管T3的源极电连接，第四晶体管T4的源极被配置为与数据线Data电连接以接收数据信号，第四晶体管T4的栅极被配置为与第一扫描信号线G1电连接以接收扫描信号；存储电容C的第二极板与第一电源端VDD电连接，存储电容C的第一极板与第三晶体管T3的栅极电连接；第二晶体管T2的源极与第三晶体管T3的栅极电连接，第二晶体管T2的漏极与第三晶体管T3的漏极电连接，第二晶体管T2的栅极被配置为与第二扫描信号线G2电连接以接收补偿控制信号；第一晶体管T1的源极被配置为与第一初始化信号端Vinit1电连接以接收第一复位信号，第一晶体管T1的漏极与第三晶体管T3的栅极电连接，第一晶体管T1的栅极被配置为与第一复位信号端Re1电连接以接收第一复位控制信号；第七晶体管T7的漏极被配置为与第一初始化信号端Vinit1电连接以接收第一复位信号，第七晶体管T7的源极与发光器件OLED的第一极电连接，第七晶体管T7的栅极被配置为与第二复位信号端Re2电连接以接收第 二复位控制信号；第五晶体管T5的源极与第一电源端VDD电连接，第五晶体管T5的漏极与第三晶体管T3的源极电连接，第五晶体管T5的栅极被配置为与第一使能信号端EM1电连接以接收第一发光控制信号；第六晶体管T6的源极与第三晶体管T3的漏极电连接，第六晶体管T6的漏极与发光器件OLED的第一极电连接，第六晶体管T6的栅极被配置为与第二使能信号端EM2电连接以接收第二发光控制信号；发光器件OLED的第二电极与第二电源端VSS电连接。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2所示，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
继续参照图2，扫描信号和补偿控制信号可以相同，即，第四晶体管T4的栅极和第二晶体管T2的栅极可以电连接到同一条信号线，例如第一扫描信号线G1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线G2，减少信号线的数量。又例如，第四晶体管T4的栅极和第二晶体管T2的栅极也可以分别电连接至不同的信号线，即第四晶体管T4的栅极电连接到第一扫描信号线G1，第二晶体管T2的栅极电连接到第二扫描信号线G2，而第一扫描信号线G1和第二扫描信号线G2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得第四晶体管T4的栅极和第二晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。在本公开实施例中以第四晶体管T4的栅极和第二晶体管T2的栅极电连接第一扫描信号线Ga(A)为例进行说明。
继续参照图2，第一发光控制信号和第二发光控制信号可以相同，即，第五晶体管T5的栅极和第六晶体管T6的栅极可以电连接到同一条信号线，例如第一使能信号端EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二使能信号端EM2，减少端口的数量。又例 如，第五晶体管T5的栅极和第六晶体管T6的栅极也可以分别电连接至不同的信号端，即，第五晶体管T5的栅极电连接到第一使能信号端EM1，第六晶体管T6的栅极电连接到第二使能信号端EM2，而第一使能信号端EM1和第二使能信号端EM2传输的信号相同。
需要说明的是，当第五晶体管T5和第六晶体管T6为不同类型的晶体管，例如，第五晶体管T5为P型晶体管，而第六晶体管T6为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。在本公开实施例中以第五晶体管T5和第六晶体管T6的栅极均连接使能信号端EM为例进行说明。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第一晶体管T1的栅极和第七晶体管T7的栅极可以电连接到同一条信号线，例如第一复位信号端Re1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位信号端Re2，减少信号线的数量。又例如，第一晶体管T1的栅极和第七晶体管T7的栅极也可以分别电连接至不同的信号线，即第一晶体管T1的栅极电连接到第一复位信号端Re1，第七晶体管T7的栅极电连接到第二复位信号端Re2，而第一复位信号端Re1和第二复位信号端Re2传输的信号相同。需要说明的是，第一复位信号和第二复位信号也可以不相同。在本公开实施例中以第一晶体管T1的栅极和第七晶体管T7的栅极均电连接到复位信号端Re为例。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第七晶体管T7的栅极可以电连接到扫描信号线Ga(A)以接收扫描信号作为第二子复位控制信号。
例如，第一晶体管T1的源极和第七晶体管T7的漏极分别连接到第一初始化信号端Vinit1和第二初始化信号端Vinit2，第一初始化信号端Vinit1和第二初始化信号端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一初始化信号端Vinit1和第二初始化信号端Vinit2可以相同，例如第一晶体管T1的源极和第七晶体管T7的漏极连接到同一初始化信号端。第一初始化信号端Vinit1和第二初始化信号端Vinit2可以为高压端，也可以为低 压端，只要其能够提供第一复位信号和第一复位信号以对第三晶体管T3的栅极和发光元件的第一极进行复位即可，本公开对此不作限制。例如，第一晶体管T1的源极和第七晶体管T7的漏极可以均连接至复位电源信号线Vinit。
需要说明的是，在本公开实施例中，以第一晶体管T1的栅极和第七晶体管的T7的栅极均电连接Re1；第一晶体管T1的源极和第七晶体管的T7的漏极均电连接复位电源信号线Vinit为例进行说明。另外，图2所示的像素电路中的第一复位子电路2、阈值补偿子电路8、驱动子电路1、数据写入子电路7、第一发光控制子电路51、第二发光控制子电路52、第二复位子电路4及存储子电路8仅为示意性的，第一复位子电路2、阈值补偿子电路8、驱动子电路1、数据写入子电路7、第一发光控制子电路51、第二发光控制子电路52、第二复位子电路4及存储子电路8等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图2所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管和电容的电路结构，如7T12C结构、6T1C结构、6T12C结构或者9T12C结构，本公开实施例对此不作限定。
在发明实施例中的发光器件OLED可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。当然，发光器件OLED还可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)。发光器件OLED的第一极和第二极中的一者为阳极，另一者为阴极；在本发明实施例中以发光器件OLED的第一极为阳极，第二极为阴极为例进行说明。
发明人发现，像素驱动电路中的第四晶体管漏电时，容易成显示异常，针对该问题，发明人提供如下技术方案。
第一方面，图3为本公开实施例的一种像素驱动电路的示意图；如图3 所示，本公开实施例提供一种像素驱动电路，其包括数据写入子电路7、阈值补偿子电路8、驱动子电路1和存储子电路6；其中，数据写入子电路7被配置为响应于第一扫描信号，将数据电压信号传输至驱动子电路1的第一端。阈值补偿子电路8被配置为响应于第二扫描信号，对所述驱动子电路1的阈值电压进行补偿。存储子电路6，被配置为对数据电压信号进行存储。驱动子电路1被配置为根据其第一端和控制端的电压为待驱动的发光器件OLED提供驱动电流。特别的是，本公开实施例中的数据写入子电路7可以包第四晶体管T4，第四晶体管T4的源极连接数据线Data，第四晶体管T4的漏极连接驱动子电路1的第一端，第四晶体管T4的栅极连接第一扫描线G1。而且第四晶体管T4采用氧化物薄膜晶体管。例如：第四晶体管T4为N型晶体管，给第一扫描线G1写入高电平信号，第四晶体管T4打开，数据线Data写入的数据电压则将被写入驱动子电路1的第一端。
由于本公开实施例中，由于数据写入子电路7包括第四晶体管T4，且第四晶体管T4采用氧化物薄膜晶体管，因此可以大大降低第四晶体管T4漏电而导致驱动子电路1的第一端电压被拉高，造成显示异常的问题。在一些示例中，继续参照图3，本公开实施例的像素驱动电路不仅包括上述结构，该像素驱动电路还可以包括第一复位子电路2和第二复位子电路4；第一复位子电路2被配置为响应于第一复位信号，并通过第一初始化信号对所述驱动子电路1的控制端的电压进行复位。第二复位子电路4被配置为响应于第二复位信号，并通过第二初始化信号对所述待驱动的发光器件OLED的第一极进行复位。
在一些示例中，第四晶体管T4的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
例如：第一复位子电路2包括第一晶体管T1；所述第二复位子电路4包括第七晶体管T7；其中，第一晶体管T1的源极连接第一初始化信号端Vinit1，第一晶体管T1的漏极连接驱动子电路1的控制端，第一晶体管T1的栅极连接第一复位信号端Re1。第七晶体管T7的源极连接待驱动的发光 器件OLED的第一极，第七晶体管T7的漏极连接第二初始化信号端Vinit2，第七晶体管T7的栅极连接第二复位信号端Re2。在一些示例中，第一复位信号端Re1写入的复位电压的电压值的绝对值可以大于阈值电压的绝对值的1.5倍，以保证在较短时间内能够快速达到偏置效果。例如，复位电压的电压值的绝对值可以大于阈值电压的绝对值的2倍、2.5倍或3倍，但不以此为限。第一初始化信号端Vinit1被写入的电压为
Figure PCTCN2022103292-appb-000001
例如，-2V、-3V、-4V、-5V、-6V等，但也不局限于。
在一些示例中，第一晶体管T1的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。第七晶体管T7的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。在一些示例中，如图3所示，第一晶体管T1可以采用氧化物薄膜晶体管，此时该第一晶体管T1可以为N型薄膜晶体管，该第一晶体管T1可以在形成第四晶体管T4的同时被形成。而且，第一晶体管T1采用氧化物薄膜晶体管可以有效的降低第一晶体管T1漏电而影响驱动子电路1控制端的电位的问题。在本公开实施例中，第七晶体管T7可以采用N型晶体管也可以采用P型晶体管，在本公开实施例中以第七晶体管T7采用P型晶体管为例进行描述。具体的，在初始化阶段，第一复位信号端Re1被写入的第一复位信号为高电平信号，第二复位信号端Re2被写入的第二复位信号为低电平信号，此时第一晶体管T1和第七晶体管T7均被打开，第一初始化信号上写入的第一初始化电压通过第一晶体管T1对驱动子电路1的控制端进行复位，第二初始化信号端Vinit2上写入的第二初始化电压通过第七晶体管T7对待驱动的发光器件OLED的阳极进行复位。在本公开实施例中第一晶体管T1和第七晶体管T7分别由两个复位信号端Re控制，因此可以在帧保持，通过第二复位控制线控制第七晶体管T7开启，以对发光器件OLED的阳极进行复位。其中，保持帧是指刷新两帧画面之间的时段。这样一来，可以有效的改善刷新帧和保持帧的亮度差异，降低显示面板出现闪烁(Flicker)的概率。
图4为本公开实施例的另一种像素驱动电路的示意图；如图4所示，像素驱动电路中的第一复位子电路2中的第一晶体管T1也可以采用P型晶体管，也即与第二复位子电路4中的第七晶体管T7的开关特性相同。在该种情况下，第一晶体管T1和第七晶体管T7的栅极可以同时连接同一条复位信号端Re，第一晶体管T1的源极和第七晶体管T7的漏极可以连接同一条初始化信号端Vinit，也即，第一晶体管T1和第七晶体管T7同时工作，这样一来，便于时序控制，且布线简单。
在一些示例中，如图3或4所示，本公开实施例中的像素驱动电路不仅包括上述结构，而且还可以包括第一发光控制子电路51和第二发光控制子电路52。其中，第一发光控制子电路51被配置为响应于第一发光控制信号控制第一电压是否能够被写入所述驱动子电路1的第一端。第二发光控制子电路52被配置为响应于第二发光控制信号，导通或断开驱动子电路1和待驱动的发光器件OLED之间的连接。
例如：第一发光控制子电路51包括第五晶体管T5；第二发光控制子电路52包括第六晶体管T6。其中，第五晶体管T5的源极连接第一电源端VDD，第五晶体管T5的漏极连接所述驱动子电路1的第一端，第五晶体管T5的栅极连第一使能信号端EM1。第六控制晶体管的源极连接驱动子电路1的第二端，第六控制晶体管的漏极连接待驱动的发光器件OLED的阳极，第六控制晶体管的栅极连第二使能信号端EM2。在一些示例中，第五晶体管T5和第六晶体管T6均可以采用P型晶体管，当然也可以采用N型晶体管。在本公开实施例中以第五晶体管T5和第六晶体管T6均为P型晶体管。另外，第五晶体管T5和第六晶体管T6均可以采用低温多晶硅薄膜晶体管，当然也可以采用其他类型的薄膜晶体管，在本公开实施例中以第五晶体管T5和第六晶体管T6均为低温多晶硅薄膜晶体管为例。在一些示例中，当第五晶体管T5和第六晶体管T6的开关特性相同时，第五晶体管T5的栅极和第六晶体管T6栅极可以连接同一个使能信号端EM，此时可以有效减少布线，有助于提高显示面板的像素开口率。在以下描述中以第五晶体管T5的栅极和第六晶体管T6栅极可以连接同一条使能信号端EM为例。
具体的，在发光阶段，使能信号端EM写入的发光控制信号为低电平信号，此时第五晶体管T5的栅极和第六晶体管T6同时打开，以使驱动子电路1根据第一电源端VDD上的电压和其栅极电压生成驱动发光器件OLED发光。
在一些示例中，参照图3或4，对于上述任一像素驱动电路，其中的驱动子电路1可以包括第三晶体管T3。第三晶体管T3的源极用作驱动子电路1的第一端，第三晶体管T3的漏极用作驱动子电路1的第二端，第三晶体管T3的栅极用作驱动子电路1的控制端。该第三晶体管T3的源极连接第四晶体管T4的漏极，第三晶体管T3的漏极连接待驱动的发光器件OLED的阳极，第三晶体管T3的栅极则连接存储子电路6。在该种情况下，在发光阶段，第三晶体管T3可以根据其源极和栅极的电压生成驱动电流，以驱动发光器件OLED发光。在一些示例中，第三晶体管T3的阈值电压Vth可以为-2～-5V，优选情况下，Vth可以大于或等于-4V而小于或等于-2.5V；例如，Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
在一些示例中，参照图3或5，对于上述任一像素驱动电路，其中的阈值补偿子电路8可以包括第二晶体管T2。该第二晶体管T2的源极连接驱动子电路1的控制端，第二晶体管T2的漏极连接驱动子电路1的第二端，第二晶体管T2的栅极连接第二扫描线G2。其中，第二晶体管T2可以采用P型晶体管，也可以采用N型晶体管。图3中以第二晶体管T2为P型晶体管为例。在该种情况下，在数据写入及阈值补偿阶段，第二扫描线G2写入的第二扫描信号为低电平信号，第二晶体管T2导通，以使驱动子电路1的控制端和第二端短接，以给驱动子电路1的控制端进行阈值补偿。图4中以第二晶体管T2氧化物薄膜晶体管，且该第二晶体管T2为N型晶体管，通过该种设置可以有效的降低第二晶体管T2漏电的风险，从而避免第二晶体管漏电对驱动子电路1的控制端电压造成影响。
在一些示例中，存储子电路6可以包括存储电容C，该存储电容C的第一端连接驱动子电路1的控制端，存储电容C的第二端连接第一电源端VDD。存储电容C主要用于在数据写入及阈值补偿阶段对数据线Data写入 的数据电压进行存储。
在一些示例中，图5为本公开实施例的另一种像素驱动电路的示意图；如图5所示，在该像素驱动电路中不仅可以上述结构，而且还可以包括第一扫描控制子电路10和第二扫描控制子电路11。其中，第一扫描控制子电路10被配置为在数据写入及阈值补偿阶段为第四晶体管T4提供所述第一扫描信号。第二扫描控制子电路11被配置为在数据写入及阈值补偿阶段为阈值补偿子电路8提供所述第二扫描信号第一扫描信号的起始时刻早于所述第二扫描信号的起始时刻；所述第一扫描信号的终止时刻所述第二扫描信号的终止时刻相同。例如：第一扫描信号时长为第二扫描信号时长的1.2～2.0倍。在该种情况下，可以保证在数据电压写入及阈值补偿阶段数据电压可以充分的写入。其中，第一扫描控制子电路10和第二扫描控制子电路11具体可以是移位寄存器。
以下结合具体示例对本公开实施例中的像素驱动电路进行描述。
在一个示例中，如图5所示，该像素驱动电路包括数据写入子电路7、阈值补偿子电路8、驱动子电路1、存储子电路6、第一发光控制子电路51、第二发光控制子电路52、第一复位子电路2和第二复位子电路4。其中，数据写入子电路7包括第四晶体管T4，驱动子电路1包括第三晶体管T3，阈值补偿子电路8包括第二晶体管T2，第一复位子电路2包括第一晶体管T1，第一发光控制子电路51包括第五晶体管T5，第二发光控制子电路52包括第六晶体管T6，第二复位子电路4包括第七晶体管T7。具体的，第四晶体管T4的源极连接数据线Data，第四晶体管T4的漏极连接驱动子电路1的第一端，第四晶体管T4的栅极连接第一扫描线G1，第一扫描线G1连接第一扫描控制电路。第二晶体管T2的源极连接第三晶体管T3的栅极和存储电容第二晶体管st21的第一端，第二晶体管T2的漏极连接第三晶体管T3的漏极和第六晶体管T6的源极，第二晶体管T2的栅极连接第二扫描线G2，第二扫描线G2连接第二扫描控制电路。第一晶体管T1的源极连接第一初始化信号端Vinit1，第一晶体管T1的漏极连接第三晶体管T3的栅极，第一晶体管T1的栅极连接第一复位信号端Re1。第五晶体管T5的源极连接第一 电源端VDD，第五晶体管T5的漏极连接第三晶体管T3的源极，第五晶体管T5的栅极连第一使能信号端EM1。第六控制晶体管的源极连接驱动子电路1的第二端，第六控制晶体管的漏极连接待驱动的发光器件OLED的阳极，第六控制晶体管的栅极连第二使能信号端EM2。第七晶体管T7的源极连接待驱动的发光器件OLED的第一极，第七晶体管T7的漏极连接第二初始化信号端Vinit2，第七晶体管T7的栅极连接第二复位信号端。
继续参照图5，该像素驱动电路中的第一晶体管T1和第四晶体管T4采用氧化物薄膜晶体管，且为N型晶体管。第三晶体管T3、第二晶体管T2、第五晶体管T5、第六晶体管T6和第七晶体管T7采用低温多晶硅晶体管，且为P型晶体管。
图6为图5所示的像素驱动电路工作时序图；以下结合图6的时序图对图5的像素驱动电路的工作过程进行说明。
初始化阶段(T1)：给第一复位信号端Re1写入的第一复位信号为高电平信号，给第二复位信号端Re2写入的第二复位信号为低电平信号，此时第一晶体管T1和第七晶体管T7打开。第一初始化信号端Vinit1上写入的第一初始化电压通过第一晶体管T1对第三晶体管T3的栅极电压进行复位。第二初始化信号端Vinit2上写入的第二初始化电压通过第七晶体管T7对待驱动的发光器件OLED的阳极进行复位。其中，发光器件OLED的阳极通过第七晶体管T7写入第二初始化电压(Vinit2≤VSS，VSS为使发光器件OLED的阴极所连接第二电压源电压线VSS的电压)，使发光器件OLED不再处于正向导通状态，使发光器件OLED内杂质离子定向移动形成的内部电场逐渐消失，从而恢复发光器件OLED的特性。
数据写入及阈值补偿阶段(T2)：首先第一扫描控制子电路10给第一扫描线G1写入的第一扫描信号为高电平信号，在第一扫描线G1写入第一扫描信号后的预设时间后，第二扫描控制子电路11给第二扫描线G2写入的第二扫描信号为低电平信号。也就是说，第一扫描信号的起始时刻早于第二扫描信号的起始时刻。第四晶体管T4先打开，将数据线Data上写入的数据电压写入第三晶体管T3的源极，在第四晶体管T4开启后的预设时间后第二晶 体管T2打开，将第三晶体管T3的栅极和漏极短接，将阈值电压写入第三晶体管T3的栅极，直至第三晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为第三晶体管T3的阈值电压)，并存储在存储电容第二晶体管st21第二晶体管st中。存储电容C的第一端和第二端的电压分别为Vdata+Vth和VDD。在该阶段，由于第四晶体管T4写入时间较长，可以使得数据线Data上的数据电压充足写入第三晶体管T3的源极。
发光阶段(T3)：使能信号端EM写入低电平信号，第五晶体管T5和第六晶体管T6均打开，第三晶体管T3的源极与第一电源端VDD连接，第三晶体管T3的源极电压由上一阶段的Vdata瞬时变化为VDD。发光器件OLED在第三晶体管T3的驱动下发光，此时第三晶体管T3工作在饱和区，第三晶体管T3的栅极电压为Vdata+Vth，第三晶体管T3的源极电压为VDD，故第三晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-VDD，直到下一帧的复位阶段。
发光器件OLED的发光电流等于流过第三晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
＝β(Vdata-Vdd) 2
其中，
Figure PCTCN2022103292-appb-000002
μ n是第三晶体管T3的电子迁移率，C ox是单位面积的绝缘电容，
Figure PCTCN2022103292-appb-000003
是第三晶体管T3的宽长比。
在另一个示例中，如图4所示，该像素驱动电路与图3所示的像素驱动电路的结构大致相同，区别仅在于，在该像素驱动电路中，其中的第一晶体管T1采用低温多晶硅薄膜晶体管，且为P型晶体管。也即与第二复位子电路4中的第七晶体管T7的开关特性相同。在该种情况下，第一晶体管T1和第七晶体管T7的栅极可以同时连接同一条复位信号端Re，第一晶体管T1的源极和第七晶体管T7的漏极可以连接同一条初始化信号端Vinit，也即， 第一晶体管T1和第七晶体管T7同时工作，这样一来，便于时序控制，且布线简单。
对于该像素驱动电路的工作过程仅在初始化化阶段不同，其余阶段均相同，故以下仅对初始化阶段进行介绍。
初始化阶段：给复位信号端Re写入高电平信号，第一晶体管T1和第七晶体管T7均打开，此时可以通过初始化信号端Vinit上的初始化电压对第三晶体管T3的栅极和待驱动的发光器件OLED的阳极进行复位。
在另一个示例中，图7为本公开实施例的另一种像素驱动电路的示意图；如图7所示，该像素驱动电路可以与图3所示的像素驱动电路结构大致相同，区别仅在于，在该像素驱动电路中还包括通过数据线Data与第四晶体管T4的源极连接的数据电压供给子电路12。该数据电压供给子电路12被配置为在初始化阶段，给数据线Data写入数据电压第一电压，以使数据写入子电路7传输至所述驱动子电路1的第一端；第一电压大于或者等于发光器件OLEDOLED能够显示最大亮度值对应的数据电压；或者，第一电压小于或者等于发光器件OLEDOLED能够显示最小亮度值对应的数据电压。。也就是说，在初始化阶段给第三晶体管T3的源极写入一个较大的电压，可以消除磁滞引起的第三晶体管T3的阈值电压偏移。或者，在初始化阶段给第三晶体管T3的源极写入一个较小的电压，同样可以消除磁滞引起的第三晶体管T3的阈值电压偏移。
图8为图7所示的像素驱动电路的工作时序图；以下结合图8对图7所示的像素驱动电路的工作过程进行说明。
初始化阶段(T1)：给第一复位信号端Re1写入的第一复位信号为高电平信号，给第二复位信号端Re2写入的第二复位信号为低电平信号，第一扫描信号写入的第一扫描信号为高电平信号，此时第四晶体管T4、第一晶体管T1和第七晶体管T7打开。第一初始化信号端Vinit1上写入的第一初始化电压通过第一晶体管T1对第三晶体管T3的栅极电压进行复位。第二初始化信号端Vinit2上写入的第二初始化电压通过第七晶体管T7对待驱动的发光 器件OLED的阳极进行复位。其中，发光器件OLED的阳极通过第七晶体管T7写入第二初始化电压(Vinit2≤VSS)，使发光器件OLEDOLED不再处于正向导通状态，使发光器件OLED内杂质离子定向移动形成的内部电场逐渐消失，从而恢复发光器件OLED的特性。与此同时，数据电压供给子电路12给数据线Data写入的数据电压为第一电压Vdata1，此时该第一电压Vdata1通过第四晶体管T4写入第三晶体管T3的源极。
数据写入及阈值补偿阶段(T2)：给第一扫描线G1写入第一扫描信号保持高电平信号，给第二扫描线G2写入低电平信号。第四晶体管T4保持打开，将数据线Data上写入的数据电压(第二电压Vdata)写入第三晶体管T3的源极，在第四晶体管T4开启后的预设时间后第二晶体管T2打开，将第三晶体管T3的栅极和漏极短接，将阈值电压写入第三晶体管T3的栅极，直至第三晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为BT22的阈值电压)，并存储在存储电容C中。存储电容C的第一端和第二端的电压分别为Vdata+Vth和VDD。
发光阶段(T3)：使能信号端EM写入低电平信号，第五晶体管T5和第六晶体管T6均打开，第三晶体管T3的源极与第一电源端VDD连接，第三晶体管T3的源极电压由上一阶段的Vdata瞬时变化为VDD。发光器件OLED在第三晶体管T3的驱动下发光，此时第三晶体管T3工作在饱和区，第三晶体管T3的栅极电压为Vdata+Vth，第三晶体管T3的源极电压为VDD，故第三晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-VDD，直到下一帧的复位阶段。
发光器件OLED的发光电流等于流过第三晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
＝β(Vdata-Vdd) 2
其中，
Figure PCTCN2022103292-appb-000004
μ n是第三晶体管T3的电子迁移率，C ox是单位面 积的绝缘电容，
Figure PCTCN2022103292-appb-000005
是第三晶体管T3的宽长比。
在另一个示例中，图9为本公开实施例的另一种像素驱动电路的示意图；如图9所示，该种像素驱动电路与图7所示的像素驱动电路结构大致相同，区别仅在于该像素驱动电路还包括辅助子电路29，该辅助子电路29被配置为被配置为在第三扫描信号的控制下，减小所述第四晶体管T4的漏电流。例如：所述辅助子电路29包括：第八晶体管T8；第八晶体管T8的源极连接数据线D第四晶体管t第四晶体管，第八晶体管T8的漏极连接第四晶体管T4的源极，第八晶体管T8的栅极连接第三扫描线G第四晶体管23。在一些示例中，第八晶体管T8的开关特性与第四晶体管T4的开关特性相反，也即第八晶体管T8为P型晶体管。具体的，在初始化阶段和数据写入及阈值补偿阶段，给第三扫描线G第四晶体管23写入低电平信号，给第四晶体管T4写入高电平信号，控制第四晶体管T4和第八晶体管T8同时工作。
图10为图9所示的像素驱动电路的工作时序图；以下结合图10所示的时序图对图9的像素驱动电路的工作过程进行详细说明。
初始化阶段(T1)：给第一复位信号端Re1写入的第一复位信号为高电平信号，给第二复位信号端Re2写入的第二复位信号为低电平信号，第一扫描信号写入的第一扫描信号为高电平信号，给第三扫描信号线写入点扫描信号为低电平信号，此时第四晶体管T4、第八晶体管T8、第一晶体管T1和第七晶体管T7打开。第一初始化信号端Vinit1上写入的第一初始化电压通过第一晶体管T1对第三晶体管T3的栅极电压进行复位。第二初始化信号端Vinit2上写入的第二初始化电压通过第七晶体管T7对待驱动的发光器件OLED的阳极进行复位。其中，发光器件OLED的阳极通过第七晶体管T7写入第二初始化电压(Vinit2≤VSS)，使发光器件OLEDOLED不再处于正向导通状态，使发光器件OLED内杂质离子定向移动形成的内部电场逐渐消失，从而恢复发光器件OLED的特性。与此同时，数据电压供给子电路12给数据线Data写入的数据电压为第一电压，此时该第一电压通过第四晶体管T4和第八晶体管T8写入第三晶体管T3的源极。
数据写入及阈值补偿阶段(T2)：给第一扫描线G1写入第一扫描信号保持高电平信号，给第二扫描线G2写入的第二扫描信号为低电平信号，给第三扫描线G第四晶体管23写入第三扫描信号保持低电平信号。第四晶体管T4和第八晶体管T8保持打开，将数据线Data上写入的数据电压(第二电压Vdata)写入第三晶体管T3的源极，在第四晶体管T4开启后的预设时间后第二晶体管T2打开，将第三晶体管T3的栅极和漏极短接，将阈值电压写入第三晶体管T3的栅极，直至第三晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为第三晶体管T3的阈值电压)，并存储在存储电容C中。存储电容C的第一端和第二端的电压分别为Vdata+Vth和VDD。
发光阶段(T3)：使能信号端EM写入低电平信号，第五晶体管T5和第六晶体管T6均打开，第三晶体管T3的源极与第一电源端VDD连接，第三晶体管T3的源极电压由上一阶段的Vdata瞬时变化为VDD。发光器件OLED在第三晶体管T3的驱动下发光，此时第三晶体管T3工作在饱和区，第三晶体管T3的栅极电压为Vdata+Vth，第三晶体管T3的源极电压为VDD，故第三晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-VDD，直到下一帧的复位阶段。
发光器件OLED的发光电流等于流过第三晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
＝β(Vdata-Vdd) 2
其中，
Figure PCTCN2022103292-appb-000006
μ n是第三晶体管T3的电子迁移率，C ox是单位面积的绝缘电容，
Figure PCTCN2022103292-appb-000007
是第三晶体管T3的宽长比。
第二方面，本发明实施例还提供一种显示面板，其包括上述的任意一种像素驱动电路，因此，本实施例的显示面板的显示效果较佳。
其中，显示面板可以为液晶显示装置或者电致发光显示装置，例如OLED面板、Micro LED面板，Mini LED面板，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

  1. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路和存储子电路；其中，
    所述数据写入子电路包括第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接驱动子电路的第一端，控制极连接第一扫描线；所述第四晶体管采用氧化物薄膜晶体管；
    阈值补偿子电路，被配置为响应于第二扫描信号，对所述驱动子电路的阈值电压进行补偿；
    所述存储子电路，被配置为对数据电压信号进行存储；
    所述驱动子电路，被配置为根据其第一端和控制端的电压为待驱动的发光器件提供驱动电流。
  2. 根据权利要求1所述的像素驱动电路，其中，还包括：第一复位子电路和第二复位子电路；
    所述第一复位子电路，被配置为响应于第一复位信号，并通过第一初始化信号对所述驱动子电路的控制端的电压进行复位；
    所述第二复位子电路，被配置为响应于第二复位信号，并通过第二初始化信号对所述待驱动的发光器件的第一极进行复位。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一复位子电路包括第一晶体管；所述第二复位子电路包括第七晶体管；
    所述第一晶体管的第一极连接第一初始化信号端，第二极连接所述驱动子电路的控制端，控制极连接第一复位信号端；
    所述第七晶体管的第一极连接所述待驱动的所述发光器件的第一极，第二极连接第二初始化信号端，控制极连接第二复位信号端。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一晶体管采用氧化物薄膜晶体管。
  5. 根据权利要求1所述的像素驱动电路，其中，还包括：第一发光控 制子电路和第二发光控制子电路；
    所述第一发光控制子电路，被配置为响应于第一发光控制信号，控制第一电压是否能够被写入所述驱动子电路的第一端；
    所述第二发光控制子电路，被配置为响应于第二发光控制信号，导通或断开所述驱动子电路和所述待驱动的发光器件之间的连接。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一发光控制子电路包括：第五晶体管；所述第二发光控制子电路包括：第六晶体管；
    所述第五晶体管的第一极连接第一电源端，第二极连接所述驱动子电路的第一端，控制极连接第一使能信号端；
    所述第六控制晶体管的第一极连接所述驱动子电路的第二端，第二极连接所述待驱动的发光器件的第一极，控制极连接第二使能信号端。
  7. 根据权利要求1-6中任一项所述的像素驱动电路，其中，还包括：数据电压供给子电路；
    所述数据电压供给子电路，被配置为在初始化阶段给数据线写入第一电压，以使数据写入子电路传输至所述驱动子电路的第一端；所述第一电压大于或者等于所述发光器件能够显示最大亮度值对应的数据电压；或者，所述第一电压大于或者等于所述发光器件能够显示最小亮度值对应的数据电压。
  8. 根据权利要求7所述的像素驱动电路，其中，还包括：辅助子电路；
    所述辅助子电路，被配置为在第三扫描信号的控制下，减小所述第四晶体管的漏电流。
  9. 根据权利要求8所述的像素驱动电路，其中，所述辅助子电路包括：第八晶体管；
    所述第八晶体管的第一极连接数据线，第二极连接所述第四晶体管的第一极，控制极连接第三扫描线。
  10. 根据权利要求1-6中任一项所述的像素驱动电路，其中，还包括：第一扫描控制子电路和第二扫描控制子电路：
    所述第一扫描控制子电路，被配置为在数据写入及阈值补偿阶段为第四晶体管提供所述第一扫描信号；
    所述第二扫描控制子电路，被配置为在数据写入及阈值补偿阶段为阈值补偿子电路提供所述第二扫描信号；
    所述第一扫描信号的起始时刻早于所述第二扫描信号的起始时刻；所述第一扫描信号的终止时刻所述第二扫描信号的终止时刻相同。
  11. 根据权利要求10所述的像素驱动电路，其中，所述第一扫描信号时长为所述第二扫描信号时长的1.2～2.0倍。
  12. 根据权利要求1-6中任一项所述的像素驱动电路，其中，所述驱动子电路包括：第三晶体管；
    所述第二驱动晶体管的第一极连接所述第四晶体管的第二极，第二极连接阈值补偿子电路的第二端，控制极连接所述阈值补偿子电路的第一端。
  13. 根据权利要求1-6中任一项所述的像素驱动电路，其中，所述阈值补偿子电路包括第二晶体管；
    所述第二晶体管的第一极连接所述驱动子电路的控制端，第二极连接所述驱动子电路的第二端，控制极连接第二扫描线。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第二晶体管采用氧化物薄膜晶体管。
  15. 根据权利要求1-6中任一项所述的像素驱动电路，其中，所述存储子电路包括存储电容；
    所述存储电容的第一端连接第一电源端，第二端连接所述驱动子电路的控制端。
  16. 一种显示面板，其包括权利要求1-15中任一项所述的像素驱动电路。
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