WO2021007694A1 - 像素单元、阵列基板与显示终端 - Google Patents

像素单元、阵列基板与显示终端 Download PDF

Info

Publication number
WO2021007694A1
WO2021007694A1 PCT/CN2019/095748 CN2019095748W WO2021007694A1 WO 2021007694 A1 WO2021007694 A1 WO 2021007694A1 CN 2019095748 W CN2019095748 W CN 2019095748W WO 2021007694 A1 WO2021007694 A1 WO 2021007694A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
transistor
reset
driving
display
Prior art date
Application number
PCT/CN2019/095748
Other languages
English (en)
French (fr)
Inventor
袁泽
王劭文
康佳昊
王煜闵
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2019/095748 priority Critical patent/WO2021007694A1/zh
Priority to CN201980090107.0A priority patent/CN113366562A/zh
Publication of WO2021007694A1 publication Critical patent/WO2021007694A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to the field of display driving, in particular to a pixel unit, an array substrate and a display terminal.
  • the scanning driving circuit is required to provide the gate scanning signal and the light-emitting scanning signal to cooperate with the data driving circuit to provide the image data signal to drive the pixel unit array arranged in the image display area to perform image display.
  • Each pixel unit includes a display unit that performs image display and a plurality of driving elements for driving the display unit, and the plurality of driving elements include thin film transistors and capacitors.
  • the types of thin film transistors in pixel units are all the same, that is, the types of thin film transistors that perform light emission in the display unit and those that perform image data writing are all the same.
  • N is used in pixel units.
  • Type thin film transistors or P type thin film transistors are used.
  • the leakage current is large, so that the refresh rate cannot be reduced when the pixel unit performs image display, and the overall power consumption of the display panel is large, and when the thin film transistors in the pixel unit are all N
  • a pixel unit including a driving unit, a compensation unit, a data writing unit, and a display unit.
  • the data writing unit is electrically connected to the driving unit, and is configured to write image data into the driving unit according to the first scan signal during the data writing period.
  • the driving unit is electrically connected to the display unit, and is configured to provide a driving current to the display unit according to the received light-emitting signal and the image data during the display time period to drive the display unit to perform image display.
  • the time period is after the data writing time period and does not completely overlap.
  • the compensation unit is electrically connected to the drive unit, and is used to provide a compensation voltage to the drive unit in advance when image data is written to the drive unit, and the compensation voltage is used to compensate for the drive current provided to the drive unit.
  • the driving unit includes at least one P-type transistor
  • the data writing unit or the compensation unit includes at least one N-type transistor.
  • an array substrate which includes a plurality of the aforementioned pixel units for performing image display in a display area.
  • a display terminal which includes the aforementioned array substrate.
  • the transistors in the driving unit are all P-type thin film transistors, and at the same time, one of the data writing unit or the compensation unit uses N-type thin film transistors instead of only N-type or P-type thin film transistors.
  • Transistor As a result, the overall leakage current of the pixel unit is small, and the drift of itself and the display unit can be accurately suppressed, power consumption is effectively reduced, and the display effect is better, and it can quickly adapt to high and low speed different image data display times. Refresh rate.
  • FIG. 1 is a schematic diagram of a side structure of a display terminal in an embodiment of the application
  • FIG. 2 is a schematic diagram of a planar structure of an array substrate in the display panel shown in FIG. 1;
  • FIG. 3 is a circuit block diagram of any one of the pixel units shown in FIG. 2 in the first embodiment of the application;
  • FIG. 4 is a schematic diagram of a specific circuit structure of the pixel unit shown in FIG. 3;
  • FIG. 5 is a timing diagram of the pixel unit shown in FIG. 4 during a frame of image display
  • FIG. 6 is a schematic diagram of the circuit working state of the pixel unit shown in FIG. 4 during the reset period;
  • FIG. 7 is a schematic diagram of the circuit working state of the pixel unit shown in FIG. 4 during the data writing period;
  • FIG. 8 is a schematic diagram of the circuit working state of the pixel unit shown in FIG. 4 during the display period;
  • FIG. 9 is a circuit block diagram of the pixel unit shown in FIG. 2 in the second embodiment of the application.
  • FIG. 10 is a circuit block diagram of the pixel unit shown in FIG. 2 in the third embodiment of the application;
  • FIG. 11 is a circuit block diagram of the pixel unit shown in FIG. 2 in the fourth embodiment of this application;
  • FIG. 12 is a circuit block diagram of the pixel unit shown in FIG. 2 in the fifth embodiment of this application;
  • FIG. 13 is a circuit block diagram of the pixel unit shown in FIG. 2 in the sixth embodiment of the application.
  • FIG. 1 is a schematic diagram of a side structure of a display terminal 10 in an embodiment of the application.
  • the display terminal 10 includes a display panel 11 and other components (not shown), and the other components include a power supply module, a signal processor module, a signal sensing module, and the like.
  • the display panel 11 includes an image display area 11a and a non-display area 11b.
  • the display area 11a is used to perform image display
  • the non-display area 11b is arranged around the display area 11a to arrange other auxiliary components or modules.
  • the display panel 11 includes an array substrate 11c and an opposite substrate 11d, and is sandwiched between The display medium layer 11e of the array substrate 11c and the counter substrate 11d.
  • the display medium in the display medium layer is an organic light emitting semiconductor material (Organic Electroluminescence Diode, OLED).
  • FIG. 2 is a schematic diagram of the planar structure of the array substrate 11 c in the display panel 11 shown in FIG. 1.
  • the corresponding image display area 11a in the array substrate 11c includes a plurality of m*n pixel units (Pixel) P, m data lines (Data Line) 120, and n scan drive lines (Scan Line) arranged in a matrix. ) 130 and n emission lines (Emission Line) 140, m and n are natural numbers greater than 1.
  • the plurality of data lines 120 are insulated from each other and arranged in parallel at a first predetermined distance along the second direction Y, and the multiple scan drive lines 130 are insulated from each other and arranged in parallel at a second predetermined distance along the first direction X.
  • the light-emitting drive lines 140 are also insulated from each other and arranged in parallel at a second predetermined distance along the first direction X, and a plurality of scan lines 130, a plurality of light-emitting drive lines 140, and a plurality of data lines 120 are insulated from each other.
  • the second directions Y are perpendicular to each other.
  • the m data lines 120 are respectively defined as D1, D2, ..., Dm-1, Dm according to the position order;
  • the n scan driving lines 130 are respectively defined as G1, G2, ... according to the position order , Gn;
  • the n scanning light-emitting lines 140 are respectively defined as E1, E2, ..., En according to the position order.
  • Each pixel unit P is electrically connected to a scan driving line 130 extending along the first direction X, a light emitting driving line 140, and a data line 120 extending along the second direction Y.
  • the display terminal 10 further includes a timing control circuit 101 for driving pixel units for image display, a data driver circuit (Data Driver) 102, a scan driver circuit (Scan Driver) 103, and a light-emitting driver
  • the circuit (Emission Driver) 104 is provided on the array substrate 11c.
  • the data driving circuit 102 is electrically connected to the plurality of data lines 120 for transmitting image data (Data) for display to the plurality of pixel units P through the plurality of data lines 120 in the form of data voltages.
  • Data image data
  • the scan driving circuit 103 is configured to be electrically connected to the plurality of scan driving lines 130 and used to output a scan signal Gn through the plurality of scan driving lines 130 to control when the pixel unit P receives image data. Among them, the scan driving circuit 103 outputs scan signals G1, G2, ..., Gn from the scan driving lines G1, G2,.
  • the light-emitting driving circuit 104 is used for electrically connecting with the plurality of light-emitting driving lines 140 for outputting a light-emitting signal En through the plurality of light-emitting driving lines 140 for controlling when the pixel unit P emits light according to the received image data. Among them, the light-emitting driving circuit 104 sequentially outputs scan signals E1, E2, ..., En from the light-emitting driving lines E1, E2,.
  • the timing control circuit 101 is electrically connected to the data drive circuit 102, the scan drive circuit 103, and the light-emitting drive circuit 104, respectively, for controlling the working timing of the data drive circuit 102, the scan drive circuit 103, and the light-emitting drive circuit 104, that is, the output corresponds to
  • the timing control signal of ⁇ is sent to the data driving circuit 102, the scan driving circuit 103, and the light-emitting driving circuit 104 to control when to output the corresponding scan signal Gn, light-emitting signal En, and image data Data.
  • the circuit elements in the scan driving circuit 103 and the pixel units P in the display panel 11 are manufactured in the display panel 11 in the same manufacturing process, that is, GOA (Gate Driver on Array) technology.
  • the circuit elements and the pixel units P in the display panel 11 are manufactured in the display panel 11 in the same manufacturing process, that is, EOA (Emitter on Array) technology.
  • the display terminal 10 also includes other auxiliary circuits for jointly completing image display, such as an image receiving and processing circuit (Graphics Processing Unit, GPU), a power supply circuit, etc., which are not described in detail in this embodiment.
  • image receiving and processing circuit Graphics Processing Unit, GPU
  • power supply circuit etc.
  • FIG. 3 is a circuit block diagram of any pixel unit 100 in the pixel unit P shown in FIG. 2 in the first embodiment of the application.
  • the pixel unit 100 includes: a data writing unit 101, a driving unit 102, a display unit 103, a compensation unit 104, an auxiliary unit 105, a first reset unit 106, and a second reset unit 107.
  • the pixel unit 100 displays a frame of image during the display process including three consecutive time periods H1 to H3 arranged in sequence and continuous without interval, where H1 is the reset period, H2 is the data writing period, and H3 is the display period.
  • the data writing unit 101 is electrically connected to the driving unit 102 for writing image data Data into the driving unit 102 according to the first scan signal Gn during the data writing period H2.
  • the driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data during the display period H3, so as to drive the display unit 103 to perform light emission and perform image display.
  • the display period H3 is after the data writing period H2 and does not completely overlap.
  • the compensation unit 104 is electrically connected to the driving unit 102 and is configured to provide a compensation voltage to the driving unit 102 in advance when the image data Data is written into the driving unit 102 during the data writing period H2.
  • the compensation voltage is used to compensate the voltage drift generated by the driving unit 102 itself when the driving unit 102 provides a driving current to the display unit 103.
  • the auxiliary unit 105 is electrically connected between the display unit 103 and the driving unit 102, and is used to be in an electrical cut-off state during the data writing period H2 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically cut off.
  • the sexual disconnection prevents the image data Data from being transmitted to the display unit 103 in the non-display stage and affecting the correct image display.
  • the auxiliary unit 105 is in the on state during the display period H3 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically connected, and the driving current has been transmitted to the display unit 103.
  • the first reset unit 106 is electrically connected to the display unit 103, and is configured to write a reset voltage into the display unit 103 during the reset period T1 according to the reset signal, so that the display unit is in an initial display voltage state.
  • the first reset unit 106 is used to eliminate the current and voltage remaining in the display unit 103 in the previous display stage, and ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display stage.
  • the second reset unit 107 is electrically connected to the drive unit 102, and is used to write the reset voltage Vint into the drive unit 102 during the reset period T1 according to the reset signal, so that the drive unit 102 is in the initial drive voltage state to eliminate the previous one.
  • the current and voltage remaining in the driving unit 102 in the display phase ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display phase.
  • the reset period T3 is before the data writing period H2 and does not completely overlap.
  • FIG. 4 is a schematic diagram of a specific circuit structure of the pixel unit 100 shown in FIG. 3.
  • the pixel unit 100 is any one of the plurality of pixel units P in the nth row that is scanned and turned on by the scan signal output by the scan line Gn.
  • the data writing unit 101 includes a writing transistor T1, the gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, the drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and the source of the writing transistor T1 The pole is electrically connected to the first node Ns in the driving unit 102.
  • the writing transistor T1 is an N-type oxide Oxide thin film transistor (Thin Film Transistor, TFT).
  • the N-type oxide Oxide thin film transistor may be a zinc oxide (ZnO) TFT, GaZnO TFT, InZnO TFT, AlZnO TFT, or InGaZnO TFT (InGaZnO TFT, IGZO TFT).
  • the writing transistor T1 may also be a thin film transistor (TFT) of P-type low temperature poly-silicon (LTPS).
  • TFT thin film transistor
  • LTPS P-type low temperature poly-silicon
  • the driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs.
  • the gate of the first driving transistor T2 is electrically connected to the driving node Nn
  • the source of the first driving transistor T2 is electrically connected to the first node Ns
  • the drain of the first driving transistor T2 is electrically connected to the second node Nd.
  • the driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively.
  • the driving voltage terminal Vdd is used to provide the light-emitting driving voltage ELVDD required by the display unit 103, for example, 4.5-7V.
  • the gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.
  • the first driving transistor T2 and the second driving transistor T4 are thin film transistors TFT of P-type low temperature polysilicon LTPS.
  • the driving unit 102 only includes the first driving transistor T2 and does not include the second driving transistor T4.
  • the display unit 103 is an organic light emitting diode OLED, wherein the anode of the organic light emitting diode OLED is electrically connected to the display node Na, and the cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal ELVSS.
  • the compensation unit 104 includes a compensation transistor T3, wherein the gate of the compensation transistor T3 is electrically connected to the light-emitting drive line En, the source of the compensation transistor T3 is electrically connected to the driving node Nn, and the drain of the compensation transistor T3 is electrically connected to the second node Nd .
  • the compensation transistor T3 is an N-type oxide Oxide TFT.
  • the auxiliary unit 105 includes an auxiliary transistor T5, wherein the gate of the auxiliary transistor T5 is electrically connected to the first scan line Gn, the source of the auxiliary transistor T5 is electrically connected to the second node Nd, and the drain of the auxiliary transistor T5 is electrically connected to the display node Na.
  • the auxiliary transistor T5 is a P-type LTPS TFT.
  • the first reset unit 106 includes a first reset transistor T6, wherein the gate of the first reset transistor T6 is electrically connected to the second scan line Gn-1, the source of the first reset transistor T6 is electrically connected to the light-emitting node Na, The drain of the reset transistor T6 is electrically connected to the reset voltage terminal Vint.
  • the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the low reference voltage ELVSS can be -1.5V to 0V.
  • the second reset unit 107 includes a second reset transistor T7, wherein the gate of the second reset transistor T7 is electrically connected to the second scan line Gn-1, the source of the second reset transistor T7 is electrically connected to the driving node Nn, The drain of the reset transistor T4 is electrically connected to the reset voltage terminal Vint. Among them, the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the second scan line Gn-1 and the first scan line Gn are two adjacent scan lines, and they both output scan signals in two adjacent scan periods.
  • the first reset transistor T6 and the second reset transistor T7 are N-type oxide Oxide TFTs.
  • the transistors in the driving unit 102 and the auxiliary unit 105 are all P-type TFTs.
  • the source of the P-type TFT can accurately receive the light-emitting driving voltage ELVDD of a fixed value, so the source voltage will not be affected by the drain terminal at all.
  • the electrically connected display unit 103 is affected.
  • the on and off of the P-type TFT is determined by the voltage difference between the gate and the source.
  • Both the P-type TFT in the driving unit 102 and the auxiliary unit 105 can accurately ensure that the source and drain currents will not be affected by the display unit 103 through the gate voltage.
  • the drift of the light-emitting diode OLED itself in the display unit 103 will not directly affect the source node voltage and the driving current of the first and second driving transistors T2 and T4 in the driving unit 102, which can accurately and effectively prevent
  • the driving current in the display unit 103 is affected by the display unit 103 and drifts, which has a better compensation effect.
  • the data writing unit 101, the compensation unit 104, the first reset unit 106, and the second reset unit 107 all use N-type TFTs. Therefore, the data writing unit 101, the compensation unit 104, the first reset unit 106 and the second reset unit
  • the leakage current of the TFT in 107 is small, which can effectively prevent the voltage and current of the first node Ns, the second node Nd, the driving node Nn, and the light-emitting node Na from being interfered, and better protection is obtained.
  • the voltage and current protection of the aforementioned nodes are better, so it can quickly respond to the accurate writing and display of image data, that is, it can quickly adapt to the refresh rate (Refresh Rate) of different image data display at high and low speeds, and Due to the small leakage current, the pixel unit 100 can fully match and adapt to the low power consumption mode driving mode.
  • FIG. 5 is a timing diagram of the pixel unit 100 shown in FIG. 4 during a frame of image display.
  • the graph corresponding to En is the voltage waveform of the light-emitting signal En output on the light-emitting drive line En.
  • Gn-1 and Gn are respectively the waveform diagrams of the scan line signals output by the second scan line Gn-1 and the first scan line Gn;
  • Data is the image data Data received by the pixel unit 100 in the frame image and needs to perform image display Waveform diagram;
  • VNn is the voltage waveform diagram of the drive node.
  • FIG. 6 is a schematic diagram of the working state of the circuit H1 of the pixel unit 100 shown in FIG. 4 during the reset period.
  • the light-emitting signal En is at a high level
  • the scan signal Gn-1 is at a high level
  • the scan signal Gn is at a low level. Therefore, the writing transistor T1 in the data writing unit 101 is at a low level.
  • the first driving transistor T2 and the second driving transistor T4 in the driving unit 102 are in the off state under the control of the high-level light-emitting signal En
  • the compensation transistor T3 in the compensation unit 104 is in the off state under the control of the scanning signal Gn.
  • the auxiliary transistor T5 is turned on under the control of the low-level scanning signal Gn.
  • the first reset transistor T6 and the second reset unit of the first reset unit 106 are turned on.
  • the second reset transistor T7 in 107 is in a conducting state under the control of the high level of the scan signal Gn-1.
  • the compensation transistor T3 since the compensation transistor T3 is in the on state, the second node Nd and the driving node Nn have the same potential, and the auxiliary transistor T5 is in the on state. Therefore, the driving capacitor Cs passes through the driving node Nn, the compensation transistor T3, and the second The node Nd, the auxiliary transistor T5, and the light-emitting diode OLED constitute a discharge loop, and the current from the drive electric contact Nn flows along the discharge loop through the compensation transistor T3, the second node Nd, the auxiliary transistor T5, and the light-emitting diode OLED to the low reference voltage terminal ELVSS.
  • the voltage VNn of the driving node Nn since the previous time will continue to decrease with the discharging process until it reaches the low reference voltage ELVSS.
  • the first reset transistor T6 is also in the on state, the reset voltage provided by the reset voltage terminal Vint is output to the display node Na, and the driving capacitor Cs passes through the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5, and The light-emitting diode OLED forms a discharge loop, and the voltage VNs of the display node Ns decreases with the discharge process from the previous voltage until it reaches the low reference voltage ELVSS.
  • the voltages of the driving node Nn and the display node Na in the driving unit 102 are both the reference voltage ELVSS, which effectively eliminates the residual voltage on the driving node Nn and the display node Na during the image display process of the previous frame. Voltage to ensure that the driving node Nn and the display node Na are both at the initial low reference voltage ELVSS.
  • FIG. 7 is a schematic diagram of the working state of the H2 circuit of the pixel unit 100 shown in FIG. 4 during the data writing period.
  • the light-emitting signal En continues to be at a high level
  • the scanning signal Gn-1 is at a low level
  • the scanning signal Gn changes from a low level to a high level
  • the image data Data provides the data voltage Vdata.
  • the writing transistor T1 in the data writing unit 101 is in an on state under the control of the high-level scan signal Gn, and the data voltage Vdata is transmitted to the first node Ns through the writing transistor T1.
  • the voltage VNn of the driving node Nn is the low reference voltage ELVSS
  • the low reference voltage ELVSS applied to the gate of the gate must be less than the data voltage Vdata applied to the source. Therefore, the first driving transistor T2 is in a conducting state.
  • the compensation transistor T3 in the compensation unit 104 is in a conducting state under the control of the high-level light-emitting signal En, that is, the source and drain of the compensation transistor T3 are electrically connected, and thus, the gate of the first driving transistor T2 The electrode and the drain are directly electrically connected to form a diode connection. Then, at this time, the voltage VNn of the driving node Nn is charged with the data voltage Vdata through the first driving transistor T2.
  • Vth is the threshold voltage when the second transistor T2 is turned on
  • the data voltage Vdata stops charging the driving node Nn
  • the driving node Nn Due to the non-mutation characteristic of the driving capacitor Cs, the driving node Nn
  • the voltage VNn is maintained at Vata-Vth. It can be seen that the threshold voltage Vth of the first driving transistor T2 is written to the driving node Nn along with the data voltage Vdata.
  • the second driving transistor T4 in the driving unit 102 is in the off state under the control of the high-level light-emitting signal En
  • the auxiliary transistor T5 in the auxiliary unit 105 is in the off state under the control of the high-level scanning signal Gn
  • the first reset unit 106 The first reset transistor T6 and the second reset transistor T7 in the second reset unit 107 are in an off state under the control of the low level of the scan signal Gn-1.
  • FIG. 8 is a schematic diagram of the working state of the circuit H3 of the pixel unit 100 shown in FIG. 4 during the display period.
  • the light-emitting signal En jumps from a high level to a low level
  • the scanning signal Gn-1 continues to be at a low level
  • the scanning signal Gn jumps from a high level to a low level
  • the image data Data changes from The data voltage Vdata jumps to a low level, that is, the data signal stops writing.
  • the writing transistor T1 in the data writing unit 101 is in an off state under the control of the low-level scan signal Gn.
  • the second transistor T4 in the driving unit 102 is in a conductive state under the control of the low-level light-emitting signal En, so that the light-emitting driving voltage ELVDD of the driving voltage terminal Vdd is transmitted to the first node Ns.
  • the gate voltage Vdata-Vth of the second transistor T2 is obviously smaller than the light-emitting driving voltage ELVDD, so the second transistor T2 is in the on state.
  • the compensation transistor T3 in the compensation unit 104 is in the off state under the control of the low-level light-emitting signal En, and the auxiliary transistor T5 in the auxiliary unit 105 is in the on state under the control of the low-level scan signal Gn.
  • the light-emitting driving voltage ELVDD is further transmitted to the light-emitting diode OLED in the display unit 103 through the second driving transistor T2 and the auxiliary transistor T5.
  • the width of the channel, L is the length of the conductive channel, that is, K is the size of the conductive channel of the second driving transistor, electron mobility and other related parameters.
  • the driving current Ids for the light emitting diode OLED in the display unit 103 has no relationship with the threshold voltage Vth of the first driving transistor T2, that is, the threshold voltage of the first driving transistor T2 is adjusted in advance at the data writing node.
  • the voltage Vth is written to the driving node Nn, so that the threshold voltage Vth of the first driving transistor T2 is offset during the light-emitting display phase, and then the threshold voltage Vth drift of the first driving transistor T2 is compensated and eliminated, and the display unit 103 is prevented from emitting light.
  • the light-emitting brightness of the diode OLED is affected by the threshold voltage drift of the first driving transistor T2 and cannot achieve the correct brightness.
  • the display of the display unit 103 in all the pixel units P in all the display areas will not have inconsistent brightness curves due to the different threshold voltages Vth of the first driving transistors T2 in different positions during the manufacturing process and the use process. That is, it is ensured that the display brightness of all the pixel units P in the display area is uniform without being affected by the parameters of the first driving transistor T2.
  • the first reset transistor T6 in the first reset unit 106 and the second reset transistor T7 in the second reset unit 107 are in an off state under the control of the low level of the scan signal Gn-1.
  • FIG. 9 is a circuit block diagram of the pixel unit 200 shown in FIG. 2 in the second embodiment of the application.
  • the circuit structure and working principle of the pixel unit 200 in this example and the pixel 100 in the first embodiment are basically the same.
  • the pixel unit 200 does not include the first reset unit 106, that is, the pixel unit 200 only It includes a data writing unit 101, a driving unit 102, a display unit 103, a compensation unit 104, an auxiliary unit 105, and a second reset unit 107.
  • the data writing unit 103 is electrically connected to the driving unit 101 for writing image data Data into the driving unit 101 according to the first scan signal Gn during the data writing period H2.
  • the driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data during the display period H3, so as to drive the display unit 103 to perform light emission and perform image display.
  • the display period H3 is after the data writing period H2 and does not completely overlap.
  • the compensation unit 104 is electrically connected to the driving unit 102 and is configured to provide a compensation voltage to the driving unit 102 in advance when the image data Data is written into the driving unit 102 during the data writing period H2.
  • the compensation voltage is used to compensate the voltage drift generated by the driving unit 102 itself when the driving unit 102 provides a driving current to the display unit 103.
  • the auxiliary unit 105 is electrically connected between the display units 103, and is used for being in an electrical cut-off state during the data writing period H2 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically disconnected, It prevents the image data Data from being transmitted to the display unit 103 in the non-display stage and affecting the correct image display.
  • the auxiliary unit 105 is in the on state during the display period H3 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically connected, and the driving current has been transmitted to the display unit 103.
  • the second reset unit 107 is electrically connected to the drive unit 102, and is used to write the reset voltage Vint into the drive unit 102 during the reset period H1 according to the reset signal, so that the drive unit 102 is in the initial drive voltage state to eliminate the previous one.
  • the current and voltage remaining in the driving unit 102 in the display phase ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display phase.
  • the data writing unit 101 includes a writing transistor T1.
  • the gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, and the drain of the writing transistor T1 is electrically connected to one of the data lines. Dm, the source of the writing transistor T1 is electrically connected to the first node Ns in the driving unit 102.
  • the writing transistor T1 is an N-type oxide Oxide thin film transistor TFT.
  • the driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs.
  • the gate of the first driving transistor T2 is electrically connected to the driving node Nn
  • the source of the first driving transistor T2 is electrically connected to the first node Ns
  • the drain of the first driving transistor T2 is electrically connected to the second node Nd.
  • the driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively.
  • the driving voltage terminal Vdd is used to provide the light emitting driving voltage ELVDD required by the display unit 103, for example, 4.5-5V.
  • the gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.
  • the first driving transistor T2 and the second driving transistor T4 are P-type low temperature poly-silicon (LTPS) thin film transistors (TFT).
  • LTPS low temperature poly-silicon
  • TFT thin film transistors
  • the display unit 103 is an organic light emitting diode OLED, wherein the anode of the organic light emitting diode OLED is electrically connected to the display node Na, and the cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal Vss.
  • the compensation unit 104 includes a compensation transistor T3, wherein the gate of the compensation transistor T3 is electrically connected to the light-emitting drive line En, the source of the compensation transistor T3 is electrically connected to the driving node Nn, and the drain of the compensation transistor T3 is electrically connected to the second node Nd .
  • the compensation transistor T3 is an N-type oxide Oxide TFT.
  • the auxiliary unit 105 includes an auxiliary transistor T5, wherein the gate of the auxiliary transistor T5 is electrically connected to the first scan line Gn, the source of the auxiliary transistor T5 is electrically connected to the second node Nd, and the drain of the auxiliary transistor T5 is electrically connected to the display node Na.
  • the auxiliary transistor T5 is a P-type LTPS TFT.
  • the second reset unit 107 includes a second reset transistor T7, wherein the gate of the second reset transistor T7 is electrically connected to the second scan line Gn-1, the source of the second reset transistor T7 is electrically connected to the driving node Nn, The drain of the reset transistor T4 is electrically connected to the reset voltage terminal Vint. Among them, the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the second reset transistor T7 is an N-type oxide Oxide TFT.
  • the transistors in the driving unit 102 and the auxiliary unit 105 are all P-type TFTs. Therefore, the drift of the light-emitting diode OLED in the display unit 103 will not directly affect the first and second driving transistors T2 and T4 in the driving unit 102.
  • the source node voltage can effectively prevent the driving current provided to the display unit 103 from drifting, and has a better compensation effect.
  • the data writing unit 101, the compensation unit 104, and the second reset unit 107 all adopt N-type TFTs. Therefore, the leakage current of the TFTs in the data writing unit 101, the compensation unit 104, and the second reset unit 107 is small, which can effectively prevent The voltages and currents of the first node Ns, the second node Nd, and the light-emitting node Na are disturbed, and are better protected.
  • the voltage and current protection of the aforementioned nodes are better, so it can quickly respond to the accurate writing and display of image data, that is, it can quickly adapt to the refresh rate (Refresh Rate) of different image data display at high and low speeds, and Due to the small leakage current, the pixel unit 100 can fully match and adapt to the low power consumption mode driving mode.
  • the specific working sequence and working process of the pixel unit 200 are basically the same as the working sequence of the pixel unit 100, except that in the reset period H1 (FIG. 5), the first reset unit 106 does not reset the display node Na to a preset voltage , And the working principle of other thin film transistors TFT in the corresponding working time period is the same as the working time sequence, which will not be repeated in this embodiment.
  • the second reset unit 107 performs reset on the driving node Nn.
  • the compensation transistor T3 is in the on state
  • the second node Nd has the same potential as the drive node Nn
  • the auxiliary transistor T5 is in the on state. Therefore, the drive capacitor Cs passes through the drive node Nn, the compensation transistor T3, and the second node.
  • Nd, auxiliary transistor T5, and light-emitting diode OLED constitute a discharge circuit, and the current flows from the driving electric contact Nn along with the discharge circuit through the compensation transistor T3, the second node Nd, auxiliary transistor T5, and the light-emitting diode OLED to the low reference voltage terminal ELVSS, where During the discharging process, the voltage VNn of the driving node Nn since the previous time will continue to decrease along with the discharging process until it reaches the same low reference voltage ELVSS as the reset voltage.
  • the drive capacitor Cs forms a discharge loop through the drive node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5, and the light emitting diode OLED.
  • the voltage VNs of the display node Ns since the previous time decreases with the discharge process until reset. Time period H1 ends.
  • FIG. 10 is a circuit block diagram of the pixel unit 300 shown in FIG. 2 in the third embodiment of the application.
  • the circuit structure and working principle of the pixel unit 300 in this example and the pixel 100 in the first embodiment are basically the same.
  • the pixel unit 300 does not include the second reset unit 107, that is, the pixel unit 200 only It includes a data writing unit 101, a driving unit 102, a display unit 103, a compensation unit 104, an auxiliary unit 105, and a first reset unit 106.
  • the data writing unit 103 is electrically connected to the driving unit 101 for writing image data Data into the driving unit 101 according to the first scan signal Gn during the data writing period H2.
  • the driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data during the display period H3, so as to drive the display unit 103 to perform light emission and perform image display.
  • the display period H3 is after the data writing period H2 and does not completely overlap.
  • the compensation unit 104 is electrically connected to the driving unit 102 and is configured to provide a compensation voltage to the driving unit 102 in advance when the image data Data is written into the driving unit 102 during the data writing period H2.
  • the compensation voltage is used to compensate the voltage drift generated by the driving unit 102 itself when the driving unit 102 provides a driving current to the display unit 103.
  • the auxiliary unit 105 is electrically connected between the display units 103, and is used for being in an electrical cut-off state during the data writing period H2 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically disconnected, It prevents the image data Data from being transmitted to the display unit 103 in the non-display stage and affecting the correct image display.
  • the auxiliary unit 105 is in the on state during the display period H3 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically connected, and the driving current has been transmitted to the display unit 103.
  • the first reset unit 106 is electrically connected to the display unit 103, and is configured to write a reset voltage into the display unit 103 during the reset period H1 according to the reset signal, so that the display unit is in an initial display voltage state.
  • the data writing unit 101 includes a writing transistor T1.
  • the gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, and the drain of the writing transistor T1 is electrically connected to one of the data lines. Dm, the source of the writing transistor T1 is electrically connected to the first node Ns in the driving unit 102.
  • the writing transistor T1 is an N-type oxide Oxide thin film transistor (Thin Film Transistor, TFT).
  • the N-type oxide Oxide thin film transistor may be a zinc oxide (ZnO) TFT, GaZnO TFT, InZnO TFT, AlZnO TFT, or InGaZnO TFT (InGaZnO TFT, IGZO TFT).
  • ZnO zinc oxide
  • GaZnO TFT GaZnO TFT
  • InZnO TFT AlZnO TFT
  • InGaZnO TFT InGaZnO TFT, IGZO TFT
  • the driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs.
  • the gate of the first driving transistor T2 is electrically connected to the driving node Nn
  • the source of the first driving transistor T2 is electrically connected to the first node Ns
  • the drain of the first driving transistor T2 is electrically connected to the second node Nd.
  • the driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively.
  • the driving voltage terminal Vdd is used to provide the light emitting driving voltage ELVDD required by the display unit 103, for example, 4.5-5V.
  • the gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.
  • the first driving transistor T2 and the second driving transistor T4 are P-type low temperature poly-silicon (LTPS) thin film transistors (TFT).
  • LTPS low temperature poly-silicon
  • TFT thin film transistors
  • the display unit 103 is an organic light emitting diode OLED, wherein the anode of the organic light emitting diode OLED is electrically connected to the display node Na, and the cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal Vss.
  • the compensation unit 104 includes a compensation transistor T3, wherein the gate of the compensation transistor T3 is electrically connected to the light-emitting drive line En, the source of the compensation transistor T3 is electrically connected to the driving node Nn, and the drain of the compensation transistor T3 is electrically connected to the second node Nd .
  • the compensation transistor T3 is an N-type oxide Oxide TFT.
  • the auxiliary unit 105 includes an auxiliary transistor T5, wherein the gate of the auxiliary transistor T5 is electrically connected to the first scan line Gn, the source of the auxiliary transistor T5 is electrically connected to the second node Nd, and the drain of the auxiliary transistor T5 is electrically connected to the display node Na.
  • the auxiliary transistor T5 is a P-type LTPS TFT.
  • the first reset unit 106 is electrically connected to the display unit 103, and is configured to write a reset voltage into the display unit 103 during the reset period H1 according to the reset signal, so that the display unit is in an initial display voltage state.
  • the transistors in the driving unit 102 and the auxiliary unit 105 are all P-type TFTs. Therefore, the drift of the light-emitting diode OLED in the display unit 103 will not directly affect the first and second driving transistors T2 and T4 in the driving unit 102.
  • the source node voltage can effectively prevent the driving current provided to the display unit 103 from drifting, and has a better compensation effect.
  • the data writing unit 101, the compensation unit 104, and the first reset unit 106 all adopt N-type TFTs. Therefore, the leakage current of the TFTs in the data writing unit 101, the compensation unit 104, and the first reset unit 106 is small, which can effectively prevent The voltages and currents of the first node Ns, the second node Nd, the driving node Nn, and the light-emitting node Na are disturbed and are better protected.
  • the voltage and current protection of the aforementioned nodes are better, so it can quickly respond to the accurate writing and display of image data, that is, it can quickly adapt to the refresh rate (Refresh Rate) of different image data display at high and low speeds, and Due to the small leakage current, the pixel unit 100 can fully match and adapt to the low power consumption mode driving mode.
  • the specific working timing and working process of the pixel unit 300 are basically the same as the working timing of the pixel unit 100, except that in the reset period H1 (FIG. 5), the second reset unit 107 does not reset the driving node Na to a preset voltage , And the working principle of other thin film transistors TFT in the corresponding working time period is the same as the working time sequence, which will not be repeated in this embodiment.
  • the compensation transistor T3 is in the on state
  • the second node Nd has the same potential as the drive node Nn
  • the auxiliary transistor T5 is in the on state. Therefore, the drive capacitor Cs passes through the drive node Nn, the compensation transistor T3, and the second node.
  • Nd, auxiliary transistor T5, and light-emitting diode OLED constitute a discharge circuit, and the current flows from the driving electric contact Nn along with the discharge circuit through the compensation transistor T3, the second node Nd, auxiliary transistor T5, and the light-emitting diode OLED to the low reference voltage terminal ELVSS, where During the discharging process, the voltage VNn of the driving node Nn from the previous time decreases with the discharging process until the reset period H1 ends.
  • the first reset transistor T6 is in a conducting state, and the reset voltage provided by the reset voltage terminal Vint is output to the display node Na.
  • the driving capacitor Cs the driving node Nn, the compensation transistor T3, the second node Nd, the auxiliary transistor T5 and the light emitting
  • the discharge circuit formed by the diode OLED shows that the voltage VNs of the node Ns since the previous time will continue to decrease with the discharge process until it reaches the low reference voltage ELVSS which is the same as the reset voltage.
  • FIG. 11 is a circuit block diagram of the pixel unit 400 shown in FIG. 2 in the fourth embodiment of the application.
  • the circuit structure and working principle of the pixel unit 400 in this example are basically the same as those of the pixel 100 in the first embodiment. The difference is that the pixel unit 400 does not include the auxiliary unit 105, that is, the pixel unit 200 only includes data.
  • the data writing unit 103 is electrically connected to the driving unit 101 for writing image data Data into the driving unit 101 according to the first scan signal Gn during the data writing period H2.
  • the driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data during the display period H3, so as to drive the display unit 103 to perform light emission and perform image display.
  • the display period H3 is after the data writing period H2 and does not completely overlap.
  • the compensation unit 104 is electrically connected to the driving unit 102 and is configured to provide a compensation voltage to the driving unit 102 in advance when the image data Data is written into the driving unit 102 during the data writing period H2.
  • the compensation voltage is used to compensate the voltage drift generated by the driving unit 102 itself when the driving unit 102 provides a driving current to the display unit 103.
  • the first reset unit 106 is electrically connected to the display unit 103, and is configured to write a reset voltage into the display unit 103 during the reset period H1 according to the reset signal, so that the display unit is in an initial display voltage state.
  • the first reset unit 106 is used to eliminate the current and voltage remaining in the display unit 103 in the previous display stage, and ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display stage.
  • the second reset unit 107 is electrically connected to the drive unit 102, and is used to write the reset voltage Vint into the drive unit 102 during the reset period H1 according to the reset signal, so that the drive unit 102 is in the initial drive voltage state to eliminate the previous one.
  • the current and voltage remaining in the driving unit 102 in the display phase ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display phase.
  • the reset period T3 is before the data writing period H2 and does not completely overlap.
  • the data writing unit 101 includes a writing transistor T1, the gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, the drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and the writing transistor The source of T1 is electrically connected to the first node Ns in the driving unit 102.
  • the writing transistor T1 is an N-type oxide Oxide thin film transistor (Thin Film Transistor, TFT).
  • the N-type oxide Oxide thin film transistor may be a zinc oxide (ZnO) TFT, GaZnO TFT, InZnO TFT, AlZnO TFT, or InGaZnO TFT (InGaZnO TFT, IGZO TFT).
  • the driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs.
  • the gate of the first driving transistor T2 is electrically connected to the driving node Nn
  • the source of the first driving transistor T2 is electrically connected to the first node Ns
  • the drain of the first driving transistor T2 is electrically connected to the second node Nd.
  • the driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively.
  • the driving voltage terminal Vdd is used to provide the light emitting driving voltage ELVDD required by the display unit 103, for example, 4.5-5V.
  • the gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.
  • the first driving transistor T2 and the second driving transistor T4 are thin film transistors TFT of P-type low temperature polysilicon LTPS.
  • the display unit 103 is an organic light emitting diode OLED, wherein the anode of the organic light emitting diode OLED is electrically connected to the display node Na, and the cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal Vss.
  • the compensation unit 104 includes a compensation transistor T3, wherein the gate of the compensation transistor T3 is electrically connected to the light-emitting drive line En, the source of the compensation transistor T3 is electrically connected to the driving node Nn, and the drain of the compensation transistor T3 is electrically connected to the second node Nd .
  • the compensation transistor T3 is an N-type oxide Oxide TFT.
  • the first reset unit 106 includes a first reset transistor T6, wherein the gate of the first reset transistor T6 is electrically connected to the second scan line Gn-1, the source of the first reset transistor T6 is electrically connected to the light-emitting node Na, The drain of the reset transistor T6 is electrically connected to the reset voltage terminal Vint.
  • the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the low reference voltage ELVSS may be -1.5V to 0V.
  • the light-emitting node Na overlaps with the second node Nd.
  • the second reset unit 107 includes a second reset transistor T7, wherein the gate of the second reset transistor T7 is electrically connected to the second scan line Gn-1, the source of the second reset transistor T7 is electrically connected to the driving node Nn, The drain of the reset transistor T4 is electrically connected to the reset voltage terminal Vint. Among them, the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the second scan line Gn-1 and the first scan line Gn are two adjacent scan lines, and they both output scan signals in two adjacent scan periods.
  • the first reset transistor T6 and the second reset transistor T7 are N-type oxide Oxide TFTs.
  • the transistors of the driving unit 102 are all P-type TFTs. Therefore, the drift of the light emitting diode OLED in the display unit 103 will not directly affect the source node voltages of the first and second driving transistors T2 and T4 in the driving unit 102. This can effectively prevent the driving current provided to the display unit 103 from drifting, and has a better compensation effect.
  • the data writing unit 101, the compensation unit 104, the first reset unit 106, and the second reset unit 107 all use N-type TFTs. Therefore, the data writing unit 101, the compensation unit 104, the first reset unit 106 and the second reset unit
  • the leakage current of the TFT in 107 is small, which can effectively prevent the voltage and current of the first node Ns, the second node Nd, the driving node Nn, and the light-emitting node Na from being interfered, and better protection is obtained.
  • the voltage and current protection of the aforementioned nodes are better, so it can quickly respond to the accurate writing and display of image data, that is, it can quickly adapt to the refresh rate (Refresh Rate) of different image data display at high and low speeds, and Due to the small leakage current, the pixel unit 100 can fully match and adapt to the low power consumption mode driving mode.
  • FIG. 12 is a circuit block diagram of the pixel unit 500 shown in FIG. 2 in the fifth embodiment of the application.
  • the pixel unit 500 only includes a data writing unit 101, a driving unit 102, a display unit 103, and a compensation unit. 104, the auxiliary unit 105, the first reset unit 106 and the second reset unit 107.
  • the pixel unit 100 displays a frame of image during the display process including three consecutive time periods H1 to H3 arranged in sequence and continuous without interval, where H1 is the reset period, H2 is the data writing period, and H3 is the display period.
  • the difference between the pixel unit 500 in this embodiment and the pixel unit 100 in the first embodiment is that the data writing unit 101, the compensation unit 104, the first reset unit 106, and the second reset unit 107 can use a thin film of P-type low temperature polysilicon LTPS. Transistor TFT.
  • the data writing unit 103 is electrically connected to the driving unit 101 for writing image data Data into the driving unit 101 according to the first scan signal Gn during the data writing period H2.
  • the driving unit 102 is electrically connected to the display unit 103, and is configured to provide a driving current to the display unit 103 according to the received light-emitting signal En and the image data during the display period H3, so as to drive the display unit 103 to perform light emission and perform image display.
  • the display period H3 is after the data writing period H2 and does not completely overlap.
  • the compensation unit 104 is electrically connected to the driving unit 102 and is configured to provide a compensation voltage to the driving unit 102 in advance when the image data Data is written into the driving unit 102 during the data writing period H2.
  • the compensation voltage is used to compensate the voltage drift generated by the driving unit 102 itself when the driving unit 102 provides a driving current to the display unit 103.
  • the auxiliary unit 105 is electrically connected between the display units 103, and is used for being in an electrical cut-off state during the data writing period H2 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically disconnected, It prevents the image data Data from being transmitted to the display unit 103 in the non-display stage and affecting the correct image display.
  • the auxiliary unit 105 is in the on state during the display period H3 under the control of the first scan signal Gn, so that the display unit 103 and the driving unit 102 are electrically connected, and the driving current has been transmitted to the display unit 103.
  • the first reset unit 106 is electrically connected to the display unit 103, and is configured to write a reset voltage into the display unit 103 during the reset period H1 according to the reset signal, so that the display unit is in an initial display voltage state.
  • the first reset unit 106 is used to eliminate the current and voltage remaining in the display unit 103 in the previous display stage, and ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display stage.
  • the second reset unit 107 is electrically connected to the drive unit 102, and is used to write the reset voltage into the drive unit 102 during the reset period H1 according to the reset signal, so that the drive unit 102 is in the initial drive voltage state to eliminate the previous display
  • the current and voltage remaining in the driving unit 102 in the phase ensure that each pixel unit 100 can accurately perform the display of image data in each frame of image display phase.
  • the reset period T3 is before the data writing period H2 and does not completely overlap.
  • the data writing unit 101 includes a writing transistor T1, the gate of the writing transistor T1 is electrically connected to the first scan driving line Gn, the drain of the writing transistor T1 is electrically connected to one of the data lines Dm, and the writing transistor The source of T1 is electrically connected to the first node Ns in the driving unit 102.
  • the writing transistor T1 is a P-type oxide LTPS TFT.
  • the write transistor T1 needs a low-level start signal during the data writing period H2, that is, the start signal needs to be a low-level scan signal Gn output by the scan driving line Gn.
  • the driving unit 102 includes a first driving transistor T2, a second driving transistor T4, and a driving capacitor Cs.
  • the gate of the first driving transistor T2 is electrically connected to the driving node Nn
  • the source of the first driving transistor T2 is electrically connected to the first node Ns
  • the drain of the first driving transistor T2 is electrically connected to the second node Nd.
  • the driving capacitor Cs is electrically connected to the driving voltage terminal Vdd and the driving node Nn, respectively.
  • the driving voltage terminal Vdd is used to provide the light emitting driving voltage ELVDD required by the display unit 103, for example, 4.5-5V.
  • the gate of the second driving transistor T4 is electrically connected to the light-emitting driving line En, the source of the second driving transistor T4 is electrically connected to the driving voltage terminal Vdd, and the drain of the second driving transistor T4 is electrically connected to the first node Ns.
  • the first driving transistor T2 and the second driving transistor T4 are P-type low temperature poly-silicon (LTPS) thin film transistors (TFT).
  • LTPS low temperature poly-silicon
  • TFT thin film transistors
  • the display unit 103 is an organic light emitting diode OLED, wherein the anode of the organic light emitting diode OLED is electrically connected to the display node Na, and the cathode of the organic light emitting diode OLED is electrically connected to the low reference voltage terminal Vss.
  • the compensation unit 104 includes a compensation transistor T3, wherein the gate of the compensation transistor T3 is electrically connected to the light-emitting drive line En, the source of the compensation transistor T3 is electrically connected to the driving node Nn, and the drain of the compensation transistor T3 is electrically connected to the second node Nd .
  • the compensation transistor T3 is an N-type oxide TFT, but the gate of the supplementary transistor T3 is separately connected to the scanning light-emitting line En, and is not connected in parallel with the gate of the second driving transistor T4 and then connected to the scanning transmitter. Light En.
  • the supplementary transistor T3 can only perform control corresponding to the transition of the light-emitting signal En in the data writing period H2, and does not conflict with the control of the second driving transistor T4.
  • FIG. 13 is a circuit block diagram of the pixel unit shown in FIG. 2 in the sixth embodiment of this application.
  • the compensation transistor T3 is a P Type LTPS TFT
  • the P-type LTPS TFT is used to effectively reduce leakage current
  • the data writing period H2 receives a low-level start signal
  • the start signal may be a low-level light-emitting signal En.
  • the compensation transistor T3 is two series-connected P-type LTPS TFTs (not shown in the figure). The two series-connected P-type LTPS TFTs are used to effectively reduce the leakage current and are used for data writing.
  • a low-level start signal is received, and the start signal may be a low-level light-emitting signal En.
  • the auxiliary unit 105 includes an auxiliary transistor T5, wherein the gate of the auxiliary transistor T5 is electrically connected to the first scan line Gn, the source of the auxiliary transistor T5 is electrically connected to the second node Nd, and the drain of the auxiliary transistor T5 is electrically connected to the display node Na.
  • the auxiliary transistor T5 is a P-type LTPS TFT.
  • the first reset unit 106 includes a first reset transistor T6, wherein the gate of the first reset transistor T6 is electrically connected to the second scan line Gn-1, the source of the first reset transistor T6 is electrically connected to the light-emitting node Na, The drain of the reset transistor T6 is electrically connected to the reset voltage terminal Vint.
  • the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the low reference voltage ELVSS may be -1.5V to 0V.
  • the second reset unit 107 includes a second reset transistor T7, wherein the gate of the second reset transistor T7 is electrically connected to the second scan line Gn-1, the source of the second reset transistor T7 is electrically connected to the driving node Nn, The drain of the reset transistor T4 is electrically connected to the reset voltage terminal Vint. Among them, the reset voltage terminal Vint provides a low reference voltage ELVSS as the reset voltage.
  • the first reset transistor T6 and the second reset transistor T7 may also be P-type LTPS TFTs or N-type oxide TFTs.
  • the first reset transistor T6 and the second reset transistor T7 need to use a low-level start signal during the reset period H1, that is, It is that the start signal needs to be a low-level scan signal Gn output by the scan driving line Gn-1.
  • the leakage current is small, which can effectively prevent the voltage of the first node Ns, the second node Nd, the driving node Nn, and the light-emitting node Na , The current is interfered, and get better protection.
  • the voltage and current protection of the aforementioned nodes are better, so it can quickly respond to the accurate writing and display of image data, that is, it can quickly adapt to the refresh rate (Refresh Rate) of different image data display at high and low speeds, and Due to the small leakage current, the pixel unit 100 can fully match and adapt to the low power consumption mode driving mode.
  • the transistors in the driving unit 102 and the auxiliary unit 105 are all P-type TFTs. Therefore, the drift of the light-emitting diode OLED in the display unit 103 will not directly affect the first and second driving transistors T2 and T4 in the driving unit 102.
  • the source node voltage can effectively prevent the driving current provided to the display unit 103 from drifting, and has a better compensation effect.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开一种像素单元(100)，包括驱动单元(102)、补偿单元(104)、数据写入单元(101)以及显示单元(103)。数据写入单元(101)在数据写入时间段(H2)依据第一扫描信号将图像数据写入驱动单元(102)。驱动单元(102)在显示时间段(H3)依据接收到的发光信号与图像数据提供驱动电流至显示单元(103)以驱动显示单元(103)执行图像显示。补偿单元(104)在图像数据写入驱动单元(102)时预先提供补偿电压至驱动单元(102)，以补偿驱动单元(102)产生的电压漂移。驱动单元(102)包括至少一个P型晶体管，数据写入单元(101)以及补偿单元(104)中至少包括一个N型晶体管。本申请还进一步公开包括前述像素单元的阵列基板(11c)与显示终端(10)。

Description

像素单元、阵列基板与显示终端 技术领域
本发明涉及显示驱动领域，特别是涉及一种像素单元、阵列基板与显示终端。
背景技术
对于自发光显示面板图像显示过程中，需要扫描驱动电路提供栅极扫描信号与发光扫描信号配合数据驱动电路提供图像数据信号驱动设置在图像显示区的像素单元阵列执行图像显示。
每个像素单元中包括执行图像显示的显示单元以及用于驱动显示单元的多个驱动元件，多个驱动元件包括薄膜晶体管和电容。目前而言，像素单元中的薄膜晶体管的类型均完全相同，也即是无论执行显示单元发光的薄膜晶体管，还是执行图像数据写入的薄膜晶体管的类型均完全相同，例如像素单元中均采用N型的薄膜晶体管或者均采用P型的薄膜晶体管。但是，当像素单元中的薄膜晶体管均为P型时漏电流较大而导致像素单元执行图像显示时刷新率无法降低且显示面板整体功耗较大，而当像素单元中的薄膜晶体管均为N型时则容易产生漂移而导致多个显示单元针对相同的图像数据的显示亮度不完全相同，从而无法均匀性地显示图像数据。
发明内容
为解决前述问题，提供一种显示效果较佳的像素单元。
本申请一实施例中，提供一种像素单元，包括驱动单元、补偿单元、数据写入单元以及显示单元。所述数据写入单元电性连接所述驱动单元，用于在数据写入时间段依据第一扫描信号将图像数据写入所述驱动单元。所述驱动单元与显示单元电性连接，用于在显示时间段依据接收到的发光信号与所述图像数据提供驱动电流至所述显示单元，以驱动所述显示单元执行图像显示，所述显示时间段在所述数据写入时间段之后且不完全重叠。所述补偿单元电性连接所述驱动单元，用于在图像数据写入所述驱动单元时预先提供补偿电压至所述驱动单元，所述补偿电压用于补偿在所述驱动单元提供驱动电流至显示单元时所述驱动单元产生的电压漂移。其中，所述驱动单元包括至少一个P型晶体管，所述数据写入单元或者所述补偿单元至少包括一个N型晶体管。
本申请一实施例中，提供一种阵列基板，包括位于显示区内的多个用于执行图像显示的前述的像素单元。
本申请一实施例中，提供一种显示终端，包括前述阵列基板。
相较于现有技术，所述驱动单元中的晶体管均为P型的薄膜晶体管，同时数据写入单元或者补偿单元其中之一采用N型薄膜晶体管，而并非单一采用N型或者P型的薄膜晶体管。由此，像素单元的整体漏电流较小，且能够准确抑制把自身以及所述显示单元的漂移，有效降低功耗且具有较佳的显示效果，并能够快速适应高、低速不同图像数据显示时的刷新率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例中显示终端侧面结构示意图；
图2为图1所示显示面板中阵列基板的平面结构示意图；
图3为本申请第一实施例中如图2所示多个像素单元中任意一个像素单的电路框图；
图4为图3所示像素单元的具体的电路结构示意图；
图5为图4所示像素单元在一帧图像显示过程中的时序图；
图6为图4所示像素单元在复位时间段电路工作状态示意图；
图7为图4所示像素单元在数据写入时间段电路工作状态示意图；
图8为图4所示像素单元在显示时间段电路工作状态示意图；
图9为本申请第二实施例中如图2所示像素单元的电路框图；
图10为本申请第三实施例中如图2所示像素单元的电路框图；
图11为本申请第四实施例中如图2所示像素单元的电路框图；
图12为本申请第五实施例中如图2所示像素单元的电路框图；
图13为本申请第六实施例中如图2所示像素单元的电路框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面结合附图，具体说明显示终端中像素单元的电路结构及其工作过程。
图1为本申请一实施例中显示终端10侧面结构示意图。如图1所示，显示终端10包括显示面板11与其他元部件(图未示)，所述其他元部件包括电源模组、信号处理器模组、信号感测模组等。
其中，显示面板11包括图像用显示区11a与非显示区11b。显示区11a用于执行图像显示，非显示区11b环绕设置于显示区11a周围以设置其他辅助部件或者模组，具体地，显示面板11包括有阵列基板11c与对向基板11d，以及夹设于阵列基板11c与对向基板11d的显示介质层11e。本实施例中，显示介质层中的显示介质为有机发光半导体材料(Organic Electroluminescence Diode，OLED)。
请参阅图2，其为图1所示显示面板11中阵列基板11c的平面结构示意图。如图2所示，阵列基板11c中对应图像显示区11a包括多个呈矩阵排列的m*n像素单元(Pixel)P、m条数据线(Data Line)120、n条扫描驱动线(Scan Line)130以及n条发光驱动线(Emission Line)140，m、n为大于1的自然数。
其中，该多条数据线120沿第二方向Y间隔第一预定距离相互绝缘且平行排列，该多条扫描驱动线130沿第一方向X亦间隔第二预定距离相互绝缘且平行排列，多条发光驱动线140沿第一方向X亦间隔第二预定距离相互绝缘且平行排列，并且多条扫描线130、多条发光驱动线140与多条数据线120相互绝缘，所述第一方向X与第二方向Y相互垂直。
为便于说明，所述m条数据线120按照位置顺序分别定义为D1、D2、……，Dm-1、Dm；所述n条扫描驱动线130按照位置顺序分别定义为G1、G2、……，Gn；所述n条扫描发光线140按照位置顺序分别定义为E1、E2、……，En。每一个像素单元P对应电性连接一条沿着第一方向X延伸设置的扫 描驱动线130、一条发光驱动线140以及沿着第二方向Y延伸设置的数据线120。
对应显示面板11的非显示区11b，显示终端10进一步包括的用于驱动像素单元进行图像显示的时序控制电路101、数据驱动电路(Data Driver)102、扫描驱动电路(Scan Driver)103以及发光驱动电路(Emission Driver)104设置于阵列基板11c。
其中，数据驱动电路102与该多条数据线120电性连接，用于将待显示用的图像数据(Data)通过该多条数据线120以数据电压的形式传输至该多个像素单元P。
扫描驱动电路103用于与该多条扫描驱动线130电性连接，用于通过该多条扫描驱动线130输出扫描信号Gn用于控制像素单元P何时接收图像数据。其中，扫描驱动电路103按照位置排列顺序自多条扫描驱动线130按照扫描周期依次自扫描驱动线G1、G2、……，Gn输出扫描信号G1、G2、……，Gn。
发光驱动电路104用于与该多条发光驱动线140电性连接，用于通过该多条发光驱动线140输出发光信号En用于控制像素单元P何时依据接收图像数据进行发光。其中，发光驱动电路104按照位置排列顺序自多条发光驱动线140按照扫描周期依次自发光驱动线E1、E2、……，En输出扫描信号E1、E2、……，En。
时序控制电路101分别与数据驱动电路102、扫描驱动电路103与发光驱动电路104电性连接，用于控制数据驱动电路102、扫描驱动电路103以及发光驱动电路104的工作时序，也即是输出对应的时序控制信号至数据驱动电路102、扫描驱动电路103以及发光驱动电路104，以控制何时输出对应的扫描信号Gn、发光信号En以及图像数据Data。
本实施例中，扫描驱动电路103中的电路元件与显示面板11中的像素单元P同一制程制作于显示面板11中，也即是GOA(Gate Driver on Array)技术，扫发光动电路104中的电路元件与显示面板11中的像素单元P同一制程制作于显示面板11中，也即是EOA(Emitter on Array)技术。
可以理解，显示终端10还包括有其他辅助电路用于共同完成图像的显示，例如图像接收处理电路(Graphics Processing Unit，GPU)、电源电路等，本实施例中不再对其进行赘述。
请参阅图3，其为本申请第一实施例中如图2所示像素单元P中任意一个像素单元100的电路框图。如图3所示，像素单元100包括：数据写入单元101、驱动单元102、显示单元103、补偿单元104、辅助单元105、第一复位单元106以及第二复位单元107。像素单元100执行一帧图像的显示过程中包括H1-H3三个依序排列且连续无间隔的时间段，其中，H1为复位时间段，H2为数据写入时间段，H3为显示时间段。
如图3-4所示，数据写入单元101电性连接驱动单元102，用于在数据写入时间段H2依据第一扫描信号Gn将图像数据Data写入驱动单元102。
驱动单元102与显示单元103电性连接，用于在显示时间段H3依据接收到的发光信号En与图像数据配合提供驱动电流至显示单元103，以驱动显示单元103执行发光并且进行图像显示。显示时间段H3在数据写入时间段H2之后且不完全重叠。
补偿单元104电性连接驱动单元102，用于在数据写入时间段H2的过程中在图像数据Data写入驱动单元102时预先提供补偿电压至驱动单元102。补偿电压用于补偿在驱动单元102提供驱动电流至显示单元103时驱动单元102本身产生的电压漂移。
辅助单元105电性连接于显示单元103和驱动单元102之间，用于在第一扫描信号Gn控制下于数据写入时间段H2处于电性截止状态，以使得显示单元103与驱动单元102电性断开，防止图像数据Data在非显示阶段传输至显示单元103而影响正确的图像显示。同时，辅助单元105在第一扫描信号Gn控制下于显示时间段H3处于导通状态，使得显示单元103与驱动单元102电性导通，已将驱动电流传输至显示单元103。
第一复位单元106电性连接显示单元103，用于依据复位信号在复位时间段T1将复位电压写入所述显示单元103，使得所述显示单元处于初始显示电压状态。第一复位单元106用于消除前一个显示阶段残留于显示单元103内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。
第二复位单元107电性连接于所述驱动单元102，用于在依据复位信号在复位时间段T1将复位电压Vint写入驱动单元102，使得驱动单元102处于初始驱动电压状态，以消除前一个显示阶段残留于驱动单元102内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。其中，复位时间段T3在数据写入时间段H2之前且不完全重叠。
具体地，请参阅图4，其为图3所示像素单元100的具体的电路结构示意图。如图4所示，其中，需要说明的是，像素单元100为第n行中多个像素单元P由扫描线Gn输出的扫描信号进行扫描开启的其中任意一个像素单元。
数据写入单元101包括写入晶体管T1，写入晶体管T1的栅极电性连接第一扫描驱动线Gn，写入晶体管T1的漏极电性连接其中一条数据线Dm，写入晶体管T1的源极电性连接驱动单元102中的第一节点Ns。本实施例中，写入晶体管T1为N型氧化物Oxide的薄膜晶体管(Thin Film Transistor，TFT)，具体地，N型氧化物Oxide的薄膜晶体管可以为以氧化锌(ZnO)TFT、GaZnO TFT、InZnO TFT、AlZnO TFT或者铟镓锌氧化物TFT(InGaZnO TFT，IGZO TFT)。
在本申请其他实施例中，写入晶体管T1还可以为P型低温多晶硅(Low Temperature Poly-silicon,LTPS)的薄膜晶体管(Thin Film Transistor，TFT)。
驱动单元102包括第一驱动晶体管T2、第二驱动晶体管T4以及驱动电容Cs。其中，第一驱动晶体管T2的栅极电性连接驱动节点Nn，第一驱动晶体管T2的源极电性连接第一节点Ns，第一驱动晶体管T2的漏极电性连接第二节点Nd。驱动电容Cs分别电性连接于驱动电压端Vdd与驱动节点Nn。驱动电压端Vdd用于提供显示单元103所需的发光驱动电压ELVDD，例如为4.5～7V。
第二驱动晶体管T4的栅极电性连接发光驱动线En，第二驱动晶体管T4的源极电性连接驱动电压端Vdd，第二驱动晶体管T4的漏极电性连接第一节点Ns。
本实施例中，第一驱动晶体管T2与第二驱动晶体管T4为P型低温多晶硅LTPS的薄膜晶体管TFT。
在本申请其他变更实施例方式中，驱动单元102仅包括第一驱动晶体管T2，而并不包含第二驱动晶体管T4。
显示单元103为有机发光二极管OLED，其中，有机发光二极管OLED的阳极电性连接显示节点Na，有机发光二极管OLED的阴极电性连接低参考电压端ELVSS。
补偿单元104包括补偿晶体管T3，其中，补偿晶体管T3的栅极电性连接发光驱动线En，补偿晶体管T3的源极电性连接驱动节点Nn，补偿晶体管T3的漏极电性连接第二节点Nd。本实施例中，补偿晶体管T3为N型氧化物Oxide的TFT。
辅助单元105包括辅助晶体管T5，其中，辅助晶体管T5的栅极电性连接第一扫描线Gn，辅助晶体管T5的源极电性连接第二节点Nd，辅助晶体管T5的漏极电性连接显示节点Na。本实施例中，辅助晶体管T5为P型LTPS TFT。
第一复位单元106包括第一复位晶体管T6，其中，第一复位晶体管T6的栅极电性连接第二扫描线Gn-1，第一复位晶体管T6的源极电性连接发光节点Na，第一复位晶体管T6的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。本实施例中，低参考电压ELVSS可 以为-1.5V～0V。
第二复位单元107包括第二复位晶体管T7，其中，第二复位晶体管T7的栅极电性连接第二扫描线Gn-1，第二复位晶体管T7的源极电性连接驱动节点Nn，第二复位晶体管T4的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。
其中，第二扫描线Gn-1与第一扫描线Gn为相邻的两条扫描线，且二者在相邻的两个扫描周期输出扫描信号。
本实施例中，第一复位晶体管T6与第二复位晶体管T7为N型氧化物Oxide的TFT。
驱动单元102、辅助单元105中的晶体管均为P型的TFT，其中，P型TFT的源极均能够准确地接收固定值的发光驱动电压ELVDD，故而源极的电压就完全不会受到漏极端电性连接的显示单元103的影响，同时，P型的TFT的导通与截止均是由栅极与源极的电压差确定的，当源极的电压确定而不受到显示单元103影响时，驱动单元102与辅助单元105中P型TFT均能够通过栅极电压即可准确保证源漏电流不会受到显示单元103的影响。那么，显示单元103中发光二极管OLED本身的漂移也就不会直接影响到驱动单元102中第一、第二驱动晶体管T2、T4的源极节点电压以及驱动电流，从而能够准确、有效防止提供至显示单元103中的驱动电流受到显示单元103的影响而产生漂移，具有较佳的补偿效果。
数据写入单元101、补偿单元104、第一复位单元106与第二复位单元107均采用N型TFT，由此，数据写入单元101、补偿单元104、第一复位单元106与第二复位单元107中TFT的漏电流较小，能够有效防止第一节点Ns、第二节点Nd、驱动节点Nn以及发光节点Na的电压、电流受到干扰，得到较佳的保护。同时，前述节点的电压、电流保护较佳，那么就能够快速应对图像数据Data的准确写入与显示，也即是能够快速适应高、低速不同图像数据显示时的刷新率(Refresh Rate)，并且由于漏电流较小，像素单元100能够完全匹配适应低功耗模式驱动方式。
请参阅图5，其为图4所示像素单元100在一帧图像显示过程中的时序图，如图5所示，En对应的曲线图为发光驱动线En上输出的发光信号En的电压波形图，Gn-1、Gn分别为第二扫描线Gn-1与第一扫描线Gn输出的扫描线信号波形图；Data为该帧图像中像素单元100接收并且需要执行图像显示的图像数据Data的波形图；VNn为驱动节点的电压波形图。
请一并参阅图5-6，图6为图4所示像素单元100在复位时间段H1电路工作状态示意图。
在复位时间段H1，发光信号En为高电平，扫描信号Gn-1为高电平，扫描信号Gn为低电平，由此，数据写入单元101中的写入晶体管T1在低电平的扫描信号Gn控制下处于截止状态，驱动单元102中第一驱动晶体管T2与第二驱动晶体管T4在高电平的发光信号En控制下处于截止状态，补偿单元104中的补偿晶体管T3在高电平的发光信号En控制下处于导通状态，辅助单元105中辅助晶体管T5在低电平的扫描信号Gn控制处于导通状态，第一复位单元106中的第一复位晶体管T6与第二复位单元107中第二复位晶体管T7在扫描信号Gn-1的高电平控制下处于导通状态。
由此，由于补偿晶体管T3处于导通状态，第二节点Nd与驱动节点Nn的电位相同，同时，辅助晶体管T5处于导通状态，故而，驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成放电回路，电流则自驱动电接点Nn随着放电回路经过补偿晶体管T3、第二节点Nd、辅助晶体管T5、发光二极管OLED流向低参考电压端ELVSS，在此放电过程中，驱动节点Nn的电压VNn自前一次留存的电压随着放电过程会持续降低，直至达到低参考电压ELVSS。同时，第一复位晶体管T6也处于导通状态，复位电压端Vint提提供的复位电压输出至显示节点Na，对于驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成放电回路，显示节 点Ns的电压VNs自前一次留存的电压随着放电过程降低，直至达到低参考电压ELVSS。
明显可见，在复位时间段H1，驱动单元102中的驱动节点Nn以及显示节点Na的电压均为参考电压ELVSS，从而有效消除了前一帧图像显示过程中残留于驱动节点Nn以及显示节点Na的电压，保证驱动节点Nn以及显示节点Na均处于初始的低参考电压ELVSS。
请一并参阅图5、7，图7为图4所示像素单元100在数据写入时间段H2电路工作状态示意图。
在数据写入时间段H2，发光信号En继续为高电平，扫描信号Gn-1为低电平，扫描信号Gn自低电平跳变为高电平，同时图像数据Data提供数据电压Vdata。
由此，数据写入单元101中的写入晶体管T1在高电平的扫描信号Gn控制下处于导通状态，数据电压Vdata通过写入晶体管T1传输至第一节点Ns。
由于驱动节点Nn的电压VNn为低参考电压ELVSS，对于驱动单元102中第一驱动晶体管T2的栅极而言，其栅极所加载的低参考电压ELVSS势必小于源极所加载的数据电压Vdata，故而第一驱动晶体管T2处于导通状态。
补偿单元104中的补偿晶体管T3在高电平的发光信号En控制下处于导通状态，也即是补偿晶体管T3的源极与漏极电性导通，由此，第一驱动晶体管T2的栅极与漏极直接电性连接，形成二极管连接，那么，此时，驱动节点Nn的电压VNn有数据电压Vdata通过第一驱动晶体管T2进行充电，当驱动节点Nn的电压VNn充电至为Vata-Vth时，第一驱动晶体管T2处于截止状态，其中Vth为第二晶体管T2导通时的阈值电压，数据电压Vdata停止对驱动节点Nn充电，并且由于驱动电容Cs的不可突变特性，使得驱动节点Nn的电压VNn维持在Vata-Vth。可见，第一驱动晶体管T2的阈值电压Vth随着数据电压Vdata一并写入到驱动节点Nn。
驱动单元102中第二驱动晶体管T4在高电平的发光信号En控制下处于截止状态，辅助单元105中辅助晶体管T5在高电平的扫描信号Gn控制处于截止状态，第一复位单元106中的第一复位晶体管T6与第二复位单元107中第二复位晶体管T7在扫描信号Gn-1的低电平控制下处于截止状态。
请一并参阅图5、8，图8为图4所示像素单元100在显示时间段H3电路工作状态示意图。
在显示时间段H3，发光信号En自高电平跳变为低电平，扫描信号Gn-1继续位置在低电平，扫描信号Gn自高电平跳变为低电平，图像数据Data由数据电压Vdata跳变为低电平，也即是数据信号停止写入。
由此，数据写入单元101中的写入晶体管T1在低电平的扫描信号Gn控制下处于截止状态。
驱动单元102中第二晶体管T4在低电平的发光信号En控制下处于导通状态，由此，驱动电压端Vdd的发光驱动电压ELVDD的电压传输至第一节点Ns。
第二晶体管T2中栅极电压Vdata-Vth显然小于发光驱动电压ELVDD，故而第二晶体管T2处于导通状态。
补偿单元104中补偿晶体管T3在低电平的发光信号En控制下处于截止状态，而辅助单元105中的辅助晶体管T5在低电平的扫描信号Gn控制下处于导通状态。
由此，发光驱动电压ELVDD进一步通过第二驱动晶体管T2以及辅助晶体管T5传输至显示单元103中发光二极管OLED。
与此同时，通过第二驱动晶体管T2传输至显示单元103的驱动电流为：Ids＝1/2k(Vgs-Vth)^2，其中，K＝μCox W/L，W为第二晶体管T2导电沟道的宽度，L为导电沟道的长度，也即是K是第二驱动晶体管的导电沟道尺寸、电子迁移率等相关的参数。
进一步，Vgs为VNs-VNn＝ELVDD-(Vdata-Vth)，那么Vgs-Vth＝ELVDD-(Vdata-Vth)-Vth＝ ELVDD-Vdata+Vth-Vth＝ELVDD-Vdata。
明显可见，用于显示单元103中发光二极管OLED的驱动电流Ids与第一驱动晶体管T2的阈值电压Vth没有任何关系，也即是说，通过在数据写入节点提前将第一驱动晶体管T2的阈值电压Vth写入到驱动节点Nn，从而在发光显示阶段针对第一驱动晶体管T2的阈值电压Vth进行抵消，继而从而达到补偿消除针对第一驱动晶体管T2的阈值电压Vth漂移，防止显示单元103中发光二极管OLED发光亮度收到第一驱动晶体管T2阈值电压漂移的影响而无法达到正确的亮度。
同时，还能够保证所有显示区域内所有像素单元P中显示单元103的显示不会因为不同位置的第一驱动晶体管T2在制作过程、使用过程中阈值电压Vth不同而产生的亮度不一致的曲线，也即是保证显示区域内所有像素单元P显示亮度均匀一致，而不受到第一驱动晶体管T2本身参数的影响。
第一复位单元106中的第一复位晶体管T6与第二复位单元107中第二复位晶体管T7在扫描信号Gn-1的低电平控制下处于截止状态。
请参阅图9，其为本申请第二实施例中如图2所示像素单元200的电路框图。如图9所示，本实例中像素单元200与第一实施例中像素100的电路结构以及工作原理基本相同，区别在于像素单元200未包含有第一复位单元106，也即是像素单元200仅包括数据写入单元101、驱动单元102、显示单元103、补偿单元104、辅助单元105以及第二复位单元107。
其中，数据写入单元103电性连接驱动单元101，用于在数据写入时间段H2依据第一扫描信号Gn将图像数据Data写入驱动单元101。
驱动单元102与显示单元103电性连接，用于在显示时间段H3依据接收到的发光信号En与图像数据配合提供驱动电流至显示单元103，以驱动显示单元103执行发光并且进行图像显示。显示时间段H3在数据写入时间段H2之后且不完全重叠。
补偿单元104电性连接驱动单元102，用于在数据写入时间段H2的过程中在图像数据Data写入驱动单元102时预先提供补偿电压至驱动单元102。补偿电压用于补偿在驱动单元102提供驱动电流至显示单元103时驱动单元102本身产生的电压漂移。
辅助单元105电性连接于显示单元103之间，用于在第一扫描信号Gn控制下于数据写入时间段H2处于电性截止状态，以使得显示单元103与驱动单元102电性断开，防止图像数据Data在非显示阶段传输至显示单元103而影响正确的图像显示。同时，辅助单元105在第一扫描信号Gn控制下于显示时间段H3处于导通状态，使得显示单元103与驱动单元102电性导通，已将驱动电流传输至显示单元103。
第二复位单元107电性连接于所述驱动单元102，用于在依据复位信号在复位时间段H1将复位电压Vint写入驱动单元102，使得驱动单元102处于初始驱动电压状态，以消除前一个显示阶段残留于驱动单元102内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。
具体地，如图9所示数据写入单元101包括写入晶体管T1，写入晶体管T1的栅极电性连接第一扫描驱动线Gn，写入晶体管T1的漏极电性连接其中一条数据线Dm，写入晶体管T1的源极电性连接驱动单元102中的第一节点Ns。本实施例中，写入晶体管T1为N型氧化物Oxide的薄膜晶体管TFT。
驱动单元102包括第一驱动晶体管T2、第二驱动晶体管T4以及驱动电容Cs。其中，第一驱动晶体管T2的栅极电性连接驱动节点Nn，第一驱动晶体管T2的源极电性连接第一节点Ns，第一驱动晶体管T2的漏极电性连接第二节点Nd。驱动电容Cs分别电性连接于驱动电压端Vdd与驱动节点Nn。驱动电压端Vdd用于提供显示单元103所需的发光驱动电压ELVDD，例如为4.5～5V。
第二驱动晶体管T4的栅极电性连接发光驱动线En，第二驱动晶体管T4的源极电性连接驱动电压端 Vdd，第二驱动晶体管T4的漏极电性连接第一节点Ns。
本实施例中，第一驱动晶体管T2与第二驱动晶体管T4为P型低温多晶硅(Low Temperature Poly-silicon,LTPS)的薄膜晶体管(Thin Film Transistor，TFT)。
显示单元103为有机发光二极管OLED，其中，有机发光二极管OLED的阳极电性连接显示节点Na，有机发光二极管OLED的阴极电性连接低参考电压端Vss。
补偿单元104包括补偿晶体管T3，其中，补偿晶体管T3的栅极电性连接发光驱动线En，补偿晶体管T3的源极电性连接驱动节点Nn，补偿晶体管T3的漏极电性连接第二节点Nd。本实施例中，补偿晶体管T3为N型氧化物Oxide的TFT。
辅助单元105包括辅助晶体管T5，其中，辅助晶体管T5的栅极电性连接第一扫描线Gn，辅助晶体管T5的源极电性连接第二节点Nd，辅助晶体管T5的漏极电性连接显示节点Na。本实施例中，辅助晶体管T5为P型LTPS TFT。
第二复位单元107包括第二复位晶体管T7，其中，第二复位晶体管T7的栅极电性连接第二扫描线Gn-1，第二复位晶体管T7的源极电性连接驱动节点Nn，第二复位晶体管T4的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。
本实施例中，第二复位晶体管T7为N型氧化物Oxide的TFT。
驱动单元102、辅助单元105中的晶体管均为P型的TFT，由此，显示单元103中发光二极管OLED本身的漂移不会直接影响到驱动单元102中第一、第二驱动晶体管T2、T4的源级节点电压，也就能够有效防止提供至显示单元103中的驱动电流产生漂移，具有较佳的补偿效果。
数据写入单元101、补偿单元104、第二复位单元107均采用N型TFT，由此，数据写入单元101、补偿单元104、第二复位单元107中TFT的漏电流较小，能够有效防止第一节点Ns、第二节点Nd以及发光节点Na的电压、电流受到干扰，得到较佳的保护。同时，前述节点的电压、电流保护较佳，那么就能够快速应对图像数据Data的准确写入与显示，也即是能够快速适应高、低速不同图像数据显示时的刷新率(Refresh Rate)，并且由于漏电流较小，像素单元100能够完全匹配适应低功耗模式驱动方式。
像素单元200具体的工作时序以及工作过程与像素单元100的工作时序基本相同，区别仅在于复位时间段H1(图5)中，第一复位单元106未针对显示节点Na进行复位至预设的电压，而其他薄膜晶体管TFT在对应的工作时间段的工作原理与工作时序相同，本实施例不再赘述。
在复位时间段H1(图5)，仅第二复位单元107对驱动节点Nn执行复位。具体地，补偿晶体管T3处于导通状态，第二节点Nd与驱动节点Nn的电位相同，同时，辅助晶体管T5处于导通状态，故而，驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成放电回路，电流则自驱动电接点Nn随着放电回路经过补偿晶体管T3、第二节点Nd、辅助晶体管T5、发光二极管OLED流向低参考电压端ELVSS，在此放电过程中，驱动节点Nn的电压VNn自前一次留存的电压随着放电过程会持续降低，直至达到与复位电压相同的低参考电压ELVSS。
同时，对于驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成放电回路，显示节点Ns的电压VNs自前一次留存的电压随着放电过程降低，直至复位时间段H1结束。
请参阅图10，其为本申请第三实施例中如图2所示像素单元300的电路框图。如图10所示，本实例中像素单元300与第一实施例中像素100的电路结构以及工作原理基本相同，区别在于像素单元300未包含有第二复位单元107，也即是像素单元200仅包括数据写入单元101、驱动单元102、显示单元103、补偿 单元104、辅助单元105以及第一复位单元106。
其中，数据写入单元103电性连接驱动单元101，用于在数据写入时间段H2依据第一扫描信号Gn将图像数据Data写入驱动单元101。
驱动单元102与显示单元103电性连接，用于在显示时间段H3依据接收到的发光信号En与图像数据配合提供驱动电流至显示单元103，以驱动显示单元103执行发光并且进行图像显示。显示时间段H3在数据写入时间段H2之后且不完全重叠。
补偿单元104电性连接驱动单元102，用于在数据写入时间段H2的过程中在图像数据Data写入驱动单元102时预先提供补偿电压至驱动单元102。补偿电压用于补偿在驱动单元102提供驱动电流至显示单元103时驱动单元102本身产生的电压漂移。
辅助单元105电性连接于显示单元103之间，用于在第一扫描信号Gn控制下于数据写入时间段H2处于电性截止状态，以使得显示单元103与驱动单元102电性断开，防止图像数据Data在非显示阶段传输至显示单元103而影响正确的图像显示。同时，辅助单元105在第一扫描信号Gn控制下于显示时间段H3处于导通状态，使得显示单元103与驱动单元102电性导通，已将驱动电流传输至显示单元103。
第一复位单元106电性连接显示单元103，用于依据在依据复位信号在复位时间段H1将复位电压写入所述显示单元103，使得所述显示单元处于初始显示电压状态。
具体地，如图10所示数据写入单元101包括写入晶体管T1，写入晶体管T1的栅极电性连接第一扫描驱动线Gn，写入晶体管T1的漏极电性连接其中一条数据线Dm，写入晶体管T1的源极电性连接驱动单元102中的第一节点Ns。本实施例中，写入晶体管T1为N型氧化物Oxide的薄膜晶体管(Thin Film Transistor，TFT)，具体地，N型氧化物Oxide的薄膜晶体管可以为以氧化锌(ZnO)TFT、GaZnO TFT、InZnO TFT、AlZnO TFT或者铟镓锌氧化物TFT(InGaZnO TFT，IGZO TFT)。
驱动单元102包括第一驱动晶体管T2、第二驱动晶体管T4以及驱动电容Cs。其中，第一驱动晶体管T2的栅极电性连接驱动节点Nn，第一驱动晶体管T2的源极电性连接第一节点Ns，第一驱动晶体管T2的漏极电性连接第二节点Nd。驱动电容Cs分别电性连接于驱动电压端Vdd与驱动节点Nn。驱动电压端Vdd用于提供显示单元103所需的发光驱动电压ELVDD，例如为4.5～5V。
第二驱动晶体管T4的栅极电性连接发光驱动线En，第二驱动晶体管T4的源极电性连接驱动电压端Vdd，第二驱动晶体管T4的漏极电性第一节点Ns。
本实施例中，第一驱动晶体管T2与第二驱动晶体管T4为P型低温多晶硅(Low Temperature Poly-silicon,LTPS)的薄膜晶体管(Thin Film Transistor，TFT)。
显示单元103为有机发光二极管OLED，其中，有机发光二极管OLED的阳极电性连接显示节点Na，有机发光二极管OLED的阴极电性连接低参考电压端Vss。
补偿单元104包括补偿晶体管T3，其中，补偿晶体管T3的栅极电性连接发光驱动线En，补偿晶体管T3的源极电性连接驱动节点Nn，补偿晶体管T3的漏极电性连接第二节点Nd。本实施例中，补偿晶体管T3为N型氧化物Oxide的TFT。
辅助单元105包括辅助晶体管T5，其中，辅助晶体管T5的栅极电性连接第一扫描线Gn，辅助晶体管T5的源极电性连接第二节点Nd，辅助晶体管T5的漏极电性连接显示节点Na。本实施例中，辅助晶体管T5为P型LTPS TFT。
第一复位单元106电性连接显示单元103，用于依据在依据复位信号在复位时间段H1将复位电压写入所述显示单元103，使得所述显示单元处于初始显示电压状态。
驱动单元102、辅助单元105中的晶体管均为P型的TFT，由此，显示单元103中发光二极管OLED本身的漂移不会直接影响到驱动单元102中第一、第二驱动晶体管T2、T4的源级节点电压，也就能够有效防止提供至显示单元103中的驱动电流产生漂移，具有较佳的补偿效果。
数据写入单元101、补偿单元104、第一复位单元106均采用N型TFT，由此，数据写入单元101、补偿单元104、第一复位单元106中TFT的漏电流较小，能够有效防止第一节点Ns、第二节点Nd、驱动节点Nn以及发光节点Na的电压、电流受到干扰，得到较佳的保护。同时，前述节点的电压、电流保护较佳，那么就能够快速应对图像数据Data的准确写入与显示，也即是能够快速适应高、低速不同图像数据显示时的刷新率(Refresh Rate)，并且由于漏电流较小，像素单元100能够完全匹配适应低功耗模式驱动方式。
像素单元300具体的工作时序以及工作过程与像素单元100的工作时序基本相同，区别仅在于复位时间段H1(图5)中，第二复位单元107未针对驱动节点Na进行复位至预设的电压，而其他薄膜晶体管TFT在对应的工作时间段的工作原理与工作时序相同，本实施例不再赘述。
在复位时间段H1(图5)，仅第一复位单元106对显示节点Na执行复位。具体地，补偿晶体管T3处于导通状态，第二节点Nd与驱动节点Nn的电位相同，同时，辅助晶体管T5处于导通状态，故而，驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成放电回路，电流则自驱动电接点Nn随着放电回路经过补偿晶体管T3、第二节点Nd、辅助晶体管T5、发光二极管OLED流向低参考电压端ELVSS，在此放电过程中，驱动节点Nn的电压VNn自前一次留存的电压随着放电过程降低，直至复位时间段H1结束。
同时，第一复位晶体管T6处于导通状态，复位电压端Vint提提供的复位电压输出至显示节点Na，对于驱动电容Cs通过驱动节点Nn、补偿晶体管T3、第二节点Nd、辅助晶体管T5以及发光二极管OLED构成的放电回路，显示节点Ns的电压VNs自前一次留存的电压随着放电过程会持续降低，直至达到复位电压相同的低参考电压ELVSS。
请参阅图11，其为本申请第四实施例中如图2所示像素单元400的电路框图。如图11所示，本实例中像素单元400与第一实施例中像素100的电路结构以及工作原理基本相同，区别在于像素单元400未包含有辅助单元105，也即是像素单元200仅包括数据写入单元101、驱动单元102、显示单元103、补偿单元104第一复位单元106以及第二复位单元107。
数据写入单元103电性连接驱动单元101，用于在数据写入时间段H2依据第一扫描信号Gn将图像数据Data写入驱动单元101。
驱动单元102与显示单元103电性连接，用于在显示时间段H3依据接收到的发光信号En与图像数据配合提供驱动电流至显示单元103，以驱动显示单元103执行发光并且进行图像显示。显示时间段H3在数据写入时间段H2之后且不完全重叠。
补偿单元104电性连接驱动单元102，用于在数据写入时间段H2的过程中在图像数据Data写入驱动单元102时预先提供补偿电压至驱动单元102。补偿电压用于补偿在驱动单元102提供驱动电流至显示单元103时驱动单元102本身产生的电压漂移。
第一复位单元106电性连接显示单元103，用于依据在依据复位信号在复位时间段H1将复位电压写入所述显示单元103，使得所述显示单元处于初始显示电压状态。第一复位单元106用于消除前一个显示阶段残留于显示单元103内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。
第二复位单元107电性连接于所述驱动单元102，用于在依据复位信号在复位时间段H1将复位电压 Vint写入驱动单元102，使得驱动单元102处于初始驱动电压状态，以消除前一个显示阶段残留于驱动单元102内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。其中，复位时间段T3在数据写入时间段H2之前且不完全重叠。
具体地，数据写入单元101包括写入晶体管T1，写入晶体管T1的栅极电性连接第一扫描驱动线Gn，写入晶体管T1的漏极电性连接其中一条数据线Dm，写入晶体管T1的源极电性连接驱动单元102中的第一节点Ns。本实施例中，写入晶体管T1为N型氧化物Oxide的薄膜晶体管(Thin Film Transistor，TFT)，具体地，N型氧化物Oxide的薄膜晶体管可以为以氧化锌(ZnO)TFT、GaZnO TFT、InZnO TFT、AlZnO TFT或者铟镓锌氧化物TFT(InGaZnO TFT，IGZO TFT)。
驱动单元102包括第一驱动晶体管T2、第二驱动晶体管T4以及驱动电容Cs。其中，第一驱动晶体管T2的栅极电性连接驱动节点Nn，第一驱动晶体管T2的源极电性连接第一节点Ns，第一驱动晶体管T2的漏极电性连接第二节点Nd。驱动电容Cs分别电性连接于驱动电压端Vdd与驱动节点Nn。驱动电压端Vdd用于提供显示单元103所需的发光驱动电压ELVDD，例如为4.5～5V。
第二驱动晶体管T4的栅极电性连接发光驱动线En，第二驱动晶体管T4的源极电性连接驱动电压端Vdd，第二驱动晶体管T4的漏极电性第一节点Ns。
本实施例中，第一驱动晶体管T2与第二驱动晶体管T4为P型低温多晶硅LTPS的薄膜晶体管TFT。
显示单元103为有机发光二极管OLED，其中，有机发光二极管OLED的阳极电性连接显示节点Na，有机发光二极管OLED的阴极电性连接低参考电压端Vss。
补偿单元104包括补偿晶体管T3，其中，补偿晶体管T3的栅极电性连接发光驱动线En，补偿晶体管T3的源极电性连接驱动节点Nn，补偿晶体管T3的漏极电性连接第二节点Nd。本实施例中，补偿晶体管T3为N型氧化物Oxide的TFT。
第一复位单元106包括第一复位晶体管T6，其中，第一复位晶体管T6的栅极电性连接第二扫描线Gn-1，第一复位晶体管T6的源极电性连接发光节点Na，第一复位晶体管T6的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。本实施例中，低参考电压ELVSS可以为-1.5V～0V。本实施例中，发光节点Na与第二节点Nd重叠。
第二复位单元107包括第二复位晶体管T7，其中，第二复位晶体管T7的栅极电性连接第二扫描线Gn-1，第二复位晶体管T7的源极电性连接驱动节点Nn，第二复位晶体管T4的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。
其中，第二扫描线Gn-1与第一扫描线Gn为相邻的两条扫描线，且二者在相邻的两个扫描周期输出扫描信号。
本实施例中，第一复位晶体管T6与第二复位晶体管T7为N型氧化物Oxide的TFT。
驱动单元102的晶体管均为P型的TFT，由此，显示单元103中发光二极管OLED本身的漂移不会直接影响到驱动单元102中第一、第二驱动晶体管T2、T4的源级节点电压，也就能够有效防止提供至显示单元103中的驱动电流产生漂移，具有较佳的补偿效果。
数据写入单元101、补偿单元104、第一复位单元106与第二复位单元107均采用N型TFT，由此，数据写入单元101、补偿单元104、第一复位单元106与第二复位单元107中TFT的漏电流较小，能够有效防止第一节点Ns、第二节点Nd、驱动节点Nn以及发光节点Na的电压、电流受到干扰，得到较佳的保护。同时，前述节点的电压、电流保护较佳，那么就能够快速应对图像数据Data的准确写入与显示，也即是能够快速适应高、低速不同图像数据显示时的刷新率(Refresh Rate)，并且由于漏电流较小，像素单元 100能够完全匹配适应低功耗模式驱动方式。
请参阅图12，其为本申请第五实施例中如图2所示像素单元500的电路框图。如图12所示，本实例中像素单元400与第一实施例中像素100的电路结构以及工作原理基本相同，像素单元500仅包括数据写入单元101、驱动单元102、显示单元103、补偿单元104、辅助单元105第一复位单元106以及第二复位单元107。像素单元100执行一帧图像的显示过程中包括H1-H3三个依序排列且连续无间隔的时间段，其中，H1为复位时间段，H2为数据写入时间段，H3为显示时间段。本实施例中像素单元500与第一实施例中像素单元100的区别在于数据写入单元101、补偿单元104、第一复位单元106以及第二复位单元107中可以采用P型低温多晶硅LTPS的薄膜晶体管TFT。
其中，数据写入单元103电性连接驱动单元101，用于在数据写入时间段H2依据第一扫描信号Gn将图像数据Data写入驱动单元101。
驱动单元102与显示单元103电性连接，用于在显示时间段H3依据接收到的发光信号En与图像数据配合提供驱动电流至显示单元103，以驱动显示单元103执行发光并且进行图像显示。显示时间段H3在数据写入时间段H2之后且不完全重叠。
补偿单元104电性连接驱动单元102，用于在数据写入时间段H2的过程中在图像数据Data写入驱动单元102时预先提供补偿电压至驱动单元102。补偿电压用于补偿在驱动单元102提供驱动电流至显示单元103时驱动单元102本身产生的电压漂移。
辅助单元105电性连接于显示单元103之间，用于在第一扫描信号Gn控制下于数据写入时间段H2处于电性截止状态，以使得显示单元103与驱动单元102电性断开，防止图像数据Data在非显示阶段传输至显示单元103而影响正确的图像显示。同时，辅助单元105在第一扫描信号Gn控制下于显示时间段H3处于导通状态，使得显示单元103与驱动单元102电性导通，已将驱动电流传输至显示单元103。
第一复位单元106电性连接显示单元103，用于依据在依据复位信号在复位时间段H1将复位电压写入所述显示单元103，使得所述显示单元处于初始显示电压状态。第一复位单元106用于消除前一个显示阶段残留于显示单元103内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。
第二复位单元107电性连接于所述驱动单元102，用于在依据复位信号在复位时间段H1将复位电压写入驱动单元102，使得驱动单元102处于初始驱动电压状态，以消除前一个显示阶段残留于驱动单元102内的电流、电压，保证每一个像素单元100能够在每一帧图像显示阶段准确执行图像数据的显示。其中，复位时间段T3在数据写入时间段H2之前且不完全重叠。
具体地，数据写入单元101包括写入晶体管T1，写入晶体管T1的栅极电性连接第一扫描驱动线Gn，写入晶体管T1的漏极电性连接其中一条数据线Dm，写入晶体管T1的源极电性连接驱动单元102中的第一节点Ns。
本实施例中，写入晶体管T1为P型氧化物LTPS的TFT。对应地，写入晶体管T1需要在数据写入时间段H2低电平的启动信号，也即是所述启动信号需为扫描驱动线Gn输出的低电平的扫描信号Gn。
驱动单元102包括第一驱动晶体管T2、第二驱动晶体管T4以及驱动电容Cs。其中，第一驱动晶体管T2的栅极电性连接驱动节点Nn，第一驱动晶体管T2的源极电性连接第一节点Ns，第一驱动晶体管T2的漏极电性连接第二节点Nd。驱动电容Cs分别电性连接于驱动电压端Vdd与驱动节点Nn。驱动电压端Vdd用于提供显示单元103所需的发光驱动电压ELVDD，例如为4.5～5V。
第二驱动晶体管T4的栅极电性连接发光驱动线En，第二驱动晶体管T4的源极电性连接驱动电压端 Vdd，第二驱动晶体管T4的漏极电性第一节点Ns。
本实施例中，第一驱动晶体管T2与第二驱动晶体管T4为P型低温多晶硅(Low Temperature Poly-silicon,LTPS)的薄膜晶体管(Thin Film Transistor，TFT)。
显示单元103为有机发光二极管OLED，其中，有机发光二极管OLED的阳极电性连接显示节点Na，有机发光二极管OLED的阴极电性连接低参考电压端Vss。
补偿单元104包括补偿晶体管T3，其中，补偿晶体管T3的栅极电性连接发光驱动线En，补偿晶体管T3的源极电性连接驱动节点Nn，补偿晶体管T3的漏极电性连接第二节点Nd。
本实施例中，补偿晶体管T3为N型氧化物TFT，但是补充晶体管T3的栅极单独连接至扫描发光线En，而并未与第二驱动晶体管T4的栅极并联然后再一同连接至扫描发光线En。由此，补充晶体管T3能够在数据写入时间段H2中对应发光信号En的变换仅进行控制，而不会与第二驱动晶体管T4的控制发生冲突。
本申请一变更实施例中，请参阅图13所示，其中，图13为本申请第六实施例中如图2所示像素单元的电路框图，如图13所示，补偿晶体管T3为一个P型LTPS的TFT，该P型LTPS的TFT用于有效降低漏电流，并且在数据写入时间段H2中，接收低电平的启动信号，所述启动信号可以为低电平的发光信号En。在本申请其他实施例中，补偿晶体管T3为两个串联的P型LTPS的TFT(图未示出)，该两个串联的P型LTPS的TFT用于有效降低漏电流，并且在数据写入时间段H2中，接收低电平的启动信号，所述启动信号可以为低电平发光信号En。
辅助单元105包括辅助晶体管T5，其中，辅助晶体管T5的栅极电性连接第一扫描线Gn，辅助晶体管T5的源极电性连接第二节点Nd，辅助晶体管T5的漏极电性连接显示节点Na。本实施例中，辅助晶体管T5为P型LTPS TFT。
第一复位单元106包括第一复位晶体管T6，其中，第一复位晶体管T6的栅极电性连接第二扫描线Gn-1，第一复位晶体管T6的源极电性连接发光节点Na，第一复位晶体管T6的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。本实施例中，低参考电压ELVSS可以为-1.5V～0V。
第二复位单元107包括第二复位晶体管T7，其中，第二复位晶体管T7的栅极电性连接第二扫描线Gn-1，第二复位晶体管T7的源极电性连接驱动节点Nn，第二复位晶体管T4的漏极电性连接复位电压端Vint。其中，复位电压端Vint提供低参考电压ELVSS作为复位电压。
本实施例中，第一复位晶体管T6与第二复位晶体管T7亦可采用P型LTPS的TFT或者N型氧化物的TFT。对应地，当第一复位晶体管T6与第二复位晶体管T7为P型LTPS的TFT时，第一复位晶体管T6与第二复位晶体管T7需要在复位时间段H1采用低电平的启动信号，也即是所述启动信号需为扫描驱动线Gn-1输出的低电平的扫描信号Gn。
当第一复位单元106与第二复位单元107中TFT为N型氧化物的TFT时，漏电流较小，能够有效防止第一节点Ns、第二节点Nd、驱动节点Nn以及发光节点Na的电压、电流受到干扰，得到较佳的保护。同时，前述节点的电压、电流保护较佳，那么就能够快速应对图像数据Data的准确写入与显示，也即是能够快速适应高、低速不同图像数据显示时的刷新率(Refresh Rate)，并且由于漏电流较小，像素单元100能够完全匹配适应低功耗模式驱动方式。
驱动单元102、辅助单元105中的晶体管均为P型的TFT，由此，显示单元103中发光二极管OLED本身的漂移不会直接影响到驱动单元102中第一、第二驱动晶体管T2、T4的源级节点电压，也就能够有效防止提供至显示单元103中的驱动电流产生漂移，具有较佳的补偿效果。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (28)

  1. 一种像素单元，其特征在于，包括：驱动单元、补偿单元、数据写入单元以及显示单元，其中：
    所述数据写入单元电性连接所述驱动单元，用于在数据写入时间段依据第一扫描信号将图像数据写入所述驱动单元；
    所述驱动单元与显示单元电性连接，用于在显示时间段依据接收到的发光信号与所述图像数据提供驱动电流至所述显示单元，以驱动所述显示单元执行图像显示，
    所述补偿单元电性连接所述驱动单元，用于在图像数据写入所述驱动单元时预先提供补偿电压至所述驱动单元，所述补偿电压用于补偿在所述驱动单元提供驱动电流至显示单元时所述驱动单元产生的电压漂移；
    其中，所述驱动单元包括至少一个P型晶体管，所述数据写入单元以及所述补偿单元中至少包括一个N型晶体管。
  2. 根据权利要求1所述的像素单元，其特征在于，所述显示时间段在所述数据写入时间段之后且不完全重叠。
  3. 根据权利要求2所述的像素单元，其特征在于，所述驱动单元包括第一驱动晶体管、第二驱动晶体管以及驱动电容，其中，
    所述第一驱动晶体管的栅极电性连接驱动节点，所述第一驱动晶体管的源极电性连接第一节点，所述第一驱动晶体管的漏极电性连接第二节点；
    驱动电容分别电性连接于驱动电压端与所述驱动节点，所述驱动电压端用于提供所述显示单元显示所需的发光驱动电压；
    所述第二驱动晶体管的栅极电性连接发光驱动线以接收发光信号，所述第二驱动晶体管的源极电性连接所述驱动电压端，所述第二驱动晶体管的漏极电性所述第一节点。
  4. 根据权利要求3所述的像素单元，其特征在于，所述第一驱动晶体管与第二驱动晶体管为P型低温多晶硅的薄膜晶体管。
  5. 根据权利要求4所述的像素单元，其特征在于，所述补偿单元包括补偿晶体管，所述补偿晶体管的栅极电性连接所述发光驱动线，所述补偿晶体管的源极电性连接所述驱动节点，所述补偿晶体管的漏极电性连接所述第二节点，所述补偿晶体管用于在数据写入时间段在所述发光信号控制下处于导通状态，以将所述补偿电压存储至所述驱动节点。
  6. 根据权利要求5所述的像素单元，其特征在于，所述补偿晶体管为N型氧化物薄膜晶体管，且所述补偿晶体管在数据写入时间段接收自发光驱动线输出的高电平的发光信号并处于导通状态。
  7. 根据权利要求5所述的像素单元，其特征在于，所述补偿晶体管包括P型低温多晶硅的薄膜晶体管，且所述补偿晶体管在数据写入时间段接收自发光驱动线输出的低电平的发光信号以处于导通状态。
  8. 根据权利要求5所述的像素单元，其特征在于，所述补偿单元包括两个串联的P型低温多晶硅的薄膜晶体管。
  9. 根据权利要求5所述的像素单元，其特征在于，所述数据写入单元包括写入晶体管，写入晶体管的栅极电性连接第一扫描驱动线，写入晶体管的漏极电性连接其中一条数据线用于接收图像数据，所述写入晶体管的源极电性连接所述第一节点，在所述数据写入时间段时所述写入晶体管在所述第一扫描驱动线输出的扫描信号下处于导通状态，以将所述图像数据写入所述驱动节点。
  10. 根据权利要求9所述的像素单元，其特征在于，所述写入晶体管为N型氧化物薄膜晶体管，且 所述写入晶体管在数据写入时间段接收自所述第一扫描线输出的高电平的扫描信号并处于导通状态。
  11. 根据权利要求9所述的像素单元，其特征在于，所述写入晶体管为P型低温多晶硅薄膜晶体管，且所述写入晶体管在数据写入时间段接收自所述第一扫描线输出的低电平的扫描信号并处于导通状态。
  12. 根据权利要求9所述的像素单元，其特征在于，所述像素单元还包括辅助单元，所述辅助单元电性连接于所述驱动单元与所述显示单元之间，用于在所述第一扫描信号控制下于所述数据写入时间段处于电性截止状态，使得所述显示单元与所述驱动单元电性断开；并且在第一扫描信号控制下于所述显示时间段处于导通状态，使得所述显示单元与所述驱动单元电性导通，并且将驱动电流与图像数据传输至所述显示单元执行图像显示。
  13. 根据权利要求12所述的像素单元，其特征在于，所述辅助单元包括辅助晶体管，所述辅助晶体管T栅极电性连接所述第一扫描线，所述辅助晶体管的源极电性连接所述第二节点，所述辅助晶体管的漏极电性连接显示节点，在所述显示时间段所述辅助晶体管在所述第一扫描线输出的扫描信号下处于导通状态。
  14. 根据权利要求13所述的像素单元，其特征在于，所述辅助晶体管为P型低温多晶硅薄膜晶体管，且所述辅助晶体管在显示时间段接收自所述第一扫描线输出的低电平的扫描信号且处于导通状态，在所述数据写入时间段接收自所述第一扫描线输出的高电平的扫描信号以处于截止状态。
  15. 根据权利要求13所述的像素单元，其特征在于，所述像素单元还包括第一复位单元，所述第一复位单元电性连接所述显示单元，用于依据在所述复位时间段将复位电压写入所述显示单元，使得所述显示单元处于初始显示电压状态，所述复位时间段在所述显示时间段之前且不完全重叠。
  16. 根据权利要求13所述的像素单元，其特征在于，所述像素驱动电路包括第二复位单元，所述第二复位单元电性连接于所述驱动单元，用于在复位时间段将复位电压写入所述驱动单元，使得所述驱动单元处于初始驱动电压状态，所述复位时间段在所述显示时间段之前且不完全重叠。
  17. 根据权利要求13所述的像素单元，其特征在于，所述像素驱动电路包括第一复位单元与第二复位单元，其中，
    所述第一复位单元电性连接所述显示单元，用于依据在所述复位时间段将复位电压写入所述显示单元，使得所述显示单元处于初始显示电压状态；
    所述第二复位单元电性连接于所述驱动单元，用于在复位时间段将复位电压写入所述驱动单元，使得所述驱动单元处于初始驱动电压状态；
    所述复位时间段在所述显示时间段之前且不完全重叠。
  18. 根据权利要求9所述的像素单元，其特征在于，所述像素驱动电路包括第一复位单元与第二复位单元，其中，
    所述第一复位单元电性连接所述显示单元，用于在复位时间段将复位电压写入所述显示单元，使得所述显示单元处于初始显示电压状态；
    所述第二复位单元电性连接于所述驱动单元，用于在复位时间段将复位电压写入所述驱动单元，使得所述驱动单元处于初始驱动电压状态；
    所述复位时间段在所述显示时间段之前且不完全重叠。
  19. 根据权利要求15-18任意一项所述的像素单元，其特征在于，
    所述第一复位单元包括第一复位晶体管，所述第一复位晶体管的栅极电性连接第二扫描线，所述第一复位晶体管的源极电性连接发光节点，所述第一复位晶体管的漏极电性连接复位电压端，在所述复位 时间段根据所述第二扫描线输出的扫描信号的控制处于导通状态，将所述复位电压端提供的所述复位电压传输至所述显示单元。
  20. 根据权利要求19所述的像素单元，其特征在于，所述复位电压端提供低参考电压作为所述复位电压，所述低参考电电压的范围为-1.5V～0V。
  21. 根据权利要求19所述的像素单元，其特征在于，所述第一复位晶体管为N型氧化物的薄膜晶体管，且在所述复位时间段自所述第二扫描线输出的高电平的扫描信号并处于导通状态，在所述数据写入时间段与所述显示时间段自所述第二扫描线输出的低电平的扫描信号且处于截止状态。
  22. 根据权利要求19所述的像素单元，其特征在于，所述第一复位晶体管为P型低温多晶硅薄膜晶体管，且在所述复位时间段自所述第二扫描线输出的低电平的扫描信号且处于导通状态，在所述数据写入时间段与所述显示时间段自所述第二扫描线输出的高电平的扫描信号且处于截止状态。
  23. 根据权利要求15-18任意一项所述的像素单元，其特征在于，所述第二复位单元包括第二复位晶体管，所述第二复位晶体管的栅极电性连接第二扫描线，所述第二复位晶体管的源极电性连接驱动节点，所述第二复位晶体管的漏极电性连接复位电压端，在所述复位时间段根据所述第二扫描线输出的扫描信号的控制处于导通状态，将所述复位电压端提供的所述复位电压传输至所述显示单元。
  24. 根据权利要求23所述的像素单元，其特征在于，所述复位电压端提供低参考电压作为复位电压，所述低参考电压的范围为-1.5V～0V。
  25. 根据权利要求24所述的像素单元，其特征在于，所述第二复位晶体管为N型氧化物的薄膜晶体管，且在所述复位时间段自所述第二扫描线输出的高电平的扫描信号且处于导通状态，在所述数据写入时间段与所述显示时间段自所述第二扫描线输出的低电平的扫描信号且处于截止状态。
  26. 根据权利要求24所述的像素单元，其特征在于，所述第二复位晶体管为P型低温多晶硅薄膜晶体管，且在所述复位时间段自所述第二扫描线输出的低电平的扫描信号以处于导通状态，在所述数据写入时间段与所述显示时间段自所述第二扫描线输出的高电平的扫描信号且处于截止状态。
  27. 一种阵列基板，其特征在于，包括位于显示区内的多个用于执行图像显示的如权利要求1-25项任意一项的像素单元。
  28. 一种显示终端，其特征在于，包括权利要求27所述的阵列基板。
PCT/CN2019/095748 2019-07-12 2019-07-12 像素单元、阵列基板与显示终端 WO2021007694A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2019/095748 WO2021007694A1 (zh) 2019-07-12 2019-07-12 像素单元、阵列基板与显示终端
CN201980090107.0A CN113366562A (zh) 2019-07-12 2019-07-12 像素单元、阵列基板与显示终端

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/095748 WO2021007694A1 (zh) 2019-07-12 2019-07-12 像素单元、阵列基板与显示终端

Publications (1)

Publication Number Publication Date
WO2021007694A1 true WO2021007694A1 (zh) 2021-01-21

Family

ID=74210087

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/095748 WO2021007694A1 (zh) 2019-07-12 2019-07-12 像素单元、阵列基板与显示终端

Country Status (2)

Country Link
CN (1) CN113366562A (zh)
WO (1) WO2021007694A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113009741A (zh) * 2021-03-09 2021-06-22 北海惠科光电技术有限公司 一种阵列基板、显示面板及其制作方法
CN113808532A (zh) * 2021-08-25 2021-12-17 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114842806A (zh) * 2022-04-29 2022-08-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN114974126A (zh) * 2022-06-29 2022-08-30 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832229A (zh) * 2012-08-31 2012-12-19 京东方科技集团股份有限公司 发光器件的像素电路及驱动方法和显示装置
CN104050917A (zh) * 2014-06-09 2014-09-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN104361857A (zh) * 2014-11-04 2015-02-18 深圳市华星光电技术有限公司 有机发光显示器像素驱动电路
CN104916257A (zh) * 2015-07-15 2015-09-16 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN106652913A (zh) * 2016-12-13 2017-05-10 上海天马有机发光显示技术有限公司 一种像素驱动电路、显示面板、显示设备和像素驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004361737A (ja) * 2003-06-05 2004-12-24 Nippon Hoso Kyokai <Nhk> 有機発光ダイオード駆動回路及びそれを用いたディスプレイ装置
CN105096831B (zh) * 2015-08-21 2018-03-27 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN107452331B (zh) * 2017-08-25 2023-12-05 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN109523956B (zh) * 2017-09-18 2022-03-04 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109599062A (zh) * 2017-09-30 2019-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107863069B (zh) * 2017-12-14 2024-04-26 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832229A (zh) * 2012-08-31 2012-12-19 京东方科技集团股份有限公司 发光器件的像素电路及驱动方法和显示装置
CN104050917A (zh) * 2014-06-09 2014-09-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN104361857A (zh) * 2014-11-04 2015-02-18 深圳市华星光电技术有限公司 有机发光显示器像素驱动电路
CN104916257A (zh) * 2015-07-15 2015-09-16 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN106652913A (zh) * 2016-12-13 2017-05-10 上海天马有机发光显示技术有限公司 一种像素驱动电路、显示面板、显示设备和像素驱动方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113009741A (zh) * 2021-03-09 2021-06-22 北海惠科光电技术有限公司 一种阵列基板、显示面板及其制作方法
CN113009741B (zh) * 2021-03-09 2022-07-08 北海惠科光电技术有限公司 一种阵列基板、显示面板及其制作方法
CN113808532A (zh) * 2021-08-25 2021-12-17 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN113808532B (zh) * 2021-08-25 2022-09-27 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114842806A (zh) * 2022-04-29 2022-08-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN114842806B (zh) * 2022-04-29 2023-12-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN114974126A (zh) * 2022-06-29 2022-08-30 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置

Also Published As

Publication number Publication date
CN113366562A (zh) 2021-09-07

Similar Documents

Publication Publication Date Title
US11574588B2 (en) Pixel driving circuit and driving method thereof and display device
US10700146B2 (en) Pixel and organic light-emitting display device having the same
CN110660360B (zh) 像素电路及其驱动方法、显示面板
US10354592B2 (en) AMOLED pixel driver circuit
US20190259785A1 (en) Pixel circuit of active-matrix light-emitting diode comprising oxide semiconductor transistor and silicon semiconductor transistor and display panel having the same
US11670221B2 (en) Display panel and display device with bias adjustment
WO2018045667A1 (zh) Amoled像素驱动电路及驱动方法
WO2021007694A1 (zh) 像素单元、阵列基板与显示终端
WO2019037499A1 (zh) 像素电路及其驱动方法、显示装置
US9548024B2 (en) Pixel driving circuit, driving method thereof and display apparatus
CN108777131B (zh) Amoled像素驱动电路及驱动方法
WO2018094954A1 (zh) 一种像素电路及其驱动方法、显示装置
WO2015188533A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
CN108389551B (zh) 一种像素电路及其驱动方法、显示装置
US11798473B2 (en) Pixel driving circuit and display panel
US20210193036A1 (en) Pixel unit, array substrate and display terminal
US20210193046A1 (en) Pixel unit, display panel and electronic device
WO2016119305A1 (zh) Amoled像素驱动电路及像素驱动方法
CN107369412B (zh) 一种像素电路及其驱动方法、显示装置
US20240194122A1 (en) Pixel compensation circuit, display panel, and pixel compensation method
EP4336486A1 (en) Pixel driving circuit and display panel
WO2023005597A1 (zh) 像素驱动电路及显示面板
US10276097B2 (en) Pixel circuit, driving circuit, array substrate and display device
WO2020177258A1 (zh) 像素驱动电路及显示面板
CN113096594A (zh) 像素电路、阵列基板与显示终端

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19937809

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19937809

Country of ref document: EP

Kind code of ref document: A1