WO2020206857A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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WO2020206857A1
WO2020206857A1 PCT/CN2019/095642 CN2019095642W WO2020206857A1 WO 2020206857 A1 WO2020206857 A1 WO 2020206857A1 CN 2019095642 W CN2019095642 W CN 2019095642W WO 2020206857 A1 WO2020206857 A1 WO 2020206857A1
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Prior art keywords
transistor
electrically connected
potential
node
control signal
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PCT/CN2019/095642
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English (en)
French (fr)
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蔡玉莹
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020206857A1 publication Critical patent/WO2020206857A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, and low power consumption, and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, which occupies a large area during layout design, which is not conducive to the design of high PPI (Pixels Per Inch, pixel density) display panels.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problem that the compensation structure of the existing pixel driving circuit is relatively complicated and a large area is occupied when designing the layout.
  • An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to the first control signal, the source of the third transistor is electrically connected to the drain of the fourth transistor, and the drain of the third transistor is electrically connected Connected to the second node;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the source of the fourth transistor is electrically connected to the reference signal;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage;
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor; the light emitting device is an organic light emitting diode.
  • the combination of the first control signal, the reference signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the reference signal includes A first potential and a second potential, the first potential is smaller than the second potential, and the data signal includes a reference low potential and a display high potential.
  • the potential of the second control signal remains unchanged during the threshold voltage phase, the data voltage acquisition phase, and the light emitting phase, and the potential of the second control signal Equal to the second potential.
  • the first control signal is a high potential
  • the reference signal is the first potential
  • the data signal is the reference low potential .
  • the first control signal is a high potential
  • the reference signal is the second potential
  • the data signal is changed from the reference low potential. Jump to the display high potential.
  • the first control signal is a low potential
  • the reference signal is the second potential
  • the data signal is the reference low potential
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to the first control signal, the source of the third transistor is electrically connected to the drain of the fourth transistor, and the drain of the third transistor is electrically connected Connected to the second node;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the source of the fourth transistor is electrically connected to the reference signal;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the reference signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the reference signal includes A first potential and a second potential, the first potential is smaller than the second potential, and the data signal includes a reference low potential and a display high potential.
  • the potential of the second control signal remains unchanged during the threshold voltage phase, the data voltage acquisition phase, and the light emitting phase, and the potential of the second control signal Equal to the second potential.
  • the first control signal is a high potential
  • the reference signal is the first potential
  • the data signal is the reference low potential .
  • the first control signal is a high potential
  • the reference signal is the second potential
  • the data signal is changed from the reference low potential. Jump to the display high potential.
  • the first control signal is a low potential
  • the reference signal is the second potential
  • the data signal is the reference low potential
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light-emitting device is an organic light-emitting diode.
  • An embodiment of the present application also provides a display panel, which includes a pixel drive circuit, and the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to the first control signal, the source of the third transistor is electrically connected to the drain of the fourth transistor, and the drain of the third transistor is electrically connected Connected to the second node;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the source of the fourth transistor is electrically connected to the reference signal;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the reference signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the reference signal includes a first A potential and a second potential, the first potential is smaller than the second potential, and the data signal includes a reference low potential and a display high potential.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light emitting device is an organic light emitting diode.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. Among them, the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C, and a light emitting device OLED.
  • the light emitting device OLED may be Organic light emitting diodes. That is, the embodiment of the present application adopts a pixel driving circuit with a 4T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, has a simple and stable structure, and saves costs.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node g
  • the source of the first transistor T1 is electrically connected to the first power supply voltage Vdd
  • the drain of the first transistor T1 is electrically connected to the second node s
  • the gate of the second transistor T2 is electrically connected to the first control signal S1
  • the source of the second transistor T2 is electrically connected to the data signal D
  • the drain of the second transistor T2 is electrically connected to the first node g.
  • the gate of the third transistor T3 is electrically connected to the first control signal S1
  • the source of the third transistor T3 is electrically connected to the drain of the fourth transistor T4, and the drain of the third transistor T3 is electrically connected to the second node s.
  • the gate of the fourth transistor T4 is electrically connected to the second control signal S2, and the source of the fourth transistor T4 is electrically connected to the reference signal T.
  • the first end of the capacitor C is electrically connected to the first node g, and the second end of the capacitor C is electrically connected to the second node s.
  • the anode terminal of the light emitting device OLED is electrically connected to the second node s, and the cathode terminal of the light emitting device OLED is electrically connected to the second power supply voltage Vss.
  • the voltage value of the first power supply voltage Vdd is greater than the voltage value of the second power supply voltage Vss.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal S1, the reference signal T, and the data signal D sequentially corresponds to the threshold voltage acquisition phase t1, the data voltage acquisition phase t2, and the light-emitting phase t3.
  • the reference signal T includes a first potential V1 and a second potential Vh, and the first potential V1 is smaller than the second potential Vh.
  • the data signal D includes a reference low potential Vref and a display high potential Vdata.
  • the potential of the second control signal S2 in the threshold voltage phase, the data voltage acquisition phase t2, and the light-emitting phase t3 remains unchanged, and the potential Vr of the second control signal S2 is equal to the second potential Vh.
  • the first control signal S1 is at a high potential
  • the reference signal T is at the first potential V1
  • the data signal D is at a reference low potential Vref.
  • the first control signal S1 is at a high potential
  • the reference signal T is at the second potential Vh
  • the data signal D jumps from the reference low potential Vref to the display high potential Vdata.
  • the first control signal S1 is at a low potential
  • the reference signal T is at the second potential Vh
  • the data signal D is at the reference low potential Vref.
  • FIG. 3 is a schematic diagram of the path of the threshold voltage obtaining stage t1 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal S1 is at a high potential
  • the potential Vr of the second control signal S2 is equal to the second potential Vh
  • the second potential Vh is at a high potential.
  • the reference signal T is the first potential V1, that is, at this time, the gate potential of the fourth transistor T4 is greater than the source potential of the fourth transistor T4, and the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on.
  • the data signal D is the reference low potential Vref
  • the reference signal T is the first potential V1. That is, at this time, the reference low potential Vref of the data signal D is output to the first node g, and the first potential V1 of the reference signal T is output to the first node g.
  • the reference low potential Vref of the data signal D, the potential of the second control signal S2, and the first potential V1 of the reference signal T should be set to ensure that the fourth transistor T4 works in the saturation region, and the light-emitting device OLED Close at this time.
  • the reference low potential Vref of the data signal D, the potential of the second control signal S2, and the first potential V1 of the reference signal T can be set by the following formula:
  • Vr>Vl+Vth4 Where Vr is the potential Vr of the second control signal S2, Vl is the first potential Vl of the reference signal T, Vth4 is the threshold voltage of the fourth transistor T4, Vref is the reference low potential Vref of the data signal D, and Vth1 is the first transistor
  • the threshold voltage of T1 ⁇ 1 is the carrier mobility of the first transistor T1
  • (W/L) 1 is the ratio of the width to the length of the channel of the first transistor T1
  • ⁇ 4 is the carrier mobility of the fourth transistor T4
  • (W/L) 4 is the ratio of the width to the length of the channel of the fourth transistor T4
  • Voled is the turn-on voltage of the light-emitting device OLED.
  • the current flowing through the first transistor T1 and the fourth transistor T4 can be set according to the following formula:
  • I 1 1/2Cox ⁇ 1 (W/L) 1 (Vref-Vs-Vth1) 2 , where I 1 is the current flowing through the first transistor T1, ⁇ 1 is the carrier mobility of the first transistor T1, ( W/L) 1 is the ratio of the width to the length of the channel of the first transistor T1, Vref is the reference low potential Vref of the data signal D, Vs is the potential of the second node s, and Vth1 is the threshold voltage of the first transistor T1.
  • I 4 1/2Cox ⁇ 4 (W/L) 4 (Vr-Vl-Vth4) 2 , where I 4 is the current flowing through the fourth transistor T4, ⁇ 4 is the carrier mobility of the fourth transistor T4, ( W/L) 4 is the ratio of the channel width to the length of the fourth transistor T4, Vr is the potential of the second control signal S2, Vl is the first potential V1 of the reference signal T, and Vth4 is the threshold voltage of the first transistor T1.
  • the potential of the second node s at this time can be calculated by the above two formulas:
  • FIG. 4 is a schematic diagram of the data voltage acquisition phase t2 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2. 2 and 4, in the data voltage acquisition phase t2, the first control signal S1 is high, the second control signal S2 is equal to the second potential Vh, and the second potential Vh is high, the reference signal T It is the second potential Vh potential, that is, at this time, the gate potential of the fourth transistor T4 is equal to the source potential of the fourth transistor T4, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4 is turned off.
  • the data signal D jumps from the reference low potential Vref to the display high potential Vdata, that is, at this time, the potential of the first node g jumps to the display high potential Vdata of the data signal D. Due to the coupling effect of the capacitor C, the potential of the second node s also changes accordingly.
  • Vdata is the display high potential of the data signal D Vdata
  • Vref is the reference low potential Vref of the data signal D
  • Vs is the potential of the second node s
  • Vth1 is the threshold voltage of the first transistor T1
  • ⁇ 4 is The carrier mobility of the fourth transistor T4, (W/L) 4 is the ratio of the width to the length of the channel of the fourth transistor T4, Vr is the potential of the second control signal S2, and Vl is the first potential of the reference signal T V1 and Vth4 are the threshold voltages of the first transistor T1, and ⁇ V is the influence
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase t3 under the driving timing shown in FIG. 2.
  • the first control signal S1 is at a low potential
  • the reference signal T is at the second potential Vh
  • the data signal D is at the reference low potential Vref
  • the potential of the second control signal S2 is equal to the first At the second potential Vh
  • the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, and the fourth transistor T4 is in a nearly unbiased state. That is, at this time, the threshold voltage of the fourth transistor T4 may be equal to zero for myopia. Due to the storage effect of the capacitor C, the voltage difference between the potential of the first node g and the potential of the second node s remains unchanged.
  • the pressure difference between the first node g and the second node s can be obtained according to the following formula: Among them, V g is the potential of the first node g, V s is the potential of the second node s, ⁇ 1 is the carrier mobility of the first transistor T1, and (W/L) 1 is the channel of the first transistor T1
  • Vdata is the display high potential of the data signal D Vdata
  • Vref is the reference low potential Vref of the data signal D
  • Vs is the potential of the second node s
  • Vth1 is the threshold voltage of the first transistor T1
  • ⁇ 4 is The carrier mobility of the fourth transistor T4, (W/L) 4 is the ratio of the width to the length of the channel of the fourth transistor T4, Vr is the potential of the second control signal S2, and Vl is the first potential of the reference signal T V1 and Vth4 are the threshold voltages of the first transistor T1, and ⁇ V is the influence of the high potential Vdata on
  • the threshold voltage of the fourth transistor T4 can be ignored during the light-emitting phase t3
  • the voltage difference between the first node g and the second node s can be obtained according to the following formula:
  • I OLED 1/2Cox ⁇ 1 (W/L) 1 (Vgs-Vth1) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ 1 is the carrier mobility of the first transistor T1, (W/L ) 1 is the ratio of the width to the length of the channel of the first transistor T1, and Vth1 is the threshold voltage of the first transistor T1.
  • ⁇ 1 is the carrier mobility of the first transistor T1
  • W/L ) 1 is the ratio of the width to the length of the channel of the first transistor T1
  • Vth1 is the threshold voltage of the first transistor T1.
  • the current of the light-emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.

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Abstract

本申请实施例提供的像素驱动电路及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计。
技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积的技术问题。
技术解决方案
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接 于所述第二节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压；
流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
在本申请所述的像素驱动电路中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
在本申请所述的像素驱动电路中，所述第二控制信号在所述阈值电压阶段、所述数据电压获取阶段以及所述发光阶段的电位保持不变，且所述第二控制信号的电位等于所述第二电位。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第一电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第二电位，所述数据信号由所述参考低电位跳变至所述显示高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述参考信号为所述第二电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的 源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。
在本申请所述的像素驱动电路中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
在本申请所述的像素驱动电路中，所述第二控制信号在所述阈值电压阶段、所述数据电压获取阶段以及所述发光阶段的电位保持不变，且所述第二控制信号的电位等于所述第二电位。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第一电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第二电位，所述数据信号由所述参考低电位跳变至所述显示高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述参考信号为所述第二电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的像素驱动电路中，所述发光器件为有机发光二极管。
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素驱动 电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。
在本申请所述的显示面板中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
在本申请所述的显示面板中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的显示面板中，所述发光器件为有机发光二极管。
有益效果
本申请实施例提供的像素驱动电路及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的 一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的时序图；
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段的通路示意图；
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段的通路示意图；
图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、电容C以及发光器件OLED，发光器件OLED可以为有机发光二极管。也即，本申请实施例采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为 驱动晶体管。
其中，第一晶体管T1的栅极电性连接于第一节点g，第一晶体管T1的源极电性连接于第一电源电压Vdd，第一晶体管T1的漏极电性连接于第二节点s。第二晶体管T2的栅极电性连接于第一控制信号S1，第二晶体管T2的源极电性连接于数据信号D，第二晶体管T2的漏极电性连接于第一节点g。第三晶体管T3的栅极电性连接于第一控制信号S1，第三晶体管T3的源极电性连接于第四晶体管T4的漏极，第三晶体管T3的漏极电性连接于第二节点s。第四晶体管T4的栅极电性连接于第二控制信号S2，第四晶体管T4的源极电性连接于参考信号T。电容C的第一端电性连接于第一节点g，电容C的第二端电性连接于第二节点s。发光器件OLED的阳极端电性连接于第二节点s，发光器件OLED的阴极端电性连接于第二电源电压Vss。在本申请实施例中，第一电源电压Vdd的电压值大于第二电源电压Vss的电压值。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，第一控制信号S1、参考信号T以及数据信号D相组合先后对应于阈值电压获取阶段t1、数据电压获取阶段t2以及发光阶段t3。参考信号T包括第一电位Vl和第二电位Vh，第一电位Vl小于第二电位Vh。数据信号D包括参考低电位Vref和显示高电位Vdata。
需要说明的是，在本申请实施例中，第二控制信号S2在阈值电压阶段、数据电压获取阶段t2以及发光阶段t3的电位保持不变，且第二控制信号S2的电位Vr等于第二电位Vh。
在一些实施例中，在阈值电压获取阶段t1，第一控制信号S1为高电位，参考信号T为第一电位Vl，数据信号D为参考低电位Vref。
在一些实施例中，在数据电压获取阶段t2，第一控制信号S1为高电位，参考信号T为第二电位Vh，数据信号D由参考低电位Vref跳变至显示高电位Vdata。
在一些实施例中，在发光阶段t3，第一控制信号S1为低电位，参考信号T 为第二电位Vh，数据信号D为参考低电位Vref。
具体的，请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段t1的通路示意图。首先，结合图2、图3所示，在阈值电压获取阶段t1，第一控制信号S1为高电位，第二控制信号S2的电位Vr等于第二电位Vh，且第二电位Vh为高电位，参考信号T为第一电位Vl，也即，此时，第四晶体管T4的栅极电位大于第四晶体管T4的源极电位，第二晶体管T2、第三晶体管T3以及第四晶体管T4打开。数据信号D为参考低电位Vref，参考信号T为第一电位Vl，也即，此时，数据信号D的参考低电位Vref输出至第一节点g，参考信号T的第一电位Vl输出至第二节点s。
在该阈值电压获取阶段t1，第一节点g的电位可以根据以下公式进行设置：V g＝Vref，其中，V g为第一节点g的电位，Vref为数据信号D的参考低电位Vref。
在该阈值电压获取阶段t1，数据信号D的参考低电位Vref、第二控制信号S2的电位以及参考信号T的第一电位Vl应设置成保证第四晶体管T4工作在饱和区，且发光器件OLED此时关闭。具体的，可以通过以下公式设置数据信号D的参考低电位Vref、第二控制信号S2的电位以及参考信号T的第一电位Vl：
Vr>Vl+Vth4，
Figure PCTCN2019095642-appb-000001
其中，Vr为第二控制信号S2的电位Vr，Vl为参考信号T的第一电位Vl，Vth4为第四晶体管T4的阈值电压，Vref为数据信号D的参考低电位Vref，Vth1为第一晶体管T1的阈值电压，μ1为第一晶体管T1的载流子迁移率，(W/L) 1为第一晶体管T1沟道的宽度和长度的比值，μ4为第四晶体管T4的载流子迁移率，(W/L) 4为第四晶体管T4沟道的宽度和长度的比值，Voled为发光器件OLED的开启电压。
另外，由于此时第二晶体管T2、第三晶体管T3以及第四晶体管T4打开，故此时流经第一晶体管T1和第四晶体管T4的电流相等。具体，流经第一晶体管T1的电流以及流经第四晶体管T4的电流可以根据以下公式进行设置：
I 1＝1/2Coxμ 1(W/L) 1(Vref-Vs－Vth1) 2，其中I 1为流经第一晶体管T1的电流，μ 1为第一晶体管T1的载流子迁移率，(W/L) 1为第一晶体管T1沟道的宽度和长度的比值，Vref为数据信号D的参考低电位Vref，Vs为第二节点s的电位，Vth1为第一晶体管T1的阈值电压。
I 4＝1/2Coxμ 4(W/L) 4(Vr-Vl－Vth4) 2，其中I 4为流经第四晶体管T4的电流，μ 4为第四晶体管T4的载流子迁移率，(W/L) 4为第四晶体管T4沟道的宽度和长度的比值，Vr为第二控制信号S2的电位，Vl为参考信号T的第一电位Vl，Vth4为第一晶体管T1的阈值电压。
也即，通过以上两个公式可以计算此时第二节点s的电位：
Figure PCTCN2019095642-appb-000002
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段t2的通路示意图。结合图2、图4所示，在数据电压获取阶段t2，第一控制信号S1为高电位，第二控制信号S2的电位等于第二电位Vh，且第二电位Vh为高电位，参考信号T为第二电位Vh电位，也即，此时，第四晶体管T4的栅极电位等于第四晶体管T4的源极电位，第二晶体管T2、第三晶体管T3打开、第四晶体管T4关闭。数据信号D由参考低电位Vref跳变至显示高电位Vdata，也即，此时，第一节点g的电位跳变为数据信号D的显示高电位Vdata。由于电容C耦合效应，第二节点s的电位也相应发生变化。
在该数据电压获取阶段t2，第一节点g的电位和第二节点s的电位可以根据以下公式进行设置：V g＝Vdata，
Figure PCTCN2019095642-appb-000003
其中，V g为第一节点g的电位，V s为第二节点s的电位，μ 1为第一晶体管T1的载流子迁移率，(W/L) 1为第一晶体管T1沟道的宽度和长度的比值，Vdata为数据信号D的显示高电位Vdata、Vref为数据信号D的参考低电位Vref，Vs为第二节点s的电位，Vth1为第一晶体管T1的阈值电压，μ 4为第四晶体管T4的载流子迁移率，(W/L) 4为第四晶体管T4沟道的宽度和长度的比值，Vr为第二控制信号S2的电位，Vl为参考信号T的第一电位Vl，Vth4为第一晶体管T1的阈值电压，ΔV为显示高电位Vdata对第二节点s的电位所产生的影响。
最后，请参阅图5，图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段t3的通路示意图。结合图2、图5所示，在发光阶段t3，第一控制信号S1为低电位，参考信号T为第二电位Vh，数据信号D为参考低电位Vref，第二控制信号S2的电位等于第二电位Vh，此时，第二晶体管T2、第三晶体管T3以及第四晶体管T4关闭，且第四晶体管T4处于接近无偏置状 态。也即，此时，第四晶体管T4的阈值电压可近视等于零。由于电容C的存储作用，第一节点g的电位与第二节点s的电位之间的压差保持不变。
在该发光阶段t3，第一节点g与第二节点s之间的压差可根据以下公式获得：
Figure PCTCN2019095642-appb-000004
其中，V g为第一节点g的电位，V s为第二节点s的电位，μ 1为第一晶体管T1的载流子迁移率，(W/L) 1为第一晶体管T1沟道的宽度和长度的比值，Vdata为数据信号D的显示高电位Vdata、Vref为数据信号D的参考低电位Vref，Vs为第二节点s的电位，Vth1为第一晶体管T1的阈值电压，μ 4为第四晶体管T4的载流子迁移率，(W/L) 4为第四晶体管T4沟道的宽度和长度的比值，Vr为第二控制信号S2的电位，Vl为参考信号T的第一电位Vl，Vth4为第一晶体管T1的阈值电压，ΔV为显示高电位Vdata对第二节点s的电位所产生的影响。
另外，由于在发光阶段t3，第四晶体管T4的阈值电压可以忽略不计，故第一节点g与第二节点s之间的压差可根据以下公式获得：
Figure PCTCN2019095642-appb-000005
进一步地，计算流经发光器件OLED的电流的公式为：
I OLED＝1/2Coxμ 1(W/L) 1(Vgs－Vth1) 2，其中I OLED为流经发光器件OLED的电流，μ 1为第一晶体管T1的载流子迁移率，(W/L) 1为第一晶体管T1沟道的宽度和长度的比值，Vth1为第一晶体管T1的阈值电压。将第一节点g的电位与第二节点s的电位之间的压差
Figure PCTCN2019095642-appb-000006
代入上式，即有：
Figure PCTCN2019095642-appb-000007
由此可见，发光器件OLED的电流与第一晶体管T1的阈值电压无关，实现了补偿功能。发光器件OLED发光，且流经发光器件OLED的电流与第一晶体管T1的阈值电压无关。
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压；
    流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第二控制信号在所述阈值电压阶段、所述数据电压获取阶段以及所述发光阶段的电位保持不变，且所述第二控制信号的电位等于所述第二电位。
  4. 根据权利要求3所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第一电位，所述数据信号为所述参考低电位。
  5. 根据权利要求3所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第二电位，所述数据信号由 所述参考低电位跳变至所述显示高电位。
  6. 根据权利要求3所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述参考信号为所述第二电位，所述数据信号为所述参考低电位。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。
  9. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
  10. 根据权利要求2所述的像素驱动电路，其中，所述第二控制信号在所述阈值电压阶段、所述数据电压获取阶段以及所述发光阶段的电位保持不变，且所述第二控制信号的电位等于所述第二电位。
  11. 根据权利要求10所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第一电位，所述数据信号为所述参考低电位。
  12. 根据权利要求10所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述参考信号为所述第二电位，所述数据信号由所述参考低电位跳变至所述显示高电位。
  13. 根据权利要求10所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述参考信号为所述第二电位，所述数据信号为所述参考低电位。
  14. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  15. 根据权利要求8所述的像素驱动电路，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  16. 根据权利要求8所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述第四晶体管的漏极，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于参考信号；
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端 电性连接于第二电源电压。
  18. 根据权利要求17所述的显示面板，其中，所述第一控制信号、所述参考信号以及所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述参考信号包括第一电位和第二电位，所述第一电位小于所述第二电位，所述数据信号包括参考低电位和显示高电位。
  19. 根据权利要求17所述的显示面板，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  20. 根据权利要求17所述的显示面板，其中，所述发光器件为有机发光二极管。
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CN110853575B (zh) * 2019-11-04 2021-07-06 深圳市华星光电半导体显示技术有限公司 显示面板的电压调节方法及存储介质
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016075787A (ja) * 2014-10-06 2016-05-12 株式会社Ｊｏｌｅｄ 表示装置
US20170061877A1 (en) * 2015-08-24 2017-03-02 Samsung Display Co., Ltd. Pixel circuit and organic light emitting display device having the same
CN106782340A (zh) * 2017-03-16 2017-05-31 深圳市华星光电技术有限公司 一种像素驱动电路及oled显示装置
CN106991969A (zh) * 2017-06-09 2017-07-28 京东方科技集团股份有限公司 显示面板、像素的补偿电路和补偿方法
CN107492343A (zh) * 2017-08-18 2017-12-19 深圳市华星光电半导体显示技术有限公司 用于oled显示设备的像素驱动电路、oled显示设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014119574A (ja) * 2012-12-14 2014-06-30 Samsung Display Co Ltd 電気光学装置の駆動方法および電気光学装置
CN103531151B (zh) * 2013-11-04 2016-03-02 京东方科技集团股份有限公司 Oled像素电路及驱动方法、显示装置
CN107039004B (zh) * 2017-06-08 2019-04-30 深圳市华星光电半导体显示技术有限公司 Amoled显示面板的老化补偿方法
CN107492344A (zh) * 2017-08-18 2017-12-19 深圳市华星光电半导体显示技术有限公司 用于oled显示设备的像素驱动电路、oled显示设备
KR20190074863A (ko) * 2017-12-20 2019-06-28 엘지디스플레이 주식회사 Oled 표시 장치 및 그의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016075787A (ja) * 2014-10-06 2016-05-12 株式会社Ｊｏｌｅｄ 表示装置
US20170061877A1 (en) * 2015-08-24 2017-03-02 Samsung Display Co., Ltd. Pixel circuit and organic light emitting display device having the same
CN106782340A (zh) * 2017-03-16 2017-05-31 深圳市华星光电技术有限公司 一种像素驱动电路及oled显示装置
CN106991969A (zh) * 2017-06-09 2017-07-28 京东方科技集团股份有限公司 显示面板、像素的补偿电路和补偿方法
CN107492343A (zh) * 2017-08-18 2017-12-19 深圳市华星光电半导体显示技术有限公司 用于oled显示设备的像素驱动电路、oled显示设备

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