WO2021012430A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2021012430A1
WO2021012430A1 PCT/CN2019/112695 CN2019112695W WO2021012430A1 WO 2021012430 A1 WO2021012430 A1 WO 2021012430A1 CN 2019112695 W CN2019112695 W CN 2019112695W WO 2021012430 A1 WO2021012430 A1 WO 2021012430A1
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WIPO (PCT)
Prior art keywords
node
control signal
transistor
electrically connected
potential
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PCT/CN2019/112695
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English (en)
French (fr)
Inventor
韩佰祥
聂诚磊
吴小玲
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2021012430A1 publication Critical patent/WO2021012430A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light The Emitting Diode (organic light emitting diode) display panel has the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and has been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, which occupies a large area when designing a layout, which is not conducive to the design of a high PPI (Pixels Per Inch, pixel density) display panel.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problems that the compensation structure of the existing pixel driving circuit is relatively complicated, occupies a large area when designing the layout, and the compensation effect is not good.
  • An embodiment of the present application provides a pixel driving circuit, including: a storage capacitor module, a light emitting module, a data signal input module, and a sensing module;
  • the storage capacitor module is electrically connected to a first node, a second node, and a third node, the light emitting module is electrically connected to the first node, the second node, and the third node, and the data
  • the signal input module is electrically connected to the first node, and the sensing module is electrically connected to the second node;
  • the storage capacitor module is used to store the potential of the first node, the potential of the second node, and the potential of the third node;
  • the light emitting module is connected to a first control signal and a second control signal, and is used to emit light under the control of the first control signal, the second control signal, and the potential of the first node;
  • the data signal input module receives a third control signal and a data signal, and is used to output the data signal to the first node under the control of the third control signal;
  • the sensing module is connected to a fourth control signal for detecting the initial threshold voltage of the light emitting module under the control of the fourth control signal;
  • the data signal input module is further configured to output the compensated data signal to the first node according to the initial threshold voltage under the control of the third control signal;
  • the storage capacitor module includes a first capacitor and a second capacitor
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • the first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the second node;
  • the first control signal, the second control signal, the third control signal, and the fourth control signal are all provided by an external timing device.
  • the light-emitting module includes a first transistor, a second transistor, a third transistor, and a light-emitting device
  • the gate of the first transistor is electrically connected to the first control signal, the source of the first transistor is electrically connected to a first power signal, and the drain of the first transistor is electrically connected to the The source of the second transistor;
  • the gate of the second transistor is electrically connected to the first node, and the drain of the second transistor is electrically connected to the second node;
  • the gate of the third transistor is electrically connected to the second control signal, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the The anode of the light-emitting device;
  • the cathode of the light emitting device is electrically connected to the second power signal.
  • the data signal input module includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the third control signal, the source of the fourth transistor is electrically connected to the data signal, and the drain of the fourth transistor is electrically connected to the The first node.
  • the sensing module includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the fourth control signal, the source of the fifth transistor is electrically connected to the voltage detection module, and the drain of the fifth transistor is electrically connected to the first Two nodes; the voltage detection module is used to output an initial voltage to the second node, or calculate the initial threshold voltage by detecting the potential of the second node.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductors Thin film transistors or amorphous silicon thin film transistors.
  • the sequence of the pixel driving circuit includes an initial threshold voltage processing stage and a real-time threshold voltage processing stage;
  • the initial threshold voltage processing stage includes a first initialization stage and a sensing stage; in the first initialization stage, the first control signal, the second control signal, the third control signal, and the fourth The control signals are all high potentials, the reference potential of the data signal is output to the first node, and the initial voltage is output to the second node; in the sensing phase, the first control signal, the The second control signal, the third control signal, and the fourth control signal are all high, the reference potential of the data signal continues to be output to the first node, and the voltage detection module detects the second The potential of the node calculates the initial threshold voltage;
  • the real-time threshold voltage processing stage includes a second initialization stage, a real-time threshold voltage acquisition stage, a compensation stage, and a light-emitting stage; in the second initialization stage, the first control signal, the second control signal, and the first The third control signal and the fourth control signal are both high, the compensated reference signal is output to the first node, and the compensated initial voltage is output to the second node;
  • the second control signal and the third control signal are both high potential
  • the first control signal and the fourth control signal are both low potential
  • the compensated The reference signal continues to be output to the first node, and due to the effects of the first capacitor and the second capacitor, the potential of the second node changes accordingly until the second transistor is turned off;
  • the third control signal is at a high level
  • the first control signal, the second control signal, and the fourth control signal are at a low level
  • the data signal is controlled by the compensation
  • the subsequent reference potential jumps to the display potential and is output to the first node. Due to the capacitive coupling effect, the potential of the second node also changes accordingly;
  • the first control signal and the second control signal are both at a high potential, and the third control signal and the fourth control signal are both at a low potential, and the light-emitting module emits light.
  • the embodiment of the present application also provides a pixel driving circuit, including a storage capacitor module, a light emitting module, a data signal input module, and a sensing module;
  • the storage capacitor module is electrically connected to a first node, a second node, and a third node, the light emitting module is electrically connected to the first node, the second node, and the third node, and the data
  • the signal input module is electrically connected to the first node, and the sensing module is electrically connected to the second node;
  • the storage capacitor module is used to store the potential of the first node, the potential of the second node, and the potential of the third node;
  • the light emitting module is connected to a first control signal and a second control signal, and is used to emit light under the control of the first control signal, the second control signal, and the potential of the first node;
  • the data signal input module receives a third control signal and a data signal, and is used to output the data signal to the first node under the control of the third control signal;
  • the sensing module is connected to a fourth control signal for detecting the initial threshold voltage of the light emitting module under the control of the fourth control signal;
  • the data signal input module is further configured to output the compensated data signal to the first node according to the initial threshold voltage under the control of the third control signal.
  • the storage capacitor module includes a first capacitor and a second capacitor
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • the first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the second node.
  • the light-emitting module includes a first transistor, a second transistor, a third transistor, and a light-emitting device
  • the gate of the first transistor is electrically connected to the first control signal, the source of the first transistor is electrically connected to a first power signal, and the drain of the first transistor is electrically connected to the The source of the second transistor;
  • the gate of the second transistor is electrically connected to the first node, and the drain of the second transistor is electrically connected to the second node;
  • the gate of the third transistor is electrically connected to the second control signal, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the The anode of the light-emitting device;
  • the cathode of the light emitting device is electrically connected to the second power signal.
  • the data signal input module includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the third control signal, the source of the fourth transistor is electrically connected to the data signal, and the drain of the fourth transistor is electrically connected to the The first node.
  • the sensing module includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the fourth control signal, the source of the fifth transistor is electrically connected to the voltage detection module, and the drain of the fifth transistor is electrically connected to the first Two nodes; the voltage detection module is used to output an initial voltage to the second node, or calculate the initial threshold voltage by detecting the potential of the second node.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductors Thin film transistors or amorphous silicon thin film transistors.
  • the sequence of the pixel driving circuit includes an initial threshold voltage processing stage and a real-time threshold voltage processing stage;
  • the initial threshold voltage processing stage includes a first initialization stage and a sensing stage; in the first initialization stage, the first control signal, the second control signal, the third control signal, and the fourth The control signals are all high potentials, the reference potential of the data signal is output to the first node, and the initial voltage is output to the second node; in the sensing phase, the first control signal, the The second control signal, the third control signal, and the fourth control signal are all high, the reference potential of the data signal continues to be output to the first node, and the voltage detection module detects the second The potential of the node calculates the initial threshold voltage;
  • the real-time threshold voltage processing stage includes a second initialization stage, a real-time threshold voltage acquisition stage, a compensation stage, and a light-emitting stage; in the second initialization stage, the first control signal, the second control signal, and the first The third control signal and the fourth control signal are both high, the compensated reference signal is output to the first node, and the compensated initial voltage is output to the second node;
  • the second control signal and the third control signal are both high potential
  • the first control signal and the fourth control signal are both low potential
  • the compensated The reference signal continues to be output to the first node, and due to the effects of the first capacitor and the second capacitor, the potential of the second node changes accordingly until the second transistor is turned off;
  • the third control signal is at a high level
  • the first control signal, the second control signal, and the fourth control signal are at a low level
  • the data signal is controlled by the compensation
  • the subsequent reference potential jumps to the display potential and is output to the first node. Due to the capacitive coupling effect, the potential of the second node also changes accordingly;
  • the first control signal and the second control signal are both at a high potential, and the third control signal and the fourth control signal are both at a low potential, and the light-emitting module emits light.
  • the first control signal, the second control signal, the third control signal, and the fourth control signal are all provided by an external timing device.
  • An embodiment of the present application further provides a display panel, including a pixel driving circuit, the pixel driving circuit includes: a storage capacitor module, a light emitting module, a data signal input module, and a sensing module;
  • the storage capacitor module is electrically connected to a first node, a second node, and a third node, the light emitting module is electrically connected to the first node, the second node, and the third node, and the data
  • the signal input module is electrically connected to the first node, and the sensing module is electrically connected to the second node;
  • the storage capacitor module is used to store the potential of the first node, the potential of the second node, and the potential of the third node;
  • the light emitting module is connected to a first control signal and a second control signal, and is used to emit light under the control of the first control signal, the second control signal, and the potential of the first node;
  • the data signal input module receives a third control signal and a data signal, and is used to output the data signal to the first node under the control of the third control signal;
  • the sensing module is connected to a fourth control signal for detecting the initial threshold voltage of the light emitting module under the control of the fourth control signal;
  • the data signal input module is further configured to output the compensated data signal to the first node according to the initial threshold voltage under the control of the third control signal.
  • the storage capacitor module includes a first capacitor and a second capacitor
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • the first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the second node.
  • the light emitting module includes a first transistor, a second transistor, a third transistor, and a light emitting device
  • the gate of the first transistor is electrically connected to the first control signal, the source of the first transistor is electrically connected to a first power signal, and the drain of the first transistor is electrically connected to the The source of the second transistor;
  • the gate of the second transistor is electrically connected to the first node, and the drain of the second transistor is electrically connected to the second node;
  • the gate of the third transistor is electrically connected to the second control signal, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the The anode of the light-emitting device;
  • the cathode of the light emitting device is electrically connected to the second power signal.
  • the data signal input module includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the third control signal, the source of the fourth transistor is electrically connected to the data signal, and the drain of the fourth transistor is electrically connected to the The first node.
  • the sensing module includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the fourth control signal, the source of the fifth transistor is electrically connected to the voltage detection module, and the drain of the fifth transistor is electrically connected to the first Two nodes; the voltage detection module is used to output an initial voltage to the second node, or calculate the initial threshold voltage by detecting the potential of the second node.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors Transistor or amorphous silicon thin film transistor.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 5T2C structure to effectively compensate the threshold voltage of the second transistor in each pixel, and obtain the initial threshold voltage and the real-time threshold voltage for the drive circuit
  • the compensation structure of the pixel driving circuit is relatively simple and the effect is better, so that it does not need to occupy a large area during design.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a schematic circuit diagram of a pixel drive circuit provided by an embodiment of the application.
  • FIG. 3 is a timing diagram of the initial threshold voltage processing stage of the pixel driving circuit provided by the application embodiment.
  • FIG. 4 is a timing diagram of the real-time threshold voltage processing stage of the pixel driving circuit provided by the application embodiment.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit 10 provided by the embodiment of the present application includes: a storage capacitor module 101, a light emitting module 102, a data signal input module 103 and a sensing module 104.
  • the storage capacitor module 101 is electrically connected to the first node a, the second node b, and the third node c
  • the light emitting module 102 is electrically connected to the first node a, the second node b, and the third node c
  • the data signal input module 103 It is electrically connected to the first node a
  • the sensing module 104 is electrically connected to the second node b.
  • the storage capacitor module 101 is used to store the potential of the first node a, the potential of the second node b, and the potential of the third node c.
  • the light emitting module 102 is connected to the first control signal S1 and the second control signal S2, and is used to emit light under the control of the first control signal S1, the second control signal S2, and the potential of the first node a.
  • the data signal input module 103 is connected to the third control signal S3 and the data signal Data for outputting the data signal Data to the first node a under the control of the third control signal S3.
  • the sensing module 104 is connected to the fourth control signal S4 for detecting the initial threshold voltage Vth0 of the light emitting module 102 under the control of the fourth control signal S4.
  • the data signal input module 103 is further configured to output the compensated data signal Data to the first node a under the control of the third control signal S3 according to the initial threshold voltage Vth0.
  • FIG. 2 is a schematic circuit diagram of a pixel driving circuit provided by an embodiment of the application.
  • the storage capacitor module 101 includes a first capacitor C1 and a second capacitor C2.
  • the first end of the first capacitor C1 is electrically connected to the first node a, and the second end of the first capacitor C1 is electrically connected to the second node b.
  • the first end of the second capacitor C2 is electrically connected to the third node c, and the second end of the second capacitor C2 is electrically connected to the second node b.
  • the light emitting module 102 includes a first transistor T1, a second transistor T2, a third transistor T3, and a light emitting device D.
  • the gate of the first transistor T1 is electrically connected to the first control signal S1
  • the source of the first transistor T1 is electrically connected to the first power signal VDD
  • the drain of the first transistor T1 is electrically connected to the second transistor T2.
  • the gate of the second transistor T2 is electrically connected to the first node a
  • the drain of the second transistor T2 is electrically connected to the second node b.
  • the gate of the third transistor T3 is electrically connected to the second control signal S2, the source of the third transistor T3 is electrically connected to the second node b, and the drain of the third transistor T3 is electrically connected to the anode of the light emitting device D.
  • the cathode of the light emitting device D is electrically connected to the second power signal VSS.
  • the data signal input module 103 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the third control signal S3, the source of the fourth transistor T4 is electrically connected to the data signal Data, and the drain of the fourth transistor T4 is electrically connected to the first node a.
  • the sensing module 104 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is electrically connected to the fourth control signal S4, the source of the fifth transistor T5 is electrically connected to the voltage detection module 105, and the drain of the fifth transistor T5 is electrically connected to the second node b;
  • the detection module 105 is configured to output an initial voltage Vsensing to the second node b, or calculate the initial threshold voltage Vth0 by detecting the potential of the second node b.
  • the light emitting device D may be an organic light emitting diode. That is, the embodiment of the present application adopts a pixel driving circuit with a 5T2C structure to effectively compensate the threshold voltage of the second transistor T2 in each pixel, uses fewer components, has a simple and stable structure, and saves costs.
  • both the first power signal VDD and the second power signal VSS are used to output a predetermined voltage value.
  • the output voltage value of the first power signal VDD is greater than the voltage value output of the second power signal VSS.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all provided by an external timing device.
  • FIG. 3 is a timing diagram of the initial threshold voltage processing stage of the pixel driving circuit provided by the application embodiment.
  • the pixel driving circuit of the embodiment of the present application includes an initial threshold voltage processing stage.
  • the initial threshold voltage processing stage includes a first initialization stage t1 and a sensing stage t2.
  • the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all high potentials.
  • the reference potential Vref of the data signal Data is output to the first node a, and the initial The voltage Vsensing is output to the second node b; in the sensing phase t2, the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all high potentials, and the reference potential Vref of the data signal Data
  • the output continues to the first node a, and the voltage detection module 105 calculates the initial threshold voltage Vth0 by detecting the potential of the second node b.
  • FIG. 4 is a timing diagram of the real-time threshold voltage processing stage of the pixel driving circuit provided by the application embodiment.
  • the pixel driving circuit of the embodiment of the present application includes a real-time threshold voltage processing stage.
  • the real-time threshold voltage processing stage includes a second initialization stage t3, a real-time threshold voltage acquisition stage t4, a compensation stage t5, and a light-emitting stage t6.
  • the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all high, and the compensated reference signal Data is output to the first node a.
  • the potential of the first node a is Vref+Vth0, and the initial voltage Vsensing is output to the second node b.
  • the second control signal S2 and the third control signal S3 are both high, the first control signal S1 and the fourth control signal S4 are both low, and the compensated reference signal Data continues to be output to the first For a node a, due to the effects of the first capacitor C1 and the second capacitor C2, the potential of the second node b changes accordingly until the second transistor T2 is turned off.
  • the third control signal S3 is at a high level
  • the first control signal S1, the second control signal S2, and the fourth control signal S4 are all at a low level
  • the data signal Data jumps to the display potential Vdata+Vth0 and is output To the first node a, due to the capacitive coupling effect, the potential of the second node b also changes accordingly.
  • the first control signal S1 and the second control signal S2 are both high potential
  • the third control signal S3 and the fourth control signal S4 are both low potential
  • the current of the light emitting device is independent of the threshold voltage of the second transistor, and the compensation function is realized.
  • the light emitting device emits light, and the current flowing through the light emitting device is independent of the threshold voltage of the second transistor.
  • An embodiment of the present application also provides a display panel, which includes the above pixel driving circuit.
  • a display panel which includes the above pixel driving circuit.
  • the above pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel driving circuit of the 5T2C structure is used to effectively compensate the threshold voltage of the driving transistor in each pixel, and the driving circuit is performed by obtaining the initial threshold voltage and the real-time threshold voltage. Compensation:
  • the compensation structure of the pixel driving circuit is relatively simple and the effect is better, so that it does not need to occupy a large area in the design.

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  • Computer Hardware Design (AREA)
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Abstract

本申请实施例提供的像素驱动电路及显示面板，采用5T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，且通过获取初始阈值电压以及实时阈值电压对该驱动电路进行补偿，该像素驱动电路的补偿结构较为简单，效果更佳，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，且补偿效果不佳的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点；
所述存储电容模块包括第一电容以及第二电容；
所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接；
所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
在本申请所述的像素驱动电路中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
所述发光器件的阴极电性连接于第二电源信号。
在本申请所述的像素驱动电路中，所述数据信号输入模块包括第四晶体管；
所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
在本申请所述的像素驱动电路中，所述感测模块包括第五晶体管；
所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述像素驱动电路的时序包括初始阈值电压处理阶段和实时阈值电压处理阶段；
所述初始阈值电压处理阶段包括第一初始化阶段以及感测阶段；在所述第一初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位输出至所述第一节点，所述初始电压输出至所述第二节点；在所述感测阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位继续输出至所述第一节点，所述电压探测模块通过探测所述第二节点的电位计算出所述初始阈值电压；
所述实时阈值电压处理阶段包括第二初始化阶段、实时阈值电压获取阶段、补偿阶段以及发光阶段；在所述第二初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，补偿后的所述参考信号输出至所述第一节点，补偿后的所述初始电压输出至所述第二节点；
在所述实时阈值电压探测阶段，所述第二控制信号以及所述第三控制信号均为高电位，所述第一控制信号以及所述第四控制信号均为低电位，补偿后的所述参考信号继续输出至所述第一节点，由于所述第一电容以及所述第二电容的作用，所述第二节点的电位相应变化直至所述第二晶体管关闭；
在所述补偿阶段，所述第三控制信号为高电位，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电位，所述数据信号的由所述补偿后的参考电位跳变至显示电位并输出至所述第一节点，由于电容耦合效应，所述第二节点的电位也相应变化；
在所述发光阶段，所述第一控制信号以及所述第二控制信号均为高电位，所第三控制信号以及所述第四控制信号均为低电位，所述发光模块进行发光。
本申请实施例还提供一种像素驱动电路，包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点。
在本申请所述的像素驱动电路中，所述存储电容模块包括第一电容以及第二电容；
所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接。
在本申请所述的像素驱动电路中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
所述发光器件的阴极电性连接于第二电源信号。
在本申请所述的像素驱动电路中，所述数据信号输入模块包括第四晶体管；
所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
在本申请所述的像素驱动电路中，所述感测模块包括第五晶体管；
所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述像素驱动电路的时序包括初始阈值电压处理阶段和实时阈值电压处理阶段；
所述初始阈值电压处理阶段包括第一初始化阶段以及感测阶段；在所述第一初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位输出至所述第一节点，所述初始电压输出至所述第二节点；在所述感测阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位继续输出至所述第一节点，所述电压探测模块通过探测所述第二节点的电位计算出所述初始阈值电压；
所述实时阈值电压处理阶段包括第二初始化阶段、实时阈值电压获取阶段、补偿阶段以及发光阶段；在所述第二初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，补偿后的所述参考信号输出至所述第一节点，补偿后的所述初始电压输出至所述第二节点；
在所述实时阈值电压探测阶段，所述第二控制信号以及所述第三控制信号均为高电位，所述第一控制信号以及所述第四控制信号均为低电位，补偿后的所述参考信号继续输出至所述第一节点，由于所述第一电容以及所述第二电容的作用，所述第二节点的电位相应变化直至所述第二晶体管关闭；
在所述补偿阶段，所述第三控制信号为高电位，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电位，所述数据信号的由所述补偿后的参考电位跳变至显示电位并输出至所述第一节点，由于电容耦合效应，所述第二节点的电位也相应变化；
在所述发光阶段，所述第一控制信号以及所述第二控制信号均为高电位，所第三控制信号以及所述第四控制信号均为低电位，所述发光模块进行发光。
在本申请所述的像素驱动电路中，所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
本申请实施例还提供一种显示面板，包括像素驱动电路，所述像素驱动电路包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点。
在本申请所述的显示面板中，所述存储电容模块包括第一电容以及第二电容；
所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接。
在本申请所述的显示面板中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
所述发光器件的阴极电性连接于第二电源信号。
在本申请所述的显示面板中，所述数据信号输入模块包括第四晶体管；
所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
在本申请所述的显示面板中，所述感测模块包括第五晶体管；
所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
在本申请所述的显示面板中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用5T2C结构的像素驱动电路对每一像素中的第二晶体管的阈值电压进行有效补偿，且通过获取初始阈值电压以及实时阈值电压对该驱动电路进行补偿，该像素驱动电路的补偿结构较为简单，效果更佳，从而在设计时并不需要占用大量面积。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的电路示意图；
图3为申请实施例提供的像素驱动电路的初始阈值电压处理阶段的时序图；以及
图4为申请实施例提供的像素驱动电路的实时阈值电压处理阶段的时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路10，包括：存储电容模块101、发光模块102、数据信号输入模块103以及感测模块104。存储电容模块101与第一节点a、第二节点b以及第三节点c电性连接，发光模块102与第一节点a、第二节点b以及第三节点c电性连接，数据信号输入模块103与第一节点a电性连接，感测模块104与第二节点b电性连接。
存储电容模块101用于存储第一节点a的电位、第二节点b的电位以及第三节点c的电位。发光模块102接入第一控制信号S1以及第二控制信号S2，用于在第一控制信号S1、第二控制信号S2以及第一节点a的电位控制下发光。数据信号输入模块103接入第三控制信号S3以及数据信号Data，用于在第三控制信号S3的控制下，将数据信号Data输出至第一节点a。感测模块104接入第四控制信号S4，用于在第四控制信号S4的控制下，探测发光模块102的初始阈值电压Vth0。其中，数据信号输入模块103还用于在第三控制信号S3的控制下，根据初始阈值电压Vth0将补偿后的数据信号Data输出至第一节点a。
具体的，请参阅图2，图2为本申请实施例提供的像素驱动电路的电路示意图。如图2所示，存储电容模块101包括第一电容C1以及第二电容C2。第一电容C1的第一端与第一节点a电性连接，第一电容C1的第二端与第二节点b电性连接。第二电容C2的第一端与第三节点c电性连接，第二电容C2的第二端与第二节点b电性连接。
发光模块102包括第一晶体管T1、第二晶体管T2、第三晶体管T3以及发光器件D。第一晶体管T1的栅极电性连接于第一控制信号S1，第一晶体管T1的源极电性连接于第一电源信号VDD，第一晶体管T1的漏极电性连接于第二晶体管T2的源极。第二晶体管T2的栅极电性连接于第一节点a，第二晶体管T2的漏极电性连接于第二节点b。第三晶体管T3的栅极电性连接于第二控制信号S2，第三晶体管T3的源极电性连接于第二节点b，第三晶体管T3的漏极电性连接于发光器件D的阳极。发光器件D的阴极电性连接于第二电源信号VSS。
数据信号输入模块103包括第四晶体管T4。第四晶体管T4的栅极电性连接于第三控制信号S3，第四晶体管T4的源极电性连接于数据信号Data，第四晶体管T4的漏极电性连接于第一节点a。
感测模块104包括第五晶体管T5。第五晶体管T5的栅极电性连接于第四控制信号S4，第五晶体管T5的源极电性连接于电压探测模块105，第五晶体管T5的漏极电性连接于第二节点b；电压探测模块105用于输出一初始电压Vsensing至第二节点b，或者通过探测第二节点b的电位计算出初始阈值电压Vth0。
在一些实施例中，该发光器件D可以为有机发光二极管。也即，本申请实施例采用5T2C结构的像素驱动电路对每一像素中的第二晶体管T2的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。
在一些实施例中，第一电源信号VDD和第二电源信号VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源信号VDD的输出的电压值大于第二电源信号VSS输出的电压值。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第五晶体管T5均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
在一些实施例中，第一控制信号S1、第二控制信号S2、第三控制信号S3以及第四控制信号S4均由外部时序器提供。
进一步的，请参阅图3，图3为申请实施例提供的像素驱动电路的初始阈值电压处理阶段的时序图。结合图2、图3所示，本申请实施例的像素驱动电路包括初始阈值电压处理阶段。该初始阈值电压处理阶段包括第一初始化阶段t1以及感测阶段t2。在第一初始化阶段t1，第一控制信号S1、第二控制信号S2、第三控制信号S3以及第四控制信号S4均为高电位，数据信号Data的参考电位Vref输出至第一节点a，初始电压Vsensing输出至第二节点b；在感测阶段t2，第一控制信号S1、第二控制信号S2、第三控制信号S3以及第四控制信号S4均为高电位，数据信号Data的参考电位Vref继续输出至第一节点a，电压探测模块105通过探测第二节点b的电位计算出初始阈值电压Vth0。
请参阅图4，图4为申请实施例提供的像素驱动电路的实时阈值电压处理阶段的时序图。结合图2、图4所示，本申请实施例的像素驱动电路包括实时阈值电压处理阶段。该实时阈值电压处理阶段包括第二初始化阶段t3、实时阈值电压获取阶段t4、补偿阶段t5以及发光阶段t6。在第二初始化阶段t3，第一控制信号S1、第二控制信号S2、第三控制信号S3以及第四控制信号S4均为高电位，补偿后的参考信号Data输出至第一节点a，此时，第一节点a的电位为Vref+Vth0，初始电压Vsensing输出至第二节点b。在实时阈值电压探测阶段t4，第二控制信号S2以及第三控制信号S3均为高电位，第一控制信号S1以及第四控制信号S4均为低电位，补偿后的参考信号Data继续输出至第一节点a，由于第一电容C1以及第二电容C2的作用，第二节点b的电位相应变化直至第二晶体管T2关闭。在补偿阶段t5，第三控制信号S3为高电位，第一控制信号S1、第二控制信号S2以及第四控制信号S4均为低电位，数据信号Data的跳变至显示电位Vdata+Vth0并输出至第一节点a，由于电容耦合效应，第二节点b的电位也相应变化。在发光阶段t6，第一控制信号S1以及第二控制信号S2均为高电位，所第三控制信号S3以及第四控制信号S4均为低电位，发光模块102进行发光。
因此，发光器件的电流与第二晶体管的阈值电压无关，实现了补偿功能，发光器件发光，且流经发光器件的电流与第二晶体管的阈值电压无关。
本申请实施例还提供一种显示面板，其包括以上的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用5T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，且通过获取初始阈值电压以及实时阈值电压对该驱动电路进行补偿，该像素驱动电路的补偿结构较为简单，效果更佳，从而在设计时并不需要占用大量面积。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
    所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
    所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
    所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
    所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
    所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
    其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点；
    所述存储电容模块包括第一电容以及第二电容；
    所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
    所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接；
    所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
  2. 根据权利要求1所述的像素驱动电路，其中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
    所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
    所述发光器件的阴极电性连接于第二电源信号。
  3. 根据权利要求2所述的像素驱动电路，其中，所述数据信号输入模块包括第四晶体管；
    所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
  4. 根据权利要求3所述的像素驱动电路，其中，所述感测模块包括第五晶体管；
    所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  6. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路的时序包括初始阈值电压处理阶段和实时阈值电压处理阶段；
    所述初始阈值电压处理阶段包括第一初始化阶段以及感测阶段；在所述第一初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位输出至所述第一节点，所述初始电压输出至所述第二节点；在所述感测阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位继续输出至所述第一节点，所述电压探测模块通过探测所述第二节点的电位计算出所述初始阈值电压；
    所述实时阈值电压处理阶段包括第二初始化阶段、实时阈值电压获取阶段、补偿阶段以及发光阶段；在所述第二初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，补偿后的所述参考信号输出至所述第一节点，补偿后的所述初始电压输出至所述第二节点；
    在所述实时阈值电压探测阶段，所述第二控制信号以及所述第三控制信号均为高电位，所述第一控制信号以及所述第四控制信号均为低电位，补偿后的所述参考信号继续输出至所述第一节点，由于所述第一电容以及所述第二电容的作用，所述第二节点的电位相应变化直至所述第二晶体管关闭；
    在所述补偿阶段，所述第三控制信号为高电位，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电位，所述数据信号的由所述补偿后的参考电位跳变至显示电位并输出至所述第一节点，由于电容耦合效应，所述第二节点的电位也相应变化；
    在所述发光阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号以及所述第四控制信号均为低电位，所述发光模块进行发光。
  7. 一种像素驱动电路，其包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
    所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
    所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
    所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
    所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
    所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
    其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点。
  8. 根据权利要求7所述的像素驱动电路，其中，所述存储电容模块包括第一电容以及第二电容；
    所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
    所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接。
  9. 根据权利要求8所述的像素驱动电路，其中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
    所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
    所述发光器件的阴极电性连接于第二电源信号。
  10. 根据权利要求9所述的像素驱动电路，其中，所述数据信号输入模块包括第四晶体管；
    所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
  11. 根据权利要求10所述的像素驱动电路，其中，所述感测模块包括第五晶体管；
    所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
  12. 根据权利要求11所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  13. 根据权利要求11所述的像素驱动电路，其中，所述像素驱动电路的时序包括初始阈值电压处理阶段和实时阈值电压处理阶段；
    所述初始阈值电压处理阶段包括第一初始化阶段以及感测阶段；在所述第一初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位输出至所述第一节点，所述初始电压输出至所述第二节点；在所述感测阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，所述数据信号的参考电位继续输出至所述第一节点，所述电压探测模块通过探测所述第二节点的电位计算出所述初始阈值电压；
    所述实时阈值电压处理阶段包括第二初始化阶段、实时阈值电压获取阶段、补偿阶段以及发光阶段；在所述第二初始化阶段，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电位，补偿后的所述参考信号输出至所述第一节点，补偿后的所述初始电压输出至所述第二节点；
    在所述实时阈值电压探测阶段，所述第二控制信号以及所述第三控制信号均为高电位，所述第一控制信号以及所述第四控制信号均为低电位，补偿后的所述参考信号继续输出至所述第一节点，由于所述第一电容以及所述第二电容的作用，所述第二节点的电位相应变化直至所述第二晶体管关闭；
    在所述补偿阶段，所述第三控制信号为高电位，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电位，所述数据信号的由所述补偿后的参考电位跳变至显示电位并输出至所述第一节点，由于电容耦合效应，所述第二节点的电位也相应变化；
    在所述发光阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号以及所述第四控制信号均为低电位，所述发光模块进行发光。
  14. 根据权利要求7所述的像素驱动电路，其中，所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
  15. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：存储电容模块、发光模块、数据信号输入模块以及感测模块；
    所述存储电容模块与第一节点、第二节点以及第三节点电性连接，所述发光模块与所述第一节点、所述第二节点以及所述第三节点电性连接，所述数据信号输入模块与所述第一节点电性连接，所述感测模块与所述第二节点电性连接；
    所述存储电容模块用于存储所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位；
    所述发光模块接入第一控制信号以及第二控制信号，用于在所述第一控制信号、所述第二控制信号以及所述第一节点的电位控制下发光；
    所述数据信号输入模块接入第三控制信号以及数据信号，用于在所述第三控制信号的控制下，将所述数据信号输出至所述第一节点；
    所述感测模块接入第四控制信号，用于在所述第四控制信号的控制下，探测所述发光模块的初始阈值电压；
    其中，所述数据信号输入模块还用于在所述第三控制信号的控制下，根据所述初始阈值电压将补偿后的所述数据信号输出至所述第一节点。
  16. 根据权利要求15所述的显示面板，其中，所述存储电容模块包括第一电容以及第二电容；
    所述第一电容的第一端与所述第一节点电性连接，所述第一电容的第二端与所述第二节点电性连接；
    所述第二电容的第一端与所述第三节点电性连接，所述第二电容的第二端与所述第二节点电性连接。
  17. 根据权利要求16所述的显示面板，其中，所述发光模块包括第一晶体管、第二晶体管、第三晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的源极电性连接于第一电源信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的漏极电性连接于所述第二节点；
    所述第三晶体管的栅极电性连接于所述第二控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述发光器件的阳极；
    所述发光器件的阴极电性连接于第二电源信号。
  18. 根据权利要求17所述的显示面板，其中，所述数据信号输入模块包括第四晶体管；
    所述第四晶体管的栅极电性连接于所述第三控制信号，所述第四晶体管的源极电性连接于所述数据信号，所述第四晶体管的漏极电性连接于所述第一节点。
  19. 根据权利要求18所述的显示面板，其中，所述感测模块包括第五晶体管；
    所述第五晶体管的栅极电性连接于所述第四控制信号，所述第五晶体管的源极电性连接于电压探测模块，所述第五晶体管的漏极电性连接于所述第二节点；所述电压探测模块用于输出一初始电压至所述第二节点，或者通过探测所述第二节点的电位计算出所述初始阈值电压。
  20. 根据权利要求19所述的显示面板，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
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