WO2020173035A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2020173035A1
WO2020173035A1 PCT/CN2019/095454 CN2019095454W WO2020173035A1 WO 2020173035 A1 WO2020173035 A1 WO 2020173035A1 CN 2019095454 W CN2019095454 W CN 2019095454W WO 2020173035 A1 WO2020173035 A1 WO 2020173035A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
control signal
node
driving circuit
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PCT/CN2019/095454
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English (en)
French (fr)
Inventor
蔡玉莹
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020173035A1 publication Critical patent/WO2020173035A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, which occupies a large area when designing a layout, which is not conducive to the design of a high PPI (Pixels Per Inch, pixel density) display panel.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problem that the compensation structure of the existing pixel driving circuit is relatively complicated and a large area is occupied when designing the layout.
  • An embodiment of the present application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to the cathode of the light emitting device, and the drain of the first transistor is electrically connected to the second node. voltage;
  • the gate of the second transistor is electrically connected to the second control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the second control signal of the capacitor. end;
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the capacitor Second end
  • the gate of the fourth transistor is electrically connected to the first control signal
  • the source of the fourth transistor is electrically connected to the second node
  • the drain of the fourth transistor is electrically connected to the first control signal.
  • the gate of the fifth transistor is electrically connected to the first control signal, the source of the fifth transistor is electrically connected to a current source for outputting a preset current value, and the drain of the fifth transistor is Electrically connected to the second node;
  • the first end of the capacitor is electrically connected to the first node
  • the anode terminal of the light emitting device is electrically connected to the first power supply voltage
  • the third transistor and the first transistor are mirrored transistors, and the current flowing through the light emitting device has nothing to do with the threshold voltage of the first transistor; the light emitting device is an organic light emitting diode.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase; the data
  • the signal includes a reference high potential and a display low potential.
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a high potential, and the data signal is the reference high potential.
  • the first control signal in the data voltage acquisition phase, is at a low potential, the second control signal is at a high potential, and the data signal is jumped from the reference high potential Change to the display low potential.
  • the first control signal in the light-emitting phase, is a low potential, the second control signal is a low potential, and the data signal is the reference high potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to the cathode of the light emitting device, and the drain of the first transistor is electrically connected to the second node. voltage;
  • the gate of the second transistor is electrically connected to the second control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the second control signal of the capacitor. end;
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the capacitor Second end
  • the gate of the fourth transistor is electrically connected to the first control signal
  • the source of the fourth transistor is electrically connected to the second node
  • the drain of the fourth transistor is electrically connected to the first control signal.
  • the gate of the fifth transistor is electrically connected to the first control signal, the source of the fifth transistor is electrically connected to a current source for outputting a preset current value, and the drain of the fifth transistor is Electrically connected to the second node;
  • the first end of the capacitor is electrically connected to the first node
  • the anode terminal of the light emitting device is electrically connected to the first power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase; the data
  • the signal includes a reference high potential and a display low potential.
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a high potential, and the data signal is the reference high potential.
  • the first control signal in the data voltage acquisition phase, is at a low potential, the second control signal is at a high potential, and the data signal is jumped from the reference high potential Change to the display low potential.
  • the first control signal in the light-emitting phase, is a low potential, the second control signal is a low potential, and the data signal is the reference high potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • the third transistor and the first transistor are mirrored transistors, and the current flowing through the light-emitting device is independent of the threshold voltage of the first transistor.
  • the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • the light-emitting device is an organic light-emitting diode.
  • An embodiment of the present application also provides a display panel, which includes a pixel drive circuit, and the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to the cathode of the light emitting device, and the drain of the first transistor is electrically connected to the second node. voltage;
  • the gate of the second transistor is electrically connected to the second control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the second control signal of the capacitor. end;
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the capacitor Second end
  • the gate of the fourth transistor is electrically connected to the first control signal
  • the source of the fourth transistor is electrically connected to the second node
  • the drain of the fourth transistor is electrically connected to the first control signal.
  • the gate of the fifth transistor is electrically connected to the first control signal, the source of the fifth transistor is electrically connected to a current source for outputting a preset current value, and the drain of the fifth transistor is Electrically connected to the second node;
  • the first end of the capacitor is electrically connected to the first node
  • the anode terminal of the light emitting device is electrically connected to the first power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase; the data signal Including reference high potential and display low potential.
  • the third transistor and the first transistor are mirrored transistors, and the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light emitting device is an organic light emitting diode.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 5T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided in the embodiment of the application in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 5T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a capacitor C, and a light emitting device OLED.
  • the light emitting device OLED may be an organic light emitting diode. That is, the embodiment of the present application adopts the pixel driving circuit of the 5T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, has a simple and stable structure, and saves costs.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node g
  • the source of the first transistor T1 is electrically connected to the cathode terminal of the light emitting device OLED
  • the drain of the first transistor T1 is electrically connected to the second power source Voltage VSS.
  • the gate of the second transistor T2 is electrically connected to the second control signal Vs2
  • the source of the second transistor T2 is electrically connected to the data signal D
  • the drain of the second transistor T2 is electrically connected to the second end of the capacitor C.
  • the gate of the third transistor T3 is electrically connected to the first node g, the source of the third transistor T3 is electrically connected to the second node s, and the drain of the third transistor T3 is electrically connected to the second end of the capacitor C.
  • the gate of the fourth transistor T4 is electrically connected to the first control signal Vs1, the source of the fourth transistor T4 is electrically connected to the second node s, and the drain of the fourth transistor T4 is electrically connected to the first node g.
  • the gate of the fifth transistor T5 is electrically connected to the first control signal Vs1, the source of the fifth transistor T5 is electrically connected to a current source A for outputting a preset current value, and the drain of the fifth transistor T5 is electrically connected Connected to the second node s.
  • the first end of the capacitor C is electrically connected to the first node g.
  • the anode terminal of the light emitting device OLED is electrically connected to the first power supply voltage Vdd.
  • both the first power supply voltage Vdd and the second power supply voltage VSS are used to output a predetermined voltage value.
  • the output voltage value of the first power supply voltage Vdd is greater than the output voltage value of the second power supply voltage VSS.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal Vs1, the second control signal Vs2, and the data signal D corresponds to the threshold voltage acquisition stage t1, the data voltage acquisition stage t2, and the light-emitting stage t3.
  • the data signal D includes a reference high potential Vref and a display low potential Vdata. It can be understood that the potential value of the reference high potential Vref is greater than the potential value of the display low potential Vdata.
  • the first control signal Vs1 is at a high potential
  • the second control signal Vs2 is at a high potential
  • the data signal D is a reference high potential Vref.
  • the first control signal Vs1 is at a low level
  • the second control signal Vs2 is at a high level
  • the data signal D jumps from the reference high level Vref to the display low level Vdata.
  • the first control signal Vs1 is at a low potential
  • the second control signal Vs2 is at a low potential
  • the data signal D is a reference high potential Vref.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase in the driving sequence shown in FIG. 2.
  • the first control signal Vs1 is at a high potential
  • the fourth transistor T4 and the fifth transistor T5 are turned on
  • the current source A outputs a preset current.
  • the transistor T5 outputs to the second node s, and outputs to the first node g via the fourth transistor T4.
  • the preset current output by the current source A causes the light emitting device OLED to be turned off at this time, and the preset current flows through the third transistor T3, that is, the third transistor T3 is turned on at this time.
  • the second control signal Vs2 is at a high potential
  • the second transistor T2 is turned on
  • the data signal D is at the reference high potential Vref at this time. That is, at this time, the reference high potential Vref of the data signal D is output to the second end of the capacitor C through the second transistor T2.
  • the drain of the third transistor T3 is electrically connected to the second power supply voltage VSS, at this time, the potential of the drain terminal of the third transistor T3 is equal to the potential of the second power supply voltage VSS.
  • the carrier mobility of W3 and L3 are respectively the width and length of the channel of the third transistor T3, and Iref is the current value output by the current source A.
  • FIG. 4 is a schematic diagram of the data voltage acquisition phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the second control signal Vs2 is at a high potential
  • the second transistor T2 is turned on
  • the data signal D jumps from the reference high potential Vref to the display low potential Vdata at this time. That is, at this time, the potential of the second terminal of the capacitor C also jumps from the reference high potential Vref to the display low potential Vdata.
  • the first control signal Vs1 is at a low level, and the fourth transistor T4 and the fifth transistor T5 are turned off, that is, at this time, the preset current output by the current source A fails to be output to the first node g and the second node s.
  • the potential of the first node g is first equal to the potential during the threshold voltage acquisition phase t1.
  • the second terminal of the capacitor C jumps from the reference high potential Vref to the display low potential Vdata during the data voltage acquisition phase t2. Therefore, in the data voltage acquisition phase t2, the potential change amount of the first node g may be approximately equal to the voltage difference between the reference high potential Vref and the display low potential Vdata.
  • FIG. 5 is a schematic diagram of the light-emitting phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal Vs1 is at a low potential
  • the second control signal Vs2 is at a low potential
  • the data signal D is a reference high potential Vref
  • the fifth transistor T5 is turned off. Due to the storage effect of the capacitor C, the potential of the first node g remains unchanged. That is, the potential of the first node g is equal to the potential of the first node g in the data voltage acquisition phase t2.
  • the drain of the third transistor T3 is electrically connected to the second power supply voltage VSS at this time, the potential of the drain of the third transistor T3 is equal to the potential of the second power supply voltage VSS.
  • I OLED 1/2Cox( ⁇ 1W1/L1)(Vgs-Vth1) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ 1 is the carrier mobility of the first transistor T1T1, W1 and L1 are the first The width and length of the channel of the transistor T1, Vgs is the voltage difference between the gate and the drain of the first transistor T1, and Vth1 is the threshold voltage of the first transistor T1. In the embodiment of the present application, the voltage difference between the gate and the drain of the first transistor T1 is equal to the voltage difference between the potential of the first node g and the potential of the drain of the first transistor T1.
  • the threshold voltage of the first transistor T1 is equal to the threshold voltage of the second transistor T2
  • the potential of the gate of the first transistor T1 is equal to that of the first transistor T1.
  • I OLED 1/2Cox( ⁇ 1W1/L1)(2Iref/ ⁇ 3Cox(W3/L3)+Vth3+Vdata-Vref-Vth1) 2
  • the current of the light-emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.

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Abstract

本申请实施例提供的像素驱动电路及显示面板，采用5T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
所述电容的第一端电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源电压；
所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考高电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述数据信号由所述参考高电位跳变至所述显示低电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为所述参考高电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述第一电源电压的电压值大于所述第二电源电压的电压值。
本申请实施例还提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
所述电容的第一端电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源电压。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考高电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述数据信号由所述参考高电位跳变至所述显示低电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为所述参考高电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的像素驱动电路中，所述第一电源电压的电压值大于所述第二电源电压的电压值。
在本申请所述的像素驱动电路中，所述发光器件为有机发光二极管。
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
所述电容的第一端电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源电压。
在本申请所述的显示面板中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
在本申请所述的显示面板中，所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的显示面板中，所述发光器件为有机发光二极管。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用5T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的时序图；
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段的通路示意图；
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段的通路示意图；
图5为为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
本申请实施例提供的像素驱动电路及显示面板，采用5T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、电容C以及发光器件OLED。发光器件OLED可以为有机发光二极管。也即，本申请实施例采用5T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为驱动晶体管。
其中，第一晶体管T1的栅极电性连接于第一节点g，第一晶体管T1的源极电性连接于发光器件OLED的阴极端，第一晶体管T1的漏极电性连接于第二电源电压VSS。第二晶体管T2的栅极电性连接于第二控制信号Vs2，第二晶体管T2的源极电性连接于数据信号D，第二晶体管T2的漏极电性连接于电容C的第二端。第三晶体管T3的栅极电性连接于第一节点g，第三晶体管T3的源极电性连接于第二节点s，第三晶体管T3的漏极电性连接于电容C的第二端。第四晶体管T4的栅极电性连接于第一控制信号Vs1，第四晶体管T4的源极电性连接于第二节点s，第四晶体管T4的漏极电性连接于第一节点g。第五晶体管T5的栅极电性连接于第一控制信号Vs1，第五晶体管T5的源极电性连接于一用于输出预设电流值的电流源A，第五晶体管T5的漏极电性连接于所述第二节点s。电容C的第一端电性连接于第一节点g。发光器件OLED的阳极端电性连接于第一电源电压Vdd。
在一些实施例中，第一电源电压Vdd和第二电源电压VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源电压Vdd的输出的电压值大于第二电源电压VSS输出的电压值。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第五晶体管T5均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，第一控制信号Vs1、第二控制信号Vs2、数据信号D相组合先后对应于阈值电压获取阶段t1、数据电压获取阶段t2以及发光阶段t3。数据信号D包括参考高电位Vref以及显示低电位Vdata。可以理解的，参考高电位Vref的电位值大于显示低电位Vdata的电位值。
在一些实施例中，在阈值电压获取阶段t1，第一控制信号Vs1为高电位，第二控制信号Vs2为高电位，数据信号D为参考高电位Vref。
在一些实施例中，在数据电压获取阶段t2，第一控制信号Vs1为低电位，第二控制信号Vs2为高电位，数据信号D由参考高电位Vref跳变至显示低电位Vdata。
在一些实施例中，在发光阶段t3，第一控制信号Vs1为低电位，第二控制信号Vs2为低电位，数据信号D为参考高电位Vref。
具体的，请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段的通路示意图。首先，结合图2、图3所示，在阈值电压获取阶段t1，第一控制信号Vs1为高电位，第四晶体管T4以及第五晶体管T5打开，电流源A输出一预设电流，经第五晶体管T5输出至第二节点s，以及经第四晶体管T4输出至第一节点g。需要说明的是，该电流源A输出的这一预设电流使得发光器件OLED此时关断，并且该预设电流流经第三晶体管T3，也即，此时第三晶体管T3打开。
与此同时，在阈值电压获取阶段t1，第二控制信号Vs2为高电位，第二晶体管T2打开，数据信号D此时为参考高电位Vref。也即，此时，数据信号D的参考高电位Vref经第二晶体管T2输出至电容C的第二端。另外，由于第三晶体管T3的漏极与第二电源电压VSS电性连接，此时，第三晶体管T3漏极端的电位等于第二电源电压VSS的电位。
在该阈值电压获取阶段t1，第一节点g的电位和第三晶体管T3漏极的电位可以根据以下公式进行设置：V g=2Iref/μ3Cox(W3/L3)+Vth3+Vs，Vs=VSS,其中，V g为第一节点gg的电位，V s为第三晶体管T3的漏极的电位，Vth3第三晶体管T3的阈值电压，VSS为第二电源电压VSS的电位，μ3为第三晶体管T3的载流子迁移率，W3和L3分别为第三晶体管T3的沟道的宽度和长度，Iref为电流源A输出的电流值。
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段的通路示意图。结合图2、图4所示，在数据电压获取阶段t2，第二控制信号Vs2为高电位，第二晶体管T2打开，数据信号D此时由参考高电位Vref跳变至显示低电位Vdata。也即，此时，电容C的第二端的电位也由参考高电位Vref跳变至显示低电位Vdata。
另外，在数据电压获取阶段t2，第一控制信号Vs1为低电位，第四晶体管T4以及第五晶体管T5关闭，也即，此时，电流源A输出的预设电流未能输出至第一节点g以及第二节点s。然而，在阈值电压获取阶段t1时，第一节点g的电位由于电容C的存储作用，第一节点g的电位先是等于阈值电压获取阶段t1时的电位。但是，由于电容C耦合效用，电容C的第二端在数据电压获取阶段t2由参考高电位Vref跳变至显示低电位Vdata。因此，在数据电压获取阶段t2，第一节点g的电位变化量可以近似等于参考高电位Vref与显示低电位Vdata之间的压差。
在该数据电压获取阶段t2，第一节点g的电位和第三晶体管T3漏极的电位可以根据以下公式进行设置：V g=2Iref/μ3Cox(W/L)+Vth3+Vs+Vdata-Vref，Vs=VSS,其中，V g为第一节点g的电位，V s为第三晶体管T3的漏极的电位，Vth3第三晶体管T3的阈值电压，VSS为第二电源电压VSS的电位，μ3为第三晶体管T3的载流子迁移率，W3和L3分别为第三晶体管T3的沟道的宽度和长度，Iref为电流源A输出的电流值，Vdata为数据信号D的显示低电位Vdata，Vref为数据信号D的参考高电位Vref。
最后，请参阅图5，图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。结合图2、图5所示，在发光阶段t3，第一控制信号Vs1为低电位，第二控制信号Vs2为低电位，数据信号D为参考高电位Vref，第二晶体管T2、第四晶体管T4以及第五晶体管T5关闭。由于电容C的存储作用，第一节点g的电位保持不变。也即，第一节点g的电位等于第一节点g在数据电压获取阶段t2时的电位。另外，由于此时第三晶体管T3的漏极与第二电源电压VSS电性连接，第三晶体管T3的漏极的电位等于第二电源电压VSS的电位。
在该发光阶段t3，第一节点g与第三晶体管T3漏极之间的压差可根据以下公式获得：V gs=V g-Vs=V g-VSS=2Iref/μ3Cox(W3/L3)+Vth3+Vdata-Vref，其中，V gs为第一节点g的电位与第三晶体管T3的漏极的电位之间的压差，V g为第一节点g的电位，V s为第三晶体管T3的漏极的电位，Vth3为第三晶体管T3的阈值电压，VSS为第二电源电压VSS的电位，μ3为第三晶体管T3的载流子迁移率，W3和L3分别为第三晶体管T3的沟道的宽度和长度，Iref为电流源A输出的电流值，Vdata为数据信号D的显示低电位Vdata，Vref为数据信号D的参考高电位Vref。
进一步地，计算流经发光器件OLED的电流的公式为：
I OLED＝1/2Cox(μ1W1/L1)(Vgs－Vth1) 2，其中I OLED为流经发光器件OLED的电流，μ1为第一晶体管T1T1的载流子迁移率，W1和L1分别为第一晶体管T1的沟道的宽度和长度，Vgs为第一晶体管T1的栅极与漏极极之间的压差，Vth1为第一晶体管T1的阈值电压。在本申请实施例中，第一晶体管T1的栅极与漏极之间的压差等于第一节点g的电位与第一晶体管T1的漏极的电位之间的压差。另外，由于第一晶体管T1与第三晶体管T3为镜像晶体管，也即，第一晶体管T1的阈值电压等于第二晶体管T2的阈值电压，第一晶体管T1的栅极的电位与第一晶体管T1的漏极的电位之间的压差等于第三晶体管T3的栅极的电位与第三晶体管T3的漏极的电位之间的压差。故将第一节点g的电位与第三晶体管T3的漏极的电位之间的压差V gs=2Iref/μCox(W/L)+Vth3+Vdata-Vref以及Vth1=Vth3代入上式，即有：
I OLED＝1/2Cox(μ1W1/L1)(2Iref/μ3Cox(W3/L3)+Vth3+Vdata-Vref-Vth1) 2
＝1/2Cox(μ1W1/L1)(2Iref/μ3Cox(W3/L3)+Vdata-Vref) 2
由此可见，发光器件OLED的电流与第一晶体管T1的阈值电压无关，实现了补偿功能。发光器件OLED发光，且流经发光器件OLED的电流与第一晶体管T1的阈值电压无关。
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
    所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
    所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
    所述电容的第一端电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源电压；
    所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
  3. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考高电位。
  4. 根据权利要求2所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述数据信号由所述参考高电位跳变至所述显示低电位。
  5. 根据权利要求2所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为所述参考高电位。
  6. 根据权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一电源电压的电压值大于所述第二电源电压的电压值。
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
    所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
    所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
    所述电容的第一端电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源电压。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
  10. 根据权利要求9所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考高电位。
  11. 根据权利要求9所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述数据信号由所述参考高电位跳变至所述显示低电位。
  12. 根据权利要求9所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为所述参考高电位。
  13. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  14. 根据权利要求8所述的像素驱动电路，其中，所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  15. 根据权利要求8所述的像素驱动电路，其中，所述第一电源电压的电压值大于所述第二电源电压的电压值。
  16. 根据权利要求8所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于所述发光器件的阴极端，所述第一晶体管的漏极电性连接于第二电源电压；
    所述第二晶体管的栅极电性连接于第二控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述电容的第二端；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点，所述第三晶体管的漏极电性连接于所述电容的第二端；
    所述第四晶体管的栅极电性连接于第一控制信号，所述第四晶体管的源极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于一用于输出预设电流值的电流源，所述第五晶体管的漏极电性连接于所述第二节点；
    所述电容的第一端电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源电压。
  18. 根据权利要求17所述的显示面板，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括参考高电位以及显示低电位。
  19. 根据权利要求17所述的显示面板，其中，所述第三晶体管与所述第一晶体管为镜像晶体管，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  20. 根据权利要求17所述的显示面板，其中，所述发光器件为有机发光二极管。
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