CN111063294B - 一种像素驱动电路及显示面板 - Google Patents

一种像素驱动电路及显示面板 Download PDF

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CN111063294B
CN111063294B CN201911330186.6A CN201911330186A CN111063294B CN 111063294 B CN111063294 B CN 111063294B CN 201911330186 A CN201911330186 A CN 201911330186A CN 111063294 B CN111063294 B CN 111063294B
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thin film
film transistor
control signal
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CN111063294A (zh
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张丽君
陈书志
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/627,794 priority patent/US11315487B2/en
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • H01L29/772—Field effect transistors
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Abstract

本发明提供一种像素驱动电路及显示面板，该像素驱动电路包括：第三薄膜晶体管的栅极接入第一控制信号，所述第二薄膜晶体管的栅极电性连接于所述第一节点，所述第二薄膜晶体管的漏极电性连接于所述第二节点；所述第二薄膜晶体管的源极电性连接于所述第一薄膜晶体管的漏极；所述第六薄膜晶体管的栅极接入所述第三控制信号，所述第六薄膜晶体管的源极电性连接于所述第二节点，所述第六薄膜晶体管的漏极电性连接于所述发光器件的阳极；所述发光器件的阴极与第二电源电压连接；所述第一电容的一端与所述第一节点电性连接，所述第一电容的另一端与所述第二节点电性连接。本发明的像素驱动电路及显示面板，能够提高显示效果。

Description

一种像素驱动电路及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素驱动电路及显示面板。
【背景技术】
如图1和图2所示，现有的像素驱动电路为2T1 C架构，其包括第一薄膜晶体管T11和第二薄膜晶体管T21，在具体工作过程中，在一帧内(F 1内)，WR处于高电位时，T11开启，Vdata信号写入Cst的一端，数据信号Vdata相对于WR延迟t0时段，WR处于低电位时，T11关闭，Cst将Vdata的电位存储，直至T11再次开启写入新的Vdata信号为止。但是Vdata信号写入瞬间，发光器件D0有电流流过，且其电流(I＝1/2K(VGS-Vth)2)发光器件点亮，可以根据Vdata值的不同显示不同灰阶。从上式中可以看出，发光器件的电流值(即LED的亮度)与T21的栅漏极电压VGS以及阈值电压Vth相关。
然而，受薄膜晶体管制作工艺的限制，不同像素对应的第二薄膜晶体管的Vth(即阈值电压)无法保证完全一致，即使输入相同的其他信号的条件下，流过发光二极管的电流也会有差别，导致亮度不同。宏观上，即产生mura，从而影响显示效果。
因此，有必要提供一种像素驱动电路，以解决现有技术所存在的问题。
【发明内容】
本发明的目的在于提供一种像素驱动电路及显示面板，能够避免产生mura，提高显示效果。
为解决上述技术问题，本发明提供一种像素驱动电路，包括：
第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第六薄膜晶体管、第一电容以及发光器件；
所述第三薄膜晶体管的栅极接入第一控制信号，所述第三薄膜晶体管的源极接入数据信号，所述第三薄膜晶体管的漏极电性连接于所述第一节点；
所述第一薄膜晶体管的栅极接入第三控制信号，所述第一薄膜晶体管的源极接入第一电源电压；
所述第二薄膜晶体管的栅极电性连接于所述第一节点，所述第二薄膜晶体管的漏极电性连接于所述第二节点；所述第二薄膜晶体管的源极电性连接于所述第一薄膜晶体管的漏极；
所述第六薄膜晶体管的栅极接入所述第三控制信号，所述第六薄膜晶体管的源极电性连接于所述第二节点，所述第六薄膜晶体管的漏极电性连接于所述发光器件的阳极；
所述发光器件的阴极与第二电源电压连接；
所述第一电容的一端与所述第一节点电性连接，所述第一电容的另一端与所述第二节点电性连接。
本发明还提供一种显示面板，其包括上述像素驱动电路。
本发明的像素驱动电路及显示面板，通过对现有的像素驱动电路进行改进，从而使得流过发光器件的电流与阈值电压无关，从而避免产生mura，提高了显示效果。
【附图说明】
图1为现有像素驱动电路的结构示意图；
图2为现有像素驱动电路的时序图；
图3为现有第二薄膜晶体管的第一种特性曲线；
图4为现有第二薄膜晶体管的第二种特性曲线；
图5为本发明一实施方式的像素驱动电路的结构示意图；
图6为本发明像素驱动电路的时序图；
图7为本发明像素驱动电路处于初始化阶段的结构示意图；
图8为本发明像素驱动电路处于阈值电压存储阶段的结构示意图；
图9为本发明像素驱动电路处于调控阶段的结构示意图；
图10为本发明像素驱动电路处于数据写入阶段及发光显示阶段的结构示意图；
图11为本发明像素驱动电路处于发光显示阶段的结构示意图；
图12为本发明像素驱动电路中不同颜色的像素的电流变化示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
如图1所示，其中所述第一薄膜晶体管T11的栅极接入控制信号WR，源极接入数据信号Vdata，漏极与第二薄膜晶体管T21的栅极连接，发光器件D0的阳极接入第一电源电压VDD，阴极与第二薄膜晶体管T21的源极连接，第二薄膜晶体管T21的漏极与第二电源电压VSS连接，电容Cst的一端与第二薄膜晶体管T21的栅极连接，电容Cst的另一端与第二薄膜晶体管T21的漏极连接，第二薄膜晶体管T21的栅极和漏极电压分别为VG和VS。
以两个像素对应的第二薄膜晶体管为例，其中一个像素对应的第二薄膜晶体管的阈值电压Vth＝0，另外一个像素对应的第二薄膜晶体管的阈值电压Vth大于0，两者的特性曲线分别如图3和图4所示，图3和图4中横坐标表示VGS电压，单位为V，纵坐标表示流过发光二极管的电流IDS，单位为A，也即输入相同的其他信号的条件下，流过发光二极管的电流也会有差别，导致亮度不同
请参照图5至图12，本发明的像素驱动电路包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第六薄膜晶体管T6、第一电容Cst以及发光器件D1；
所述第三薄膜晶体管T3的栅极接入第一控制信号WR，所述第三薄膜晶体管T3的源极接入数据信号Vdata，所述第三薄膜晶体管T3的漏极电性连接于所述第一节点Q。
所述第一薄膜晶体管T1的栅极接入第三控制信号EM，所述第一薄膜晶体管T1的源极接入第一电源电压OVDD；在一实施方式中，所述第三控制信号EM为使能信号。
所述第二薄膜晶体管T2的栅极电性连接于所述第一节点Q，所述第二薄膜晶体管T2的漏极电性连接于所述第二节点M；所述第二薄膜晶体管T2的源极电性连接于所述第一薄膜晶体管T1的漏极。
所述第六薄膜晶体管T6的栅极接入所述第三控制信号EM，所述第六薄膜晶体管T6的源极电性连接于所述第二节点M，所述第六薄膜晶体管T6的漏极电性连接于所述发光器件D1的阳极。
所述发光器件D1的阴极与第二电源电压OVSS连接；在一实施方式中，所述发光器件D1可为有机发光二极管。其中，所述第一电源电压OVDD以及所述第二电源电压OVSS均为直流电压，且所述第一电源电压OVDD大于所述第二电源电压OVSS。在一实施方式中，所述发光器件D1为有机发光二极管。
所述第一电容Cst的一端与所述第一节点Q电性连接，所述第一电容Cst的另一端与所述第二节点M电性连接。
在一实施方式中，上述像素驱动电路还可包括第五薄膜晶体管T5。
所述第五薄膜晶体管T5的栅极接入第二控制信号PWM，所述第五薄膜晶体管T5的源极接入第一参考电压Vpre，所述第五薄膜晶体管T5的漏极电性连接于所述第一节点Q。
在另一实施方式中，上述像素驱动电路还可包括第四薄膜晶体管T4、此外还可包括第二电容C1。
所述第四薄膜晶体管T4的栅极接入第四控制信号INIT，所述第四薄膜晶体管T4的源极接入第二参考电压Vref，所述第四薄膜晶体管T4的漏极电性连接于所述第二节点M；第四控制信号INIT可为初始化信号。其中所述第一参考电压Vpre和所述第二参考电压Vref均为恒定电压。
所述第二电容C1的一端与所述第一薄膜晶体管T1的源极电性连接，所述第二电容C1的另一端与所述第四薄膜晶体管T4的漏极电性连接。
其中在一实施方式中，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的至少一种。
其中，在一实施方式中，所述第一控制信号WR、所述第二控制信号PWM、所述第三控制信号EM以及所述第四控制信号INIT均由外部时序控制器提供。
在一实施方式中，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6均为N型薄膜晶体管。
所述第一控制信号WR、所述第二控制信号PWM、所述第三控制信号EM以及所述第四控制信号INIT相组合先后对应于初始化阶段、阈值电压存储阶段、调控阶段、数据写入阶段及发光显示阶段；
如图6所示，在所述初始化阶段(t1)，所述第二控制信号PWM、所述第三控制信号EM以及所述第四控制信号INIT均为高电平；所述第一控制信号WR为低电平；
在所述阈值电压存储阶段(t2)，所述第二控制信号PWM和所述第三控制信号EM均为高电平；所述第四控制信号INIT和所述第一控制信号WR为低电平；
在所述调控阶段(t3)，所述第一控制信号WR、所述第二控制信号PWM以及所述第四控制信号INIT均为低电平；所述第三控制信号EM为高电平；
在所述数据写入阶段(t4)，所述第二控制信号PWM、所述第三控制信号EM以及所述第四控制信号INIT均为低电平；所述第一控制信号WR为高电平；
在所述发光阶段(t5)，所述第一控制信号WR、所述第二控制信号PWM以及所述第四控制信号INIT均为低电平；所述第三控制信号EM为高电平。
其中，当所述第一控制信号WR为高电平时，所述数据信号Vdata为高电平。
在具体工作过程中，以一帧为例：
在初始化阶段，如图7所示，其中VG、VS的电压复位(Reset)，结合图6，由于第四控制信号INIT和第二控制信PWM均为高电平，T4、T5同时打开，使Vpre写入第二薄膜晶体管T2的栅极，使得VG等于Vpre，Vref写入第二薄膜晶体管T2的漏极，使得VS等于Vref，Vref电位会使前一帧发光的D1熄灭。第一控制信号WR为低电平，T3关闭。
在所述阈值电压存储阶段，如图8所示，由于第四控制信号INIT为低电平，T4关闭、VS的电位处于漂浮(floating)状态，由于第三控制信号EM为高电平，T1处于开启状态，VG为高电平，T2开始处于开启状态，OVDD通过T1、T2向T2的漏极S充电，直至漏极电压VS等于Vpre-Vth，此时T2关闭，此时VS的电压包含Vth信息。
在所述调控阶段，如图9所示，由于第二控制信PWM为低电平，T5关闭，此时像素驱动电路内的电压无变化，该阶段主要用来调控发光时间占比(即该阶段持续时间越长，相应地发光阶段的时间占比越短，则累计的亮度越低)从而实现亮度调节的功能。
在所述数据写入阶段，如图10所示，由于第一控制信WR为高电平，T3打开，使得T2的栅极写入Vdata，VG等于Vdata，数据信号Vdate也为高电平，T2打开，第三控制信号EM为低电平，此时T1和T6均关闭，由于VS的电位同样处于Floating状态，在Cst、C1的耦合作用下VS的电压相应变化，稳定后VS同样包含Vth。T6的作用为使得D1维持在关闭状态。
在所述发光阶段，如图11所示，由于第一控制信WR为低电平，T3关闭，第三控制信号EM为高电平，T1、T6均打开，D1点亮，此时T2的栅极和漏极的电压分别与数据写入阶段对应的电压相等。
流过二极管D1两端的电压V1如下：
V1＝VGS-Vth-OVSS＝VG-VS-Vth-OVSS＝Vdate-(Vpre-Vth)-Vth-OVSS＝Vdate-Vpre-OVSS
也即D1的电流I＝1/2K(Vdate-Vpre-OVSS)2
可见，VGS中包含的Vth值被消掉，使得流过发光器件的电流与Vth无关。
如图12所示，分别给出红色发光器件11、蓝色发光器件12、绿色发光器件13的电流变化百分比与ΔVth的关系图，横坐标标识ΔVth，纵坐标表示电流变化百分比，当ΔVth在-0.6～0.4内时，电流变化维持在3％以内，可见有效地降低了Vth对电流的影响，避免产生背板mura，从而提高了显示效果。
本发明还提供一种显示面板，其包括上述像素驱动电路。
本发明的像素驱动电路及显示面板，通过对现有的像素驱动电路进行改进，从而使得流过发光器件的电流与阈值电压无关，从而避免产生mura，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (5)

1.一种像素驱动电路，其特征在于，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第六薄膜晶体管、第一电容以及发光器件；
所述第三薄膜晶体管的栅极接入第一控制信号，所述第三薄膜晶体管的源极接入数据信号，所述第三薄膜晶体管的漏极电性连接于第一节点；
所述第一薄膜晶体管的栅极接入第三控制信号，所述第一薄膜晶体管的源极接入第一电源电压；
所述第二薄膜晶体管的栅极电性连接于所述第一节点，所述第二薄膜晶体管的漏极电性连接于第二节点；所述第二薄膜晶体管的源极电性连接于所述第一薄膜晶体管的漏极；
所述第六薄膜晶体管的栅极接入所述第三控制信号，所述第六薄膜晶体管的源极电性连接于所述第二节点，所述第六薄膜晶体管的漏极电性连接于所述发光器件的阳极；
所述发光器件的阴极与第二电源电压连接；
所述第一电容的一端与所述第一节点电性连接，所述第一电容的另一端与所述第二节点电性连接；
所述第一控制信号、第二控制信号、所述第三控制信号以及第四控制信号相组合先后对应于初始化阶段、阈值电压存储阶段、调控阶段、数据写入阶段及发光显示阶段：
在所述初始化阶段，所述第二控制信号、所述第三控制信号以及所述第四控制信号均为高电平；所述第一控制信号为低电平；
在所述阈值电压存储阶段，所述第二控制信号和所述第三控制信号均为高电平；所述第四控制信号和所述第一控制信号均为低电平；
在所述调控阶段，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电平；所述第三控制信号为高电平；
在所述数据写入阶段，所述第二控制信号、所述第三控制信号以及所述第四控制信号均为低电平；所述第一控制信号为高电平；
在所述发光显示阶段，所述第一控制信号、所述第二控制信号以及所述第四控制信号均为低电平；所述第三控制信号为高电平；
所述像素驱动电路还包括第四薄膜晶体管、第五薄膜晶体管以及第二电容；
所述第五薄膜晶体管的栅极接入第二控制信号，所述第五薄膜晶体管的源极接入第一参考电压，所述第五薄膜晶体管的漏极电性连接于所述第一节点；
所述第四薄膜晶体管的栅极接入第四控制信号，所述第四薄膜晶体管的源极接入第二参考电压，所述第四薄膜晶体管的漏极电性连接于所述第二节点；
所述第二电容的一端与所述第一薄膜晶体管的源极电性连接，所述第二电容的另一端与所述第四薄膜晶体管的漏极电性连接。
2.根据权利要求1所述的像素驱动电路，其特征在于，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管均为N型薄膜晶体管。
3.根据权利要求1所述的像素驱动电路，其特征在于，当所述第一控制信号为高电平时，所述数据信号为高电平。
4.根据权利要求1所述的像素驱动电路，其特征在于，所述发光器件为有机发光二极管。
5.一种显示面板，其特征在于，包括权利要求1-4任一项所述的像素驱动电路。
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