WO2020224072A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2020224072A1
WO2020224072A1 PCT/CN2019/099366 CN2019099366W WO2020224072A1 WO 2020224072 A1 WO2020224072 A1 WO 2020224072A1 CN 2019099366 W CN2019099366 W CN 2019099366W WO 2020224072 A1 WO2020224072 A1 WO 2020224072A1
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WO
WIPO (PCT)
Prior art keywords
control signal
transistor
electrically connected
module
node
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Application number
PCT/CN2019/099366
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English (en)
French (fr)
Inventor
吴小玲
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020224072A1 publication Critical patent/WO2020224072A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and a capacitor, commonly known as a 2T1C circuit, but the transistor has the problem of threshold voltage drift.
  • the OLED pixel drive circuit requires a corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, its operation is relatively difficult, and the light-emitting time of the light-emitting device is relatively short.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problem that the compensation structure of the existing pixel driving circuit is relatively complicated and a large area is occupied when designing the layout.
  • the embodiment of the present application provides a pixel driving circuit, including: a compensation module, a light emitting module, a switch module, and a detection module; the compensation module, the switch module, and the detection module are all connected to the light emitting module, and the detection The module is connected to the compensation module;
  • the compensation module is connected to a first control signal and a data signal, and the compensation module is configured to output the data signal to the light emitting module under the control of the first control signal;
  • the detection module is connected to a second control signal and a third control signal, the detection module is used to output an initial voltage to the light emitting module under the control of the second control signal, and the detection module is also used to Detecting the threshold voltage of the light-emitting module under the control of the third control signal;
  • the compensation module is further configured to compensate the data signal according to the threshold voltage under the control of the first control signal
  • the switch module is used to turn off when the light-emitting module emits light
  • the light emitting module includes a first transistor and a light emitting device
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a third node;
  • the anode of the light emitting device is electrically connected to the power supply voltage, and the cathode of the light emitting device is electrically connected to the second node;
  • the first control signal, the second control signal and the third control signal are all provided by an external timing device.
  • the compensation module includes a second transistor and a storage capacitor
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the First node
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the third node.
  • the detection module includes a first digital switch and a second digital switch
  • the first terminal of the first digital switch and the first terminal of the second digital switch are both electrically connected to the third node, and the second terminal of the first digital switch is electrically connected to the initial voltage ,
  • the second terminal of the second digital switch is electrically connected to an external detection circuit, the external detection circuit is used to detect the threshold voltage, and the control terminal of the first digital switch is electrically connected to the second control Signal, the control terminal of the second digital switch is electrically connected to the third control signal.
  • the switch module includes a third transistor
  • the gate of the third transistor is electrically connected to the first control signal, the source of the third transistor is electrically connected to the power supply voltage, and the drain of the third transistor is electrically connected to the The second node.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the timing of the pixel driving circuit includes external detection timing and circuit working timing
  • the external detection sequence includes a first initialization phase and a sensing phase
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the gate of the first transistor is connected to the data signal
  • the reference voltage of the first transistor is connected to the initial voltage
  • the first control signal and the third control signal are both at a high level, the second control signal is at a low level, and the source of the first transistor continues to be connected to the data signal
  • the external detection circuit detects the voltage output by the drain of the first transistor for calculating the threshold voltage of the first transistor
  • the working sequence of the circuit includes a second initialization phase, a compensation phase, and a light-emitting phase;
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the gate of the first transistor is connected to the data signal
  • the reference voltage of the first transistor is connected to the initial voltage
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the compensation module compensates the data signal according to the threshold voltage ;
  • the first control signal, the second control signal, and the third control signal are all at a low potential, and the light-emitting module emits light.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • An embodiment of the present application also provides a pixel driving circuit, including: a compensation module, a light emitting module, a switch module, and a detection module; the compensation module, the switch module, and the detection module are all connected to the light emitting module, the The detection module is connected to the compensation module;
  • the compensation module is connected to a first control signal and a data signal, and the compensation module is configured to output the data signal to the light emitting module under the control of the first control signal;
  • the detection module is connected to a second control signal and a third control signal, the detection module is used to output an initial voltage to the light emitting module under the control of the second control signal, and the detection module is also used to Detecting the threshold voltage of the light-emitting module under the control of the third control signal;
  • the compensation module is further configured to compensate the data signal according to the threshold voltage under the control of the first control signal
  • the switch module is used to turn off when the light-emitting module emits light.
  • the light-emitting module includes a first transistor and a light-emitting device
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a third node;
  • the anode of the light emitting device is electrically connected to the power supply voltage, and the cathode of the light emitting device is electrically connected to the second node.
  • the compensation module includes a second transistor and a storage capacitor
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the First node
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the third node.
  • the detection module includes a first digital switch and a second digital switch
  • the first terminal of the first digital switch and the first terminal of the second digital switch are both electrically connected to the third node, and the second terminal of the first digital switch is electrically connected to the initial voltage ,
  • the second terminal of the second digital switch is electrically connected to an external detection circuit, the external detection circuit is used to detect the threshold voltage, and the control terminal of the first digital switch is electrically connected to the second control Signal, the control terminal of the second digital switch is electrically connected to the third control signal.
  • the switch module includes a third transistor
  • the gate of the third transistor is electrically connected to the first control signal, the source of the third transistor is electrically connected to the power supply voltage, and the drain of the third transistor is electrically connected to the The second node.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the timing of the pixel driving circuit includes external detection timing and circuit working timing
  • the external detection sequence includes a first initialization phase and a sensing phase
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the gate of the first transistor is connected to the data signal
  • the reference voltage of the first transistor is connected to the initial voltage
  • the first control signal and the third control signal are both at a high level, the second control signal is at a low level, and the source of the first transistor continues to be connected to the data signal
  • the external detection circuit detects the voltage output by the drain of the first transistor for calculating the threshold voltage of the first transistor
  • the working sequence of the circuit includes a second initialization phase, a compensation phase, and a light-emitting phase;
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the gate of the first transistor is connected to the data signal
  • the reference voltage of the first transistor is connected to the initial voltage
  • the first control signal and the second control signal are both at a high level, the third control signal is at a low level, and the compensation module compensates the data signal according to the threshold voltage ;
  • the first control signal, the second control signal, and the third control signal are all at a low potential, and the light-emitting module emits light.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the first control signal, the second control signal, and the third control signal are all provided by an external timing device.
  • An embodiment of the application also provides a display panel, which includes a pixel drive circuit, the pixel drive circuit includes: a compensation module, a light emitting module, a switch module, and a detection module; the compensation module, the switch module, and the detection module Are connected to the light emitting module, and the detection module is connected to the compensation module;
  • the compensation module is connected to a first control signal and a data signal, and the compensation module is configured to output the data signal to the light emitting module under the control of the first control signal;
  • the detection module is connected to a second control signal and a third control signal, the detection module is used to output an initial voltage to the light emitting module under the control of the second control signal, and the detection module is also used to Detecting the threshold voltage of the light-emitting module under the control of the third control signal;
  • the compensation module is further configured to compensate the data signal according to the threshold voltage under the control of the first control signal
  • the switch module is used to turn off when the light-emitting module emits light.
  • the light-emitting module includes a first transistor and a light-emitting device
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a third node;
  • the anode of the light emitting device is electrically connected to the power supply voltage, and the cathode of the light emitting device is electrically connected to the second node.
  • the compensation module includes a second transistor and a storage capacitor
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the First node
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the third node.
  • the detection module includes a first digital switch and a second digital switch
  • the first terminal of the first digital switch and the first terminal of the second digital switch are both electrically connected to the third node, and the second terminal of the first digital switch is electrically connected to the initial voltage ,
  • the second terminal of the second digital switch is electrically connected to an external detection circuit, the external detection circuit is used to detect the threshold voltage, and the control terminal of the first digital switch is electrically connected to the second control Signal, the control terminal of the second digital switch is electrically connected to the third control signal.
  • the pixel drive circuit and display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 3T1C structure, and perform effective compensation by detecting the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, thereby It does not need to take up a lot of area during design.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a schematic circuit diagram of a pixel drive circuit provided by an embodiment of the application.
  • FIG. 3 is a timing diagram of the external detection timing of the pixel driving circuit provided by the application embodiment.
  • FIG. 4 is a timing diagram of the circuit working timing of the pixel driving circuit provided by the application embodiment.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • the digital switches described in the embodiments of the present application all include a first terminal, a second terminal, and a control terminal.
  • the control terminal When the control terminal is connected to a high-level signal, the first terminal and the second terminal are conducted; when the control terminal is connected When the low potential signal is input, the first terminal and the second terminal are cut off.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a compensation module 104, a light emitting module 101, a switch module 102, and a detection module 103.
  • the compensation module 104, the switch module 102, and the detection module 103 are all connected to the light emitting module 101, and the detection module 103 is connected to the compensation module 104.
  • the compensation module 104 accesses the first control signal S1 and the data signal Data, and the compensation module 104 is configured to output the data signal Data to the light emitting module 101 under the control of the first control signal S1.
  • the detection module 103 is connected to the second control signal S2 and the third control signal S3.
  • the detection module 103 is used to output the initial voltage Vcm to the light emitting module 101 under the control of the second control signal S2.
  • the detection module 103 is also used to The threshold voltage of the light emitting module 101 is detected under the control of the control signal S3.
  • the compensation module 104 is also used to compensate the data signal Data according to the threshold voltage under the control of the first control signal S1; the switch module 102 is used to turn off when the light-emitting module 101 emits light.
  • the light-emitting module 101 includes a first transistor T1 and a light-emitting device D.
  • the gate of the first transistor T1 is electrically connected to the first node a
  • the source of the first transistor T1 is electrically connected to the second node b
  • the drain of the first transistor T1 is electrically connected to the third node c.
  • the anode of the light emitting device D is electrically connected to the power supply voltage VDD
  • the cathode of the light emitting device D is electrically connected to the second node b.
  • the light emitting device D may be an organic light emitting diode.
  • the first transistor T1 is a driving transistor.
  • the compensation module 104 includes a second transistor T2 and a storage capacitor C.
  • the gate of the second transistor T2 is electrically connected to the first control signal S1
  • the source of the second transistor T2 is electrically connected to the data signal Data
  • the drain of the second transistor T2 is electrically connected to the first node a.
  • the first end of the storage capacitor C is electrically connected to the first node a
  • the second end of the storage capacitor C is electrically connected to the third node c.
  • the detection module 103 includes a first digital switch M1 and a second digital switch M2.
  • the first terminal of the first digital switch M1 and the first terminal of the second digital switch M2 are both electrically connected to the third node c, the second terminal of the first digital switch M1 is electrically connected to the initial voltage Vcm, and the second digital switch
  • the second terminal of M2 is electrically connected to the external detection circuit M3, and the external detection circuit M3 is used to detect the threshold voltage.
  • the control terminal of the first digital switch M1 is electrically connected to the second control signal S2.
  • the second digital switch M2 controls The terminal is electrically connected to the third control signal S3.
  • the switch module 102 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the first control signal S1, the source of the third transistor T3 is electrically connected to the power supply voltage VDD, and the drain of the third transistor T3 is electrically connected to the second node b.
  • the light-emitting device D is disposed at the source terminal of the first transistor T1, so as to avoid the difference in the capacitance and the turn-on voltage inside the light-emitting device D, causing the voltage at the first terminal of the storage capacitor C to be equal to The voltage at the second terminal is different.
  • the third transistor T3 at both ends of the light emitting device D, the light emitting device D can be controlled to emit light, which prevents the light emitting device D from emitting light all the time, reduces the aging of the light emitting device D, and further improves the life of the light emitting device D.
  • the cathode of the light emitting device D is connected to the source of the first transistor T1, and the first transistor T1 is in a saturated state during operation.
  • the voltage drop caused by the resistance of the cathode or anode of the light emitting device D does not affect the flow through the first transistor T1.
  • the current thereby improving the uniformity of the current.
  • the embodiment of the present application adopts a pixel driving circuit with a 3T1C structure, and performs effective compensation by detecting the threshold voltage of the driving transistor in each pixel. It uses fewer components, has a simple and stable structure, and saves costs.
  • the power supply voltage VDD is used to output a predetermined voltage value.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • the first control signal S1, the second control signal S2, and the third control signal S3 are all provided by an external timing device.
  • FIG. 3 is a timing diagram of the external detection timing of the pixel driving circuit provided by the application embodiment.
  • the pixel driving circuit of the embodiment of the present application includes external detection timing.
  • the external detection sequence includes a first initialization phase t1 and a sensing phase t2;
  • the first control signal S1 and the second control signal S2 are both at a high potential, the third control signal S3 is at a low potential, and the gate of the first transistor T1 is connected to the reference voltage Vdata of the data signal Data.
  • the drain of a transistor T1 is connected to the initial voltage Vcm.
  • the first control signal S1 and the third control signal S3 are both high, and the second control signal S2 is low.
  • the source of the first transistor T1 continues to be connected to the reference voltage Vdata of the data signal Data, and the external The detection circuit M3 detects the voltage output by the drain of the first transistor T1 for calculating the threshold voltage of the first transistor T1.
  • FIG. 4 is a timing diagram of the circuit working sequence of the pixel driving circuit provided by the application embodiment.
  • the pixel driving circuit of the embodiment of the present application includes circuit operation timings.
  • the working sequence of the circuit includes a second initialization phase t3, a compensation phase t4, and a light-emitting phase t5.
  • the first control signal S1 and the second control signal S2 are both at a high potential
  • the third control signal S3 is at a low potential
  • the gate of the first transistor T1 is connected to the reference voltage Vdata of the data signal Data
  • the drain of a transistor T1 is connected to the initial voltage Vcm.
  • the compensation phase t4 the first control signal S1 and the second control signal S2 are both at a high level, and the third control signal S3 is at a low level, and the compensation module 104 compensates the data signal Data according to the threshold voltage Vth.
  • the first control signal S1, the second control signal S2, and the third control signal S3 are all low potentials, and the light-emitting module 101 emits light.
  • the current of the light-emitting device D is independent of the threshold voltage of the driving transistor, and a compensation function is realized.
  • the light-emitting device D emits light, and the current flowing through the light-emitting device D is independent of the threshold voltage of the driving transistor.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 3T1C structure, and perform effective compensation by detecting the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, thereby It does not need to take up a lot of area when designing.

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Abstract

一种像素驱动电路及显示面板。采用3T1C结构的像素驱动电路，并通过探测每一像素中的驱动晶体管的阈值电压进而进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，其操作难度较大，且发光器件的发光时间较短。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
所述开关模块用于在所述发光模块发光时截止；
所述发光模块包括第一晶体管以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点；
所述第一控制信号，所述第二控制信号以及所述第三控制信号均由外部时序器提供。
在本申请所述的像素驱动电路中，所述补偿模块包括第二晶体管以及存储电容；
所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
在本申请所述的像素驱动电路中，所述探测模块包括第一数字开关以及第二数字开关；
所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
在本申请所述的像素驱动电路中，所述开关模块包括第三晶体管；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述电源电压，所述第三晶体管的漏极电性连接于所述第二节点。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述像素驱动电路的时序包括外部探测时序以及电路工作时序；
所述外部探测时序包括第一初始化阶段以及感测阶段；
在所述第一初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
在所述感测阶段，所述第一控制信号以及所述第三控制信号均为高电位，所述第二控制信号为低电位，所述第一晶体管的源极继续接入所述数据信号的参考电压，所述外部探测电路检测到所述第一晶体管的漏极输出的电压以供计算出所述第一晶体管的阈值电压；
所述电路工作时序包括第二初始化阶段、补偿阶段以及发光阶段；
在所述第二初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
在所述补偿阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述补偿模块根据所述阈值电压对所述数据信号进行补偿；
在所述发光阶段，所述第一控制信号、所述第二控制信号以及所述第三控制信号均为低电位，所述发光模块发光。
在本申请所述的像素驱动电路中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
本申请实施例还提供一种像素驱动电路，包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
所述开关模块用于在所述发光模块发光时截止。
在本申请所述的像素驱动电路中，所述发光模块包括第一晶体管以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点。
在本申请所述的像素驱动电路中，所述补偿模块包括第二晶体管以及存储电容；
所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
在本申请所述的像素驱动电路中，所述探测模块包括第一数字开关以及第二数字开关；
所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
在本申请所述的像素驱动电路中，所述开关模块包括第三晶体管；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述电源电压，所述第三晶体管的漏极电性连接于所述第二节点。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述像素驱动电路的时序包括外部探测时序以及电路工作时序；
所述外部探测时序包括第一初始化阶段以及感测阶段；
在所述第一初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
在所述感测阶段，所述第一控制信号以及所述第三控制信号均为高电位，所述第二控制信号为低电位，所述第一晶体管的源极继续接入所述数据信号的参考电压，所述外部探测电路检测到所述第一晶体管的漏极输出的电压以供计算出所述第一晶体管的阈值电压；
所述电路工作时序包括第二初始化阶段、补偿阶段以及发光阶段；
在所述第二初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
在所述补偿阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述补偿模块根据所述阈值电压对所述数据信号进行补偿；
在所述发光阶段，所述第一控制信号、所述第二控制信号以及所述第三控制信号均为低电位，所述发光模块发光。
在本申请所述的像素驱动电路中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的像素驱动电路中，所述第一控制信号，所述第二控制信号以及所述第三控制信号均由外部时序器提供。
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
所述开关模块用于在所述发光模块发光时截止。
在本申请所述的显示面板中，所述发光模块包括第一晶体管以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点。
在本申请所述的显示面板中，所述补偿模块包括第二晶体管以及存储电容；
所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
在本申请所述的显示面板中，所述探测模块包括第一数字开关以及第二数字开关；
所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用3T1C结构的像素驱动电路，并通过探测每一像素中的驱动晶体管的阈值电压进而进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的电路示意图；
图3为申请实施例提供的像素驱动电路的外部探测时序的时序图；以及
图4为申请实施例提供的像素驱动电路的电路工作时序的时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
另外，本申请实施例所述的数字开关均包括第一端、第二端以及控制端，其中，当控制端接入高电位信号时，第一端与第二端导通；当控制端接入低电位信号时，第一端与第二端截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：补偿模块104、发光模块101、开关模块102以及探测模块103。补偿模块104、开光模块102以及探测模块103均与发光模块101连接，探测模块103与补偿模块104连接。
其中，补偿模块104接入第一控制信号S1以及数据信号Data，补偿模块104用于在第一控制信号S1的控制下将数据信号Data输出至发光模块101。探测模块103接入第二控制信号S2以及第三控制信号S3，探测模块103用于在第二控制信号S2的控制下将初始电压Vcm输出至发光模块101，探测模块103还用于在第三控制信号S3的控制下检测发光模块101的阈值电压。补偿模块104还用于在第一控制信号S1的控制下根据阈值电压对数据信号Data进行补偿；开关模块102用于在发光模块101发光时截止。
具体的，请参阅图2，图2为本申请实施例提供的像素驱动电路的电路示意图。如图2所示，该发光模块101包括第一晶体管T1以及发光器件D。第一晶体管T1的栅极电性连接于第一节点a，第一晶体管T1的源极电性连接于第二节点b，第一晶体管T1的漏极电性连接于第三节点c。发光器件D的阳极电性连接于电源电压VDD，发光器件D的阴极电性连接于所述第二节点b。在一些实施例中，该发光器件D可以为有机发光二极管。其中，该第一晶体管T1为驱动晶体管。
该补偿模块104包括第二晶体管T2以及存储电容C。第二晶体管T2的栅极电性连接于第一控制信号S1，第二晶体管T2的源极电性连接于数据信号Data，第二晶体管T2的漏极电性连接于第一节点a。存储电容C的第一端电性连接于第一节点a，存储电容C的第二端电性连接于第三节点c。
该探测模块103包括第一数字开关M1以及第二数字开关M2。第一数字开关M1的第一端以及第二数字开关M2的第一端均电性连接于第三节点c，第一数字开关M1的第二端电性连接于初始电压Vcm，第二数字开关M2的第二端电性连接于外部探测电路M3，该外部探测电路M3用于探测阈值电压，第一数字开关M1的控制端电性连接于第二控制信号S2，第二数字开关M2的控制端电性连接于第三控制信号S3。
该开关模块102包括第三晶体管T3。第三晶体管T3的栅极电性连接于第一控制信号S1，第三晶体管T3的源极电性连接于电源电压VDD，第三晶体管T3的漏极电性连接于第二节点b。
需要说明的是，本申请实施例通过将发光器件D设置在第一晶体管T1的源极端，从而可以避免因发光器件D内部的电容及开启电压的不同，造成存储电容C第一端的电压与第二端的电压不同。并且，通过设置第三晶体管T3位于发光器件D的两端，从而可以控制发光器件D发光，避免了发光器件D一直发光，减弱发光器件D老化，进而提高发光器件D寿命。另外，发光器件D的阴极与第一晶体管T1的源极相连，第一晶体管T1在工作时处于饱和状态，因发光器件D的阴极或阳极电阻引起的压降，不影响流经第一晶体管T1的电流，进而提高了电流的均匀性。
本申请实施例采用3T1C结构的像素驱动电路，并通过探测每一像素中的驱动晶体管的阈值电压进二进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。
在一些实施例中，电源电压VDD用于输出一预设电压值。第一晶体管T1、第二晶体管T2以及第三晶体管T3均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
在一些实施例中，第一控制信号S1，第二控制信号S2以及第三控制信号S3均由外部时序器提供。
进一步的，请参阅图3，图3为申请实施例提供的像素驱动电路的外部探测时序的时序图。结合图2、图3所示，本申请实施例的像素驱动电路包括外部探测时序。该外部探测时序包括第一初始化阶段t1以及感测阶段t2；
在第一初始化阶段t1，第一控制信号S1以及第二控制信号S2均为高电位，第三控制信号S3为低电位，第一晶体管T1的栅极接入数据信号Data的参考电压Vdata，第一晶体管T1的漏极接入初始电压Vcm。在感测阶段t2，第一控制信号S1以及第三控制信号S3均为高电位，第二控制信号S2为低电位，第一晶体管T1的源极继续接入数据信号Data的参考电压Vdata，外部探测电路M3检测到第一晶体管T1的漏极输出的电压以供计算出第一晶体管T1的阈值电压。
请参阅图4，图4为申请实施例提供的像素驱动电路的电路工作时序的时序图。结合图2、图4所示，本申请实施例的像素驱动电路包括电路工作时序。该电路工作时序包括第二初始化阶段t3、补偿阶段t4以及发光阶段t5。在第二初始化阶段t3，第一控制信号S1以及第二控制信号S2均为高电位，第三控制信号S3为低电位，第一晶体管T1的栅极接入数据信号Data的参考电压Vdata，第一晶体管T1的漏极接入初始电压Vcm。在补偿阶段t4，第一控制信号S1以及第二控制信号S2均为高电位，第三控制信号S3为低电位，补偿模块104根据阈值电压Vth对数据信号Data进行补偿。在发光阶段t5，第一控制信号S1、第二控制信号S2以及第三控制信号S3均为低电位，发光模块101发光。
因此，发光器件D的电流与驱动晶体管的阈值电压无关，实现了补偿功能，发光器件D发光，且流经发光器件D的电流与驱动晶体管的阈值电压无关。
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用3T1C结构的像素驱动电路，并通过探测每一像素中的驱动晶体管的阈值电压进而进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
    所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
    所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
    所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
    所述开关模块用于在所述发光模块发光时截止；
    所述发光模块包括第一晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点；
    所述第一控制信号，所述第二控制信号以及所述第三控制信号均由外部时序器提供。
  2. 根据权利要求1所述的像素驱动电路，其中，所述补偿模块包括第二晶体管以及存储电容；
    所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述探测模块包括第一数字开关以及第二数字开关；
    所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
  4. 根据权利要求3所述的像素驱动电路，其中，所述开关模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述电源电压，所述第三晶体管的漏极电性连接于所述第二节点。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  6. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路的时序包括外部探测时序以及电路工作时序；
    所述外部探测时序包括第一初始化阶段以及感测阶段；
    在所述第一初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
    在所述感测阶段，所述第一控制信号以及所述第三控制信号均为高电位，所述第二控制信号为低电位，所述第一晶体管的源极继续接入所述数据信号的参考电压，所述外部探测电路检测到所述第一晶体管的漏极输出的电压以供计算出所述第一晶体管的阈值电压；
    所述电路工作时序包括第二初始化阶段、补偿阶段以及发光阶段；
    在所述第二初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
    在所述补偿阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述补偿模块根据所述阈值电压对所述数据信号进行补偿；
    在所述发光阶段，所述第一控制信号、所述第二控制信号以及所述第三控制信号均为低电位，所述发光模块发光。
  7. 根据权利要求6所述的像素驱动电路，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  8. 一种像素驱动电路，其包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
    所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
    所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
    所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
    所述开关模块用于在所述发光模块发光时截止。
  9. 根据权利要求8所述的像素驱动电路，其中，所述发光模块包括第一晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点。
  10. 根据权利要求9所述的像素驱动电路，其中，所述补偿模块包括第二晶体管以及存储电容；
    所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
  11. 根据权利要求10所述的像素驱动电路，其中，所述探测模块包括第一数字开关以及第二数字开关；
    所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
  12. 根据权利要求11所述的像素驱动电路，其中，所述开关模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的源极电性连接于所述电源电压，所述第三晶体管的漏极电性连接于所述第二节点。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  14. 根据权利要求12所述的像素驱动电路，其中，所述像素驱动电路的时序包括外部探测时序以及电路工作时序；
    所述外部探测时序包括第一初始化阶段以及感测阶段；
    在所述第一初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
    在所述感测阶段，所述第一控制信号以及所述第三控制信号均为高电位，所述第二控制信号为低电位，所述第一晶体管的源极继续接入所述数据信号的参考电压，所述外部探测电路检测到所述第一晶体管的漏极输出的电压以供计算出所述第一晶体管的阈值电压；
    所述电路工作时序包括第二初始化阶段、补偿阶段以及发光阶段；
    在所述第二初始化阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述第一晶体管的栅极接入所述数据信号的参考电压，所述第一晶体管的漏极接入所述初始电压；
    在所述补偿阶段，所述第一控制信号以及所述第二控制信号均为高电位，所述第三控制信号为低电位，所述补偿模块根据所述阈值电压对所述数据信号进行补偿；
    在所述发光阶段，所述第一控制信号、所述第二控制信号以及所述第三控制信号均为低电位，所述发光模块发光。
  15. 根据权利要求14所述的像素驱动电路，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  16. 根据权利要求8所述的像素驱动电路，其中，所述第一控制信号，所述第二控制信号以及所述第三控制信号均由外部时序器提供。
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：补偿模块、发光模块、开关模块以及探测模块；所述补偿模块、所述开光模块以及所述探测模块均与所述发光模块连接，所述探测模块与所述补偿模块连接；
    所述补偿模块接入第一控制信号以及数据信号，所述补偿模块用于在所述第一控制信号的控制下将所述数据信号输出至所述发光模块；
    所述探测模块接入第二控制信号以及第三控制信号，所述探测模块用于在所述第二控制信号的控制下将初始电压输出至所述发光模块，所述探测模块还用于在所述第三控制信号的控制下检测所述发光模块的阈值电压；
    所述补偿模块还用于在所述第一控制信号的控制下根据所述阈值电压对所述数据信号进行补偿；
    所述开关模块用于在所述发光模块发光时截止。
  18. 根据权利要求17所述的显示面板，其中，所述发光模块包括第一晶体管以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述发光器件的阳极电性连接于电源电压，所述发光器件的阴极电性连接于所述第二节点。
  19. 根据权利要求18所述的显示面板，其中，所述补偿模块包括第二晶体管以及存储电容；
    所述第二晶体管的栅极电性连接于所述第一控制信号，所述第二晶体管的源极电性连接于所述数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第三节点。
  20. 根据权利要求19所述的显示面板，其中，所述探测模块包括第一数字开关以及第二数字开关；
    所述第一数字开关的第一端以及所述第二数字开关的第一端均电性连接于所述第三节点，所述第一数字开关的第二端电性连接于所述初始电压，所述第二数字开关的第二端电性连接于外部探测电路，所述外部探测电路用于探测所述阈值电压，所述第一数字开关的控制端电性连接于所述第二控制信号，所述第二数字开关的控制端电性连接于所述第三控制信号。
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CN101582235A (zh) * 2008-05-17 2009-11-18 乐金显示有限公司 发光显示器及其驱动方法
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CN108399894A (zh) * 2018-03-28 2018-08-14 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN108877667A (zh) * 2018-07-26 2018-11-23 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
CN109584788A (zh) * 2019-01-22 2019-04-05 京东方科技集团股份有限公司 像素驱动电路、像素单元及驱动方法、阵列基板、显示装置
CN110060630A (zh) * 2019-05-06 2019-07-26 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板

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