WO2017045376A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2017045376A1
WO2017045376A1 PCT/CN2016/075464 CN2016075464W WO2017045376A1 WO 2017045376 A1 WO2017045376 A1 WO 2017045376A1 CN 2016075464 W CN2016075464 W CN 2016075464W WO 2017045376 A1 WO2017045376 A1 WO 2017045376A1
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Prior art keywords
node
transistor
signal
control
unit
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PCT/CN2016/075464
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English (en)
French (fr)
Inventor
栗峰
王宝强
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to EP16781656.0A priority Critical patent/EP3355296B1/en
Priority to US15/307,182 priority patent/US10192484B2/en
Publication of WO2017045376A1 publication Critical patent/WO2017045376A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
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    • G09G2300/0421—Structural details of the set of electrodes
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • OLED Organic Light-emitting diodes
  • the working principle is that electrons and holes combine to generate radiation, that is, directly convert electrical energy into light energy, so a stable current is needed to control the illumination.
  • OLEDs are driven by a drive transistor (English: Drive Thin Film Transistor, DTFT), which is usually a P-type switch.
  • the gate of the DTFT is connected to the data input terminal V data
  • the source is connected to the constant voltage input terminal V DD
  • the drain is connected to the OLED.
  • a voltage difference V GS is generated between the V DD of the source and the V data of the gate, thereby causing the DTFT to be turned on to drive the OLED
  • the driving current I OLED K(V GS - V th ) 2 of the OLED , wherein V th is The threshold voltage of the DTFT itself, K is a constant.
  • the threshold voltage Vth of the DTFT may affect the driving current I OLED flowing through the OLED, and the threshold voltage of the DTFT in each pixel unit may be caused by manufacturing process errors, device aging, and the like. Vth drifts, causing a deviation in the driving current flowing through the OLED, thereby affecting the display effect.
  • Embodiments of the present invention provide a pixel circuit and a driving method thereof, a display panel, and a display device, which can avoid the influence of a threshold voltage drift of a driving transistor on a driving current of an active light emitting device, thereby improving uniformity of a display image.
  • a pixel circuit comprising: a preset unit, a compensation unit, a data writing unit, a driving unit, an energy storage unit, and a light emitting unit.
  • the preset unit is connected to the first scan signal end, the first node, the second node, the third node, and the second level end.
  • the presetting unit is configured to connect the first node and the third node with the second level end under the control of the signal of the first scanning signal end; and connect the first scanning signal end with the second node.
  • the compensation unit is connected to the second scan signal end, the first node, the second node, the third node, the fourth node, and the second level end.
  • the compensation unit is configured to connect the first node and the third node with the second level terminal under the control of the signal of the second scan signal end; and connect the fourth node with the second node.
  • the data writing unit is connected to the third scanning signal terminal, the data signal terminal and the first node, and is configured to connect the data signal terminal to the first node under the control of the signal of the third scanning signal terminal.
  • the energy storage unit is coupled to the first node and the second node and configured to store a voltage between the first node and the second node.
  • the driving unit is connected to the second node, the third node, and the fourth node, and is configured to output a driving signal to the third node under the control of the voltage between the second node and the fourth node.
  • the light emitting unit includes a light emitting control unit and a light emitting device.
  • the illumination control unit is connected to the control signal end, the third node, the fourth node, the first level end and the light emitting device; the light emitting device is connected to the illumination control unit and the second level terminal.
  • the illumination control unit is configured to connect the first level end to the fourth node under the control of the control signal end, and connect the third node to the light emitting device; the light emitting device is configured to be at the driving signal and the signal of the second level end Control the light.
  • the preset unit includes: a third transistor, a fourth transistor, and a fifth transistor.
  • the control electrode of the third transistor is connected to the first scan signal end, the first end of the third transistor is connected to the first scan signal end, and the second end of the third transistor is connected to the second node.
  • the control electrode of the fourth transistor is connected to the first scan line number terminal, the first end of the fourth transistor is connected to the first node, and the second end of the fourth transistor is connected to the second level terminal.
  • the control electrode of the fifth transistor is connected to the first scan signal terminal, the first end of the fifth transistor is connected to the third node, and the second end of the fifth transistor is connected to the second level terminal.
  • the compensation unit comprises: a sixth transistor, a seventh transistor, and an eighth transistor.
  • the control electrode of the sixth transistor is connected to the second scan signal terminal, the first end of the sixth transistor is connected to the first node, and the second end of the sixth transistor is connected to the second level terminal.
  • the control electrode of the seventh transistor is connected to the second scan signal terminal, the first end of the seventh transistor is connected to the fourth node, and the second end of the seventh transistor is connected to the second node.
  • the control electrode of the eighth transistor is connected to the second scan signal terminal, the first end of the eighth transistor is connected to the third node, and the second end of the eighth transistor is connected to the second level terminal.
  • the data writing unit includes: a first transistor, a control electrode of the first transistor is connected to the third scan signal end, and the first end of the first transistor is connected to the data signal end, and the first transistor is The two ends are connected to the first node.
  • the driving unit includes a second transistor, the control electrode of the second transistor is connected to the second node, the first end of the second transistor is connected to the fourth node, and the second end of the second transistor is first Node connection.
  • the energy storage unit includes a first capacitor, a first pole of the first capacitor is coupled to the first node, and a second pole of the first capacitor is coupled to the second node.
  • the illumination control unit comprises a ninth transistor and a tenth transistor
  • the illumination device comprises an organic light emitting diode.
  • the control electrode of the ninth transistor is connected to the control signal terminal, the first end of the ninth transistor is connected to the first level terminal, and the second end of the ninth transistor is connected to the fourth node.
  • the control electrode of the tenth transistor is connected to the control signal end, the first end of the tenth transistor is connected to the third node, and the second end of the tenth transistor is connected to the first electrode of the organic light emitting diode.
  • the second pole of the organic light emitting diode is connected to the second level terminal.
  • a display panel comprising any of the above pixel circuits.
  • a display device comprising the above display panel.
  • a driving method of a pixel circuit for driving any one of the above pixel circuits including: in a first stage, the pre-setting unit turns the first node under the control of a signal of the first scanning signal end And the level of the third node is connected to the second level end; and the first scan signal end is connected to the second node.
  • the signal of the compensation unit at the second scanning signal end The level of the first node and the third node are connected to the second level end and the fourth node is connected to the second node.
  • the energy storage unit stores the threshold voltage of the drive unit.
  • the data writing unit connects the data signal end to the first node under the control of the signal of the third scanning signal terminal.
  • the driving unit outputs a driving signal to the third node under the control of the voltage between the second node and the fourth node.
  • the illumination control unit connects the first level end to the fourth node under the control of the signal at the control signal end, and connects the third node to the first pole of the light emitting device; the control of the signal of the light emitting device at the driving signal and the second level end Under the light.
  • the preset unit includes: a third transistor, a fourth transistor, and a fifth transistor.
  • the third transistor, the fourth transistor, and the fifth transistor are both in an on state under the control of the signal at the first scan signal end, and the first node is connected to the second level terminal through the fourth transistor, and the third The node is connected to the second level terminal through the fifth transistor.
  • the first scan signal terminal is connected to the second node through the third transistor.
  • the compensation unit comprises: a sixth transistor, a seventh transistor, and an eighth transistor.
  • the sixth transistor, the seventh transistor, and the eighth transistor are both in an on state under the control of the signal at the second scan signal end, and the first node is connected to the second level terminal through the sixth transistor, and the third The node is connected to the second level terminal through the eighth transistor.
  • the second node is connected to the fourth node through the seventh transistor.
  • the data writing unit comprises: a first transistor.
  • the first transistor In the third stage, the first transistor is in an on state under the control of the signal at the third scanning signal terminal.
  • the data signal terminal is connected to the first node through the first transistor.
  • the light emitting unit includes a ninth transistor, a tenth transistor, and an organic light emitting diode.
  • the ninth transistor and the tenth transistor are both in an on state under the control of the signal at the control signal end, and the first level terminal is connected to the fourth node through the ninth transistor, and the third node is passed through the tenth transistor and the organic
  • the first pole of the light emitting diode is connected, and the organic light emitting diode is controlled to emit light by a driving signal and a signal of the second level end connected to the second pole of the organic light emitting diode.
  • Embodiments of the present invention provide a pixel circuit and a driving method thereof, a display panel, and a display device, which are capable of performing threshold voltage compensation on a driving unit by a compensation unit to avoid driving crystals of the driving unit
  • the influence of the threshold voltage drift of the body tube on the driving current of the active light emitting device improves the uniformity of the displayed image.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic circuit diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram showing a signal timing state of the pixel circuit shown in FIG. 2;
  • FIG. 4 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a first stage
  • FIG. 5 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a second stage
  • FIG. 6 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a third stage
  • FIG. 7 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in the fourth stage.
  • the transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the transistors used in the embodiments of the present invention include driving transistors, mainly in addition to the driving transistors. It is a switching transistor. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable.
  • the gate is controlled extremely, and in order to distinguish the two poles of the transistor except the gate, The source is referred to as the first end and the drain is referred to as the second end. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present invention includes two types of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off.
  • the driving transistor includes a P type and an N type, wherein the P type driving transistor has a low level at the gate voltage (the gate voltage is less than the source voltage), And the absolute value of the voltage difference of the gate source is greater than the threshold voltage in an amplified state or a saturated state; wherein the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the gate source When the absolute value of the differential pressure is greater than the threshold voltage, it is in an amplified state or a saturated state.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention.
  • an embodiment of the present invention provides a pixel circuit including: a preset unit 11 , a compensation unit 12 , a data writing unit 13 , a driving unit 14 , an energy storage unit 15 , and a light emitting unit 16 .
  • the presetting unit 11 is connected to the first scanning signal terminal S1, the first node a, the second node b, the third node c, and the second level terminal V2.
  • the presetting unit 11 is configured to connect the first node a and the third node c with the second level terminal V2 under the control of the signal of the first scanning signal terminal S1; and the first scanning signal terminal S1 and the second node b connection.
  • the compensation unit 12 is connected to the second scan signal terminal S2, the first node a, the second node b, the third node c, the fourth node d, and the second level terminal V2.
  • the compensation unit 12 is configured to connect the first node a and the third node c with the second level terminal V2 under the control of the signal of the second scan signal terminal S2; and connect the fourth node d with the second node b.
  • the data writing unit 13 is connected to the third scanning signal terminal S3, the data signal terminal Data and the first node a, and is configured to use the data signal terminal Data and the first data under the control of the signal of the third scanning signal terminal S3. Node a is connected.
  • the energy storage unit 14 is coupled to the first node a and the second node b, and is configured to store a voltage between the first node a and the second node b.
  • the driving unit 15 is connected to the second node b, the third node c and the fourth node d, and is configured to output a driving signal to the third node c under the control of the voltage between the second node b and the fourth node d;
  • the light emitting unit 16 includes a light emitting control unit and a light emitting device.
  • the illumination control unit is connected to the control signal terminal EM, the third node c, the fourth node d, the first level terminal V1 and the light emitting device; the light emitting device is connected to the illumination control unit and the second level terminal V2.
  • the illumination control unit is configured to connect the signal of the first level terminal V1 with the fourth node d under the control of the signal of the control signal terminal EM, and to connect the third node c with the light emitting device.
  • the light emitting device is configured to emit light under the control of the drive signal and the signal of the second level terminal V2.
  • the presetting unit aligns the levels of the first node and the third node with the second level end under the signal control of the first scanning signal end; and writes the signal of the first scanning signal end to the second node;
  • the compensation unit aligns the levels of the first node and the third node with the second level end under the signal control of the second scanning signal end;
  • the compensation unit discharges the second node through the fourth node under the control of the signal of the second scanning signal end;
  • the energy storage unit stores the threshold voltage of the driving unit; again, the data writing unit writes the signal of the data signal end to the first node under the control of the third scanning signal end; finally, the driving unit is under the control of the second node and the fourth node Outputting a driving signal to the third node;
  • the lighting unit writes the signal of the first level end to the fourth node under the control of the control signal end, receives the driving signal of the third node under the control of the control signal end,
  • the pixel circuit provided by the embodiment of the present invention can perform threshold voltage compensation on the driving unit by the compensation unit to avoid the influence of the threshold voltage drift of the driving transistor of the driving unit on the driving current of the active light emitting device, thereby improving the uniformity of the display image.
  • FIG. 2 is a schematic circuit diagram of the pixel circuit shown in FIG. 1.
  • the pre-set unit 11 includes a third transistor M3, a fourth transistor M4, and a fifth crystal M5 tube.
  • the gate of the third transistor M3 is connected to the first scanning signal terminal S1, the first terminal of the third transistor M3 is connected to the first scanning signal terminal S1, and the second terminal of the third transistor M3 is connected to the second node b.
  • the gate of the fourth transistor M4 is connected to the first scan line number terminal S1, the first end of the fourth transistor M4 is connected to the first node a, and the second end of the fourth transistor M4 is connected to the second level terminal V2.
  • Fifth The gate of the transistor M5 is connected to the first scanning signal terminal S1, the first terminal of the fifth transistor M5 is connected to the third node c, and the second terminal of the fifth transistor M5 is connected to the second level terminal V2.
  • the compensation unit 12 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
  • the gate of the sixth transistor M6 is connected to the second scan signal terminal S2, the first end of the sixth transistor M6 is connected to the first node a, and the second end of the sixth transistor M6 is connected to the second level terminal V2.
  • the gate of the seventh transistor M7 is connected to the second scan signal terminal S2, the first end of the seventh transistor M7 is connected to the fourth node d, and the second end of the seventh transistor M7 is connected to the second node b.
  • the gate of the eighth transistor M8 is connected to the second scan signal terminal S2, the first end of the eighth transistor M8 is connected to the third node c, and the second end of the eighth transistor M8 is connected to the second level terminal V2.
  • the data writing unit 13 includes a first transistor M1, the gate of the first transistor M1 is connected to the third scanning signal terminal S3, the first end of the first transistor M1 is connected to the data signal terminal Data, and the second transistor M1 is second.
  • the terminal is connected to the first node a.
  • the driving unit 14 includes a second transistor M2, the gate of the second transistor M2 is connected to the second node b, the first end of the second transistor M2 is connected to the fourth node d, and the second end of the second transistor M2 is connected to the first node a connection.
  • the energy storage unit 15 includes a first capacitor C1.
  • the first pole of the first capacitor C1 is connected to the first node a, and the second pole of the first capacitor C1 is connected to the second node b.
  • the light emitting unit 16 includes a light emitting control unit including a ninth transistor M9 and a tenth transistor M10, and a light emitting device including an organic light emitting diode OLED.
  • the gate of the ninth transistor M9 is connected to the control signal terminal EM, the first terminal of the ninth transistor M9 is connected to the first level terminal V1, and the second terminal of the ninth transistor M9 is connected to the fourth node d.
  • the gate of the tenth transistor M10 is connected to the control signal terminal EM, the first end of the tenth transistor M10 is connected to the third node c, and the second end of the tenth transistor M10 is connected to the first electrode of the organic light emitting diode OLED.
  • the second pole of the organic light emitting diode OLED is connected to the second level terminal V2.
  • the second transistor M2 is a driving transistor, and the other transistors are switching transistors.
  • the function of each unit in the process of threshold voltage compensation for the driving unit will be briefly described below.
  • the third transistor M3, the fourth transistor M4, and the fifth transistor M5 in the presetting unit 11 are both in an on state under the signal control of the first scanning signal terminal S1, and the first node a is The level is aligned with the second level terminal V2 through the fourth transistor M4, and the level of the third node c is aligned with the second level terminal V2 through the fifth transistor M5.
  • the signal of the first scan signal terminal S1 is written to the second node b through the third transistor M3.
  • the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 in the compensation unit 12 are both in an on state under the control of the signal of the second scanning signal terminal S2, and the level of the first node a is passed through the sixth transistor M6.
  • the second level terminal V2 is aligned with the second level terminal V2
  • the level of the third node c is aligned with the second level terminal V2 through the eighth transistor M8.
  • the second node b is discharged through the seventh transistor M7 and the fourth node d.
  • the first transistor M1 in the data writing unit 13 is in an on state under the control of the signal of the third scanning signal terminal S3.
  • the signal of the data signal terminal Data is written to the first node a through the first transistor M1.
  • the ninth transistor M9 and the tenth transistor M10 are both in an on state under the control of the signal of the control signal terminal EM, and the signal of the first level terminal V1 is written into the fourth node d through the ninth transistor M9.
  • the driving signal of the third node c is input to the first pole of the organic light emitting diode OLED through the tenth transistor M10, and the organic light emitting diode OLED is controlled by the driving signal and the signal of the second level terminal V2 of the second pole and the organic light emitting diode OLED.
  • C1 in the energy storage unit stores the threshold voltage of M2 in the driving unit, in the lighting phase, threshold voltage compensation of M2 in the driving unit can be directly performed through the stored threshold voltage.
  • each of the above transistors is of the same type of "N-type” or "P-type” transistor.
  • the light emitting device herein may be an active light emitting diode OLED.
  • the level V 2 of the second level terminal V2 is lower than the level V 1 of the first level terminal V1.
  • the low level can be a ground terminal.
  • the first extremely anode OLED is taken as an example.
  • the pixel circuit provided by the embodiment of the invention can perform threshold voltage compensation on the driving unit by the compensation unit, thereby avoiding the influence of the threshold voltage drift of the driving transistor of the driving unit on the driving current of the active light emitting device, thereby improving the uniformity of the display image.
  • FIG. 3 is a schematic diagram showing a signal timing state of the pixel circuit shown in FIG.
  • the driving method of the pixel circuit includes: in the first stage, the signal on the first scanning signal end is valid, and the signal control of the preset unit at the first scanning signal end The levels of the first node and the third node are connected to the second level end; and the first scan signal end is connected to the second node.
  • the signal of the second scanning signal end is valid, and the compensation unit connects the first node and the third node with the second level end under the control of the signal of the second scanning signal end, and connects the fourth node with the second node.
  • the energy storage unit stores the threshold voltage of the drive unit.
  • the signal of the third scanning signal end is valid
  • the signal of the data signal end is valid
  • the data writing unit connects the data signal end with the first node under the control of the signal of the third scanning signal end.
  • the signal of the control signal terminal is valid
  • the driving unit outputs the driving signal to the third node under the control of the voltage between the second node and the fourth node.
  • the light-emitting unit connects the first level end to the fourth node under the control of the control signal end, receives the driving signal of the third node, and emits light under the control of the driving signal and the signal of the second level end.
  • the preset unit includes: a third transistor, a fourth transistor, and a fifth transistor.
  • the third transistor, the fourth transistor, and the fifth transistor are both in an on state under the control of the signal of the first scan signal terminal, and the level of the first node is connected to the second level terminal through the fourth transistor.
  • the level of the third node is connected to the second level terminal through the fifth transistor.
  • the signal of the first scan signal terminal is connected to the second node through the third transistor.
  • the compensation unit comprises: a sixth transistor, a seventh transistor, and an eighth transistor.
  • the sixth transistor, the seventh transistor, and the eighth transistor are both in an on state under the signal control of the second scan signal terminal, and the level of the first node is connected to the second level terminal through the sixth transistor, The level of the third node is connected to the second level terminal through the eighth transistor.
  • the second node is connected to the fourth node through the seventh transistor.
  • the data writing unit comprises: a first transistor.
  • the first transistor In the third stage, the first transistor is in an on state under the control of the signal at the third scanning signal terminal.
  • the signal at the data signal end is connected to the first node through the first transistor.
  • the light emitting unit includes a ninth transistor, a tenth transistor, and an organic light emitting diode.
  • the ninth transistor and the tenth transistor are both in an on state under the control of the signal at the control signal end, and the signal at the first level is connected to the fourth node through the ninth transistor, and the third node is passed through the tenth transistor.
  • the first pole of the organic light emitting diode is connected, and the organic light is controlled by the driving signal and the signal of the second level end connected to the second pole of the organic light emitting diode
  • the photodiode emits light.
  • the driving method of the pixel circuit provided by the embodiment of the invention can perform threshold voltage compensation on the driving unit by the compensation unit, thereby avoiding the influence of the threshold voltage drift of the driving transistor of the driving unit on the driving current of the active light emitting device, thereby improving the display image. Uniformity.
  • FIG. 4 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a first stage.
  • FIG. 5 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in the second stage.
  • FIG. 6 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in the third stage.
  • FIG. 7 is a schematic equivalent circuit diagram of the pixel circuit shown in FIG. 2 in the fourth stage.
  • the solid lines indicate the transistors and the lines that are turned on, and the broken lines indicate the transistors and the lines that are not turned on.
  • each transistor is an "N" type transistor, a high-level V DD signal is applied to the V1 terminal, and a low-level V SS signal is applied to the V2 terminal as an example.
  • FIG. 3 is a schematic diagram of a signal timing state of the pixel circuit, and an equivalent circuit diagram of the working states of the pixel circuits provided in FIGS. 4-7, and an embodiment of the present invention provides a pixel.
  • the driving method of the circuit, the working principle of the circuit is divided into four parts, they are the preset stage of the first stage T1, the threshold voltage writing stage of the M2 of the second stage T2, and the third stage T3 is the data signal writing stage.
  • the fourth stage T4 is the lighting stage.
  • S1, S3, and EM are low-voltage cutoff signals, and S2 is a high-voltage turn-on signal. status.
  • M2, M6, M7, and M8 are turned on, and node b is discharged to the threshold voltage (V th ) of M2 through M7 and M8, and the potentials of nodes a and c remain at a low level.
  • capacitor C1 holds the threshold voltage of M2 on the C1 capacitor.
  • M1 is turned on, Data input data signal V Data , node a point potential is consistent with V Data , since M7, M8 are turned off, due to the bootstrap action of capacitor C1, node b point potential is V Data + V th .
  • S1, S2, and S3 are low-voltage cutoff signals
  • EM is a high-voltage turn-on signal state.
  • M9 and M10 are turned on, and the potential of the node b in the light-emitting phase is the same as that in the T3 phase, and both are V Data + V th . Since M2 is in the saturation phase, according to the transistor saturation region current formula:
  • V GS is the voltage difference between the source and gate of M2
  • ⁇ , C ox is the process constant
  • W is the M2 channel width
  • L is the channel length of the transistor
  • both W and L are selectively designtable constants
  • V DD is the set value, so it can be seen from the above equation that the operating current I OLED is not affected by the threshold voltage V th , only related to V Data . It completely solves the problem that the threshold voltage drift of M2 due to the process process and long-time operation, eliminates the influence on the I OLED , and ensures the normal operation of the OLED.
  • Embodiments of the present invention provide a display panel including the above-described pixel circuit.
  • Embodiments of the present invention provide a display device including the above display panel.
  • the display device can also be a display device such as an electronic paper, a mobile phone, a television, a digital photo frame, or the like.
  • the display device provided by the embodiment of the invention can perform threshold voltage compensation on the driving unit by the compensation unit to avoid the influence of the threshold voltage drift of the driving transistor of the driving unit on the driving current of the active light emitting device, thereby improving the uniformity of the display image.

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Abstract

像素电路及其驱动方法、显示面板和显示装置，涉及显示技术领域，能够避免驱动晶体管阈值电压漂移对有源发光器件驱动电流的影响。该像素电路包括：预置单元（11）、补偿单元（12）、数据写入单元（13），驱动单元（14）、储能单元（15）、发光单元（16）；能够用于显示器制造。

Description

像素电路及其驱动方法、显示面板和显示装置
本申请要求2015年9月17日递交的中国专利申请第201510596094.8号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及像素电路及其驱动方法、显示面板和显示装置。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，简称AMOLED)面板具有能耗低、生产成本低、视角宽、响应速度快等优点，因此AMOLED显示器已经逐渐取代传统的液晶显示器。有机发光二极管(OLED)属于电流驱动，其工作原理是电子和空穴结合产生辐射光，也就是直接把电能转化为光能，所以显示时需要稳定的电流来控制发光。
目前OLED是通过一个驱动晶体管(英文：Drive Thin Film Transistor，简称：DTFT)进行驱动，DTFT通常是P型的开关管。DTFT的栅极连接数据输入端Vdata，源极连接恒压的电源输入端VDD，漏极连接OLED。由源极的VDD与栅极的Vdata之间产生电压差VGS，从而使得DTFT导通以驱动OLED，OLED的驱动电流IOLED＝K(VGS-Vth)2，其中Vth为DTFT本身的阈值电压，K为常数。
由上述驱动电流公式可以看出，DTFT的阈值电压Vth会对流过OLED的驱动电流IOLED会产生影响，而由于制造工艺的误差、器件老化等原因，会使各个像素单元中DTFT的阈值电压Vth产生漂移，对流过OLED的驱动电流造成偏差，进而影响显示效果。
发明内容
本发明的实施例提供一种像素电路及其驱动方法、显示面板和显示装置，能够避免驱动晶体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
根据本发明的第一个方面，提供一种像素电路包括：预置单元、补偿单元、数据写入单元、驱动单元、储能单元和发光单元。预置单元与第一扫描信号端、第一节点、第二节点、第三节点和第二电平端连接。预置单元被配置为在第一扫描信号端的信号的控制下将第一节点以及第三节点与第二电平端连接；并将第一扫描信号端与第二节点连接。补偿单元与第二扫描信号端、第一节点、第二节点、第三节点、第四节点和第二电平端连接。补偿单元被配置为在第二扫描信号端的信号的控制下将第一节点以及第三节点与第二电平端连接；并将第四节点与第二节点连接。数据写入单元与第三扫描信号端、数据信号端和第一节点连接，其被配置为在第三扫描信号端的信号的控制下将数据信号端与第一节点连接。储能单元与第一节点和第二节点连接，其被配置为存储第一节点和第二节点间的电压。驱动单元与第二节点、第三节点和第四节点连接，被配置为在第二节点和第四节点之间的电压的控制下向第三节点输出驱动信号。发光单元包括发光控制单元和发光器件。发光控制单元与控制信号端、第三节点、第四节点、第一电平端和发光器件连接；发光器件与发光控制单元和第二电平端连接。发光控制单元被配置为在控制信号端的控制下，将第一电平端与第四节点连接，并将第三节点与发光器件连接；发光器件被配置为在驱动信号和第二电平端的信号的控制下发光。
在本发明的实施例中，预置单元包括：第三晶体管、第四晶体管和第五晶体管。第三晶体管的控制极与第一扫描信号端连接，第三晶体管的第一端与第一扫描信号端连接，第三晶体管的第二端与第二节点连接。第四晶体管的控制极与第一扫描线号端连接，第四晶体管的第一端与第一节点连接，第四晶体管的第二端与第二电平端连接。第五晶体管的控制极与第一扫描信号端连接，第五晶体管的第一端与第三节点连接，第五晶体管的第二端与第二电平端连接。
在本发明的实施例中，补偿单元包括：第六晶体管、第七晶体管和第八晶体管。第六晶体管的控制极与第二扫描信号端连接，第六晶体管的第一端与第一节点连接，第六晶体管的第二端与第二电平端连接。第七晶体管的控制极与第二扫描信号端连接，第七晶体管的第一端与第四节点连接，第七晶体管的第二端与第二节点连接。第八晶体管的控制极与第二扫描信号端连接，第八晶体管的第一端与第三节点连接，第八晶体管的第二端与第二电平端连接。
在本发明的实施例中，数据写入单元包括：第一晶体管，第一晶体管的控制极与第三扫描信号端连接，第一晶体管的第一端与数据信号端连接，第一晶体管的第二端与第一节点连接。
在本发明的实施例中，驱动单元包括第二晶体管，第二晶体管的控制极与第二节点连接，第二晶体管的第一端与第四节点连接，第二晶体管的第二端与第一节点连接。
在本发明的实施例中，储能单元包括第一电容，第一电容的第一极与第一节点连接，第一电容的第二极与第二节点连接。
在本发明的实施例中，发光控制单元包括第九晶体管和第十晶体管，发光器件包括有机发光二极管。第九晶体管的控制极与控制信号端连接，第九晶体管的第一端与第一电平端连接，第九晶体管的第二端与第四节点连接。第十晶体管的控制极与控制信号端连接，第十晶体管的第一端与第三节点连接，第十晶体管的第二端与有机发光二极管的第一极连接。有机发光二极管的第二极与第二电平端连接。
根据本发明的第二个方面，提供一种显示面板，包括上述任一像素电路。
根据本发明的第三个方面，提供一种显示装置，包括上述的显示面板。
根据本发明的第四个方面，提供一种像素电路的驱动方法，用于驱动上述任一像素电路，包括：第一阶段，预置单元在第一扫描信号端的信号的控制下将第一节点以及第三节点的电平与第二电平端连接；并将第一扫描信号端与第二节点连接。第二阶段，补偿单元在第二扫描信号端的信号 的控制下将第一节点以及第三节点的电平与第二电平端连接并将第四节点与第二节点连接。储能单元存储驱动单元的阈值电压。第三阶段，数据写入单元在第三扫描信号端的信号的控制下将数据信号端与第一节点连接。第四阶段，驱动单元在第二节点和第四节点之间的电压的控制下向第三节点输出驱动信号。发光控制单元在控制信号端的信号的控制下，将第一电平端与第四节点连接，将第三节点与发光器件的第一极连接；发光器件在驱动信号和第二电平端的信号的控制下发光。
在本发明的实施例中，预置单元包括：第三晶体管、第四晶体管和第五晶体管。在第一阶段，第三晶体管、第四晶体管和第五晶体管在第一扫描信号端的信号的控制下均为导通状态，将第一节点通过第四晶体管与第二电平端连接，将第三节点通过第五晶体管与第二电平端连接。将第一扫描信号端通过第三晶体管与第二节点连接。
在本发明的实施例中，补偿单元包括：第六晶体管、第七晶体管和第八晶体管。在第二阶段，第六晶体管、第七晶体管和第八晶体管在第二扫描信号端的信号的控制下均为导通状态，将第一节点通过第六晶体管与第二电平端连接，将第三节点通过第八晶体管与第二电平端连接。将第二节点通过第七晶体管与第四节点连接。
在本发明的实施例中，数据写入单元包括：第一晶体管。第三阶段，第一晶体管在第三扫描信号端的信号的控制下为导通状态。将数据信号端通过第一晶体管与第一节点连接。
在本发明的实施例中，发光单元包括第九晶体管、第十晶体管和有机发光二极管。第四阶段，第九晶体管、第十晶体管在控制信号端的信号的控制下均处于导通状态，将第一电平端通过第九晶体管与第四节点连接，将第三节点通过第十晶体管与有机发光二极管的第一极连接，通过驱动信号和与有机发光二极管的第二极连接的第二电平端的信号控制有机发光二极管发光。
本发明的实施例提供像素电路及其驱动方法、显示面板和显示装置，能够通过补偿单元对驱动单元进行阈值电压补偿，避免驱动单元的驱动晶 体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本发明的实施例提供的一种像素电路结构示意图；
图2为图1所示的像素电路的示意性的电路图；
图3为图2所示的像素电路的信号时序状态示意图；
图4为图2所示的像素电路在第一阶段的示意性的等效电路图；
图5为图2所示的像素电路在第二阶段的示意性的等效电路图；
图6为图2所示的像素电路在第三阶段的示意性的等效电路图；
图7为图2所示的像素电路在第四阶段的示意性的等效电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管包括驱动晶体管，在驱动晶体管之外主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，控制极为栅极，并且为区分晶体管除栅极之外的两极， 将其中源极称为第一端，漏极称为第二端。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本发明实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止；驱动晶体管包括P型和N型，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态；其中N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。
图1为根据本发明的实施例提供的一种像素电路结构示意图。参照图1所示，本发明的实施例提供一种像素电路，包括：预置单元11、补偿单元12、数据写入单元13、驱动单元14、储能单元15和发光单元16。预置单元11与第一扫描信号端S1、第一节点a、第二节点b、第三节点c和第二电平端V2连接。预置单元11被配置为在第一扫描信号端S1的信号的控制下将第一节点a以及第三节点c与第二电平端V2连接；并将第一扫描信号端S1与第二节点b连接。补偿单元12与第二扫描信号端S2、第一节点a、第二节点b、第三节点c、第四节点d和第二电平端V2连接。补偿单元12被配置为在第二扫描信号端S2的信号的控制下将第一节点a以及第三节点c与第二电平端V2连接；并将第四节点d与第二节点b连接。
数据写入单元13与第三扫描信号端S3、数据信号端Data和第一节点a连接，其被配置为用于在第三扫描信号端S3的信号的控制下将数据信号端Data与第一节点a连接。
储能单元14与第一节点a和第二节点b连接，其被配置为存储第一节点a和第二节点b间的电压。
驱动单元15与第二节点b、第三节点c和第四节点d连接，其被配置为在第二节点b和第四节点d之间的电压的控制下向第三节点c输出驱动信号；
发光单元16包括发光控制单元和发光器件。发光控制单元与控制信号端EM、第三节点c、第四节点d、第一电平端V1和发光器件连接；发光器件与发光控制单元和第二电平端V2连接。发光控制单元被配置为在控制信号端EM的信号的控制下，将第一电平端V1的信号与第四节点d连接，并将第三节点c与发光器件连接。发光器件被配置为在驱动信号和第二电平端V2的信号的控制下发光。
以下简要在对驱动单元15进行阈值电压补偿的过程中，各个单元的功能。首先，预置单元在第一扫描信号端的信号控制下将第一节点以及第三节点的电平与第二电平端拉齐；并将第一扫描信号端的信号写入第二节点；其次，补偿单元在第二扫描信号端的信号控制下将第一节点以及第三节点的电平与第二电平端拉齐；补偿单元在第二扫描信号端的信号控制下通过第四节点对第二节点放电；储能单元存储驱动单元的阈值电压；再次，数据写入单元在第三扫描信号端的控制下将数据信号端的信号写入第一节点；最后，驱动单元在第二节点和第四节点的控制下向第三节点输出驱动信号；发光单元在控制信号端的控制下，将第一电平端的信号写入第四节点，在控制信号端的控制下接收第三节点的驱动信号，并在驱动信号和第二电平端的信号控制下发光。其中由于储能单元存储了驱动单元的阈值电压，因此在发光阶段，可以直接通过该存储的阈值电压对驱动单元进行阈值电压补偿。
本发明的实施例提供的像素电路，能够通过补偿单元对驱动单元进行阈值电压补偿避免驱动单元的驱动晶体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
图2为图1所示的像素电路的示意性的电路图。参照图2所示，预置单元11包括：第三晶体管M3、第四晶体管M4和第五晶体M5管。第三晶体管M3的栅极与第一扫描信号端S1连接，第三晶体管M3的第一端与第一扫描信号端S1连接，第三晶体管M3的第二端与第二节点b连接。第四晶体管M4的栅极与第一扫描线号端S1连接，第四晶体管M4的第一端与第一节点a连接，第四晶体管M4的第二端与第二电平端V2连接。第五 晶体管M5的栅极与第一扫描信号端S1连接，第五晶体管M5的第一端与第三节点c连接，第五晶体管M5的第二端与第二电平端V2连接。
补偿单元12包括：第六晶体管M6、第七晶体管M7和第八晶体管M8。第六晶体管M6的栅极与第二扫描信号端S2连接，第六晶体管M6的第一端与第一节点a连接，第六晶体管M6的第二端与第二电平端V2连接。第七晶体管M7的栅极与第二扫描信号端S2连接，第七晶体管M7的第一端与第四节点d连接，第七晶体管M7的第二端与第二节点b连接。第八晶体管M8的栅极与第二扫描信号端S2连接，第八晶体管M8的第一端与第三节点c连接，第八晶体管M8的第二端与第二电平端V2连接。
数据写入单元13包括：第一晶体管M1，第一晶体管M1的栅极与第三扫描信号端S3连接，第一晶体管M1的第一端与数据信号端Data连接，第一晶体管M1的第二端与第一节点a连接。
驱动单元14包括第二晶体管M2，第二晶体管M2的栅极与第二节点b连接，第二晶体管M2的第一端与第四节点d连接，第二晶体管M2的第二端与第一节点a连接。
储能单元15包括第一电容C1，第一电容C1的第一极与第一节点a连接，第一电容C1的第二极与第二节点b连接。
发光单元16包括发光控制单元和发光器件，发光控制单元包括第九晶体管M9和第十晶体管M10，发光器件包括有机发光二极管OLED。第九晶体管M9的栅极与控制信号端EM连接，第九晶体管M9的第一端与第一电平端V1连接，第九晶体管M9的第二端与第四节点d连接。第十晶体管M10的栅极与控制信号端EM连接，第十晶体管M10的第一端与第三节点c连接，第十晶体管M10的第二端与有机发光二极管OLED的第一极连接。有机发光二极管OLED的第二极与第二电平端V2连接。
其中第二晶体管M2为驱动晶体管，其他各个晶体管为开关晶体管。其中，以下简要描述在对驱动单元进行阈值电压补偿过程中，各个单元的功能。首先，预置单元11中第三晶体管M3、第四晶体管M4和第五晶体管M5在第一扫描信号端S1的信号控制下均为导通状态，将第一节点a的 电平通过第四晶体管M4与第二电平端V2拉齐，将第三节点c的电平通过第五晶体管M5与第二电平端V2拉齐。将第一扫描信号端S1的信号通过第三晶体管M3写入第二节点b。其次，补偿单元12中第六晶体管M6、第七晶体管M7和第八晶体管M8在第二扫描信号端S2的信号控制下均为导通状态，将第一节点a的电平通过第六晶体管M6与第二电平端V2拉齐，将第三节点c的电平通过第八晶体管M8与第二电平端V2拉齐。将第二节点b通过第七晶体管M7与第四节点d与进行放电。再次，数据写入单元13中第一晶体管M1在第三扫描信号端S3的信号控制下为导通状态。将数据信号端Data的信号通过第一晶体管M1写入第一节点a。最后，发光单元14中，第九晶体管M9、第十晶体管M10在控制信号端EM的信号控制下均处于导通状态，将第一电平端V1的信号通过第九晶体管M9写入第四节点d，将第三节点c的驱动信号通过第十晶体管M10输入有机发光二极管OLED的第一极，通过驱动信号和有机发光二极管OLED的第二极与的第二电平端V2的信号控制有机发光二极管OLED发光。其中由于储能单元中的C1存储了驱动单元中M2的阈值电压，因此在发光阶段，可以直接通过该存储的阈值电压对驱动单元中的M2进行阈值电压补偿。
上述的各个晶体管为同一类型的“N型”或“P型”晶体管，当然在显示面板的制程工艺中，若全采用同一类型的晶体管有利于减少制程工艺，保证器件性能的统一性，优选采用“N”型的晶体管。此外，这里的发光器件可以为有源发光二极管OLED，当该OLED的第一极为阳极时，第二电平端V2的电平V2低于第一电平端V1的电平V1。在本发明的实施例中，低电平可以为接地端。图2中是以第一极为阳极OLED为例的。
本发明实施例提供的像素电路能够通过补偿单元对驱动单元进行阈值电压补偿，避免驱动单元的驱动晶体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
图3为图2所示的像素电路的信号时序状态示意图。以下，结合图3对于像素电路的驱动方法进行描述。像素电路的驱动方法包括：第一阶段，第一扫描信号端上的信号有效，预置单元在第一扫描信号端的信号的控制 下将第一节点以及第三节点的电平与第二电平端连接；并将第一扫描信号端与第二节点连接。第二阶段，第二扫描信号端的信号有效，补偿单元在第二扫描信号端的信号的控制下将第一节点以及第三节点与第二电平端连接，并将第四节点与第二节点连接。储能单元存储驱动单元的阈值电压。第三阶段，第三扫描信号端的信号有效，数据信号端的信号有效，数据写入单元在第三扫描信号端的信号的控制下将数据信号端与第一节点连接。第四阶段，控制信号端的的信号有效，驱动单元在第二节点和第四节点之间的电压的控制下向第三节点输出驱动信号。发光单元在控制信号端的控制下，将第一电平端与第四节点连接，接收第三节点的驱动信号，并在驱动信号和第二电平端的信号控制下发光。
在本发明的实施例中，预置单元包括：第三晶体管、第四晶体管和第五晶体管。在第一阶段，第三晶体管、第四晶体管和第五晶体管在第一扫描信号端的信号的控制下均为导通状态，将第一节点的电平通过第四晶体管与第二电平端连接，将第三节点的电平通过第五晶体管与第二电平端连接。将第一扫描信号端的信号通过第三晶体管与第二节点连接。
在本发明的实施例中，补偿单元包括：第六晶体管、第七晶体管和第八晶体管。在第二阶段，第六晶体管、第七晶体管和第八晶体管在第二扫描信号端的信号控制下均为导通状态，将第一节点的电平通过第六晶体管与第二电平端连接，将第三节点的电平通过第八晶体管与第二电平端连接。将第二节点通过第七晶体管与第四节点连接。
在本发明的实施例中，数据写入单元包括：第一晶体管。第三阶段，第一晶体管在第三扫描信号端的信号的控制下为导通状态。将数据信号端的信号通过第一晶体管与第一节点连接。
在本发明的实施例中，发光单元包括第九晶体管、第十晶体管和有机发光二极管。第四阶段，第九晶体管、第十晶体管在控制信号端的信号控制下均处于导通状态，将第一电平端的信号通过第九晶体管与第四节点连接，将第三节点通过第十晶体管与有机发光二极管的第一极连接，通过驱动信号和与有机发光二极管的第二极俩接的第二电平端的信号控制有机发 光二极管发光。
本发明实施例提供的像素电路的驱动方法，能够通过补偿单元对驱动单元进行阈值电压补偿，避免驱动单元的驱动晶体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
以下对于驱动方法进行进一步的说明。图4为图2所示的像素电路在第一阶段的示意性的等效电路图。图5为图2所示的像素电路在第二阶段的示意性的等效电路图。图6为图2所示的像素电路在第三阶段的示意性的等效电路图。图7为图2所示的像素电路在第四阶段的示意性的等效电路图。图4～7各个附图中采用实线表示导通的晶体管及线路，虚线表示未导通的晶体管及线路。这里以各个晶体管均为“N”型晶体管，V1端施加高电平VDD信号，V2端施加低电平VSS信号为例。参照图2提供的像素电路，图3提供的像素电路的信号时序状态示意图，同时参照图4～7所提供的像素电路的各个阶段工作状态的等效电路示意图，本发明实施例提供一种像素电路的驱动方法，该电路工作原理分成四个部分，他们分别是第一阶段T1的预置阶段，第二阶段T2的M2的阈值电压写入阶段，第三阶段T3是数据信号写入阶段，第四阶段T4是发光阶段。
T1的预置阶段：S1＝1，S2＝0，S3＝0，EM＝0，需要说明的是，以下实施例中，“0”表示低电平；“1”表示高电平。S1＝1表示在第一扫描信号端施加了高电平的信号，以此类推。参照图4所示的等效电路图，S2、S3、EM为低压截止信号，S1为高压导通信号状态。此时M3、M4、M5导通，节点b点为高电平，而节点a、c点保持低电平。
T2的阈值电压写入阶段：S1＝0，S2＝1，S3＝0，EM＝0，参照图5所示的等效电路图，S1、S3、EM为低压截止信号，S2为高压导通信号状态。此时M2、M6、M7、M8导通，节点b点通过M7和M8放电至M2的阈值电压(Vth)，节点a、c点电位仍然保持低电平。这样电容C1便将M2的阈值电压保存在C1电容上。
T3的数据信号写入阶段：S1＝0，S2＝0，S3＝1，EM＝0，参照图6所示的等效电路图，S1、S2、EM为低压截止信号，S3为高压导通信号状态。 此时M1导通，Data输入数据信号VData，节点a点电位与VData保持一致，由于M7、M8截止，由于电容C1的自举作用，节点b点电位为VData+Vth。
T4的发光阶段：S1＝0，S2＝0，S3＝0，EM＝1，参照图7所示的等效电路图，S1、S2、S3为低压截止信号，EM为高压导通信号状态。此时M9、M10导通，保持节点b在发光阶段电位与T3阶段相同，都是VData+Vth。由于M2处于饱和阶段，根据晶体管饱和区电流公式可知：
Figure PCTCN2016075464-appb-000001
其中，VGS为M2源极和栅极之间的电压差，
Figure PCTCN2016075464-appb-000002
μ、Cox为工艺常数，W为M2沟道宽度，L为晶体管的沟道长度，W、L都为可选择性设计的常数，因此电流大小只与VData和VDD相关联。而VDD是设定的值，所以由上式中可以看到工作电流IOLED已经不受阈值电压Vth的影响，只与VData有关。彻底解决了M2由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对IOLED的影响，保证OLED的正常工作。
本发明的实施例提供一种显示面板，包括上述的像素电路。
本发明的实施例提供一种显示装置，包括上述的显示面板。另外，显示装置还可以为电子纸、手机、电视、数码相框等等显示设备。
本发明实施例提供的显示装置，能够通过补偿单元对驱动单元进行阈值电压补偿避免驱动单元的驱动晶体管的阈值电压漂移对有源发光器件驱动电流的影响，进而提高了显示图像的均匀性。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明 的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种像素电路，包括：预置单元、补偿单元、数据写入单元、驱动单元、储能单元和发光单元；
    所述预置单元与第一扫描信号端、第一节点、第二节点、第三节点和第二电平端连接；所述预置单元被配置为在所述第一扫描信号端的信号的控制下将所述第一节点以及所述第三节点与所述第二电平端连接；并将所述第一扫描信号端与所述第二节点连接；
    所述补偿单元与第二扫描信号端、第一节点、第二节点、第三节点、第四节点和所述第二电平端连接；所述补偿单元被配置为在所述第二扫描信号端的信号的控制下将所述第一节点以及所述第三节点与所述第二电平端连接；并将所述第四节点与所述第二节点连接；
    所述数据写入单元与第三扫描信号端、数据信号端和所述第一节点连接，其被配置为在所述第三扫描信号端的信号的控制下将所述数据信号端与所述第一节点连接；
    所述储能单元与所述第一节点和所述第二节点连接，被配置为存储所述第一节点和所述第二节点间的电压；
    所述驱动单元与所述第二节点、第三节点和第四节点连接，被配置为在所述第二节点和所述第四节点之间的电压的控制下向所述第三节点输出驱动信号；
    发光单元包括发光控制单元和发光器件；
    所述发光控制单元与控制信号端、第三节点、第四节点、第一电平端和所述发光器件连接；所述发光器件与所述发光控制单元和第二电平端连接；发光控制单元被配置为在所述控制信号端的信号的控制下，将所述第一电平端与所述第四节点连接，并将所述第三节点与所述发光器件连接；所述发光器件被配置为所述驱动信号和所述第二电平端的信号的控制下发光。
  2. 根据权利要求1所述的像素电路，其中，所述预置单元包括：第三晶体管、第四晶体管和第五晶体管；
    所述第三晶体管的控制极与所述第一扫描信号端连接，所述第三晶体管的第一端与所述第一扫描信号端连接，所述第三晶体管的第二端与所述第二节点连接；
    所述第四晶体管的控制极与所述第一扫描线号端连接，所述第四晶体管的第一端与所述第一节点连接，所述第四晶体管的第二端与所述第二电平端连接；
    所述第五晶体管的控制极与所述第一扫描信号端连接，所述第五晶体管的第一端与所述第三节点连接，所述第五晶体管的第二端与所述第二电平端。
  3. 根据权利要求1所述的像素电路，其特征在于，所述补偿单元包括：第六晶体管、第七晶体管和第八晶体管；
    所述第六晶体管的控制极与所述第二扫描信号端连接，所述第六晶体管的第一端与所述第一节点连接，所述第六晶体管的第二端与所述第二电平端连接；
    所述第七晶体管的控制极与所述第二扫描信号端连接，所述第七晶体管的第一端与所述第四节点连接，所述第七晶体管的第二端与所述第二节点连接；
    所述第八晶体管的控制极与所述第二扫描信号端连接，所述第八晶体管的第一端与所述第三节点连接，所述第八晶体管的第二端与所述第二电平端连接。
  4. 根据权利要求1所述的像素电路，其中，所述数据写入单元包括：第一晶体管，所述第一晶体管的控制极与所述第三扫描信号端连接，所述第一晶体管的第一端与所述数据信号端连接，所述第一晶体管的第二端与所述第一节点连接。
  5. 根据权利要求1所述的像素电路，其中，所述驱动单元包括第二晶体管，所述第二晶体管的控制极与所述第二节点连接，所述第二晶体管的第一端与所述第四节点连接，所述第二晶体管的第二端与所述第一节点连接。
  6. 根据权利要求1所述的像素电路，其中，所述储能单元包括第一电容，所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述第二节点连接。
  7. 根据权利要求1所述的像素电路，其中，所述发光控制单元包括第九晶体管和第十晶体管，所述发光器件包括有机发光二极管；
    所述第九晶体管的控制极与所述控制信号端连接，所述第九晶体管的第一端与所述第一电平端连接，所述第九晶体管的第二端与所述第四节点连接；
    所述第十晶体管的控制极与所述控制信号端连接，所述第十晶体管的第一端与所述第三节点连接，所述第十晶体管的第二端与所述有机发光二极管的第一极连接；
    所述有机发光二极管的第二极与所述第二电平端连接。
  8. 一种显示面板，包括如权利要求1-7中任一项所述的像素电路。
  9. 一种显示装置，包括如权利要求8所述的显示面板。
  10. 一种像素电路的驱动方法，用于驱动如权利要求1-7中任意一项所述的像素电路，包括：
    第一阶段，预置单元在第一扫描信号端的信号的控制下将第一节点以及第三节点与第二电平端连接；并将第一扫描信号端与第二节点连接；
    第二阶段，补偿单元在第二扫描信号端的信号的控制下将第一节点以及第三节点与第二电平端连接；并将第四节点与第二节点连接；储能单元存储驱动单元的阈值电压；
    第三阶段，数据写入单元在第三扫描信号端的信号的控制下将数据信号端与第一节点连接；
    第四阶段，驱动单元在第二节点和第四节点之间的电压的控制下向第三节点输出驱动信号；发光控制单元在控制信号端的信号的控制下，将第一电平端与第四节点连接，将第三节点与发光器件的第一极连接；发光器件在驱动信号和第二电平端的信号的控制下发光。
  11. 根据权利要求10所述的方法，其中，所述预置单元包括：第三晶 体管、第四晶体管和第五晶体管；
    在所述第一阶段，第三晶体管、第四晶体管和第五晶体管在所述第一扫描信号端的信号的控制下均为导通状态，将所述第一节点通过所述第四晶体管与所述第二电平端连接，将所述第三节点通过所述第五晶体管与所述第二电平端连接；将所述第一扫描信号端通过所述第三晶体管与所述第二节点连接。
  12. 根据权利要求10所述的方法，其中，所述补偿单元包括：第六晶体管、第七晶体管和第八晶体管；
    在所述第二阶段，第六晶体管、第七晶体管和第八晶体管在所述第二扫描信号端的信号的控制下均为导通状态，将所述第一节点通过所述第六晶体管与所述第二电平端连接，将所述第三节点通过所述第八晶体管与所述第二电平端连接；将所述第二节点通过所述第七晶体管与所述第四节点连接。
  13. 根据权利要求10所述的方法，其中，所述数据写入单元包括：第一晶体管；
    第三阶段，第一晶体管在所述第三扫描信号端的信号的控制下为导通状态；将数据信号端通过所述第一晶体管与第一节点连接。
  14. 根据权利要求10所述的方法，其中，所述发光单元包括第九晶体管、第十晶体管和有机发光二极管；
    第四阶段，第九晶体管、第十晶体管在所述控制信号端的信号的控制下均处于导通状态，将第一电平端通过所述第九晶体管与第四节点连接，将所述第三节点通过所述第十晶体管与所述有机发光二极管的第一极连接，通过所述驱动信号和与所述有机发光二极管的第二极连接的第二电平端的信号控制所述有机发光二极管发光。
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