WO2020140717A1 - 像素电路及其驱动方法、显示面板、显示装置 - Google Patents

像素电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2020140717A1
WO2020140717A1 PCT/CN2019/124759 CN2019124759W WO2020140717A1 WO 2020140717 A1 WO2020140717 A1 WO 2020140717A1 CN 2019124759 W CN2019124759 W CN 2019124759W WO 2020140717 A1 WO2020140717 A1 WO 2020140717A1
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Prior art keywords
circuit
potential
node
sub
transistor
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PCT/CN2019/124759
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English (en)
French (fr)
Inventor
徐攀
林奕呈
王国英
王玲
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京东方科技集团股份有限公司
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Priority to US16/959,011 priority Critical patent/US11361712B2/en
Publication of WO2020140717A1 publication Critical patent/WO2020140717A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and its driving method, display panel, and display device.
  • AMOLED Active matrix light emitting diode
  • each pixel unit includes an AMOLED and a pixel circuit, and the pixel circuit can provide a driving current to the AMOLED to drive the AMOLED to emit light.
  • the pixel circuit generally includes: a driving transistor, a switching transistor and a capacitor.
  • the switching transistor can output the data voltage provided by the data signal terminal to the driving transistor, and the driving transistor can convert the data voltage into a driving current for driving the AMOLED to emit light, and the magnitude of the driving current and the threshold voltage Vth of the driving transistor Related.
  • the present disclosure provides a pixel circuit, a driving method thereof, a display panel, and a display device.
  • the technical solutions are as follows:
  • a pixel circuit includes: a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, and a driving sub-circuit;
  • the data writing sub-circuit is respectively connected to the first control signal terminal, the data signal terminal and the first node.
  • the data writing sub-circuit is used to respond to the first control signal provided by the first control signal terminal to The first node outputs a data signal from the data signal terminal;
  • the compensation sub-circuit is respectively connected to the second control signal terminal, the first power supply terminal and the first node.
  • the compensation sub-circuit is used to respond to the second control signal provided by the second control signal terminal
  • the first node outputs a first power signal from the first power terminal;
  • the storage subcircuit is respectively connected to the first node and the second node, and the storage subcircuit is used to adjust the potential of the second node according to the potential of the first node;
  • the driver sub-circuit is respectively connected to the first node, the first power supply terminal and the second node, the second node is connected to the light-emitting unit, and the driver sub-circuit is used at the first node and Driven by the first power signal, the light-emitting unit is driven to emit light.
  • the compensation sub-circuit includes: a first transistor
  • the gate of the first transistor is connected to the second control signal terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first Node connection.
  • the data writing sub-circuit includes: a second transistor
  • the gate of the second transistor is connected to the first control signal terminal, the first electrode of the second transistor is connected to the data signal terminal, and the second electrode of the second transistor is connected to the first node connection.
  • the driving sub-circuit includes: a driving transistor
  • the gate of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the first power supply terminal, and the second electrode of the driving transistor is connected to the second node.
  • the storage sub-circuit includes: a capacitor
  • One end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the second node.
  • the pixel circuit further includes: a detection sub-circuit;
  • the detection sub-circuit is respectively connected to a third control signal terminal, a detection signal line and the second node, and the detection sub-circuit is used to respond to the third control signal provided by the third control signal terminal to the
  • the second node outputs a detection signal from the detection signal line, and outputs the potential of the second node to the detection signal line, and the detection signal line is connected to an external compensation circuit of the display panel.
  • the detection sub-circuit includes: a third transistor
  • the gate of the third transistor is connected to the third control signal terminal, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the detection signal line connection.
  • the transistors included in each sub-circuit in the pixel circuit are N-type transistors.
  • a driving method of a pixel circuit which is applied to the pixel circuit as described in the above aspect, and the method includes:
  • the potential of the first control signal provided by the first control signal terminal is the first potential
  • the potential of the second control signal provided by the second control signal terminal is both second Potential
  • the data writing sub-circuit outputs the data signal to the first node in response to the first control signal
  • the potential of the first control signal is the second potential
  • the potential of the second control signal is the first potential
  • the potential of the first power signal provided by the first power terminal is the second potential
  • the compensation The sub-circuit outputs the first power signal to the first node in response to the second control signal
  • the storage sub-circuit adjusts the potential of the second node according to the potential of the first node
  • the potential of the first control signal is the first potential
  • the potential of the second control signal is the second potential
  • the potential of the data signal is the first potential
  • the data writing sub-circuit responds to The first control signal outputs the data signal to the first node
  • the storage sub-circuit adjusts the potential of the second node according to the potential of the first node
  • the potential of the first control signal is the second potential
  • the potential of the first power signal is the first potential
  • the driving sub-circuit is responsive to the potential of the first power signal and the first node, Drive the light emitting unit to emit light.
  • the pixel circuit further includes: a detection sub-circuit;
  • the potential of the third control signal provided by the third control signal terminal is the first potential
  • the potential of the detection signal provided by the detection signal line is the second potential
  • the detection sub-circuit is responsive to the third The control signal outputs the detection signal to the second node.
  • the method further includes:
  • the potential of the third control signal is the first potential
  • the detection sub-circuit outputs the potential of the second node to the detection signal line in response to the third control signal, and the detection signal The line outputs the potential of the second node to the external compensation circuit of the display panel.
  • the fifth stage is performed during the blanking stage of the display panel; after entering the blanking stage, before performing the fifth stage, the method further includes:
  • the first stage, the second stage, and the third stage are sequentially executed.
  • the first potential is a high potential relative to the second potential.
  • a display panel including a plurality of pixel units.
  • Each of the pixel units includes the pixel circuit as described above and a light emitting unit connected to the pixel circuit.
  • a display device comprising: a source drive circuit, and the display panel according to the above aspect;
  • the source driving circuit is respectively connected to a data signal terminal connected to each pixel circuit in the display panel, and the source driving circuit is used to provide a data signal to the data signal terminal.
  • each of the pixel circuits further includes: a detection sub-circuit, the detection sub-circuit is connected to a detection signal line; the display device further includes: an external compensation circuit;
  • the detection signal line connected to the detection sub-circuit in each pixel circuit is connected to the external compensation circuit, and each pixel circuit is used to output the detection signal line to the external compensation circuit through the detection signal line.
  • the potential of the second node in the pixel circuit, and the external compensation circuit is used to adjust the potential of the data signal input to the source driving circuit according to the potential of the second node.
  • the detection sub-circuits in the pixel units in the same column are connected to the same detection signal line.
  • the display device includes: a plurality of pixels, each of the pixels includes a plurality of adjacent pixel units; the detection sub-circuits in the plurality of adjacent pixel units are detected by the same stripe Signal cable connection.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of each signal terminal in another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode; or the drain electrode may be referred to as the first electrode and the source electrode is referred to as the second electrode.
  • the middle end of the transistor is a gate, the signal input end is a source, and the signal output end is a drain.
  • the switching transistors used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, where the P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • multiple signals in various embodiments of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential only represent the potential of the signal with 2 state quantities, and do not represent the first potential or
  • the second potential has a specific value.
  • the Vth of the driving transistor may be different between different pixel units, and the Vth of the driving transistor will drift with time, the driving current of the AMOLED flowing through each pixel unit will be different, which may cause the AMOLED display device to display the brightness The uniformity is low and the display effect is poor.
  • the Vth of the driving transistor in order to ensure the uniformity of the display brightness of the display device and improve the display effect of the display device, it is necessary to compensate the Vth of the driving transistor.
  • the pixel circuit may include: a data writing sub-circuit 10, a compensation sub-circuit 20, a storage sub-circuit 30, and a driving sub-circuit 40.
  • the data writing sub-circuit 10 may be connected to the first control signal terminal S1, the data signal terminal D0, and the first node P1, respectively.
  • the data writing sub-circuit 10 may output the data signal from the data signal terminal D0 to the first node P1 in response to the first control signal provided by the first control signal terminal S1.
  • the data writing sub-circuit 10 may output the data signal from the data signal terminal D0 to the first node P1 when the potential of the first control signal is the first potential.
  • the first potential may be an effective potential.
  • the compensation sub-circuit 20 may be connected to the second control signal terminal S2, the first power supply terminal VDD, and the first node P1, respectively.
  • the compensation sub-circuit 20 may output the first power signal from the first power terminal VDD to the first node P1 in response to the second control signal provided by the second control signal terminal S2.
  • the compensation sub-circuit 20 may output the first power signal from the first power terminal VDD to the first node P1 when the potential of the second control signal is the first potential.
  • the storage sub-circuit 30 may be connected to the first node P1 and the second node P2, respectively.
  • the storage sub-circuit 30 can adjust the potential of the second node P2 according to the potential of the first node P1.
  • the storage sub-circuit 30 may adjust the potential of the second node P2 according to the potential of the first node P1 through a coupling effect.
  • the driving sub-circuit 40 is respectively connected to the first node P1, the first power supply terminal VDD, and the second node P2, and the second node P2 may be connected to the light emitting unit L0.
  • the driving sub-circuit 40 can drive the light emitting unit L0 to emit light under the drive of the first node P1 and the first power signal.
  • the driving sub-circuit 40 may be driven by the first node P1 and the first power signal when the potential of the first node P1 is the first potential and the potential of the first power signal is the first potential.
  • the light emitting unit L0 outputs a driving current, thereby driving the light emitting unit L0 to emit light.
  • the embodiments of the present disclosure provide a pixel circuit. Since the compensation sub-circuit in the pixel circuit can output the first power signal to the first node, the storage sub-circuit can adjust the second node according to the potential of the first node The potential. Therefore, by controlling the potential of each control signal terminal, the driving current output by the driver sub-circuit to the light-emitting unit can be made independent of the threshold voltage of the transistor in the driver sub-circuit.
  • the pixel circuit provided by the embodiment of the present disclosure can compensate the threshold voltage of the transistor in the driver sub-circuit through internal compensation, which solves the problem that the threshold voltage of the transistor in the driver sub-circuit is different or drifts, causing flow
  • the driving current of each light-emitting unit is different, which in turn leads to the problem of uneven display brightness of the display device, which improves the display effect of the display device.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG. 2, the pixel circuit may further include: a detection sub-circuit 50.
  • the detection sub-circuit 50 may be connected to the third control signal terminal S3, the detection signal line SENSE, and the second node P2, respectively.
  • the detection sub-circuit 50 may output the detection signal from the detection signal line SENSE to the second node P2 and the potential of the second node P2 to the detection signal line SENSE in response to the third control signal provided by the third control signal terminal S3.
  • the detection signal line SENSE may be connected to an external compensation circuit of the display panel (not shown in FIG. 2).
  • the detection signal line SENSE may output the received potential of the second node P2 to an external compensation circuit.
  • the external compensation circuit can adjust the potential of the data signal input to the source driving circuit according to the potential of the second node P2, so that the source driving circuit provides the data signal terminal D0 connected to the pixel circuit according to the adjusted potential of the data signal The data signal, thereby achieving external compensation of the Vth of the transistor in the driving sub-circuit.
  • the detection sub-circuit 50 may output the detection signal from the detection signal line SENSE to the second node P2 and the potential of the second node P2 to the detection signal line SENSE when the potential of the third control signal is the first potential
  • the potential of the detection signal is the second potential.
  • the second potential may be an invalid potential, and the second potential may be a low potential relative to the first potential.
  • the pixel circuit provided by the embodiment of the present disclosure on the one hand, by controlling the potential of each control signal terminal, the driving current output from the transistor in the driving sub-circuit to the light-emitting unit can be independent of the threshold voltage of the transistor, that is, the internal compensation can be used to The threshold voltage of the transistor in the driving sub-circuit is compensated.
  • the detection sub-circuit can output the potential of the second node to the detection signal line connected to the external compensation circuit
  • the external compensation circuit can adjust the potential of the data signal according to the potential of the collected light-emitting unit, that is, it can be passed through the external The compensation method compensates the threshold voltage of the transistor in the driving sub-circuit.
  • the internal compensation may not be able to effectively compensate the Vth of the transistor in the driving sub-circuit, that is, the compensation range of the internal compensation method is limited.
  • external compensation can be used to effectively compensate the Vth of the transistors in the driving sub-circuits, external compensation is generally performed in the blanking stage or when the display device is turned off. Therefore, when external compensation is used, The compensation time is longer and the real-time performance is poor.
  • the pixel circuit provided by the embodiment of the present disclosure can not only realize the internal compensation of the threshold voltage of the transistor in the driving sub-circuit, but also realize the external compensation of the threshold voltage of the transistor in the driving sub-circuit, so the pixel circuit
  • the compensation range is larger, the compensation time is shorter, and the real-time performance is better.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the compensation sub-circuit 20 may include: a first transistor M1.
  • the gate of the first transistor M1 may be connected to the second control signal terminal S2, the first electrode of the first transistor M1 may be connected to the first power supply terminal VDD, and the second electrode of the first transistor M1 may be connected to the first node P1 connection.
  • the data writing sub-circuit 10 may include: a second transistor M2.
  • the gate of the second transistor M2 may be connected to the first control signal terminal S1, the first electrode of the second transistor M2 may be connected to the data signal terminal D0, and the second electrode of the second transistor M2 may be connected to the first node P1 connection.
  • the storage sub-circuit 30 may include: a capacitor C.
  • One end of the capacitor C may be connected to the first node P1, and the other end of the capacitor C may be connected to the second node P2.
  • the capacitor C can adjust the potential of the second node P2 according to the potential of the first node P1 through the coupling action.
  • the driving sub-circuit 40 may include: a driving transistor M0.
  • the gate of the driving transistor M0 may be connected to the first node P1, the first electrode of the driving transistor M0 may be connected to the first power supply terminal VDD, and the second electrode of the driving transistor M0 may be connected to the second node P2, the first The two node P2 may be connected to the light emitting unit L0.
  • the driving transistor M0 may drive the light emitting unit L0 to emit light under the driving of the first node P1 and the first power signal.
  • the driving transistor M0 may drive light emission under the drive of the first node P1 and the first power signal Unit L0 emits light.
  • the detection sub-circuit 50 may include: a third transistor M3.
  • the gate of the third transistor M3 may be connected to the third control signal terminal S3, the first electrode of the third transistor M3 may be connected to the second node P2, and the second electrode of the third transistor M3 may be connected to the detection signal line SENSE connection.
  • the pixel circuit may further include: an intrinsic capacitance C0 of the light emitting unit L0.
  • One end of the intrinsic capacitor C0 may be connected to the second node P2
  • the other end of the intrinsic capacitor C0 may be connected to one end of the light emitting unit L0 (such as the cathode of the light emitting unit L0), and the cathode of the light emitting unit L0 may also be connected to Low level power supply terminal VSS connection.
  • the other end of the light emitting unit L0 (such as the anode of the light emitting unit L0) may be connected to the second electrode of the driving transistor M0.
  • the transistor included in the data writing sub-circuit 10, the transistor included in the compensation sub-circuit 20, the transistor included in the storage sub-circuit 30, the transistor included in the detection sub-circuit 50, and the driving transistor M0 may all be N Type transistor.
  • each of the transistors may be an Oxide thin film transistor (TFT), or each of the transistors may also be an amorphous silicon (a-Si) TFT, which is not described in the embodiments of the present disclosure. Be limited.
  • the embodiments of the present disclosure provide a pixel circuit. Since the compensation sub-circuit in the pixel circuit can output the first power signal to the first node (the gate of the driving transistor), the storage sub-circuit can be based on the first The potential of the node adjusts the potential of the second node (the second electrode of the driving transistor). Therefore, by controlling the potential of each control signal terminal, the driving current output by the driving transistor to the light-emitting unit can be independent of the threshold voltage of the driving transistor, that is, the threshold voltage of the driving transistor can be compensated by internal compensation.
  • the external compensation circuit can adjust the voltage of the data signal according to the collected potential of the light emitting unit, that is, the external compensation Way to compensate the threshold voltage of the driving transistor.
  • the pixel circuit can realize internal compensation of the threshold voltage of the driving transistor, it can also realize external compensation of the threshold voltage of the driving transistor. Therefore, when the pixel circuit compensates the threshold voltage of the driving transistor, the compensation range is larger, the compensation time is shorter, and the real-time performance is better.
  • FIG. 4 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure, which can be applied to the pixel circuit shown in any one of FIGS. 1 to 3. As shown in FIG. 4, the method may include:
  • Step 301 In the first stage, the potential of the first control signal provided by the first control signal terminal is the first potential, the potential of the second control signal provided by the second control signal terminal, and the potential of the data signal provided by the data signal terminal are both For the second potential, the data writing sub-circuit outputs a data signal to the first node in response to the first control signal, thereby realizing the reset of the first node.
  • Step 302. In the second stage, the potential of the first control signal is the second potential, the potential of the second control signal is the first potential, the potential of the first power signal provided by the first power terminal is the second potential, and the compensation subcircuit responds The second control signal outputs the first power signal to the first node, and the storage sub-circuit adjusts the potential of the second node according to the potential of the first node.
  • Step 303 In the third stage, the potential of the first control signal is the first potential, the potential of the second control signal is the second potential, the potential of the data signal is the first potential, and the data writing sub-circuit responds to the first control signal, The data signal is output to the first node, and the storage sub-circuit adjusts the potential of the second node according to the potential of the first node.
  • Step 304 In the fourth stage, the potential of the first control signal is the second potential, the potential of the first power signal is the first potential, and the transistor in the driving sub-circuit drives light emission in response to the potential of the first power signal and the first node The unit glows.
  • the embodiments of the present disclosure provide a driving method of a pixel circuit. Since the compensation sub-circuit can output the first power signal to the first node, the storage sub-circuit can adjust the potential of the second node according to the potential of the first node. Therefore, by controlling the potential of each control signal terminal, the driving current output by the transistor in the driver sub-circuit to the light-emitting unit can be independent of the threshold voltage of the transistor in the driver sub-circuit, that is, the driver sub-circuit can be compensated by internal compensation. The threshold voltage of the transistor is compensated.
  • the pixel circuit provided by the embodiment of the present disclosure can compensate the threshold voltage of the transistor in the driver sub-circuit through internal compensation, which solves the problem that the threshold voltage of the transistor in the driver sub-circuit is different or drifts, causing flow
  • the driving current of each light-emitting unit is different, which in turn leads to the problem of uneven display brightness of the display device, which improves the display effect of the display device.
  • the pixel circuit may further include a detection sub-circuit 50.
  • the detection sub-circuit 50 may be connected to the third control signal terminal S3, the detection signal line SENSE, and the second node P2, respectively.
  • the potential of the third control signal provided by the third control signal terminal is the first potential
  • the potential of the detection signal provided by the detection signal line is the second potential.
  • the detection sub-circuit 50 may In response to the third control signal, the detection signal is output to the second node, so that the second node is reset.
  • the method may further include:
  • Step 305 In the fifth stage, the potential of the third control signal is the first potential, and the detection sub-circuit outputs the potential of the second node to the detection signal line in response to the third control signal, and the detection signal line outputs the potential of the second node to The external compensation circuit of the display panel.
  • the detection sub-circuit can output the potential of the second node to the detection signal line connected to the external compensation circuit, so that the external compensation circuit can adjust the potential of the data signal according to the collected potential of the light emitting unit, that is,
  • the threshold voltage of the transistor in the driving sub-circuit is compensated by external compensation. Since the pixel circuit can realize both internal compensation of the threshold voltage of the transistor in the driving sub-circuit and external compensation of the threshold voltage of the transistor in the driving sub-circuit. Therefore, when the pixel circuit compensates the threshold voltage of the transistor in the driving sub-circuit, the compensation range is larger, the compensation time is shorter, and the real-time performance is better.
  • the fifth stage may be performed during the blanking stage of the display panel, that is, the Vth of the transistors in the driving sub-circuits compensated by external compensation may be performed during the blanking stage.
  • the fifth stage may be performed in the vertical blanking (VBlank) stage of the display panel.
  • the method may further include: sequentially performing the first stage, the second stage, and the third stage.
  • the potential of the second node ie, the potential of the light emitting unit
  • the detection signal line can output the adjusted potential of the second node to the external compensation circuit, so that the external compensation circuit can accurately adjust the potential of the data signal according to the adjusted potential of the second node, and improve external compensation Accuracy.
  • the first potential is higher than the second potential
  • the potential that is, the potential of the signal of the first potential is greater than the potential of the signal of the second potential
  • FIG. 5 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • the potential of the data signal provided by the data signal terminal D0 and the potential of the detection signal provided by the sense signal line SENSE are the second potential.
  • the potential of the first control signal provided by the first control signal terminal S1 and the potential of the third control signal provided by the third control signal terminal S3 are both the first potential, and the potential of the second control signal provided by the second control signal terminal S2 It is the second potential.
  • the potential of the first control signal and the potential of the third control signal are both positive potentials, and the potential of the second control signal is a negative potential.
  • the second transistor M2 and the third transistor M3 are turned on, and the first transistor M1 is turned off.
  • the data signal terminal D0 outputs the data signal at the second potential to the first node P1 through the second transistor M2, so that the first node P1 is reset.
  • the detection signal line SENSE outputs the detection signal at the second potential to the second node P2 through the third transistor M3, so that the second node P2 is reset.
  • This first phase T1 may also be referred to as a reset phase.
  • the potential Vref1 of the data signal and the potential Vref2 of the detection signal may be the same, for example, both may be 0 to 3 volts (V).
  • the potential of the first power signal provided by the first power terminal VDD is the second potential, and the potential of the first control signal and the third control signal both jump to the second potential.
  • the potential jumps to the first potential.
  • the second transistor M2 and the third transistor M3 are turned off, and the first transistor M1 is turned on.
  • the first power terminal VDD outputs the first power signal at the second potential to the first node P1 through the first transistor M1.
  • the potential of the second electrode (ie, the second node P2) of the driving transistor M0 is the difference between the potential of the first node P1 and the threshold voltage Vth of the driving transistor M0.
  • This second phase T2 may be referred to as an internal compensation phase.
  • the potential V P2 of the second node P2 should be less than the turn-on voltage V OLED of the light emitting unit L0.
  • the potential of the first power signal in the second stage T2 is VDD_L, which should satisfy: VDD_L ⁇ V OLED +Vth.
  • the potential of the first power signal should be VDD_L and should also satisfy VDD_L>Vref2+Vth. That is, the potential VDD_L of the first power supply signal in the second stage T2 may satisfy: Vref2+Vth ⁇ VDD_L ⁇ V OLED +Vth.
  • the turn-on voltage V OLED is generally about 3V. If the light-emitting unit L0 is a two-layer white OLED (WOLED), the turn-on voltage V OLED is generally about 5V. If the light-emitting unit L0 is a triple-layer WOLED, the turn-on voltage V OLED is generally about 8V.
  • WOLED two-layer white OLED
  • the turn-on voltage V OLED is generally about 5V.
  • the turn-on voltage V OLED is generally about 8V.
  • the potential VDD_L of the first power signal in the second stage T2 may be about 2V.
  • the potential jump of the data signal becomes the first potential
  • the potential jump of the first control signal becomes the first potential
  • the potential jump of the second control signal becomes the second potential
  • the potential of the third control signal remains It is the second potential.
  • the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on.
  • the data signal terminal D0 outputs the data signal at the first potential to the first node P1 through the second transistor M2.
  • This third stage T3 may also be referred to as a data writing stage.
  • the potential of the first power signal jumps to the first potential
  • the potential of the first control signal also jumps to the second potential
  • the potential of the second control signal and the potential of the third control signal remain at the second Potential.
  • the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off.
  • the driving transistor M0 may output a driving current to the light emitting element L0 under the control of the first node P1 and the first power signal to drive the light emitting element L0 to emit light.
  • This fourth stage T4 may also be referred to as a display stage.
  • the potential of the first power signal may be VDD_H.
  • the gate of the transistor M0 is connected to the first node P1, and the second electrode (ie, source) of the driving transistor M0 is connected to the second node P2. Therefore, in the fourth stage T4, the gate-source voltage Vgs (ie, the potential difference between the gate potential Vg and the source potential Vs) of the driving transistor M0 is:
  • the driving current I generated by the driving transistor M0 can be expressed as:
  • K satisfies: ⁇ is the carrier mobility of the driving transistor M0, C OX is the capacitance of the gate insulating layer of the driving transistor M0, and W/L is the width-to-length ratio of the driving transistor M0.
  • the driving current I generated by the driving transistor M0 can be calculated as:
  • the pixel circuit can compensate the Vth of the driving transistor M0 through internal compensation, which avoids the problem of uneven display brightness of the display panel due to the drift of the Vth of the driving transistor M0, effectively ensuring the display of the display panel Uniformity of brightness.
  • the potential of the third control signal jumps to the second potential, and the potentials of the first control signal and the second control signal remain at the first potential.
  • the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 is turned on.
  • the potential of the second node P2 is output to the detection signal line SENSE through the third transistor M3.
  • the potential Vsense on the detection signal line SENSE gradually rises.
  • the detection signal line SENSE can output the potential of the second node P2 to an external compensation circuit, and the external compensation circuit can adjust the data input to the source driving circuit according to the potential of the second node P2 The potential of the signal, so that the source driving circuit provides a data signal to the data signal terminal D0 connected to the pixel circuit according to the adjusted potential of the data signal, thereby achieving external compensation of the Vth of the driving transistor M0.
  • This fifth stage T5 may also be referred to as an external compensation stage.
  • the external compensation circuit can also determine the magnitude of the electron mobility of the driving transistor M0 according to the collected driving currents of the different driving transistors M0 output to the light emitting unit L0. By adjusting the potential of the data signal, the electron mobility of the driving transistor M0 can also be compensated.
  • the first to fourth stages T1 to T4 may be performed at the display stage T10 of the display panel, and the fifth stage T5 may be performed at the blanking stage T20 of the display panel.
  • FIG. 6 is another timing diagram of the blanking phase at each signal end provided by an embodiment of the present disclosure.
  • the blanking stage T20 before the fifth stage T5, it may further include a first stage T1, a second stage T2, and a third stage T3.
  • the first stage T1, the second stage T2, the third stage T3, and the fifth stage T5 reference may be made to the foregoing description, and details are not described herein again.
  • the embodiments of the present disclosure provide a driving method for a pixel circuit.
  • the compensation sub-circuit can output a first power signal to the first node, and the storage sub-circuit can adjust the first circuit according to the potential of the first node.
  • the potential of the two nodes Therefore, by controlling the potential of each control signal terminal, the driving current output by the transistor in the driver sub-circuit to the light-emitting unit can be independent of the threshold voltage of the transistor, that is, the threshold voltage of the transistor in the driver sub-circuit can be adjusted by internal compensation. make up.
  • the external compensation circuit can adjust the potential of the data signal according to the collected potential of the light-emitting unit, that is, the external compensation Way to compensate the threshold voltage of the transistor in the driving sub-circuit.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure can not only realize the internal compensation of the threshold voltage of the transistor in the driving sub-circuit, but also realize the external compensation of the threshold voltage of the transistor in the driving sub-circuit,
  • the compensation range is larger, the compensation time is shorter, and the real-time performance is better.
  • the display panel 100 may include: a plurality of pixel units 00, and each pixel unit 00 may include: a pixel circuit 01 and a pixel circuit 01 connected to the pixel circuit 01
  • the pixel circuit 01 may be a pixel circuit as shown in any one of FIGS. 1 to 3.
  • the light emitting unit 02 may be OLED or AMOLED.
  • the display device may include: a display panel 100 and a source driving circuit 200.
  • the display panel 100 may be the display panel shown in FIG. 7.
  • the source driving circuit 200 may be connected to the data signal terminal connected to each pixel circuit 01 in the display panel 100 respectively.
  • the source driving circuit 200 may be used to provide a data signal to the data signal terminal.
  • each pixel circuit 01 further includes a detection sub-circuit, which is connected to the detection signal line.
  • the display device may further include: an external compensation circuit 300.
  • the detection signal lines connected to the detection sub-circuits in each pixel circuit 01 may all be connected to the external compensation circuit 300.
  • the detection sub-circuit in each pixel circuit 01 may output the potential of the second node in the pixel circuit 01 to the external compensation circuit 300 through the detection signal line.
  • the external compensation circuit 300 may adjust the potential of the data signal input to the source driving circuit 200 according to the potential of the second node.
  • the source driving circuit 200 may provide a data signal to the data signal terminal according to the adjusted potential of the data signal, thereby achieving external compensation of the threshold voltage of the driving transistor.
  • the detection sub-circuit in the pixel circuit 01 in the pixel unit 00 in the same column may be connected to the same detection signal line.
  • the display device may further include a plurality of pixels, and each pixel includes a plurality of adjacent pixel units 00.
  • the detection sub-circuits in adjacent pixel units 00 may be connected to the same detection signal line.
  • each pixel 00 includes three adjacent pixel units (the three pixel units may be red, green, and blue pixel units), the three adjacent pixel units include three
  • the detection sub-circuits in each pixel circuit can be connected to the same detection signal line.
  • each detection signal line may be connected to the detection sub-circuits in the three columns of pixel units. For example, if the display panel includes 1000 columns of pixels, and each pixel includes three pixel units arranged in rows, each detection signal line may be connected to a detection sub-circuit in a pixel circuit of 3000 pixel units.
  • the display device may be: an OLED display device, an AMOLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and any other products or components with display functions.

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Abstract

一种像素电路（01）及其驱动方法、显示面板（100）、显示装置，属于显示技术领域，像素电路（01）包括数据写入子电路（10）、补偿子电路（20）、存储子电路（30）和驱动子电路（40）；由于补偿子电路（20）可以向第一节点（P1）输出第一电源信号，存储子电路（30）可以根据第一节点（P1）的电位调节第二节点（P2）的电位；因此可以使得输出至发光单元（02）的驱动电流与驱动子电路（40）中的晶体管（M0）的阈值电压无关，即实现对驱动子电路（40）中的晶体管（M0）阈值电压的内部补偿，改善了由于驱动子电路（40）中的晶体管（M0）的阈值电压而造成流过各发光元件（L0）的驱动电流存在差异，显示装置显示亮度不均匀的问题。

Description

像素电路及其驱动方法、显示面板、显示装置
本公开要求于2019年01月02日提交的申请号为201910002345.3、发明名称为“像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示面板、显示装置。
背景技术
有源矩阵发光二极管(active matrix organic light emitting diode，AMOLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。
AMOLED显示装置中，每个像素单元中均包括一个AMOLED和一个像素电路，该像素电路可以向AMOLED提供驱动电流来驱动AMOLED发光。该像素电路一般包括：一个驱动晶体管，一个开关晶体管和一个电容。该开关晶体管可以将数据信号端提供的数据电压输出至该驱动晶体管，该驱动晶体管可以将该数据电压转化为用于驱动AMOLED发光的驱动电流，并且该驱动电流的大小与驱动晶体管的阈值电压Vth相关。
发明内容
本公开提供了一种像素电路及其驱动方法、显示面板、显示装置，技术方案如下：
一方面，提供了一种像素电路，所述像素电路包括：数据写入子电路、补偿子电路、存储子电路和驱动子电路；
所述数据写入子电路分别与第一控制信号端、数据信号端和第一节点连接，所述数据写入子电路用于响应于所述第一控制信号端提供的第一控制信号，向所述第一节点输出来自所述数据信号端的数据信号；
所述补偿子电路分别与第二控制信号端、第一电源端和所述第一节点连接， 所述补偿子电路用于响应于所述第二控制信号端提供的第二控制信号，向所述第一节点输出来自所述第一电源端的第一电源信号；
所述存储子电路分别与所述第一节点和第二节点连接，所述存储子电路用于根据所述第一节点的电位调节所述第二节点的电位；
所述驱动子电路分别与所述第一节点、所述第一电源端连接和第二节点连接，所述第二节点与发光单元连接，所述驱动子电路用于在所述第一节点和所述第一电源信号的驱动下，驱动所述发光单元发光。
可选的，所述补偿子电路包括：第一晶体管；
所述第一晶体管的栅极与所述第二控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述第一节点连接。
可选的，所述数据写入子电路包括：第二晶体管；
所述第二晶体管的栅极与所述第一控制信号端连接，所述第二晶体管的第一极与所述数据信号端连接，所述第二晶体管的第二极与所述第一节点连接。
可选的，所述驱动子电路包括：驱动晶体管；
所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与所述第一电源端连接，所述驱动晶体管的第二极与所述第二节点连接。
可选的，所述存储子电路包括：电容器；
所述电容器的一端与所述第一节点连接，所述电容器的另一端与所述第二节点连接。
可选的，所述像素电路还包括：检测子电路；
所述检测子电路分别与第三控制信号端、检测信号线和所述第二节点连接，所述检测子电路用于响应于所述第三控制信号端提供的第三控制信号，向所述第二节点输出来自所述检测信号线的检测信号，以及向所述检测信号线输出所述第二节点的电位，所述检测信号线与显示面板的外部补偿电路连接。
可选的，所述检测子电路包括：第三晶体管；
所述第三晶体管的栅极与所述第三控制信号端连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极与所述检测信号线连接。
可选的，所述像素电路中各个子电路包括的晶体管均为N型晶体管。
另一方面，提供了一种像素电路的驱动方法，应用于如上述方面所述的像素电路，所述方法包括：
第一阶段，第一控制信号端提供的第一控制信号的电位为第一电位，第二控制信号端提供的第二控制信号的电位，以及数据信号端提供的数据信号的电位均为第二电位，数据写入子电路响应于所述第一控制信号，向第一节点输出所述数据信号；
第二阶段，所述第一控制信号的电位为第二电位，所述第二控制信号的电位为第一电位，第一电源端提供的第一电源信号的电位为第二电位，所述补偿子电路响应于所述第二控制信号，向所述第一节点输出所述第一电源信号，存储子电路根据所述第一节点的电位调节第二节点的电位；
第三阶段，所述第一控制信号的电位为第一电位，所述第二控制信号的电位为第二电位，所述数据信号的电位为第一电位，所述数据写入子电路响应于所述第一控制信号，向所述第一节点输出所述数据信号，所述存储子电路根据所述第一节点的电位调节所述第二节点的电位；
第四阶段，所述第一控制信号的电位为第二电位，所述第一电源信号的电位为第一电位，驱动子电路响应于所述第一电源信号和所述第一节点的电位，驱动发光单元发光。
所述像素电路还包括：检测子电路；
所述第一阶段中，第三控制信号端提供的第三控制信号的电位为第一电位，检测信号线提供的检测信号的电位为第二电位，所述检测子电路响应于所述第三控制信号，向第二节点输出所述检测信号。
可选的，所述方法还包括：
第五阶段，所述第三控制信号的电位为第一电位，所述检测子电路响应于所述第三控制信号，向所述检测信号线输出所述第二节点的电位，所述检测信号线将所述第二节点的电位输出至显示面板的外部补偿电路。
可选的，所述第五阶段在显示面板的消隐阶段执行；在进入所述消隐阶段后，在执行所述第五阶段之前，所述方法还包括：
依次执行所述第一阶段、所述第二阶段和所述第三阶段。
可选的，所述第一电位相对于所述第二电位为高电位。
另一方面，提供了一种显示面板，所述显示面板包括：多个像素单元每个所述像素单元包括：如上述方面所述的像素电路以及与所述像素电路连接的发光单元。
又一方面，提供了一种显示装置，所述显示装置包括：源极驱动电路，以及如上述方面所述的显示面板；
所述源极驱动电路分别与所述显示面板中每个像素电路所连接的数据信号端连接，所述源极驱动电路用于向所述数据信号端提供数据信号。
可选的，每个所述像素电路还包括：检测子电路，所述检测子电路与检测信号线连接；所述显示装置还包括：外部补偿电路；
每个所述像素电路中的所述检测子电路所连接的检测信号线均与所述外部补偿电路连接，每个所述像素电路用于通过所述检测信号线向所述外部补偿电路输出所述像素电路中第二节点的电位，所述外部补偿电路用于根据所述第二节点的电位，调整输入至所述源极驱动电路的数据信号的电位。
可选的，所述显示面板中，位于同一列的所述像素单元中的检测子电路与同一条所述检测信号线连接。
可选的，所述显示装置包括：多个像素，每个所述像素包括相邻的多个所述像素单元；所述相邻的多个所述像素单元中的检测子电路与同一条检测信号线连接。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素电路的结构示意图；
图2是本公开实施例提供的另一种像素电路的结构示意图；
图3是本公开实施例提供的又一种像素电路的结构示意图；
图4是本公开实施例提供的一种像素电路的驱动方法流程图；
图5是本公开实施例提供的一种像素电路中各信号端的时序图；
图6是本公开实施例提供的另一种像素电路中各信号端的时序图；
图7是本公开实施例提供的一种显示面板的结构示意图；
图8是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极；或者可以将漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位，第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。
由于不同像素单元之间驱动晶体管的Vth可能不同，且驱动晶体管的Vth随时间会发生漂移，因此流过各个像素单元的AMOLED的驱动电流则会存在差异，进而可能会使得AMOLED显示装置显示亮度的均匀性较低，显示效果较差。随着显示技术的发展，为了保证显示装置显示亮度的均匀性，改善显示装置的显示效果，需要对驱动晶体管的Vth进行补偿。
本公开实施例提供了一种像素电路，如图1所示，该像素电路可以包括：数据写入子电路10、补偿子电路20、存储子电路30和驱动子电路40。
该数据写入子电路10可以分别与第一控制信号端S1、数据信号端D0和第一节点P1连接。该数据写入子电路10可以响应于第一控制信号端S1提供的第一控制信号，向第一节点P1输出来自数据信号端D0的数据信号。
示例的，该数据写入子电路10可以在第一控制信号的电位为第一电位时，向第一节点P1输出来自数据信号端D0的数据信号。在本公开实施例中，该第一电位可以为有效电位。
该补偿子电路20可以分别与第二控制信号端S2、第一电源端VDD和第一 节点P1连接。该补偿子电路20可以响应于第二控制信号端S2提供的第二控制信号，向第一节点P1输出来自第一电源端VDD的第一电源信号。
示例的，该补偿子电路20可以在第二控制信号的电位为第一电位时，向第一节点P1输出来自第一电源端VDD的第一电源信号。
该存储子电路30可以分别与第一节点P1和第二节点P2连接。该存储子电路30可以根据第一节点P1的电位调节第二节点P2的电位。
示例的，该存储子电路30可以通过耦合作用，根据第一节点P1的电位调节第二节点P2的电位。
该驱动子电路40分别与第一节点P1、第一电源端VDD以及第二节点P2连接，该第二节点P2可以与发光单元L0连接。该驱动子电路40可以在第一节点P1和第一电源信号的驱动下，驱动发光单元L0发光。
示例的，该驱动子电路40可以在第一节点P1的电位为第一电位，以及第一电源信号的电位为第一电位时，在第一节点P1和该第一电源信号的驱动下，向发光单元L0输出驱动电流，从而驱动该发光单元L0发光。
综上所述，本公开实施例提供了一种像素电路，由于该像素电路中的补偿子电路可以向第一节点输出第一电源信号，存储子电路可以根据第一节点的电位调节第二节点的电位。因此通过控制各控制信号端的电位，可以使得驱动子电路输出至发光单元的驱动电流与驱动子电路中的晶体管的阈值电压无关。也即是，本公开实施例提供的像素电路可以通过内部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿，解决了由于驱动子电路中的晶体管的阈值电压不同或漂移，造成流过各个发光单元的驱动电流存在差异，继而导致显示装置的显示亮度不均匀的问题，改善了显示装置的显示效果。
图2是本公开实施例提供的另一种像素电路的结构示意图，如图2所示，该像素电路还可以包括：检测子电路50。
该检测子电路50可以分别与第三控制信号端S3、检测信号线SENSE和第二节点P2连接。该检测子电路50可以响应于第三控制信号端S3提供的第三控制信号，向第二节点P2输出来自检测信号线SENSE的检测信号，以及向检测信号线SENSE输出第二节点P2的电位。且该检测信号线SENSE可以与显示面板的外部补偿电路连接(图2中未示出)。
在本公开实施例中，该检测信号线SENSE可以将接收到的第二节点P2的 电位输出至外部补偿电路。该外部补偿电路可以根据该第二节点P2的电位调整输入至源极驱动电路的数据信号的电位，从而使得源极驱动电路根据调整后的数据信号的电位向像素电路连接的数据信号端D0提供数据信号，从而实现对驱动子电路中的晶体管的Vth进行外部补偿。
示例的，该检测子电路50可以在第三控制信号的电位为第一电位时，向第二节点P2输出来自检测信号线SENSE的检测信号，以及向检测信号线SENSE输出第二节点P2的电位，该检测信号的电位为第二电位。在本公开实施例中，该第二电位可以为无效电位，且该第二电位相对于第一电位可以为低电位。
本公开实施例提供的像素电路，一方面，通过控制各控制信号端的电位，可以使得驱动子电路中的晶体管输出至发光单元的驱动电流与晶体管的阈值电压无关，即可以通过内部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。另一方面，由于检测子电路可以向与外部补偿电路连接的检测信号线输出第二节点的电位，因此可以使得外部补偿电路根据采集到的发光单元的电位调整数据信号的电位，即可以通过外部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。
由于当驱动子电路中的晶体管的Vth发生偏移的程度较大时，采用内部补偿可能无法对驱动子电路中的晶体管的Vth进行有效补偿，即内部补偿方式的补偿范围有限。而虽然采用外部补偿可以实现对驱动子电路中的晶体管的Vth进行有效补偿，但是，由于外部补偿一般是在消隐(Blanking)阶段或显示装置处于关机的状态下进行，因此采用外部补偿时，补偿时间较长，实时性较差。而本公开实施例提供的像素电路既可以实现对驱动子电路中的晶体管的阈值电压的内部补偿，又可以实现对驱动子电路中的晶体管的阈值电压的外部补偿，因此该像素电路对驱动子电路中的晶体管的阈值电压进行补偿时，其补偿范围较大，补偿时间较短，实时性较好。
图3是本公开实施例提供的另一种像素电路的结构示意图。如图3所示，该补偿子电路20可以包括：第一晶体管M1。
该第一晶体管M1的栅极可以与第二控制信号端S2连接，该第一晶体管M1的第一极可以与第一电源端VDD连接，该第一晶体管M1的第二极可以与第一节点P1连接。
可选的，该数据写入子电路10可以包括：第二晶体管M2。
该第二晶体管M2的栅极可以与第一控制信号端S1连接，该第二晶体管M2的第一极可以与数据信号端D0连接，该第二晶体管M2的第二极可以与第一节点P1连接。
可选的，该存储子电路30可以包括：电容器C。
该电容器C的一端可以与第一节点P1连接，该电容器C的另一端可以与第二节点P2连接。该电容器C可以通过耦合作用，根据第一节点P1的电位调节第二节点P2的电位。
可选的，如图3所示，该驱动子电路40可以包括：驱动晶体管M0。
该驱动晶体管M0的栅极可以与第一节点P1连接，该驱动晶体管M0的第一极可以与第一电源端VDD连接，该驱动晶体管M0的第二极可以与第二节点P2连接，该第二节点P2可以与发光单元L0连接。该驱动晶体管M0可以在第一节点P1和第一电源信号的驱动下，驱动发光单元L0发光。
示例的，该驱动晶体管M0可以在第一节点P1的电位为第一电位，以及第一电源信号的电位为第一电位时，在第一节点P1和该第一电源信号的驱动下，驱动发光单元L0发光。
可选的，如图3所示，该检测子电路50可以包括：第三晶体管M3。
该第三晶体管M3的栅极可以与第三控制信号端S3连接，该第三晶体管M3的第一极可以与第二节点P2连接，该第三晶体管M3的第二极可以与检测信号线SENSE连接。
可选的，参考图3可以看出，该像素电路中还可以包括：发光单元L0的本征电容C0。该本征电容C0的一端可以与第二节点P2连接，该本征电容C0的另一端可以与发光单元L0的一端(如发光单元L0的阴极)连接，且该发光单元L0的阴极还可以与低电平电源端VSS连接。该发光单元L0的另一端(如发光单元L0的阳极)可以与驱动晶体管M0的第二极连接。
可选的，该数据写入子电路10包括的晶体管、该补偿子电路20包括的晶体管、该存储子电路30包括的晶体管、该检测子电路50包括的晶体管和该驱动晶体管M0可以均为N型晶体管。并且该各个晶体管可以均为氧化物(Oxide)薄膜晶体管(thin film transistor，TFT)，或者该各个晶体管也可以均为非晶硅(amorphous silicon，a-Si)TFT，本公开实施例对此不做限定。
综上所述，本公开实施例提供了一种像素电路，由于该像素电路中的补偿 子电路可以向第一节点(驱动晶体管的栅极)输出第一电源信号，存储子电路可以根据第一节点的电位调节第二节点(驱动晶体管的第二极)的电位。因此通过控制各控制信号端的电位，可以使得驱动晶体管输出至发光单元的驱动电流与驱动晶体管的阈值电压无关，即可以通过内部补偿的方式对驱动晶体管的阈值电压进行补偿。
并且，由于检测子电路可以向与外部补偿电路连接的检测信号线输出第二节点的电位，因此可以使得外部补偿电路根据采集到的发光单元的电位调整数据信号的电压，即可以通过外部补偿的方式对驱动晶体管的阈值电压进行补偿。通过对驱动晶体管的阈值电压进行补偿，解决了由于不同像素单元之间驱动晶体管的阈值电压不同或驱动晶体管的阈值电压发生漂移，造成流过各个发光单元的驱动电流存在差异，显示装置的显示亮度不均匀的问题，改善了显示装置的显示效果。
另外，由于该像素电路既可以实现对驱动晶体管的阈值电压进行内部补偿，又可以实现对驱动晶体管的阈值电压进行外部补偿。因此该像素电路对驱动晶体管的阈值电压进行补偿时，其补偿范围较大，补偿时间较短，实时性较好。
图4是本公开实施例提供的一种像素电路的驱动方法流程图，可以应用于如图1至图3任一所示的像素电路中。如图4所示，该方法可以包括：
步骤301、第一阶段，第一控制信号端提供的第一控制信号的电位为第一电位，第二控制信号端提供的第二控制信号的电位，以及数据信号端提供的数据信号的电位均为第二电位，数据写入子电路响应于第一控制信号，向第一节点输出数据信号，从而实现对第一节点的复位。
步骤302、第二阶段，第一控制信号的电位为第二电位，第二控制信号的电位为第一电位，第一电源端提供的第一电源信号的电位为第二电位，补偿子电路响应于第二控制信号，向第一节点输出第一电源信号，存储子电路根据第一节点的电位调节第二节点的电位。
步骤303、第三阶段，第一控制信号的电位为第一电位，第二控制信号的电位为第二电位，数据信号的电位为第一电位，数据写入子电路响应于第一控制信号，向第一节点输出数据信号，存储子电路根据第一节点的电位调节第二节点的电位。
步骤304、第四阶段，第一控制信号的电位为第二电位，第一电源信号的电位为第一电位，驱动子电路中的晶体管响应于第一电源信号和第一节点的电位，驱动发光单元发光。
综上所述，本公开实施例提供了一种像素电路的驱动方法。由于补偿子电路可以向第一节点输出第一电源信号，存储子电路可以根据第一节点的电位调节第二节点的电位。因此通过控制各控制信号端的电位，可以使得驱动子电路中的晶体管输出至发光单元的驱动电流与该驱动子电路中的晶体管的阈值电压无关，即可以通过内部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。也即是，本公开实施例提供的像素电路可以通过内部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿，解决了由于驱动子电路中的晶体管的阈值电压不同或漂移，造成流过各个发光单元的驱动电流存在差异，继而导致显示装置的显示亮度不均匀的问题，改善了显示装置的显示效果。
可选的，在本公开实施例中，参考图2和图3，该像素电路还可以包括检测子电路50。该检测子电路50可以分别与第三控制信号端S3、检测信号线SENSE和第二节点P2连接。
在上述步骤301所示的第一阶段中，第三控制信号端提供的第三控制信号的电位为第一电位，检测信号线提供的检测信号的电位为第二电位，该检测子电路50可以响应于所述第三控制信号，向第二节点输出该检测信号，从而实现对该第二节点的复位。
可选的，如图4所示，该方法还可以包括：
步骤305、第五阶段，第三控制信号的电位为第一电位，检测子电路响应于第三控制信号，向检测信号线输出第二节点的电位，检测信号线将第二节点的电位输出至显示面板的外部补偿电路。
在本公开实施例中，检测子电路可以向与外部补偿电路连接的检测信号线输出第二节点的电位，因此可以使得外部补偿电路根据采集到的发光单元的电位调整数据信号的电位，即可以通过外部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。由于该像素电路既可以实现对驱动子电路中的晶体管的阈值电压的内部补偿，又可以实现对驱动子电路中的晶体管的阈值电压的外部补偿。因此该像素电路对驱动子电路中的晶体管的阈值电压进行补偿时，其补偿范围较大，补偿时间较短，实时性较好。
在本公开实施例中，该第五阶段可以在显示面板的消隐阶段执行，即采用外部补偿的方式对驱动子电路中的晶体管的Vth进行补偿可以在消隐阶段执行。例如，该第五阶段可以在显示面板的垂直消隐(vertical blanking，VBlank)阶段执行。
可选的，在进入消隐阶段后，在执行该第五阶段之前，该方法还可以包括：依次执行第一阶段、第二阶段和第三阶段。
也即是，可以在进入消隐阶段后，在对驱动子电路中的晶体管的Vth进行外部补偿之前，先通过执行第一阶段至第三阶段来调节第二节点的电位(即发光单元的电位)。之后，再执行第五阶段以进行外部补偿。由此，可以使得检测信号线将调节后的第二节点的电位输出至外部补偿电路，进而使得外部补偿电路可以根据调节后的第二节点的电位对数据信号的电位进行精确调节，提高外部补偿的精确性。
以图3所示的像素电路为例，并以像素电路中驱动晶体管M0、第一晶体管M1、第二晶体管M2和第三晶体管M3均为N型晶体管，第一电位相对于第二电位为高电位(即第一电位的信号的电位大于第二电位的信号的电位)为例，详细介绍本公开实施例提供的像素电路的驱动原理。
图5是本公开实施例提供的一种像素电路中各信号端的时序图。如图5所示，在第一阶段T1，数据信号端D0提供的数据信号的电位和感测信号线SENSE提供的检测信号的电位为第二电位。第一控制信号端S1提供的第一控制信号的电位，以及第三控制信号端S3提供的第三控制信号的电位均为第一电位，第二控制信号端S2提供的第二控制信号的电位为第二电位。例如，第一控制信号的电位和第三控制信号的电位均为正电位，第二控制信号的电位为负电位。第二晶体管M2和第三晶体管M3开启，第一晶体管M1关断。数据信号端D0通过该第二晶体管M2向第一节点P1输出处于第二电位的数据信号，从而实现对第一节点P1的复位。检测信号线SENSE通过第三晶体管M3向第二节点P2输出处于第二电位的检测信号，从而实现对第二节点P2的复位。该第一阶段T1也可以称为复位阶段。
在本公开实施例中，该第一阶段T1中，数据信号的电位Vref1和检测信号的电位Vref2可以相同，例如可以均为0至3伏特(V)。
例如，假设在该第一阶段T1中，数据信号的电位Vref1和检测信号的电位 Vref2均为0V，则在该第一阶段T1中该第一节点P1的电位V P1和第二节点P2的电位V P2即满足：V P1＝V P2＝0V。
在第二阶段T2，第一电源端VDD提供的第一电源信号的电位为第二电位，第一控制信号的电位和第三控制信号的电位均跳变为第二电位，第二控制信号的电位跳变为第一电位。第二晶体管M2和第三晶体管M3关断，第一晶体管M1开启。第一电源端VDD通过该第一晶体管M1向第一节点P1输出处于第二电位的第一电源信号。由于驱动晶体管M0的第一极也与第一电源端VDD连接，该驱动晶体管M0的栅极与第一节点P1连接，因此在该第二阶段T2中，该驱动晶体管M0的栅极和第一极的电位即相同，该驱动晶体管M0的连接方式变为二极管连接方式。该驱动晶体管M0的第二极(即第二节点P2)的电位为：第一节点P1的电位与驱动晶体管M0的阈值电压Vth的差值。该第二阶段T2可以称为内部补偿阶段。
例如，假设第一电源信号的电位为VDD_L，则在该第二阶段T2，该第一节点的电位V P1即为：V P1＝VDD_L。相应的，该第二节点P2的电位V P2即为：V P2＝VDD_L-Vth。
需要说明的是，在该第二阶段T2中，为了避免发光单元L0漏电发光，该第二节点P2的电位V P2应当小于该发光单元L0的启亮电压V OLED。相应的，第一电源信号在该第二阶段T2的电位为VDD_L应当满足：VDD_L＜V OLED+Vth。另外，在该第二阶段T2，为了实现二极管式的补偿，第一电源信号的电位为VDD_L还应当满足VDD_L>Vref2+Vth。也即是，在该第二阶段T2中该第一电源信号的电位VDD_L可以满足：Vref2+Vth＜VDD_L＜V OLED+Vth。
其中，若该发光单元L0为单色OLED，则该启亮电压V OLED一般为3V左右。若该发光单元L0为两叠层的白色OLED(WOLED)，则该启亮电压V OLED一般为5V左右。若该发光单元L0为三叠层WOLED，则该启亮电压V OLED一般为8V左右。
示例的，假设发光单元L0为单色OLED，Vref2＝0V，Vth为0至1V，则第一电源信号在该第二阶段T2中的电位VDD_L可以为2V左右。
在第三阶段T3，数据信号的电位跳变为第一电位，第一控制信号的电位跳变为第一电位，第二控制信号的电位跳变为第二电位，第三控制信号的电位保持为第二电位。第一晶体管M1和第三晶体管M3关断，第二晶体管M2开启。 数据信号端D0通过该第二晶体管M2向第一节点P1输出处于第一电位的数据信号。该第三阶段T3也可以称为数据写入阶段。
例如，假设该数据信号的电位为Vdata，则在该第三阶段T3，该第一节点的电位V P1即为：V P1＝Vdata。由于在第二阶段T2中，该第一节点P1的电位V P1为：V P1＝VDD_L，因此在该第三阶段T3中，该第一节点P1的电位变化量即为：Vdata-VDD_L。由于该像素电路中还包括发光单元L0的本征电容C0，因此在电容器C的耦合作用下，该第二节点P2的电位变化量即为：α(Vdata-VDD_L)，其中，α满足：α＝C/(C0+C)。并且，由于在第二阶段T2中，该第二节点P2的电位变为：V P2＝VDD_L-Vth。因此在该第三阶段T3中，该电容器C通过耦合作用可以将第二节点P2的电位V P2调节为：V P2＝α(Vdata-VDD_L)+VDD_L-Vth。
在第四阶段T4，第一电源信号的电位跳变为第一电位，第一控制信号的电位也跳变为第二电位，第二控制信号的电位和第三控制信号的电位保持为第二电位。第一晶体管M1、第二晶体管M2和第三晶体管M3均关断。此时，该驱动晶体管M0可以在第一节点P1和该第一电源信号的控制下，向发光元件L0输出驱动电流以驱动发光元件L0发光。该第四阶段T4也可以称为显示阶段。
例如，参考图4，在第四阶段T4中，该第一电源信号的电位可以为VDD_H。由于在第三阶段T3中，该第一节点的电位V P1为：V P1＝Vdata，第二节点P2的电位V P2为：V P2＝α(Vdata-VDD_L)+VDD_L-Vth，且由于驱动晶体管M0的栅极与第一节点P1连接，驱动晶体管M0的第二极(即源极)与第二节点P2连接。因此，在该第四阶段T4中，该驱动晶体管M0的栅源电压Vgs(即栅极电位Vg与源极电位Vs的电位差)即为：
Vgs＝Vg-Vs＝V P1-V P2＝Vdata-[α(Vdata-VDD_L)+VDD_L-Vth]
＝(1-α)(Vdata-VDD_L)+Vth     公式(1)；
其中，该驱动晶体管M0产生的驱动电流I可以表示为：
I＝K×(Vgs-Vth) 2    公式(2)；
其中，K满足：
Figure PCTCN2019124759-appb-000001
μ为驱动晶体管M0的载流子迁移率，C OX为驱动晶体管M0的栅极绝缘层的电容，W/L为驱动晶体管M0的宽长比。
将上述公式(1)得到的Vgs代入公式(2)即可以计算得到驱动晶体管M0产生的驱动电流I即为：
Figure PCTCN2019124759-appb-000002
从上述公式(3)可以看出，在发光元件L0正常工作时，用于驱动发光元件L0的驱动电流I的大小仅与数据信号端D0提供的数据信号的电位Vdata和第一电源端VDD提供的第一电源信号的电位VDD_L有关，而与驱动晶体管的阈值电压Vth无关。因此在显示阶段，该像素电路可以通过内部补偿的方式对驱动晶体管M0的Vth进行补偿，避免了由于驱动晶体管M0的Vth发生漂移而造成显示面板显示亮度不均匀的问题，有效保证了显示面板显示亮度的均一性。
可选的，该第一电源信号的电位VDD_L可以较小，从而可以保证第二节点P2的电位变为：V P2＝VDD_L-Vth所需的时间较短，进而可以缩短内部补偿的时间。
在第五阶段T5，该第三控制信号的电位跳变为第二电位，第一控制信号的电位和第二控制信号的电位保持为第一电位。第一晶体管M1和第二晶体管M2关断，第三晶体管M3开启。第二节点P2的电位通过该第三晶体管M3输出至该检测信号线SENSE。此时，参考图4，该检测信号线SENSE上的电位Vsense慢慢上升。且在本公开实施例中，该检测信号线SENSE可以将该第二节点P2的电位输出至外部补偿电路，该外部补偿电路可以根据该第二节点P2的电位调整输入至源极驱动电路的数据信号的电位，从而使得源极驱动电路根据调整后的数据信号的电位向像素电路连接的数据信号端D0提供数据信号，实现对驱动晶体管M0的Vth的外部补偿。该第五阶段T5也可以称为外部补偿阶段。
并且，在该第五阶段T5，外部补偿电路还可以根据采集到的不同驱动晶体管M0输出至发光单元L0的驱动电流，判断驱动晶体管M0的电子迁移率大小。通过对该数据信号的电位进行调节后，还可以实现对该驱动晶体管M0的电子迁移率的补偿。
在本公开实施例中，参考图4，上述第一阶段T1至第四阶段T4可以在显示面板的显示阶段T10执行，第五阶段T5可以在显示面板的消隐阶段T20执行。
可选的，由于在进入消隐阶段后，在执行第五阶段T5之前，还可以先依次执行第一阶段T1、第二阶段T2和第三阶段T3。图6是本公开实施例提供的另一种在各信号端消隐阶段的时序图。如图6所示，在消隐阶段T20中，在该第五阶段T5之前，还可以包括第一阶段T1、第二阶段T2和第三阶段T3。其中， 该第一阶段T1、第二阶段T2、第三阶段T3和第五阶段T5的驱动原理可以参考上述描述，在此不再赘述。
综上所述，本公开实施例提供了一种像素电路的驱动方法，基于该驱动方法，补偿子电路可以向第一节点输出第一电源信号，存储子电路可以根据第一节点的电位调节第二节点的电位。因此通过控制各控制信号端的电位，可以使得驱动子电路中的晶体管输出至发光单元的驱动电流与该晶体管的阈值电压无关，即可以通过内部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。
并且，由于检测子电路可以向与外部补偿电路连接的检测信号线输出第二节点的电位，因此可以使得外部补偿电路根据采集到的发光单元的电位调整数据信号的电位，即可以通过外部补偿的方式对驱动子电路中的晶体管的阈值电压进行补偿。通过对驱动子电路中的晶体管的阈值电压进行补偿，解决了由于不同驱动子电路中的晶体管的阈值电压不同或驱动子电路中的晶体管的阈值电压发生漂移，造成流过各个发光单元的驱动电流存在差异，显示装置的显示亮度不均匀的问题，改善了显示装置的显示效果。
另外，由于本公开实施例提供的像素电路的驱动方法既可以实现对驱动子电路中的晶体管的阈值电压的内部补偿，又可以实现对驱动子电路中的晶体管的阈值电压的外部补偿，因此其补偿范围较大，补偿时间较短，实时性较好。
本公开实施例还提供了一种显示面板，如图7所示，该显示面板100可以包括：多个像素单元00，每个像素单元00可以包括：像素电路01以及与该像素电路01连接的发光单元02。其中，该像素电路01可以为如图1至图3任一所示的像素电路。该发光单元02可以为OLED或者AMOLED。
本公开实施例还提供了一种显示装置，如图8所示，该显示装置可以包括：显示面板100以及源极驱动电路200。其中，该显示面板100可以为如图7所示的显示面板。该源极驱动电路200可以分别与显示面板100中每个像素电路01所连接的数据信号端连接，该源极驱动电路200可以用于向数据信号端提供数据信号。
可选的，每个像素电路01还包括检测子电路，该检测子电路与检测信号线连接。如图8所示，该显示装置还可以包括：外部补偿电路300。
该每个像素电路01中的检测子电路所连接的检测信号线可以均与外部补偿电路300连接。每个像素电路01中的检测子电路可以通过检测信号线向外部补偿电路300输出像素电路01中第二节点的电位。
外部补偿电路300可以根据第二节点的电位，调整输入至源极驱动电路200的数据信号的电位。源极驱动电路200可以根据该调整后的数据信号的电位向数据信号端提供数据信号，从而实现对驱动晶体管的阈值电压的外部补偿。
如图8所示，位于同一列的像素单元00中的像素电路01中的检测子电路可以与同一条检测信号线连接。
可选的，在本公开实施例中，该显示装置还可以包括多个像素，每个像素包括相邻的多个像素单元00。相邻的多个像素单元00中的检测子电路可以与同一条检测信号线连接。
示例的，假设每个像素00包括相邻的三个像素单元(该三个像素单元可以为红色像素单元、绿色像素单元和蓝色像素单元)时，该相邻的三个像素单元包括的三个像素电路中的检测子电路可以与同一条检测信号线连接。
若每个像素00包括的三个像素单元按行排布，则每条检测信号线可以与三列像素单元中的检测子电路连接。例如，若显示面板包括1000列像素，每个像素包括按行排列的三个像素单元，则每条检测信号线可以与3000个像素单元的像素电路中的检测子电路连接。通过使得每条检测信号线与多列像素单元的像素电路连接，可以有效减少该显示装置中所需设置的检测信号线的条数，进而减少检测信号线的占用空间。
可选的，该显示装置可以为：OLED显示装置、AMOLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路和显示装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种像素电路，所述像素电路包括：数据写入子电路、补偿子电路、存储子电路和驱动子电路；
    所述数据写入子电路分别与第一控制信号端、数据信号端和第一节点连接，所述数据写入子电路用于响应于所述第一控制信号端提供的第一控制信号，向所述第一节点输出来自所述数据信号端的数据信号；
    所述补偿子电路分别与第二控制信号端、第一电源端和所述第一节点连接，所述补偿子电路用于响应于所述第二控制信号端提供的第二控制信号，向所述第一节点输出来自所述第一电源端的第一电源信号；
    所述存储子电路分别与所述第一节点和第二节点连接，所述存储子电路用于根据所述第一节点的电位调节所述第二节点的电位；
    所述驱动子电路分别与所述第一节点、所述第一电源端和第二节点连接，所述第二节点与发光单元连接，所述驱动子电路用于在所述第一节点和所述第一电源信号的驱动下，驱动所述发光单元发光。
  2. 根据权利要求1所述的像素电路，所述补偿子电路包括：第一晶体管；
    所述第一晶体管的栅极与所述第二控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述第一节点连接。
  3. 根据权利要求1所述的像素电路，所述数据写入子电路包括：第二晶体管；
    所述第二晶体管的栅极与所述第一控制信号端连接，所述第二晶体管的第一极与所述数据信号端连接，所述第二晶体管的第二极与所述第一节点连接。
  4. 根据权利要求1所述的像素电路，所述存储子电路包括：电容器；
    所述电容器的一端与所述第一节点连接，所述电容器的另一端与所述第二节点连接。
  5. 根据权利要求1所述的像素电路，所述驱动子电路包括：驱动晶体管；
    所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与 所述第一电源端连接，所述驱动晶体管的第二极与所述第二节点连接。
  6. 根据权利要求1所述的像素电路，所述像素电路还包括：检测子电路；
    所述检测子电路分别与第三控制信号端、检测信号线和所述第二节点连接，所述检测子电路用于响应于所述第三控制信号端提供的第三控制信号，向所述第二节点输出来自所述检测信号线的检测信号，以及向所述检测信号线输出所述第二节点的电位，所述检测信号线与显示面板的外部补偿电路连接。
  7. 根据权利要求6所述的像素电路，所述检测子电路包括：第三晶体管；
    所述第三晶体管的栅极与所述第三控制信号端连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极与所述检测信号线连接。
  8. 根据权利要求1至7任一所述的像素电路，所述像素电路中各个子电路包括的晶体管均为N型晶体管。
  9. 根据权利要求7所述的像素电路，所述补偿子电路包括：第一晶体管；所述数据写入子电路包括：第二晶体管；所述驱动子电路包括：驱动晶体管；所述存储子电路包括：电容器；
    所述第一晶体管的栅极与所述第二控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述第一节点连接；
    所述第二晶体管的栅极与所述第一控制信号端连接，所述第二晶体管的第一极与所述数据信号端连接，所述第二晶体管的第二极与所述第一节点连接；
    所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与所述第一电源端连接，所述驱动晶体管的第二极与所述第二节点连接；
    所述电容器的一端与所述第一节点连接，所述电容器的另一端与所述第二节点连接；
    其中，每个所述晶体管均为N型晶体管。
  10. 一种像素电路的驱动方法，应用于如权利要求1至9任一所述的像素电路，所述方法包括：
    第一阶段，第一控制信号端提供的第一控制信号的电位为第一电位，第二控制信号端提供的第二控制信号的电位，以及数据信号端提供的数据信号的电位均为第二电位，数据写入子电路响应于所述第一控制信号，向第一节点输出所述数据信号；
    第二阶段，所述第一控制信号的电位为第二电位，所述第二控制信号的电位为第一电位，第一电源端提供的第一电源信号的电位为第二电位，补偿子电路响应于所述第二控制信号，向所述第一节点输出所述第一电源信号，存储子电路根据所述第一节点的电位调节第二节点的电位；
    第三阶段，所述第一控制信号的电位为第一电位，所述第二控制信号的电位为第二电位，所述数据信号的电位为第一电位，所述数据写入子电路响应于所述第一控制信号，向所述第一节点输出所述数据信号，所述存储子电路根据所述第一节点的电位调节所述第二节点的电位；
    第四阶段，所述第一控制信号的电位为第二电位，所述第一电源信号的电位为第一电位，驱动子电路响应于所述第一电源信号和所述第一节点的电位，驱动发光单元发光。
  11. 根据权利要求10所述的方法，所述像素电路还包括：检测子电路；
    所述第一阶段中，第三控制信号端提供的第三控制信号的电位为第一电位，检测信号线提供的检测信号的电位为第二电位，所述检测子电路响应于所述第三控制信号，向第二节点输出所述检测信号。
  12. 根据权利要求11所述的方法，所述方法还包括：
    第五阶段，所述第三控制信号的电位为第一电位，所述检测子电路响应于所述第三控制信号，向所述检测信号线输出所述第二节点的电位，所述检测信号线将所述第二节点的电位输出至显示面板的外部补偿电路。
  13. 根据权利要求12所述的方法，
    所述第五阶段在显示面板的消隐阶段执行。
  14. 根据权利要求13所述的方法，在进入所述消隐阶段后，在执行所述第 五阶段之前，所述方法还包括：
    依次执行所述第一阶段、所述第二阶段和所述第三阶段。
  15. 根据权利要求10至14任一所述的方法，所述第一电位相对于所述第二电位为高电位。
  16. 一种显示面板，所述显示面板包括：多个像素单元，每个所述像素单元包括：如权利要求1至9任一所述的像素电路，以及与所述像素电路连接的发光单元。
  17. 一种显示装置，所述显示装置包括：源极驱动电路，以及如权利要求16所述的显示面板；
    所述源极驱动电路分别与所述显示面板中每个像素电路所连接的数据信号端连接，所述源极驱动电路用于向所述数据信号端提供数据信号。
  18. 根据权利要求17所述的显示装置，每个所述像素电路还包括：检测子电路，所述检测子电路与检测信号线连接；所述显示装置还包括：外部补偿电路；
    每个所述像素电路中的所述检测子电路所连接的检测信号线均与所述外部补偿电路连接，每个所述像素电路中的所述检测子电路用于通过所述检测信号线向所述外部补偿电路输出所述像素电路中第二节点的电位；
    所述外部补偿电路用于根据所述第二节点的电位，调整输入至所述源极驱动电路的数据信号的电位。
  19. 根据权利要求18所述的显示装置，所述显示面板中，位于同一列的所述像素单元中的检测子电路与同一条所述检测信号线连接。
  20. 根据权利要求18或19所述的显示装置，所述显示装置包括：多个像素，每个所述像素包括相邻的多个所述像素单元；
    相邻的多个所述像素单元中的检测子电路与同一条所述检测信号线连接。
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